20 V, 500 mA, Low Noise LDO Regulator with Soft Start Data Sheet ADP7105 FEATURES TYPICAL APPLICATION CIRCUITS Input voltage range: 3.3 V to 20 V VIN = 8V VIN VOUT VOUT = 5V Maximum output current: 500 mA CIN + +COUT 1µF 1µF Low noise: 15 µV rms for fixed output versions SENSE PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V ON 100kΩ 100kΩ Reverse current protection OFF EUNV/LO Low dropout voltage: 350 mV at 500 mA 100kΩ PG PG IAncictiuarla accyc uovraecry li: n±e0,. l8o%ad , and temperature GND SS CSS 11641-001 −2% to +1%, T = −40°C to +125°C Figure 1. ADP7105 with Fixed Output Voltage, 5 V J −1.25% to +1%, T = 0°C to +85°C J Low quiescent current: 900 μA at V = 10 V, I = 500 mA VIN = 8V VIN VOUT VOUT = 5V Low shutdown current: <50 µA atI NV = 12 VO,U Tstable with 1CµINF + 40.2kΩ +C1µOFUT IN ADJ small 1 µF ceramic output capacitor 13kΩ 3 fixed output voltage options: 1.8, 3.3 V and 5 V OFF ON 100kΩ EN/ 100kΩ UVLO Adjustable output from 1.22 V to 19 V 100kΩ PG PG PFUorsoledgrb rpaarmcokgm craaumbrrlemen satob-lflitem s ptitar eratcn ifdsoi rto hinne UrrumVsLahOl co/uevrnerarelbnoltae cd o pnrtorotel ction GND SS CSS 11641-002 Figure 2. ADP7105 with Adjustable Output Voltage, 5 V Power-good indicator 8-lead LFCSP and 8-lead SOIC packages APPLICATIONS Regulation of noise sensitive applications: ADC and DAC circuits, precision amplifiers, high frequency oscillators, clocks, and PLLs Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP7105 is a CMOS, low dropout (LDO) linear regulator Note that throughout this data sheet, the sense function (SENSE) of that operates from 3.3 V to 20 V and provides up to 500 mA of the SENSE/ADJ pin applies to fixed output voltage models only, output current. This high input voltage LDO is ideal for regula- whereas the adjust input function (ADJ) applies to adjustable tion of high performance analog and mixed-signal circuits output voltage models only. For example, Figure 1 shows the sense operating from 1.22 V to 19 V rails. Using an advanced proprietary function, and Figure 2 shows the adjust input function. architecture, the ADP7105 provides high power supply The ADP7105 output noise voltage is 15 µV rms and is inde- rejection and low noise, and achieves excellent line and load pendent of the output voltage. A digital power-good output transient response with only a small 1 µF ceramic output allows power system monitors to check the health of the output capacitor. voltage. A user programmable precision undervoltage lockout The ADP7105 is available in three fixed output voltage options function facilitates sequencing of multiple power supplies. and an adjustable version that allows output voltages ranging The ADP7105 is available in 8-lead, 3 mm × 3 mm LFCSP and from 1.22 V to 19 V via an external feedback divider. The 8-lead SOIC packages. The LFCSP offers a very compact solution ADP7105 allows an external soft start capacitor to be connected and provides excellent thermal performance for applications that to program the startup. require up to 500 mA of output current in a small, low profile footprint. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADP7105 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications ....................................................................................... 1 Applications Information .............................................................. 18 Typical Application Circuits ............................................................ 1 Capacitor Selection .................................................................... 18 General Description ......................................................................... 1 Programmable Undervoltage Lockout (UVLO) .................... 19 Revision History ............................................................................... 2 Soft Start Function ..................................................................... 19 Specifications ..................................................................................... 3 Power-Good Feature .................................................................. 20 Input and Output Capacitor, Recommended Specifications .... 4 Noise Reduction of the Adjustable ADP7105 ........................ 20 Absolute Maximum Ratings ............................................................ 5 Current-Limit and Thermal Overload Protection ................. 21 Thermal Data ................................................................................ 5 Thermal Considerations ............................................................ 21 Thermal Resistance ...................................................................... 5 Printed Circuit Board Layout Considerations ............................ 24 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 25 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 26 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 1/2020—Rev. B to Rev. C 10/2015—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Figure 60 and Figure 61 ............................................ 17 Changes to Fixed Output Voltage Accuracy Parameter, Table 1 and Adjustable Output Voltage Accuracy Parameter, Table 1 .. 3 5/2014—Rev. 0 to Rev. A Changes to Figure 60 and Figure 61 ............................................. 17 Change to UVLO Threshold Rising Parameter, Table 1 .............. 4 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 7/2013—Revision 0: Initial Version Rev. C | Page 2 of 26

Data Sheet ADP7105 SPECIFICATIONS V = (V + 1 V) or 3.3 V (whichever is greater), EN = V , I = 10 mA, C = C = 1 µF, T = 25°C, unless otherwise noted. IN OUT IN OUT IN OUT A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V 3.3 20 V IN OPERATING SUPPLY CURRENT I I = 100 µA, V = 10 V 400 µA GND OUT IN I = 100 µA, V = 10 V, T = −40°C to +125°C 900 µA OUT IN J I = 10 mA, V = 10 V 450 µA OUT IN I = 10 mA, V = 10 V, T = −40°C to +125°C 1050 µA OUT IN J I = 300 mA, V = 10 V 750 µA OUT IN I = 300 mA, V = 10 V, T = −40°C to +125°C 1400 µA OUT IN J I = 500 mA, V = 10 V 900 µA OUT IN I = 500 mA, V = 10 V, T = −40°C to +125°C 1600 µA OUT IN J SHUTDOWN CURRENT I EN = GND, V = 12 V 40 50 µA GND-SD IN EN = GND, V = 12 V, T = −40°C to +125°C 75 µA IN J INPUT REVERSE CURRENT I EN = GND, V = 0 V, V = 20 V 0.3 µA REV-INPUT IN OUT EN = GND, V = 0 V, V = 20 V, T = −40°C to 5 µA IN OUT J +125°C OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy V I = 10 mA −0.8 +0.8 % OUT OUT 1 mA < I < 500 mA, V = (V + 1 V) to 20 V, −2 +1 % OUT IN OUT T = −40°C to +125°C J 1 mA < I < 500 mA, V = (V + 1 V) to 20 V, –1.25 +1 % OUT IN OUT T = 0°C to +85°C J Adjustable Output Voltage V I = 10 mA 1.21 1.22 1.23 V ADJ OUT Accuracy 1 mA < I < 500 mA, V = (V + 1 V) to 20 V, 1.196 1.232 V OUT IN OUT T = −40°C to +125°C J 1 mA < I < 500 mA, V = (V + 1 V) to 20 V, 1.204 1.232 V OUT IN OUT T = 0°C to +85°C J LINE REGULATION ∆V /∆V V = (V + 1 V) to 20 V, T = −40°C to +125°C −0.015 +0.015 %/V OUT IN IN OUT J LOAD REGULATION1 ∆V /∆I 1 mA < I < 500 mA 0.2 %/A OUT OUT OUT 1 mA < I < 500 mA, T = −40°C to +125°C 0.75 %/A OUT J ADJ INPUT BIAS CURRENT2 ADJ 1 mA < I < 500 mA, V = (V + 1 V) to 20 V, 10 nA I-BIAS OUT IN OUT ADJ connected to VOUT SENSE INPUT BIAS CURRENT2 SENSE 1 mA < I < 500 mA, V = (V + 1 V) to 20 V, 1 μA I-BIAS OUT IN OUT SENSE connected to VOUT, V = 1.5 V OUT DROPOUT VOLTAGE3 V I = 10 mA 20 mV DROPOUT OUT I = 10 mA, T = −40°C to +125°C 40 mV OUT J I = 150 mA 100 mV OUT I = 150 mA, T = −40°C to +125°C 175 mV OUT J I = 300 mA 200 mV OUT I = 300 mA, T = −40°C to +125°C 325 mV OUT J I = 500 mA 350 mV OUT I = 500 mA, T = −40°C to +125°C 550 mV OUT J START-UP TIME4 t C = 0 nF, I = 10 mA 625 µs START-UP SS OUT C = 10 nF, I = 10 mA 11.5 ms SS OUT CURRENT-LIMIT THRESHOLD5 I 625 775 1000 mA LIMIT PG OUTPUT LOGIC LEVEL PG Output Logic High PG I < 1 µA 1.0 V HIGH OH PG Output Logic Low PG I < 2 mA 0.4 V LOW OL PG OUTPUT THRESHOLD Output Voltage Falling PG −9.2 % FALL Output Voltage Rising PG −6.5 % RISE Rev. C | Page 3 of 26

ADP7105 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit THERMAL SHUTDOWN Thermal Shutdown Threshold TS T rising 150 °C SD J Thermal Shutdown Hysteresis TS 15 °C SD-HYS SOFT START SOURCE CURRENT SS SS = GND 1 µA I-SOURCE PROGRAMMABLE EN/UVLO UVLO Threshold Rising UVLO 3.3 V ≤ V ≤ 20 V, T = −40°C to +125°C 1.18 1.22 1.28 V RISE IN J UVLO Threshold Falling UVLO 3.3 V ≤ V ≤ 20 V, T = −40°C to +125°C, 10 kΩ in 1.13 V FALL IN J series with the enable input pin UVLO Hysteresis Current UVLO V > 1.25 V, T = −40°C to +125°C 7.5 9.8 12 µA HYS EN J Enable Pull-Down Current I EN = V 500 nA EN-IN IN Start Threshold V T = −40°C to +125°C 3.2 V START J Shutdown Threshold V T = −40°C to +125°C 2.45 V SHUTDOWN J Hysteresis 250 mV OUTPUT NOISE OUT 10 Hz to 100 kHz, V = 5.5 V, V = 1.8 V 15 µV rms NOISE IN OUT 10 Hz to 100 kHz, V = 6.3 V, V = 3.3 V 15 µV rms IN OUT 10 Hz to 100 kHz, V = 8 V, V = 5 V 15 µV rms IN OUT 10 Hz to 100 kHz, V = 12 V, V = 9 V 15 µV rms IN OUT 10 Hz to 100 kHz, V = 5.5 V, V = 1.5 V, 18 µV rms IN OUT adjustable mode 10 Hz to 100 kHz, V = 12 V, V = 5 V, adjustable 30 µV rms IN OUT mode 10 Hz to 100 kHz, V = 20 V, V = 15 V, 65 µV rms IN OUT adjustable mode POWER SUPPLY REJECTION RATIO PSRR 100 kHz, V = 4.3 V, V = 3.3 V 50 dB IN OUT 100 kHz, V = 6 V, V = 5 V 50 dB IN OUT 10 kHz, V = 4.3 V, V = 3.3 V 60 dB IN OUT 10 kHz, V = 6 V, V = 5 V 60 dB IN OUT 100 kHz, V = 3.3 V, V = 1.8 V, adjustable mode 50 dB IN OUT 100 kHz, V = 6 V, V = 5 V, adjustable mode 60 dB IN OUT 100 kHz, V = 16 V, V = 15 V, adjustable mode 60 dB IN OUT 10 kHz, V = 3.3 V, V = 1.8 V, adjustable mode 60 dB IN OUT 10 kHz, V = 6 V, V = 5 V, adjustable mode 80 dB IN OUT 10 kHz, V = 16 V, V = 15 V, adjustable mode 80 dB IN OUT 1 Based on an endpoint calculation using 1 mA and 500 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA. 2 The adjust input function (ADJ) of the SENSE/ADJ pin applies to adjustable output voltage models only; whereas the sense function (SENSE) applies to fixed output voltage models only. 3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This specification applies only for output voltages greater than 3.0 V. 4 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 5 Current-limit threshold is defined as the current at which the output voltage falls to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to fall to 90% of 5.0 V, or 4.5 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit Minimum Input and Output Capacitance1 C T = −40°C to +125°C 0.7 µF MIN A Capacitor ESR R T = −40°C to +125°C 0.001 0.2 Ω ESR A 1 Ensure that the minimum input and output capacitance is greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO regulator. Rev. C | Page 4 of 26

Data Sheet ADP7105 ABSOLUTE MAXIMUM RATINGS board design is required. The value of θ may vary, depending Table 3. JA on PCB material, layout, and environmental conditions. The Parameter Rating specified values of θ are based on a 4-layer, 4 in. × 3 in. circuit VIN to GND −0.3 V to +22 V JA board. See JEDEC JESD51-7 and JESD51-9 for detailed VOUT to GND −0.3 V to +20 V information on the board construction. For additional EN/UVLO to GND −0.3 V to VIN information, see the AN-772 Application Note, A Design and PG to GND −0.3 V to VIN Manufacturing Guide for the Lead Frame Chip Scale Package SENSE/ADJ to GND −0.3 V to VOUT (LFCSP), available at www.analog.com. SS to GND −0.3 V to +3.6 V Storage Temperature Range −65°C to +150°C Ψ is the junction-to-board thermal characterization parameter JB Operating Junction Temperature Range −40°C to +125°C with units of °C/W. The package Ψ is based on modeling and JB Soldering Conditions JEDEC J-STD-020 calculation using a 4-layer board. JEDEC JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, Stresses at or above those listed under Absolute Maximum states that thermal characterization parameters are not the same Ratings may cause permanent damage to the product. This is a as thermal resistances. ΨJB measures the component power stress rating only; functional operation of the product at these flowing through multiple thermal paths rather than through a or any other conditions above those indicated in the operational single path as in thermal resistance, θJB. Therefore, ΨJB thermal section of this specification is not implied. Operation beyond paths include convection from the top of the package as well as the maximum operating conditions for extended periods may radiation from the package, factors that make ΨJB more useful affect product reliability. in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (T ) and power THERMAL DATA B dissipation (P ) using the formula D Absolute maximum ratings apply individually only, not in T = T + (P × Ψ ) combination. The ADP7105 can be damaged when the junction J B D JB temperature (T) limit is exceeded. Monitoring ambient See JESD51-8 and JESD51-12 for more detailed information J temperature does not guarantee that TJ is within the specified about ΨJB. temperature limits. In applications with high power dissipation THERMAL RESISTANCE and poor printed circuit board (PCB) thermal resistance, the θ and Ψ are specified for the worst-case conditions, that is, a maximum ambient temperature may need to be derated. JA JB device soldered in a circuit board for surface-mount packages. In applications with moderate power dissipation and low PCB θ is a parameter for surface-mount packages with top JC thermal resistance, the maximum ambient temperature can mounted heat sinks. θ is presented here for reference only. JC exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (T) of Table 4. Thermal Resistance J the device is dependent on the ambient temperature (TA), the Package Type θJA θJC ΨJB Unit power dissipation of the device (P ), and the junction-to-ambient 8-Lead LFCSP 40.1 27.1 17.2 °C/W D thermal resistance of the package (θ ). 8-Lead SOIC 48.5 58.4 31.3 °C/W JA Maximum junction temperature (T) is calculated from the ESD CAUTION J ambient temperature (T ) and power dissipation (P ) using the A D formula T = T + (P × θ ) J A D JA Junction-to-ambient thermal resistance (θ ) of the package is JA based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal Rev. C | Page 5 of 26

ADP7105 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT1 8VIN VOUT 1 8 VIN SENSE/ADJ2 ADP7105 7PG SENSE/ADJ 2 ADP7105 7 PG TOP VIEW TOP VIEW GND3 (Not to Scale) 6GND GND 3 (Not to Scale) 6 GND SS4 5EN/UVLO SS 4 5 EN/UVLO NOTES NOTES 1.IT IS HIGHLY RECOMMENDED THAT THE 1.IT IS HIGHLY RECOMMENDED THAT THE EPPXALAPCNOKEAS EGODEN P BTAEHD EC OOBNNO NATEHRCEDT .BEODT TTOO MTH OEF G TRHOEUND 11641-003 EPPXALAPCNOKEAS EGODEN P BTAEHD EC OOBNNO NATEHRCEDT .BEODT TTOO MTH OEF G TRHOEUND 11641-004 Figure 3. Pin Configuration, LFCSP Package Figure 4. Pin Configuration, Narrow-Body SOIC Package Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor. 2 SENSE/ADJ Sense (SENSE). SENSE measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. This function applies to fixed voltage models only. Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to adjustable voltage models only. 3 GND Ground. 4 SS Soft Start. A capacitor connected to this pin determines the soft start time. 5 EN/UVLO Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used, the upper and lower thresholds are determined by the programming resistors. 6 GND Ground. 7 PG Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the part is in shutdown mode, current-limit mode, or thermal shutdown, or if V falls below 90% OUT of the nominal output voltage, PG immediately transitions low. If the power-good function is not used, the pin can be left open or connected to ground. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor. EPAD Exposed Pad. The exposed pad on the bottom of the package enhances thermal performance and is electrically connected to GND inside the package. It is highly recommended that the exposed pad be connected to the ground plane on the board. Rev. C | Page 6 of 26

Data Sheet ADP7105 TYPICAL PERFORMANCE CHARACTERISTICS V = 7.5 V, V = 5 V, I = 10 mA, C = C = 1 µF, T = 25°C, unless otherwise noted. IN OUT OUT IN OUT A 3.35 1200 LOAD = 100µA LOAD = 100µA LOAD = 1mA LOAD = 1mA LOAD = 10mA LOAD = 10mA LOAD = 100mA 1000 LOAD = 100mA 3.33 LOAD = 300mA LOAD = 300mA LOAD = 500mA A) LOAD = 500mA µ T ( 800 V)3.31 REN (OUT CUR 600 V D 3.29 N U O 400 R G 3.27 200 3.25 0 –40 –5 TJ2 (5°C) 85 125 11641-005 –40 –5 TJ2 (5°C) 85 125 11641-008 Figure 5. Output Voltage vs. Junction Temperature, VOUT = 3.3 V Figure 8. Ground Current vs. Junction Temperature, VOUT = 3.3 V 3.35 800 700 3.33 A) 600 µ V)3.31 RENT ( 500 V (OUT D CUR 400 3.29 N U 300 O R G 200 3.27 100 3.25 0 0.1 1 ILOAD10 (mA) 100 1000 11641-006 0.1 1 ILOAD10 (mA) 100 1000 11641-009 Figure 6. Output Voltage vs. Load Current, V = 3.3 V Figure 9. Ground Current vs. Load Current, V = 3.3 V OUT OUT 3.35 1200 LOAD = 100µA LOAD = 100µA LOAD = 1mA LOAD = 1mA LOAD = 10mA LOAD = 10mA LOAD = 100mA 1000 LOAD = 100mA 3.33 LOAD = 300mA LOAD = 300mA LOAD = 500mA A) LOAD = 500mA µ T ( 800 V)3.31 REN V (OUT D CUR 600 3.29 N U O 400 R G 3.27 200 3.25 0 4 6 8 10 VIN1 2(V) 14 16 18 20 11641-007 4 6 8 10 VIN1 2(V) 14 16 18 20 11641-010 Figure 7. Output Voltage vs. Input Voltage, V = 3.3 V Figure 10. Ground Current vs. Input Voltage, V = 3.3 V OUT OUT Rev. C | Page 7 of 26

ADP7105 Data Sheet 160 1400 3.3V 4.0V 140 68..00VV 1200 12.0V ENT (µA) 110200 20.0V NT (µA)1000 RR RE 800 U R C 80 U N C W D 600 DO 60 UN T O HU GR 400 S 40 LOAD = 5mA LOAD = 10mA 20 200 LLOOAADD == 120000mmAA LOAD = 300mA LOAD = 500mA 0–50 –25 0 TE2M5PERAT5U0RE (°C7)5 100 125 11641-011 03.1 3.2 3.3 VI3N. 4(V) 3.5 3.6 3.7 11641-014 Figure 11. Shutdown Current vs. Temperature at Various Input Voltages Figure 14. Ground Current vs. Input Voltage (in Dropout), V = 3.3 V OUT 350 5.05 VOUT = 3.3V LOAD = 100µA TA = 25°C 5.04 LOAD = 1mA 300 LOAD = 10mA LOAD = 100mA 5.03 LOAD = 300mA V) LOAD = 500mA m 250 5.02 E ( TAG 200 V)5.01 OUT VOL 150 V (OUT45..9090 P O R 100 4.98 D 4.97 50 4.96 0 4.95 1 10 ILOAD (mA) 100 1000 11641-012 –40°C –5°C T2J5 (°°CC) 85°C 125°C 11641-015 Figure 12. Dropout Voltage vs. Load Current, V = 3.3 V Figure 15. Output Voltage vs. Junction Temperature, V = 5 V OUT OUT 3.4 5.05 5.04 3.3 5.03 3.2 5.02 5.01 V) 3.1 V) (UT (UT5.00 O O V 3.0 V 4.99 2.9 4.98 LOAD = 5mA LOAD = 10mA 4.97 LOAD = 100mA 2.8 LOAD = 200mA LOAD = 300mA 4.96 LOAD = 500mA 2.7 4.95 3.1 3.2 3.3 VI3N. 4(V) 3.5 3.6 3.7 11641-013 0.1 1 ILOAD10 (mA) 100 1000 11641-016 Figure 13. Output Voltage vs. Input Voltage (in Dropout), V = 3.3 V Figure 16. Output Voltage vs. Load Current, V = 5 V OUT OUT Rev. C | Page 8 of 26

Data Sheet ADP7105 5.05 300 LOAD = 100µA VOUT = 5V 5.04 LLOOAADD == 11m0mAA TA = 25°C LOAD = 100mA 250 5.03 LOAD = 300mA LOAD = 500mA V) 5.02 m E ( 200 V)5.01 TAG V (OUT5.00 T VOL 150 4.99 U O 4.98 ROP 100 D 4.97 50 4.96 4.95 0 6 8 10 12VIN (V)14 16 18 20 11641-017 1 10 ILOAD (mA) 100 1000 11641-018 Figure 17. Output Voltage vs. Input Voltage, V = 5 V Figure 20. Dropout Voltage vs. Load Current, V = 5 V OUT OUT 1000 5.05 LOAD = 100µA 900 LOAD = 1mA 5.00 LOAD = 10mA LOAD = 100mA 800 LOAD = 300mA 4.95 A) µ 700 4.90 T ( REN 600 V)4.85 D CUR 500 V (OUT4.80 N 400 4.75 U O GR 300 4.70 LOAD = 5mA 200 4.65 LOAD = 10mA LOAD = 100mA 100 4.60 LLOOAADD == 230000mmAA LOAD = 500mA 0 4.55 –40 –5 TJ2 (5°C) 85 125 11641-118 4.8 4.9 5.0 VI5N. 1(V) 5.2 5.3 5.4 11641-019 Figure 18. Ground Current vs. Junction Temperature, V = 5 V Figure 21. Output Voltage vs. Input Voltage (in Dropout), V = 5 V OUT OUT 700 2500 600 2000 CURRENT (µA) 450000 CURRENT (µA)11050000 UND 300 UND O O 500 GR 200 GR LOAD = 5mA LOAD = 10mA 0 LOAD = 100mA 100 LOAD = 200mA LOAD = 300mA LOAD = 500mA 00.1 1 ILOAD10 (mA) 100 1000 11641-119 –5004.80 4.90 5.00 V5IN.1 (0V) 5.20 5.30 5.40 11641-020 Figure 19. Ground Current vs. Load Current, V = 5 V Figure 22. Ground Current vs. Input Voltage (in Dropout), V = 5 V OUT OUT Rev. C | Page 9 of 26

ADP7105 Data Sheet 1.85 900 LOAD = 100µA LOAD = 100µA LOAD = 1mA LOAD = 1mA LOAD = 10mA 800 LOAD = 10mA LOAD = 100mA LOAD = 100mA 1.83 LLOOAADD == 350000mmAA 700 LOAD = 300mA A) µ T ( 600 (V)UT1.81 URREN 500 VO D C 400 1.79 N U O 300 R G 1.77 200 100 1.75 0 –40 –5 TJ2 (5°C) 85 125 11641-021 –40 –5 TJ2 (5°C) 85 125 11641-126 Figure 23. Output Voltage vs. Junction Temperature, V = 1.8 V Figure 26. Ground Current vs. Junction Temperature, V = 1.8 V OUT OUT 1.85 700 600 1.83 A) 500 µ T ( 1.81 N (V)UT URRE 400 O C V1.79 ND 300 U O GR 200 1.77 100 1.750.1 1 ILOA1D0 (mA) 100 1000 11641-022 00.1 1 ILOAD1 0(mA) 100 1000 11641-127 Figure 24. Output Voltage vs. Load Current, V = 1.8 V Figure 27. Ground Current vs. Load Current, V = 1.8 V OUT OUT 1.85 1200 LOAD = 100µA LOAD = 100µA LOAD = 1mA LOAD = 1mA LOAD = 10mA LOAD = 10mA LOAD = 100mA 1000 LOAD = 100mA 1.83 LOAD = 300mA LOAD = 300mA LOAD = 500mA LOAD = 500mA A) µ T ( 800 V)1.81 REN (OUT CUR 600 V D 1.79 N U O 400 R G 1.77 200 1.75 0 2 4 6 8 10VIN (V1)2 14 16 18 20 11641-023 2 4 6 8 10VIN (V1)2 14 16 18 20 11641-024 Figure 25. Output Voltage vs. Input Voltage, VOUT = 1.8 V Figure 28. Ground Current vs. Input Voltage, VOUT = 1.8 V Rev. C | Page 10 of 26

Data Sheet ADP7105 5.08 2.0 LOAD = 100µA 3.3V 5.07 LOAD = 1mA 4V LOAD = 10mA 5V LOAD = 100mA 6V 5.06 LOAD = 300mA A) 8V 5.05 LOAD = 500mA ENT (µ 1.5 111025VVV R 18V V)5.04 UR 20V (OUT5.03 UT C 1.0 V P 5.02 N E I S 5.01 R E V 0.5 5.00 RE 4.99 4.98 –40 –5 TJ2 (5°C) 85 125 11641-025 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 11641-054 Figure 29. Output Voltage vs. Junction Temperature, V = 5 V, Adjustable Figure 32. Reverse Input Current vs. Temperature, V = 0 V, Different OUT IN Voltages on V OUT 5.08 5.07 5.06 5.05 EN 5.04 1 V) (UT5.03 VO VOUT 5.02 2 5.01 5.00 IIN 4.99 3 4.980.1 1 ILOAD10 (mA) 100 1000 11641-026 CCHH13 22.00m0VA CH2 2.00V MT 2 . 0 0 m5.s95ms A CH1 3.00V 11641-133 Figure 30. Output Voltage vs. Load Current, V = 5 V, Adjustable Figure 33. Start-Up Time, V and V = 6 V, C and C = 1 µF, C = 10 nF, OUT EN IN IN OUT SS I = 10 mA, V = 5 V OUT OUT 5.08 0 LOAD = 500mA LOAD = 300mA 5.07 –10 LOAD = 100mA LOAD = 10mA LOAD = 1mA 5.06 –20 5.05 –30 V (V)OUT55..0034 SRR (dB) ––5400 5.02 P –60 5.01 –70 LOAD = 100µA 5.00 LOAD = 1mA –80 LOAD = 10mA 4.99 LOAD = 100mA –90 LOAD = 300mA LOAD = 500mA 4.986 8 10 12VIN (V)14 16 18 20 11641-027 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-028 Figure 31. Output Voltage vs. Input Voltage, V = 5 V, Adjustable Figure 34. Power Supply Rejection Ratio vs. Frequency, V = 1.8 V, V = 3.3 V OUT OUT IN Rev. C | Page 11 of 26

ADP7105 Data Sheet 0 0 LOAD = 500mA LOAD = 500mA LOAD = 300mA LOAD = 300mA –10 LOAD = 100mA –10 LOAD = 100mA LOAD = 10mA LOAD = 10mA LOAD = 1mA LOAD = 1mA –20 –20 –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-029 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-032 Figure 35. Power Supply Rejection Ratio vs. Frequency, V = 3.3 V, V = 4.8 V Figure 38. Power Supply Rejection Ratio vs. Frequency, V = 5 V, V = 6.5 V OUT IN OUT IN 0 0 LOAD = 500mA LOAD = 500mA LOAD = 300mA LOAD = 300mA –10 LOAD = 100mA –10 LOAD = 100mA LOAD = 10mA LOAD = 10mA LOAD = 1mA LOAD = 1mA –20 –20 –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-030 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-033 Figure 36. Power Supply Rejection Ratio vs. Frequency, V = 3.3 V, V = 4.3 V Figure 39. Power Supply Rejection Ratio vs. Frequency, V = 5 V, V = 6 V OUT IN OUT IN 0 0 LOAD = 500mA LOAD = 500mA LOAD = 300mA LOAD = 300mA –10 LOAD = 100mA –10 LOAD = 100mA LOAD = 10mA LOAD = 10mA –20 LOAD = 1mA –20 LOAD = 1mA –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-031 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-034 Figure 37. Power Supply Rejection Ratio vs. Frequency, V = 3.3 V, V = 3.8 V Figure 40. Power Supply Rejection Ratio vs. Frequency, V = 5 V, V = 5.5 V OUT IN OUT IN Rev. C | Page 12 of 26

Data Sheet ADP7105 0 0 LOAD = 500mA LOAD = 500mA LOAD = 300mA LOAD = 300mA –10 LOAD = 100mA –10 LOAD = 100mA LOAD = 10mA LOAD = 10mA –20 LOAD = 1mA –20 LOAD = 1mA –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-035 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-038 Figure 41. Power Supply Rejection Ratio vs. Frequency, V = 5 V, V = 5.3 V Figure 44. Power Supply Rejection Ratio vs. Frequency, V = 5 V, V = 6 V, OUT IN OUT IN Adjustable with Noise Reduction Circuit 0 0 LOAD = 500mA LOAD = 300mA –10 –10 LOAD = 100mA LOAD = 10mA –20 –20 LOAD = 1mA –30 –30 B) –40 B) –40 R (d –50 R (d –50 R R S S P –60 P –60 –70 –70 –80 –80 LOAD = 500mA LOAD = 300mA –90 LOAD = 100mA –90 LOAD = 10mA LOAD = 1mA –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-036 –1000 0.25 H0E.5A0DROOM0. 7V5OLTAGE1. 0(V0) 1.25 1.50 11641-039 Figure 42. Power Supply Rejection Ratio vs. Frequency, V = 5 V, V = 5.2 V Figure 45. Power Supply Rejection Ratio vs. Headroom Voltage, 100 Hz, OUT IN V = 5 V OUT 0 0 LOAD = 500mA LOAD = 500mA LOAD = 300mA LOAD = 300mA –10 LOAD = 100mA –10 LOAD = 100mA LOAD = 10mA LOAD = 10mA LOAD = 1mA LOAD = 1mA –20 –20 –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 11641-037 –1000 0.25 H0E.5A0DROOM0. 7V5OLTAGE1. 0(V0) 1.25 1.50 11641-040 Figure 43. Power Supply Rejection Ratio vs. Frequency, V = 5 V, V = 6 V, Figure 46. Power Supply Rejection Ratio vs. Headroom Voltage, 1 kHz, OUT IN Adjustable V = 5 V OUT Rev. C | Page 13 of 26

ADP7105 Data Sheet 0 10 LOAD = 500mA 3.3V LOAD = 300mA 5V –10 LLOOAADD == 11000mmAA 5VADJ LOAD = 1mA 5VADJ NR –20 –30 1 B) –40 √Hz) d V/ RR ( –50 E (µ S S P –60 OI N 0.1 –70 –80 –90 –1000 0.25 H0E.5A0DROOM0. 7V5OLTAGE1. 0(V0) 1.25 1.50 11641-041 0.0110 100 FREQUE1NkCY (Hz) 10k 100k 11641-044 Figure 47. Power Supply Rejection Ratio vs. Headroom Voltage, 10 kHz, Figure 50. Output Noise Spectral Density, I = 10 mA, C = 1 μF LOAD OUT V = 5 V OUT 0 LOAD = 500mA LOAD = 300mA –10 LOAD = 100mA LOAD CURRENT LOAD = 10mA LOAD = 1mA –20 1 –30 B) –40 d R ( –50 R S P –60 OUTPUT VOLTAGE 2 –70 –80 –90 –1000 0.25 H0E.5A0DROOM0. 7V5OLTAGE1. 0(V0) 1.25 1.50 11641-042 CH1 500mAΩBW CH2 50mV BW TM 1200%µs A CH1 270mA 11641-045 Figure 48. Power Supply Rejection Ratio vs. Headroom Voltage, 100 kHz, Figure 51. Load Transient Response, C = C = 1 μF, I = 1 mA to IN OUT LOAD V = 5 V 500 mA, V = 1.8 V, V = 5 V OUT OUT IN 30 LOAD CURRENT 25 1 20 s) m V r E (µ 15 S NOI 2 OUTPUT VOLTAGE 10 3.3V 5 1.8V 5V 5VADJ 5VADJ NR 00.00001 0.0001 0.001ILOAD (A)0.01 0.1 1 11641-043 CH1500mAΩBW CH2 50mV BW TM 1200.µ2s% A CH1 280mA 11641-046 Figure 49. Output Noise vs. Load Current and Output Voltage, Figure 52. Load Transient Response, CIN = COUT = 1 μF, ILOAD = 1 mA to COUT = 1 μF 500 mA, VOUT = 3.3 V, VIN = 5 V Rev. C | Page 14 of 26

Data Sheet ADP7105 LOAD CURRENT INPUT VOLTAGE 1 2 OUTPUT VOLTAGE OUTPUT VOLTAGE 2 CH1500mAΩBW CH2 50mV BW TM 1200.µ2s% A CH1 300mA 11641-047 1 CH1 1V BW CH2 10mV BW TM 49µ.8s% A CH4 1.56V 11641-050 Figure 53. Load Transient Response, C = C = 1 μF, I = 1 mA to Figure 56. Line Transient Response, C = C = 1 μF, I = 500 mA, IN OUT LOAD IN OUT LOAD 500 mA, V = 5 V, V = 7 V V = 5 V OUT IN OUT INPUT VOLTAGE INPUT VOLTAGE 2 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 1 CH1 1V BW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 11641-048 CH1 1VBW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 11641-051 Figure 54. Line Transient Response, C = C = 1 μF, I = 500 mA, Figure 57. Line Transient Response, C = C = 1 μF, I = 1 mA, IN OUT LOAD IN OUT LOAD V = 1.8 V V = 1.8 V OUT OUT INPUT VOLTAGE 2 OUTPUT VOLTAGE 1 CH1 1V BW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 11641-049 Figure 55. Line Transient Response, C = C = 1 μF, I = 500 mA, IN OUT LOAD V = 3.3 V OUT Rev. C | Page 15 of 26

ADP7105 Data Sheet INPUT VOLTAGE INPUT VOLTAGE 2 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 CH1 1VBW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 11641-052 1 CH1 1VBW CH2 10mV BW TM 49µ.8s% A CH4 1.56V 11641-053 Figure 58. Line Transient Response, C = C = 1 μF, I = 1 mA, Figure 59. Line Transient Response, C = C = 1 μF, I = 1 mA, IN OUT LOAD IN OUT LOAD V = 3.3 V V = 5 V OUT OUT Rev. C | Page 16 of 26

Data Sheet ADP7105 THEORY OF OPERATION The ADP7105 is a low quiescent current, LDO linear regulator of the PMOS device is pulled higher, allowing less current to that operates from 3.3 V to 20 V and provides up to 500 mA of pass and decreasing the output voltage. output current. The ADP7105 draws a low 900 µA of quiescent The ADP7105 is available in three fixed output voltage options, current (typical) at full load, making it ideal for battery-operated 1.8 V, 3.3 V, and 5 V, and in an adjustable version with an output portable equipment. Typical shutdown current consumption is voltage that can be set from 1.22 V to 19 V by an external 40 μA at room temperature. voltage divider. The output voltage can be set according to the Optimized for use with small 1 µF ceramic capacitors, the following equation: ADP7105 provides excellent transient performance. V = 1.22 V(1 + R1/R2) OUT VIN VOUT VIN = 8V CIN + VIN VOUT R1 +COUT VOUT = 5V GND VREG SHORT-CIRCUIT, PGOOD PG 1µF ADJ 40.2kΩ 1µF THERMAL PROTECT R3 10µA SHUTDOWN OFF ON 100kRΩ4 EUNV/LO 13kRΩ2 R10P0GkΩ EN/ SENSE 100kΩ UVLO PG PG SS GND SS REFERENCE 11641-056 Figure 62. Typical Adjustable Output VoClStaSge Application Schematic 11641-075 Figure 60. Fixed Output Voltage Internal Block Diagram Ensure that the value of R2 is less than 200 kΩ to minimize VIN VOUT errors in the output voltage caused by the ADJ input current. VREG For example, when R1 and R2 each equal 200 kΩ, the output GND SHORT-CIRCUIT, PGOOD PG THERMAL voltage is 2.46 V. The output voltage error introduced by the PROTECT ADJ input current is 2 mV or 0.08%, assuming a typical ADJ 10µA SHUTDOWN input current of 10 nA at 25°C. EN/ ADJ UVLO SS The ADP7105 uses the EN/UVLO pin to enable and disable the VOUT pin under normal operating conditions. When EN/UVLO REF1E.R22EVNCE 11641-156 iosf fh. iFgohr, VauOtoUmTa ttuicr nstsa ortnu;p w, EheNn/ UENV/LUOV cLaOn bise ltoiewd, VtoO VUITN .t urns Figure 61. Adjustable Output Voltage Internal Block Diagram The ADP7105 incorporates reverse current protection circuitry Internally, the ADP7105 consists of a reference, an error amplifier, that prevents current flow backwards through the pass element a feedback voltage divider, and a PMOS pass transistor. Output when the output voltage is greater than the input voltage. A current is delivered via the PMOS pass device, which is controlled comparator senses the difference between the input and output by the error amplifier. The error amplifier compares the reference voltages. When the difference between the input voltage and voltage with the feedback voltage from the output and amplifies output voltage exceeds 55 mV, the body of the PFET is switched the difference. If the feedback voltage is lower than the reference to V and turned off or opened. In other words, the gate is OUT voltage, the gate of the PMOS device is pulled lower, allowing connected to VOUT. more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate Rev. C | Page 17 of 26

ADP7105 Data Sheet APPLICATIONS INFORMATION CAPACITOR SELECTION Figure 64 shows the capacitance vs. voltage bias characteristic of an 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a Output Capacitor capacitor is strongly influenced by the capacitor size and voltage The ADP7105 is designed for operation with small, space-saving rating. In general, a capacitor in a larger package or higher voltage ceramic capacitors but functions with most commonly used rating exhibits better stability. The temperature variation of the capacitors as long as care is taken with regard to the effective series X5R dielectric is ~±15% over the −40°C to +85°C temperature resistance (ESR) value. The ESR of the output capacitor affects the range and is not a function of package or voltage rating. stability of the LDO control loop. A minimum of 1 µF capacitance 1.2 with an ESR of 1 Ω or less is recommended to ensure the stability of the ADP7105. Transient response to changes in load current is 1.0 also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP7105 to F) 0.8 µ large changes in load current. Figure 63 shows the transient E ( C responses for an output capacitance value of 1 µF. N A 0.6 T CI A P LOAD CURRENT CA 0.4 1 0.2 00 2 4VOLTAGE (V6) 8 10 11641-058 OUTPUT VOLTAGE 2 Figure 64. Capacitance vs. Voltage Bias Characteristic Use Equation 1 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CH1 500mAΩ CH2 50mV TM 1200%µs A CH1 270mA 11641-057 wherCe:E FF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1) Figure 63. Output Transient Response, V = 1.8 V, C = 1 µF OUT OUT C is the effective capacitance at the operating voltage. BIAS Input Bypass Capacitor TEMPCO is the worst-case capacitor temperature coefficient. Connecting a 1 µF capacitor from VIN to GND reduces the TOL is the worst-case component tolerance. circuit sensitivity to PCB layout, especially when long input In this example, the worst-case temperature coefficient (TEMPCO) traces or high source impedance is encountered. If greater than over −40°C to +85°C is assumed to be 15% for an X5R dielectric. 1 µF of output capacitance is required, increase the input The tolerance of the capacitor (TOL) is assumed to be 10%, and capacitor to match it. C is 0.94 μF at 1.8 V, as shown in Figure 64. BIAS Input and Output Capacitor Properties Substituting these values in Equation 1 yields Any good quality ceramic capacitors can be used with the C = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF EFF ADP7105, as long as they meet the minimum capacitance and Therefore, the capacitor chosen in this example meets the maximum ESR requirements. Ceramic capacitors are manufac- minimum capacitance requirement of the LDO regulator tured with a variety of dielectrics, each with different behavior overtemperature and tolerance at the chosen output voltage. over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over To guarantee the performance of the ADP7105, it is imperative the necessary temperature range and dc bias conditions. X5R that the effects of dc bias, temperature, and tolerances on the or X7R dielectrics with a voltage rating of 6.3 V to 25 V are behavior of the capacitors be evaluated for each application. recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. Rev. C | Page 18 of 26

Data Sheet ADP7105 PROGRAMMABLE UNDERVOLTAGE LOCKOUT Figure 65 shows the typical hysteresis of the EN/UVLO pin. (UVLO) This prevents on/off oscillations that can occur due to noise on the EN/UVLO pin as it passes through the threshold points. The ADP7105 uses the EN/UVLO pin to enable and disable the VOUT pin under normal operating conditions. As shown in SOFT START FUNCTION Figure 65, when a rising voltage on EN/UVLO crosses the upper For applications that require a controlled startup, the ADP7105 threshold, VOUT turns on. When a falling voltage on EN/UVLO provides a programmable soft start function. Programmable crosses the lower threshold, VOUT turns off. The hysteresis of soft start is useful for reducing inrush current upon startup and the EN/UVLO threshold is determined by the Thevenin for providing voltage sequencing. To implement soft start, connect equivalent resistance in series with the EN/UVLO pin. a small ceramic capacitor from SS to GND. Upon startup, a 2.0 1 µA current source charges this capacitor. The ADP7105 1.8 start-up output voltage is limited by the voltage at SS, providing a smooth ramp-up to the nominal output voltage. The soft start 1.6 time is calculated by 1.4 t = V × (C /I ) 1.2 SS REF SS SS V) (OUT1.0 VVOOUUTT,, EENN//UUVVLLOO FRAISLEL where: V t is the soft start delay. 0.8 SS V is the 1.22 V reference voltage. 0.6 REF C is the soft start capacitance between SS and GND. SS 0.4 I is the current sourced from SS (1 µA). SS 0.2 01.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 11641-060 Wstahrte nca tphaec AitoDrP i7s 1d0is5c ihsa drgiseadb lteod G (bNyD d rthivrionugg EhN an lo iwnt)e, rtnhael s5o fktΩ EN/UVLO (V) resistor. Figure 65. Typical VOUT Response to EN/UVLO Pin Operation 7 The upper and lower thresholds are user programmable and can 6 be set using two resistors. When the EN/UVLO pin voltage is EN below 1.23 V, the LDO is disabled. When the EN/UVLO pin V) 5 voltage transitions above 1.23 V, the LDO is enabled and 10 µA GE ( 0nF 2.7nF 6.8nF 10nF hysteresis current is sourced out of the pin, raising the voltage TA 4 L O and thus providing threshold hysteresis. Typically, two external V resistors program the minimum operational voltage for the UT 3 P T LDO. The resistance values, R1 and R2, can be determined from U O 2 the following: R1 = V /10 μA 1 HYS wherRe:2 = 1.23 V × R1/(VIN − 1.23 V) 00 5 TIME (m10s) 15 11641-061 V is the desired EN/UVLO hysteresis level. Figure 67. Typical Start-Up Behavior HYS V is the desired turn-on voltage. IN Hysteresis can also be achieved by connecting a resistor in series with the EN/UVLO pin. For the example shown in Figure 66, the enable threshold is 2.46 V with a hysteresis of 1 V. VIN = 8V VIN VOUT VOUT = 5V CIN + +COUT 1µF 1µF SENSE ON 10R01kΩ 100kΩ OFF EN/ UVLO R2 PG PG 100kΩ GND SS CSS 11641-059 Figure 66. Typical EN/UVLO Pin Voltage Divider Rev. C | Page 19 of 26

ADP7105 Data Sheet POWER-GOOD FEATURE NOISE REDUCTION OF THE ADJUSTABLE ADP7105 The ADP7105 provides a power-good pin (PG) to indicate the status of the output. This open-drain output requires an The ultralow output noise of the fixed output ADP7105 is external pull-up resistor to VIN or VOUT. If the part is in achieved by keeping the LDO error amplifier in unity gain shutdown mode, current-limit mode, or thermal shutdown, or and setting the reference voltage equal to the output voltage. if V falls below 90% of the nominal output voltage, the This architecture does not apply to the adjustable output voltage OUT power-good pin (PG) immediately transitions low. During soft LDO regulator. The adjustable output ADP7105 uses the more start, the rising threshold of the power-good signal is 93.5% of conventional architecture where the reference voltage is fixed the nominal output voltage. and the error amplifier gain is a function of the output voltage. The disadvantage of the conventional LDO architecture is that The open-drain output is held low when the ADP7105 has suffi- the output voltage noise is proportional to the output voltage. cient input voltage to turn on the internal PG transistor. The PG transistor is terminated via a pull-up resistor to VOUT or VIN. The adjustable LDO circuit can be modified slightly to reduce the output voltage noise to levels close to that of the fixed output Power-good accuracy is 93.5% of the nominal regulator output ADP7105. The circuit shown in Figure 70 adds two additional voltage when this voltage is rising, with a 90.8% trip point when components to the output voltage setting resistor divider. C this voltage is falling. Regulator input voltage brownouts or NR and R are added in parallel with R to reduce the ac gain of glitches trigger power no good signals if V falls below 90.8% NR FB1 OUT the error amplifier. R is chosen to be equal to R . This limits of the nominal output voltage. NR FB2 the ac gain of the error amplifier to approximately 6 dB. The A normal power-down causes the power-good signal to go low actual gain is the parallel combination of R and R divided when V falls below 90.8%. NR FB1 OUT by R . This ensures that the error amplifier always operates at FB2 Figure 68 and Figure 69 show the typical power-good rising and greater than unity gain. falling thresholds over temperature. C is chosen by setting the reactance of C equal to R − R NR NR FB1 NR 6 at a frequency between 50 Hz and 100 Hz. This capacitor value sets –40°C –5°C the frequency so that the ac gain of the error amplifier is 3 dB +25°C 5 ++81255°C°C less than its dc gain. V) 4 VIN = 8V 1CµINF + VIN VOAUDTJ 40R.2FkBΩ1 +C10N0RnF +C1µOFUVTOUT = 5V PG ( 3 OFF ON 10R03kΩ EUNV/LO 1R3FkBΩ2 1R3NkRΩ R10P0GkΩ 2 R4 100kΩ PG PG 1 GND SS CSS 11641-064 04.2 4.3 4.4 4.5 VOU4.T6 (V) 4.7 4.8 4.9 5.0 11641-062 TheF inguories e7 0o. fN tohisee aRdedjuuscttiaobnl eM LodDifOica rteiognu tloa tAodrju csatanb blee L DfoOu Rnedg ublayt or Figure 68. Typical Power-Good Threshold vs. Output Voltage and using the following formula, assuming the noise of a fixed Temperature, V Rising OUT output LDO is approximately 15 μV: 6 –40°C –5°C  1   5 +++2812555°°CC°C 15μV× 1+1/13kΩ+1/40.2kΩ/13kΩ 4 Based on the component values shown in Figure 70, the ADP7105 has the following characteristics: V) PG ( 3 • DC gain of 4.09 (12.2 dB) • 3 dB roll-off frequency of 59 Hz 2 • High frequency ac gain of 1.76 (4.89 dB) • Noise reduction factor of 1.33 (2.59 dB) 1 • RMS noise of the ADP7105 adjustable LDO without noise reduction of 27.8 µV rms 0 4.2 4.3 4.4 4.5 VOU4.T6 (V) 4.7 4.8 4.9 5.0 11641-063 • RreMduSc ntiooinse ( aosfs tuhme iAnDg 1P57 1µ0V5 ramdjsu fsotar bfliex eLdD vOol wtaigteh onpotiisoen ) Figure 69. Typical Power-Good Threshold vs. Output Voltage and of 19.95 µV rms Temperature, V Falling OUT Rev. C | Page 20 of 26

Data Sheet ADP7105 CURRENT-LIMIT AND THERMAL OVERLOAD aware of the parameters that contribute to junction temperature PROTECTION changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between The ADP7105 is protected against damage due to excessive the junction and ambient air (θ ). The θ value is dependent on power dissipation by current and thermal overload protection JA JA the package assembly compounds that are used and the amount of circuits. The ADP7105 is designed to limit the current when the copper used to solder the package GND pins to the PCB. output load reaches 775 mA (typical). When the output load exceeds 775 mA, the output voltage is reduced to maintain a Table 6 shows typical θ values for the 8-lead SOIC and 8-lead JA constant current limit. As the output voltage drops, the current LFCSP packages for various PCB copper sizes. Table 7 shows is folded back to approximately 50 mA to minimize heat the typical Ψ values for the 8-lead SOIC and 8-lead LFCSP JB generation inside the LDO regulator. with PCB area. Thermal overload protection is included, which limits the Table 6. Typical θ Values JA junction temperature to a maximum of 150°C (typical). Under θ (°C/W) JA extreme conditions (that is, high ambient temperature and/or Copper Size (mm2) LFCSP SOIC high power dissipation) when the junction temperature starts to 251 165.1 167.8 rise above 150°C, the output is turned off, reducing the output 100 125.8 111 current to zero. When the junction temperature falls below 500 68.1 65.9 135°C, the output is turned on again, and output current is 1000 56.4 56.1 restored to its operating value. 6400 42.1 45.8 Consider the case where a hard short from VOUT to ground 1 Device soldered to minimum size pin traces. occurs. At first, the ADP7105 limits the current so that only 775 mA is conducted into the short. If self heating of the Table 7. Typical Ψ Values with PCB Area JB junction is great enough to cause its temperature to rise above Model Ψ (°C/W) JB 150°C, thermal shutdown is activated, turning off the output and 8-Lead LFCSP1 15.1 reducing the output current to zero. As the junction temperature 8-Lead SOIC 31.3 cools and falls below 135°C, the output turns on and conducts 775 mA into the short, again causing the junction temperature 1 Note that the ΨJB value for the LFCSP package accounts for PCB area, which is being used as a heat sink via the exposed pad, whereas the value in Table 4 is to rise above 150°C. This thermal oscillation between 135°C per the JEDEC standard. and 150°C causes a current oscillation between 775 mA and The junction temperature of the ADP7105 is calculated from 0 mA that continues as long as the short remains at the output. the following equation: Current-limit and thermal limit protections are intended to T = T + (P × θ ) (2) protect the device against accidental overload conditions. For J A D JA reliable operation, device power dissipation must be externally where: limited so that the junction temperature does not exceed 125°C. T is the ambient temperature. A θ is the junction-to-ambient thermal resistance. THERMAL CONSIDERATIONS JA P is the power dissipation in the die, given by D In applications with a low input-to-output voltage differential, P = [(V − V ) × I ] + (V × I ) (3) the ADP7105 does not dissipate much heat. However, in D IN OUT LOAD IN GND applications with high ambient temperature and/or high input where: voltage, the heat dissipated in the package may become V and V are the input and output voltages, respectively. IN OUT significant enough that it causes the junction temperature of the I is the load current. LOAD die to exceed the maximum junction temperature of 125°C. I is the ground current. GND When the junction temperature exceeds 150°C, the regulator Power dissipation due to ground current is quite small and can enters thermal shutdown. It recovers only after the junction be ignored. Therefore, the junction temperature equation temperature decreases below 135°C to prevent any permanent simplifies to the following: damage. Therefore, thermal analysis for the chosen application T = T + {[(V − V ) × I ] × θ } (4) J A IN OUT LOAD JA is very important to guarantee reliable performance over all As shown in Equation 4, for a given ambient temperature, input- conditions. The junction temperature of the die is the sum of to-output voltage differential, and continuous load current, a the ambient temperature of the environment and the tempera- minimum copper size requirement for the PCB exists to ensure ture rise of the package due to the power dissipation, as shown that the junction temperature does not rise above 125°C. Figure 71 in Equation 2. to Figure 76 show junction temperature calculations for different To guarantee reliable operation, the junction temperature of the ambient temperatures, power dissipation, and areas of PCB copper. ADP7105 must not exceed 125°C. To ensure that the junction temperature stays below this maximum value, the user must be Rev. C | Page 21 of 26

ADP7105 Data Sheet 145 145 135 135 125 125 C) C) E (° 115 E (° 115 UR 105 UR 105 RAT 95 RAT 95 E E MP 85 MP 85 E E N T 75 N T 75 O O TI 65 TI 65 C C UN 55 UN 55 J J 45 6400mm2 45 6400mm2 500mm2 500mm2 35 25mm2 35 25mm2 TJMAX TJMAX 250 0.2 0.4 0.T6OT0A.8L P1O.0WE1R. 2DIS1S.4IPA1T.I6ON1 (.W8)2.0 2.2 2.4 11641-065 250 0.2 0.4 0.T6OT0A.8L P1O.0WE1R. 2DIS1S.4IPA1T.I6ON1 (.W8)2.0 2.2 2.4 11641-068 Figure 71. LFCSP, T = 25°C Figure 74. SOIC, T = 25°C A A 140 140 130 130 E (°C) 120 E (°C) 120 R R U 110 U 110 T T A A ER 100 ER 100 P P M M TE 90 TE 90 N N O O TI 80 TI 80 C C N N JU 70 JU 70 6400mm2 6400mm2 60 52050mmmm22 60 52050mmmm22 TJMAX TJMAX 500 0.2 0.4TOTA0L.6 POW0E.8R DIS1S.0IPATI1O.2N (W)1.4 1.6 1.8 11641-066 500 0.2 0.4TOTA0L.6 POW0E.8R DIS1S.0IPATI1O.2N (W)1.4 1.6 1.8 11641-069 Figure 72. LFCSP, T = 50°C Figure 75. SOIC, T = 50°C A A 145 145 135 135 C) C) E (° 125 E (° 125 R R U U AT 115 AT 115 R R E E MP 105 MP 105 E E T T ON 95 ON 95 TI TI C C UN 85 UN 85 J J 6400mm2 6400mm2 75 500mm2 75 500mm2 25mm2 25mm2 TJMAX TJMAX 650 0.1 0.2TO0T.A3L P0O.W4ER0 D.5ISSIP0.A6TION0. 7(W)0.8 0.9 1.0 11641-067 650 0.1 0.2TO0T.A3L P0O.4WER0 D.5ISSI0P.A6TION0. 7(W)0.8 0.9 1.0 11641-070 Figure 73. LFCSP, T = 85°C Figure 76. SOIC, T = 85°C A A Rev. C | Page 22 of 26

Data Sheet ADP7105 In the case where the board temperature is known, use the Ψ 140 JB thermal characterization parameter to estimate the junction 120 temperature rise (see Figure 77 and Figure 78). Maximum T)J junction temperature (TJ) is calculated from the board tempera- RE ( 100 ture (TB) and power dissipation (PD) using the following ATU formula: ER 80 P M T = T + (P × Ψ ) (5) E J B D JB N T 60 O The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP package CTI 40 and 31.3°C/W for the 8-lead SOIC package (see Table 7). N U J TB = 25°C 140 20 TTBB == 5605°°CC TB = 85°C E (T)J110200 00 0.5 TO1.T0AL POW1.5ER DISS2.I0PATION2 (.W5) T3J.0MAX 3.5 11641-072 R U Figure 78. SOIC T A R 80 E P M E T 60 N O TI C 40 N U J TB = 25°C 20 TTBB == 5605°°CC TB = 85°C TJMAX 00 0.5 1.0 1.5TO2.T0AL2 .P5OW3.0ER3 D.5IS4S.I0PA4T.I5ON5 .(0W)5.5 6.0 6.5 7.0 11641-071 Figure 77. LFCSP Rev. C | Page 23 of 26

ADP7105 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP7105. However, as shown in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Use of 0805 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where space is limited. Figure 80. Example SOIC PCB Layout Figure 79. Example LFCSP PCB Layout Rev. C | Page 24 of 26

Data Sheet ADP7105 OUTLINE DIMENSIONS 3.10 2.48 3.00 SQ 2.38 (DJEEDTAEICL 9A5) 2.90 2.23 5 8 EXPOSED 1.74 PAD 1.64 0.50 1.49 0.40 IANRDEEAX 0.30 4 1 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATORAREAOPTIONS 0.80 MAX (SEEDETAILA) 0.80 0.55 NOM 0.75 SIDE VIEW 0.05 MAX 0.70 FOR PROPER CONNECTION OF 0.02 NOM THE EXPOSED PAD, REFER TO COPLANARITY THE PIN CONFIGURATION AND SEATING 0.08 FUNCTION DESCRIPTIONS PLANE 0.30 0.50 BSC 0.20 REF SECTION OF THIS DATA SHEET 0.25 0.18COMPLIANTTOJEDEC STANDARDS MO-229-WEED-4 08-17-2018-B Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-5) Dimensions shown in millimeters 5.00 3.098 4.90 4.80 0.356 8 5 6.20 4.00 6.00 3.90 5.80 2.41 3.80 0.457 1 4 FOR PROPER CONNECTION OF 1.27 BSC BOTTOM VIEW THE EXPOSED PAD, REFER TO 3.81 REF THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW SECTION OF THIS DATA SHEET. 1.75 1.65 0.50 45° 1.35 1.25 0.25 0.25 0.17 0.10 MAX SEATING PLANE 0.51 0.05 NOM 8° 1.04 REF COPLANARITY 0° 1.27 0.31 0.10 0.40 COMPLIANTTO JEDEC STANDARDS MS-012-AA 06-03-2011-B Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-2) Dimensions shown in millimeters Rev. C | Page 25 of 26

ADP7105 Data Sheet ORDERING GUIDE Temperature Output Package Package Model1 Range Voltage (V) Description Option Marking Codes ADP7105ACPZ-1.8-R7 −40°C to +125°C 1.8 8-Lead LFCSP CP-8-5 LNS ADP7105ACPZ-3.3-R7 −40°C to +125°C 3.3 8-Lead LFCSP CP-8-5 LNT ADP7105ACPZ-5.0-R7 −40°C to +125°C 5 8-Lead LFCSP CP-8-5 LNU ADP7105ACPZ-R2 −40°C to +125°C Adjustable 8-Lead LFCSP CP-8-5 LNV ADP7105ACPZ-R7 −40°C to +125°C Adjustable 8-Lead LFCSP CP-8-5 LNV ADP7105ARDZ-1.8 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-1.8-R7 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-3.3 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-3.3-R7 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-5.0 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-5.0-R7 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2 ADP7105ARDZ-R7 −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2 1 Z = RoHS Compliant Part. ©2013–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11641-0-1/20(C) Rev. C | Page 26 of 26