20 V, 300 mA, Low Noise, CMOS LDO Data Sheet ADP7102 FEATURES TYPICAL APPLICATION CIRCUITS Input voltage range: 3.3 V to 20 V VIN = 8V VIN VOUT VOUT = 5V Maximum output current: 300 mA CIN + +COUT Low noise: 15 μV rms for fixed output versions 1µF 1µF SENSE PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V ON 10R01kΩ R10P0GkΩ Reverse current protection OFF EN/ UVLO Low dropout voltage: 200 mV at 300 mA load R2 PG PG 100kΩ Initial accuracy: ±0.8% GND ALocwcu qraucieys ocevnetr cliunrere, nlota (Vd, a =n 5d V te),m Ipe =ra 7t5u0re μ: A− 2w%ith, + 310%0 m A load 09506-001 IN GND Figure 1. ADP7102 with Fixed Output Voltage, 5 V Low shutdown current: 40 μA at V = 12 V IN Stable with small 1 μF ceramic output capacitor VIN = 8V VIN VOUT VOUT = 5V 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, CIN + R1 +COUT 1µF 40.2kΩ 1µF 5 V, and 9 V ADJ R2 AFodljdubstaacbkl ceu oruretpntu lti mfroitm a n1d.2 t2h Ver tmo aVlI No −ve VrDloO ad protection OFF ON 10R03kΩ EUNV/LO 13kΩ R10P0GkΩ User programmable precision UVLO/enable 100kRΩ4 PG PG P8o-lweaedr- LgFoCoSdP i nanddic a8t-olera d SOIC packages GND 09506-002 Figure 2. ADP7102 with Adjustable Output Voltage, 5 V APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP7102 is a CMOS, low dropout linear regulator that The ADP7102 output noise voltage is 15 μV rms and is operates from 3.3 V to 20 V and provides up to 300 mA of output independent of the output voltage. A digital power-good output current. This high input voltage LDO is ideal for regulation of high allows power system monitors to check the health of the output performance analog and mixed signal circuits operating from voltage. A user programmable precision undervoltage lockout 19 V to 1.22 V rails. Using an advanced proprietary architecture, it function facilitates sequencing of multiple power supplies. provides high power supply rejection, low noise, and achieves The ADP7102 is available in 8-lead, 3 mm × 3 mm LFCSP and excellent line and load transient response with just a small 1 μF 8-lead SOIC packages. The LFCSP offers a very compact solution ceramic output capacitor. and also provides excellent thermal performance for applications The ADP7102 is available in seven fixed output voltage options requiring up to 300 mA of output current in a small, low profile and an adjustable version, which allows output voltages that footprint. range from 1.22 V to V − V via an external feedback divider. IN DO Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADP7102 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Theory of Operation ...................................................................... 17  Applications ....................................................................................... 1  Applications Information .............................................................. 18  Typical Application Circuits ............................................................ 1  Capacitor Selection .................................................................... 18  General Description ......................................................................... 1  Programable Undervoltage Lockout (UVLO) ........................... 19  Revision History ............................................................................... 2  Power-Good Feature .................................................................. 20  Specifications ..................................................................................... 3  Noise Reduction of the Adjustable ADP7102 ............................ 20  Input and Output Capacitor, Recommended Specifications .. 4  Current Limit and Thermal Overload Protection ................. 21  Absolute Maximum Ratings ............................................................ 5  Thermal Considerations ............................................................ 21  Thermal Data ................................................................................ 5  Printed Circuit Board Layout Considerations ............................ 24  ESD Caution .................................................................................. 5  Outline Dimensions ....................................................................... 25  Pin Configurations and Function Descriptions ........................... 6  Ordering Guide .......................................................................... 26  Typical Performance Characteristics ............................................. 7  REVISION HISTORY 9/15—Rev. D to Rev. E Changes to Figure 60 ...................................................................... 17 5/14—Rev. C to Rev. D Changed UVLO Threshold Rising Typ Parameter from 1.23 V to 1.22 V; Table 1 ............................................................................... 4 Changes to Power Good Section .................................................. 20 Updated Outline Dimensions ....................................................... 26 8/13—Rev. B to Rev. C Changes to Table 3 ............................................................................ 5 2/13—Rev. A to Rev. B Changes to Noise Reduction of the Adjustable ADP7102 Section .............................................................................................. 20 11/11—Rev. 0 to Rev. A Changes to Figure 50 ...................................................................... 14 10/11—Revision 0: Initial Version Rev. E | Page 2 of 28

Data Sheet ADP7102 SPECIFICATIONS V = (V + 1 V) or 3.3 V (whichever is greater), EN = V , I = 10 mA, C = C = 1 μF, T = 25°C, unless otherwise noted. IN OUT IN OUT IN OUT A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V 3.3 20 V IN OPERATING SUPPLY CURRENT I I = 100 μA, V = 10 V 400 μA GND OUT IN I = 100 μA, V = 10 V, T = −40°C to +125°C 900 μA OUT IN J I = 10 mA, V = 10 V 450 μA OUT IN I = 10 mA, V = 10 V, T = −40°C to +125°C 1050 μA OUT IN J I = 150 mA, V = 10 V 650 μA OUT IN I = 150 mA, V = 10 V, T = −40°C to +125°C 1250 μA OUT IN J I = 300 mA, V = 10 V 750 μA OUT IN I = 300 mA, V = 10 V, T = −40°C to +125°C 1400 μA OUT IN J SHUTDOWN CURRENT I EN = GND, V = 12 V 40 μA GND-SD IN EN = GND, V = 12 V, T = −40°C to +125°C 75 μA IN J INPUT REVERSE CURRENT I EN = GND, V = 0 V, V = 20 V 0.3 μA REV-INPUT IN OUT EN = GND, V = 0 V, V = 20 V, T = −40°C to +125°C 5 μA IN OUT J OUTPUT VOLTAGE ACCURACY Fixed Output Voltage V I = 10 mA −0.8 +0.8 % OUT OUT Accuracy 1 mA < I < 300 mA, V = (V + 1 V) to 20 V, −2 +1 % OUT IN OUT T = −40°C to +125°C J Adjustable Output Voltage V I = 10 mA 1.21 1.22 1.23 V ADJ OUT Accuracy 1 mA < I < 300 mA, V = (V + 1 V) to 20 V, 1.196 1.232 V OUT IN OUT T = −40°C to +125°C J LINE REGULATION ∆V /∆V V = (V + 1 V) to 20 V, T = −40°C to +125°C −0.015 +0.015 %/V OUT IN IN OUT J LOAD REGULATION1 ∆V /∆I I = 1 mA to 300 mA 0.2 %/A OUT OUT OUT I = 1 mA to 300 mA, T = −40°C to +125°C 1.0 %/A OUT J ADJ INPUT BIAS CURRENT ADJ 1 mA < I < 300 mA, V = (V + 1 V) to 20 V, 10 nA I-BIAS OUT IN OUT ADJ connected to VOUT SENSE INPUT BIAS CURRENT SENSE 1 mA < I < 300 mA, V = (V + 1 V) to 20 V, 1 μA I-BIAS OUT IN OUT SENSE connected to VOUT, V = 1.5 V OUT DROPOUT VOLTAGE2 V I = 10 mA 20 mV DROPOUT OUT I = 10 mA, T = −40°C to +125°C 40 mV OUT J I = 150 mA 100 mV OUT I = 150 mA, T = −40°C to +125°C 175 mV OUT J I = 300 mA 200 mV OUT I = 300 mA, T = −40°C to +125°C 325 mV OUT J START-UP TIME3 t V = 5 V 800 μs START-UP OUT CURRENT-LIMIT THRESHOLD4 I 450 575 750 mA LIMIT PG OUTPUT LOGIC LEVEL PG Output Logic High PG I < 1 μA 1.0 V HIGH OH PG Output Logic Low PG I < 2 mA 0.4 V LOW OL PG OUTPUT THRESHOLD Output Voltage Falling PG −9.2 % FALL Output Voltage Rising PG −6.5 % RISE Rev. E | Page 3 of 28

ADP7102 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit THERMAL SHUTDOWN Thermal Shutdown TSSD TJ rising 150 C Threshold Thermal Shutdown TSSD-HYS 15 C Hysteresis PROGRAMMABLE EN/UVLO UVLO Threshold rising UVLO 3.3 V ≤ V ≤ 20 V, T = −40°C to +125°C 1.18 1.22 1.28 V RISE IN J UVLO Threshold falling UVLO 3.3 V ≤ V ≤ 20 V, T = −40°C to +125°C, 10 kΩ 1.13 V FALL IN J in series with enable pin UVLO Hysteresis Current UVLO V > 1.25 V, T = −40°C to +125°C 7.5 9.8 12 μA HYS EN J Enable Pulldown Current I EN = V 500 nA EN-IN IN INPUT VOLTAGE Start Threshold V T = −40°C to +125°C 3.2 V START J Shutdown Threshold V T = −40°C to +125°C 2.45 V SHUTDOWN J Hysteresis 250 mV OUTPUT NOISE OUT 10 Hz to 100 kHz, V = 5.5 V, V = 1.8 V 15 μV rms NOISE IN OUT 10 Hz to 100 kHz, V = 6.3 V, V = 3.3 V 15 μV rms IN OUT 10 Hz to 100 kHz, V = 8 V, V = 5 V 15 μV rms IN OUT 10 Hz to 100 kHz, V = 12 V, V = 9 V 15 μV rms IN OUT 10 Hz to 100 kHz, V = 5.5 V, V = 1.5 V, 18 μV rms IN OUT adjustable mode 10 Hz to 100 kHz, V = 12 V, V = 5 V, 30 μV rms IN OUT adjustable mode 10 Hz to 100 kHz, V = 18 V, V = 15 V, 65 μV rms IN OUT adjustable mode POWER SUPPLY REJECTION PSRR 100 kHz, V = 4.3 V, V = 3.3 V 50 dB IN OUT RATIO 100 kHz, V = 6 V, V = 5 V 50 dB IN OUT 10 kHz, V = 4.3 V, V = 3.3 V 60 dB IN OUT 10 kHz, V = 6 V, V = 5 V 60 dB IN OUT 100 kHz, V = 3.3 V, V = 1.8 V, adjustable mode 50 dB IN OUT 100 kHz, V = 6 V, V = 5 V, adjustable mode 60 dB IN OUT 100 kHz, V = 16 V, V = 15 V, adjustable mode 60 dB IN OUT 10 kHz, V = 3.3 V, V = 1.8 V, adjustable mode 60 dB IN OUT 10 kHz, V = 6 V, V = 5 V, adjustable mode 80 dB IN OUT 10 kHz, V = 16 V, V = 15 V, adjustable mode 80 dB IN OUT 1 Based on an end point calculation using 1 mA and 300 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA. 2 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 3.0 V. 3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit Minimum Input and Output Capacitance1 C T = −40°C to +125°C 0.7 μF MIN A Capacitor ESR R T = −40°C to +125°C 0.001 0.2 Ω ESR A 1 The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. E | Page 4 of 28

Data Sheet ADP7102 ABSOLUTE MAXIMUM RATINGS In applications where high maximum power dissipation exists, Table 3. close attention to thermal board design is required. The value of θ Parameter Rating JA may vary, depending on PCB material, layout, and environmental VIN to GND −0.3 V to +22 V conditions. The specified values of θ are based on a 4-layer, VOUT to GND −0.3 V to +20 V JA 4 in. × 3 in. circuit board. See JESD51-7 and JESD51-9 for detailed EN/UVLO to GND −0.3 V to VIN information on the board construction. For additional information, PG to GND −0.3 V to VIN see the AN-617 Application Note, MicroCSP Wafer Level Chip SENSE/ADJ to GND −0.3 V to VOUT Scale Package. Storage Temperature Range −65°C to +150°C Operating Junction Temperature Range −40°C to +125°C ΨJB is the junction to board thermal characterization parameter Soldering Conditions JEDEC J-STD-020 with units of °C/W. The package’s ΨJB is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines Stresses at or above those listed under Absolute Maximum for Reporting and Using Electronic Package Thermal Information, Ratings may cause permanent damage to the product. This is a states that thermal characterization parameters are not the same stress rating only; functional operation of the product at these as thermal resistances. Ψ measures the component power or any other conditions above those indicated in the operational JB flowing through multiple thermal paths rather than a single section of this specification is not implied. Operation beyond path as in thermal resistance, θ . Therefore, Ψ thermal paths the maximum operating conditions for extended periods may JB JB include convection from the top of the package as well as radiation affect product reliability. from the package, factors that make Ψ more useful in real-world JB THERMAL DATA applications. Maximum junction temperature (T) is calculated J Absolute maximum ratings apply individually only, not in from the board temperature (TB) and power dissipation (PD) combination. The ADP7102 can be damaged when the junction using the formula temperature limit is exceeded. Monitoring ambient temperature T = T + (P × Ψ ) J B D JB does not guarantee that T is within the specified temperature J See JESD51-8 and JESD51-12 for more detailed information limits. In applications with high power dissipation and poor about Ψ . JB thermal resistance, the maximum ambient temperature may Thermal Resistance have to be derated. θ and Ψ are specified for the worst case conditions, that is, a In applications with moderate power dissipation and low JA JB device soldered in a circuit board for surface-mount packages. printed circuit board (PCB) thermal resistance, the maximum θ is a parameter for surface-mount packages with top mounted ambient temperature can exceed the maximum limit as long as JC heat sinks. θ is presented here for reference only. the junction temperature is within specification limits. The JC junction temperature (T) of the device is dependent on the J Table 4. Thermal Resistance ambient temperature (T ), the power dissipation of the device A Package Type θ θ Ψ Unit JA JC JB (P ), and the junction to ambient thermal resistance of the D 8-Lead LFCSP 40.1 27.1 17.2 °C/W package (θ ). JA 8-Lead SOIC 48.5 58.4 31.3 °C/W Maximum junction temperature (T) is calculated from the J ESD CAUTION ambient temperature (T ) and power dissipation (P ) using the A D formula T = T + (P × θ ) J A D JA Junction to ambient thermal resistance (θ ) of the package is JA based on modeling and calculation using a 4-layer board. The junction to ambient thermal resistance is highly dependent on the application and board layout. Rev. E | Page 5 of 28

ADP7102 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT1 8VIN VOUT 1 8 VIN SENSE/ADJ2 ADP7102 7PG SENSE/ADJ 2 ADP7102 7 PG GND3 (NToOt Pto V SIEcWale) 6GND GND 3 (NToOt Pto V SIEcaWle) 6 GND NC4 5EN/UVLO NC 4 5 EN/UVLO NOTES NOTES 1. NC = NO CONNECT. DO NOT CONNECTTO 1. NC = NO CONNECT. DO NOT CONNECTTO THIS PIN. THIS PIN. 2.IT IS HIGHLY RECOMMENDED THAT THE 2.IT IS HIGHLY RECOMMENDED THAT THE EPPXALAPCONKEAS EGODEN P BTAEHD EC OOBNNO NATEHRCEDT .BEODT TTOO MTH OEF G TRHOEUND 09506-003 EPPXALAPCNOKEAS EGODEN P BTAEHD EC OOBNNO NATEHRCEDT .BEODT TTOO MTH OEF G TRHOEUND 09506-104 Figure 3. LFCSP Package Figure 4. Narrow Body SOIC Package Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 μF or greater capacitor. 2 SENSE/ADJ Sense (SENSE). Measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. This function applies to fixed voltages only. Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to adjustable voltages only. 3 GND Ground. 4 NC Do Not Connect to this Pin. 5 EN/UVLO Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used, the upper and lower thresholds are determined by the programming resistors. 6 GND Ground. 7 PG Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the device is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output voltage, PG immediately transitions low. If the power-good function is not used, the pin may be left open or connected to ground. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 1 μF or greater capacitor. EPAD Exposed Pad. Exposed paddle on the bottom of the package. The EPAD enhances thermal performance and is electrically connected to GND inside the package. It is highly recommended that the EPAD be connected to the ground plane on the board. Rev. E | Page 6 of 28

Data Sheet ADP7102 TYPICAL PERFORMANCE CHARACTERISTICS V = 5 V, V = 3.3 V, I = 1 mA, C = C = 1 μF, T = 25°C, unless otherwise noted. IN OUT OUT IN OUT A 3.35 900 LOAD = 100µA LOAD=100µA LOAD = 1mA LOAD=1mA LOAD = 10mA 800 LOAD=10mA LOAD = 100mA LOAD=100mA 3.33 LOAD = 300mA 700 LOAD=300mA A) (µ 600 T 3.31 N V) RE 500 V (OUT DCUR 400 3.29 N U O 300 R G 200 3.27 100 3.25 0 –40°C –5°C T2J5 (°°CC) 85°C 125°C 09506-004 –40°C –5°C T2J5(°°CC) 85°C 125°C 09506-007 Figure 5. Output Voltage vs. Junction Temperature Figure 8. Ground Current vs. Junction Temperature 3.35 700 600 3.33 A) 500 µ T ( 3.31 N V) RE 400 (OUT CUR V 3.29 ND 300 U O GR 200 3.27 100 3.25 0 0.1 1 ILOAD10 (mA) 100 1000 09506-005 0.1 1 ILOAD10 (mA) 100 1000 09506-008 Figure 6. Output Voltage vs. Load Current Figure 9. Ground Current vs. Load Current 3.35 900 LOAD = 100µA LOAD=100µA LOAD = 1mA LOAD=1mA LOAD = 10mA 800 LOAD=10mA LOAD = 100mA LOAD=100mA 3.33 LOAD = 300mA 700 LOAD=300mA A) (µ 600 T V) 3.31 REN 500 (OUT CUR 400 V D 3.29 N U O 300 R G 200 3.27 100 3.25 0 4 6 8 10 VIN1 2(V) 14 16 18 20 09506-006 4 6 8 10 VIN12(V) 14 16 18 20 09506-009 Figure 7. Output Voltage vs. Input Voltage Figure 10. Ground Current vs. Input Voltage Rev. E | Page 7 of 28

ADP7102 Data Sheet 160 1400 3.3V 4.0V 140 6.0V 1200 8.0V 12.0V µA) 120 20.0V A)1000 ENT ( 100 NT (µ R E 800 R R U R C 80 U WN D C 600 SHUTDO 4600 GROUN 400 LOAD = 5mA LOAD = 10mA 20 200 LOAD = 100mA LOAD = 200mA LOAD = 300mA 0 0 –50 –25 0 TE2M5PERAT5U0RE (°C7)5 100 125 09506-010 3.10 3.20 3.30 V3IN.4 (0V) 3.50 3.60 3.70 09506-013 Figure 11. Shutdown Current vs. Temperature at Various Input Voltages Figure 14. Ground Current vs. Input Voltage (in Dropout) 200 5.05 VOUT = 3.3V LOAD = 100µA 180 TA = 25°C 5.04 LLOOAADD == 11m0mAA LOAD = 100mA 160 5.03 LOAD = 300mA 140 5.02 mV) 120 5.01 ROPOUT ( 10800 V (V)OUT45..9090 D 60 4.98 40 4.97 20 4.96 0 4.95 1 10 ILOAD (mA) 100 1000 09506-011 –40°C –5°C T2J5 (°°CC) 85°C 125°C 09506-014 Figure 12. Dropout Voltage vs. Load Current Figure 15. Output Voltage vs. Junction Temperature, VOUT = 5 V 3.35 5.05 3.30 5.04 5.03 3.25 5.02 3.20 5.01 V (V)OUT33..1105 V (V)OUT45..9090 3.05 4.98 3.00 4.97 LOAD = 100µA LOAD = 1mA 2.95 LOAD = 10mA 4.96 LOAD = 100mA LOAD = 300mA 4.95 2.903.10 3.20 3.30 V3IN.4 (0V) 3.50 3.60 3.70 09506-012 0.1 1 ILOAD10 (mA) 100 1000 09506-015 Figure 13. Output Voltage vs. Input Voltage (in Dropout) Figure 16. Output Voltage vs. Load Current, VOUT = 5 V Rev. E | Page 8 of 28

Data Sheet ADP7102 5.05 900 LOAD = 100µA LOAD = 100µA LOAD = 1mA LOAD = 1mA 5.04 LOAD = 10mA 800 LOAD = 10mA LOAD = 100mA LOAD = 100mA 5.03 LOAD = 300mA 700 LOAD = 300mA 5.02 µA) T ( 600 5.01 N V) RE 500 V (OUT45..9090 ND CUR 400 U O 300 4.98 R G 4.97 200 4.96 100 4.956 8 10 12VIN (V)14 16 18 20 09506-016 06 8 10 12VIN (V)14 16 18 20 09506-120 Figure 17. Output Voltage vs. Input Voltage, VOUT = 5 V Figure 20. Ground Current vs. Input Voltage, VOUT = 5 V 1000 180 900 LLLOOOAAADDD === 1110m00mAµAA 160 VTAO U=T 2 =5 °5CV LOAD = 100mA 800 LOAD = 300mA 140 T (µA) 700 V) 120 N 600 m URRE 500 OUT ( 100 D C OP 80 N 400 R U D O 60 R 300 G 40 200 100 20 0 –40°C –5°C T2J5 (°°CC) 85°C 125°C 09506-118 01 10 ILOAD (mA) 100 1000 09506-017 Figure 18. Ground Current vs. Junction Temperature, VOUT = 5 V Figure 21. Dropout Voltage vs. Load Current, VOUT = 5 V 700 5.05 600 5.00 A) 500 4.95 µ NT ( 4.90 RE 400 V) D CUR 300 V (OUT4.85 UN 4.80 O GR 200 4.75 LOAD = 5mA 100 4.70 LLOOAADD == 1100m0mAA LOAD = 200mA LOAD = 300mA 0 4.65 0.1 1 ILOAD10 (mA) 100 1000 09506-119 4.8 4.9 5.0 VI5N. 1(V) 5.2 5.3 5.4 09506-018 Figure 19. Ground Current vs. Load Current, VOUT = 5 V Figure 22. Output Voltage vs. Input Voltage (in Dropout), VOUT = 5 V Rev. E | Page 9 of 28

ADP7102 Data Sheet 2500 1.85 LOAD = 100µA LOAD = 1mA LOAD = 10mA 2000 LOAD = 100mA 1.83 LOAD = 300mA A) T (µ1500 N 1.81 URRE1000 (V)UT C O ND V 1.79 U O 500 R G LOAD = 5mA 1.77 0 LOAD = 10mA LOAD = 100mA LOAD = 200mA –5004.80 LOA4D.9 =0 300mA5.00 V5IN.1 (0V) 5.20 5.30 5.40 09506-019 1.752 4 6 8 10VIN (V1)2 14 16 18 20 09506-022 Figure 23. Ground Current vs. Input Voltage (in Dropout), VOUT = 5 V Figure 26. Output Voltage vs. Input Voltage, VOUT = 1.8 V 1.85 900 LOAD = 100µA LOAD = 100µA LOAD = 1mA LOAD = 1mA LOAD = 10mA 800 LOAD = 10mA LOAD = 100mA LOAD = 100mA 1.83 LOAD = 300mA 700 LOAD = 300mA A) T (µ 600 V) 1.81 REN 500 V (OUT D CUR 400 1.79 N U O 300 R G 200 1.77 100 1.75 0 –40°C –5°C T2J5 (°°CC) 85°C 125°C 09506-020 –40°C –5°C T2J 5(°°CC) 85°C 125°C 09506-023 Figure 24. Output Voltage vs. Junction Temperature, VOUT = 1.8 V Figure 27. Ground Current vs. Junction Temperature, VOUT = 1.8 V 1.85 700 600 1.83 A) 500 µ T ( V) 1.81 REN 400 V (OUT D CUR 300 1.79 N U O GR 200 1.77 100 1.75 0 0.1 1 ILOAD10 (mA) 100 1000 09506-021 0.1 1 ILOAD10 (mA) 100 1000 09506-128 Figure 25. Output Voltage vs. Load Current, VOUT = 1.8 V Figure 28. Ground Current vs. Load Current, VOUT = 1.8 V Rev. E | Page 10 of 28

Data Sheet ADP7102 1200 5.08 LOAD = 100µA LOAD = 100µA LOAD = 1mA 5.07 LOAD = 1mA LOAD = 10mA LOAD = 10mA 1000 LOAD = 100mA LOAD = 100mA LOAD = 300mA 5.06 LOAD = 300mA A) 5.05 T (µ 800 N 5.04 URRE 600 (V)UT5.03 C O D V 5.02 N U RO 400 5.01 G 5.00 200 4.99 02 4 6 8 10VIN (V1)2 14 16 18 20 09506-129 4.986 8 10 12VIN (V)14 16 18 20 09506-026 Figure 29. Ground Current vs. Input Voltage, VOUT = 1.8 V Figure 32. Output Voltage vs. Input Voltage, VOUT = 5 V, Adjustable 5.08 LOAD = 100µA 2.0 5.07 LLOOAADD == 11m0mAA 34.V3V LOAD = 100mA 5V 5.06 LOAD = 300mA 6V A) 8V 5.05 T (µ 1.5 1102VV 5.04 REN 1158VV V) R 20V (T5.03 CU OU N 1.0 V W 5.02 O D T 5.01 U H S 5.00 UT 0.5 O I 4.99 4.98 –40°C –5°C T2J5 (°°CC) 85°C 125°C 09506-024 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 09506-053 Figure 30. Output Voltage vs. Junction Temperature, VOUT = 5 V, Adjustable Figure 33. Reverse Input Current vs. Temperature, VIN = 0 V, Different Voltages on VOUT 5.08 0 LOAD = 300mA 5.07 –10 LLOOAADD == 11000mmAA LOAD = 1mA 5.06 –20 5.05 –30 V) 5.04 B) –40 (UT5.03 R (d –50 VO5.02 PSR –60 5.01 –70 5.00 –80 4.99 –90 4.98 0.1 1 ILOAD10 (mA) 100 1000 09506-025 –10010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 09506-027 Figure 31. Output Voltage vs. Load Current, VOUT = 5 V, Adjustable Figure 34. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V, VIN = 3.3 V Rev. E | Page 11 of 28

ADP7102 Data Sheet 0 0 LOAD = 300mA LOAD = 1mA –10 LLOOAADD == 11000mmAA –10 LLOOAADD == 11000mmAA LOAD = 1mA LOAD = 300mA –20 –20 –30 –30 B) –40 B) –40 R (d –50 R (d –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 09506-028 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09506-031 Figure 35. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, Figure 38. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6.5 V VIN = 4.8 V 0 0 LOAD = 300mA LOAD = 1mA LOAD = 100mA LOAD = 10mA –10 LOAD = 10mA –10 LOAD = 100mA LOAD = 1mA LOAD = 300mA –20 –20 –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –100 –100 10 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 09506-029 10 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09506-032 Figure 36. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, Figure 39. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V VIN = 4.3 V 0 0 LOAD = 300mA LOAD = 1mA LOAD = 100mA LOAD = 10mA –10 LOAD = 10mA –10 LOAD = 100mA LOAD = 1mA LOAD = 300mA –20 –20 –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 09506-030 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09506-033 Figure 37. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, Figure 40. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.5 V VIN = 3.8 V Rev. E | Page 12 of 28

Data Sheet ADP7102 0 0 LOAD = 1mA LOAD = 1mA LOAD = 10mA LOAD = 10mA –10 LOAD = 100mA –10 LOAD = 100mA LOAD = 300mA LOAD = 300mA –20 –20 –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09506-034 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09506-037 Figure 41. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.3 V Figure 44. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V, Adjustable with Noise Reduction Circuit 0 0 LOAD = 1mA LOAD = 1mA LOAD = 10mA LOAD = 10mA –10 LOAD = 100mA –10 LOAD = 100mA LOAD = 300mA LOAD = 300mA –20 –20 –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09506-035 –1000 0.25 H0E.5A0DROOM0. 7V5OLTAGE1. 0(V0) 1.25 1.50 09506-038 Figure 42. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.2 V Figure 45. Power Supply Rejection Ratio vs. Headroom Voltage, 100 Hz, VOUT = 5 V 0 0 LOAD = 1mA LOAD = 1mA LOAD = 10mA LOAD = 10mA –10 LOAD = 100mA –10 LOAD = 100mA LOAD = 300mA LOAD = 300mA –20 –20 –30 –30 B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09506-036 –1000 0.25 0H.5E0ADROO0.M75 VOLTAG1.E00 1.25 1.50 09506-039 Figure 43. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V, Figure 46. Power Supply Rejection Ratio vs. Headroom Voltage, 1 kHz, Adjustable VOUT = 5 V Rev. E | Page 13 of 28

ADP7102 Data Sheet 0 10 LOAD = 1mA 3.3V LOAD = 10mA 5V –10 LOAD = 100mA 5V ADJ LOAD = 300mA 5V ADJ NR –20 –30 1 B) –40 RR (d –50 V/√Hz S µ P –60 0.1 –70 –80 –90 –100 0.01 0 0.25 H0E.5A0DROOM0. 7V5OLTAGE1. 0(V0) 1.25 1.50 09506-040 10 100 FREQUE1NkCY (Hz) 10k 100k 09506-043 Figure 47. Power Supply Rejection Ratio vs. Headroom Voltage, 10 kHz, Figure 50. Output Noise Spectral Density, ILOAD = 10 mA, COUT = 1 μF VOUT = 5 V 0 LOAD = 1mA LOAD = 10mA –10 LOAD = 100mA LOAD = 300mA LOAD CURRENT –20 –30 B) –40 1 d R ( –50 R S P –60 OUTPUT VOLTAGE 2 –70 –80 –90 –1000 0.25 H0E.5A0DROOM0. 7V5OLTAGE1. 0(V0) 1.25 1.50 09506-041 CH1 200mAΩBW CH2 50mV BW TM 1200.µ4s% A CH1 76mA 09506-044 Figure 48. Power Supply Rejection Ratio vs. Headroom Voltage, 100 kHz, Figure 51. Load Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA to 300 mA, VOUT = 5 V VOUT = 1.8 V, VIN = 5 V 30 LOAD CURRENT 25 1 20 s) m V r E (µ 15 NOIS 2 OUTPUT VOLTAGE 10 3.3V 5 1.8V 5V 5VADJ 0.000001 0.0001 L0O.A00D1 CURREN0T.0 (1A) 0.15VADJ NR1 09506-042 CH1 200mAΩBW CH2 50mV BWMT 2100µ.2s% A CH1 168mA 09506-045 Figure 49. Output Noise vs. Load Current and Output Voltage, Figure 52. Load Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA to 300 mA, COUT = 1 μF VOUT = 3.3 V, VIN = 5 V Rev. E | Page 14 of 28

Data Sheet ADP7102 LOAD CURRENT INPUT VOLTAGE 1 2 OUTPUT VOLTAGE OUTPUT VOLTAGE 2 1 CH1 200mAΩBW CH2 50mV BWMT 2100µ.2s% A CH1 216mA 09506-046 CH1 1V BW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 09506-048 Figure 53. Load Transient ReVspOUoTn =se 5, CVI,N V, CIN O=U T7 = V 1 μF, ILOAD = 1 mA to 300 mA, Figure 55. Line Transient ReVspOoUTn =se 3, .C3I NV, COUT = 1 μF, ILOAD = 300 mA, INPUT VOLTAGE INPUT VOLTAGE 2 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 CH1 1V BW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 09506-047 1 CH1 1VBW CH2 10mV BWMT 49µ.8s% A CH4 1.56V 09506-049 Figure 54. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 300 mA, Figure 56. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 300 mA, VOUT = 5 V VOUT = 1.8 V Rev. E | Page 15 of 28

ADP7102 Data Sheet INPUT VOLTAGE INPUT VOLTAGE 2 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 1 CH1 1V BW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 09506-050 1 CH11V BW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 09506-052 Figure 57. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA, VOUT = 1.8 V Figure 59. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA, VOUT = 5 V INPUT VOLTAGE 2 OUTPUT VOLTAGE 1 CH1 1V BW CH2 10mV BW TM 94.µ8s% A CH4 1.56V 09506-051 Figure 58. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA, VOUT = 3.3 V Rev. E | Page 16 of 28

Data Sheet ADP7102 THEORY OF OPERATION The ADP7102 is a low quiescent current, low dropout linear If the feedback voltage is higher than the reference voltage, the regulator that operates from 3.3 V to 20 V and provides up to gate of the PMOS device is pulled higher, allowing less current 300 mA of output current. Drawing a low 750 μA of quiescent to pass and decreasing the output voltage. current (typical) at full load makes the ADP7102 ideal for battery The ADP7102 is available in seven fixed output voltage options, operated portable equipment. Typical shutdown current ranging from 1.8 V to 9 V, and in an adjustable version with an consumption is 40 μA at room temperature. output voltage that can be set to any voltage between 1.22 V and Optimized for use with small 1 μF ceramic capacitors, the 19 V by an external voltage divider. The output voltage can be set ADP7102 provides excellent transient performance. according to the following equation: V = 1.22 V(1 + R1/R2) VIN VOUT OUT VREG GND SHOTRHTE-RCMIRACLUIT, PGOOD PG VIN = 8V CIN + VIN VOUT R1 +COUT VOUT = 5V PROTECT 1µF 40.2kΩ 1µF ADJ UVELNO/ 10µA SHUTDOWN SENSE OFF ON 10R03kΩ EUNV/LO 13kRΩ2 R10P0GkΩ R4 100kΩ GND PG PG REFERENCE 09506-055 09506-057 Figure 60. Fixed Output Voltage Internal Block Diagram Figure 62. Typical Adjustable Output Voltage Application Schematic The value of R2 must be less than 200 kΩ to minimize errors in VIN VOUT the output voltage caused by the ADJ pin input current. For VREG example, when R1 and R2 each equal 200 kΩ, the output voltage is GND SHORT-CIRCUIT, PGOOD PG THERMAL 2.44 V. The output voltage error introduced by the ADJ pin input PROTECT current is 2 mV or 0.08%, assuming a typical ADJ pin input current 10µA SHUTDOWN of 10 nA at 25°C. EN/ SENSE UVLO The ADP7102 uses the EN/UVLO pin to enable and disable the VOUT pin under normal operating conditions. When EN/UVLO REF1E.R22EVNCE 09506-056 iasu htoigmha, tVicO sUtaTrt utupr, nEsN o/nU; VwLhOen c EanN b ise ltoiewd, VtoO VUINT .t urns off. For Figure 61. Adjustable Output Voltage Internal Block Diagram The ADP7102 incorporates reverse current protections Internally, the ADP7102 consists of a reference, an error circuitry that prevents current flow backwards through the pass amplifier, a feedback voltage divider, and a PMOS pass transistor. element when the output voltage is greater than the input voltage. A Output current is delivered via the PMOS pass device, which is comparator senses the difference between the input and output controlled by the error amplifier. The error amplifier compares voltages. When the difference between the input voltage and output the reference voltage with the feedback voltage from the output voltage exceeds 55 mV, the body of the PFET is switched to V OUT and amplifies the difference. If the feedback voltage is lower than and turned off or opened. In other words, the gate is connected the reference voltage, the gate of the PMOS device is pulled lower, to VOUT. allowing more current to pass and increasing the output voltage. Rev. E | Page 17 of 28

ADP7102 Data Sheet APPLICATIONS INFORMATION CAPACITOR SELECTION Figure 64 depicts the capacitance vs. voltage bias characteristic Output Capacitor of an 0402, 1 μF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage The ADP7102 is designed for operation with small, space-saving rating. In general, a capacitor in a larger package or higher voltage ceramic capacitors but functions with most commonly used rating exhibits better stability. The temperature variation of the capacitors as long as care is taken with regard to the effective series X5R dielectric is ~ ±15% over the −40°C to +85°C temperature resistance (ESR) value. The ESR of the output capacitor affects range and is not a function of package or voltage rating. the stability of the LDO control loop. A minimum of 1 μF 1.2 capacitance with an ESR of 0.2 Ω or less is recommended to ensure the stability of the ADP7102. Transient response to changes 1.0 in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response F) 0.8 of the ADP7102 to large changes in load current. Figure 63 shows µ E ( the transient responses for an output capacitance value of 1 μF. NC A 0.6 T CI A P CA 0.4 LOAD CURRENT 0.2 1 0 0 2 4VOLTAGE (V6) 8 10 09506-059 2 OUTPUT VOLTAGE Figure 64. Capacitance vs. Voltage Characteristic Use Equation 1 to determine the worst case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CH1 200mAΩBW CH2 50mV BW TM 1200.µ4s% A CH1 76mA 09506-058 wherCe:E FF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1) Figure 63. Output Transient Response, VOUT = 1.8 V, COUT = 1 μF C is the effective capacitance at the operating voltage. BIAS Input Bypass Capacitor TEMPCO is the worst case capacitor temperature coefficient. Connecting a 1 μF capacitor from VIN to GND reduces the TOL is the worst case component tolerance. circuit sensitivity to PCB layout, especially when long input traces In this example, the worst case temperature coefficient (TEMPCO) or high source impedance are encountered. If greater than 1 μF of over −40°C to +85°C is assumed to be 15% for an X5R dielectric. output capacitance is required, the input capacitor should be The tolerance of the capacitor (TOL) is assumed to be 10%, and increased to match it. C is 0.94 μF at 1.8 V, as shown in Figure 64. BIAS Input and Output Capacitor Properties Substituting these values in Equation 1 yields Any good quality ceramic capacitors can be used with the C = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF EFF ADP7102, as long as they meet the minimum capacitance and Therefore, the capacitor chosen in this example meets the maximum ESR requirements. Ceramic capacitors are manufac- minimum capacitance requirement of the LDO over temperature tured with a variety of dielectrics, each with different behavior and tolerance at the chosen output voltage. over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the To guarantee the performance of the ADP7102, it is imperative necessary temperature range and dc bias conditions. X5R or X7R that the effects of dc bias, temperature, and tolerances on the dielectrics with a voltage rating of 6.3 V to 50 V are recommended. behavior of the capacitors be evaluated for each application. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. Rev. E | Page 18 of 28

Data Sheet ADP7102 PROGRAMABLE UNDERVOLTAGE LOCKOUT (UVLO) VIN = 8V VIN VOUT VOUT = 5V The ADP7102 uses the EN/UVLO pin to enable and disable the CIN + +COUT 1µF 1µF SENSE VOUT pin under normal operating conditions. As shown in R1 RPG Figure 65, when a rising voltage on EN crosses the upper threshold, ON 100kΩ 100kΩ OFF EN/ VOUT turns on. When a falling voltage on EN/UVLO crosses the R2 UVLO 100kΩ PG PG lower threshold, VOUT turns off. The hysteresis of the EN/UVLO GND tinh rseesrhieosl dw iist hd ethteer mENin/e Ud VbyL Oth ep iTnh. evenin equivalent resistance 09506-061 Figure 66. Typical EN Pin Voltage Divider 2.0 1.8 Figure 65 shows the typical hysteresis of the EN/UVLO pin. This prevents on/off oscillations that can occur due to noise 1.6 on the EN pin as it passes through the threshold points. 1.4 The ADP7102 uses an internal soft start to limit the inrush 1.2 current when the output is enabled. The start-up time for the 1.0 VVOOUUTT,, EENN FRAISLEL 3.3 V option is approximately 580 μs from the time the EN active 0.8 threshold is crossed to when the output reaches 90% of its final 0.6 value. As shown in Figure 67, the start-up time is dependent on the output voltage setting. 0.4 0.2 6 01.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 09506-060 5 5V Figure 65. Typical VOUT Response to EN Pin Operation The upper and lower thresholds are user programmable and can 4 be set using two resistors. When the EN/UVLO pin voltage is V) 3.3V below 1.22 V, the LDO is disabled. When the EN/UVLO pin (UT 3 O V voltage transitions above 1.22 V, the LDO is enabled and 10 μA hysteresis current is sourced out of the pin raising the voltage, 2 ENABLE thus providing threshold hysteresis. Typically, two external resistors program the minimum operational voltage for the LDO. 1 The resistance values, R1 and R2 can be determined from: 0 RR21 == 1V.H2Y2S /V10 × μ RA1 /(V − 1.22 V) 0 500 TIM10E0 (0µs) 1500 2000 09506-062 IN Figure 67. Typical Start-Up Behavior where: V is the desired turn on voltage. IN V is the desired EN/UVLO hysteresis level. HYS Hysteresis can also be achieved by connecting a resistor in series with EN/UVLO pin. For the example shown in Figure 66, the enable threshold is 2.44 V with a hysteresis of 1 V. Rev. E | Page 19 of 28

ADP7102 Data Sheet POWER-GOOD FEATURE NOISE REDUCTION OF THE ADJUSTABLE ADP7102 The ADP7102 provides a power-good pin (PG) to indicate the The ultralow output noise of the fixed output ADP7102 is status of the output. This open-drain output requires an external achieved by keeping the LDO error amplifier in unity gain and pull-up resistor to VOUT. If the device is in shutdown mode, setting the reference voltage equal to the output voltage. This current-limit mode, or thermal shutdown, or if it falls below architecture does not work for an adjustable output voltage LDO. 90% of the nominal output voltage, the power-good pin (PG) The adjustable output ADP7102 uses the more conventional immediately transitions low. During soft start, the rising architecture where the reference voltage is fixed and the error threshold of the power-good signal is 93.5% of the nominal amplifier gain is a function of the output voltage. The disadvantage output voltage. of the conventional LDO architecture is that the output voltage noise is proportional to the output voltage. The open-drain output is held low when the ADP7102 has sufficient input voltage to turn on the internal PG transistor. The The adjustable LDO circuit may be modified slightly to reduce PG transistor is terminated via a pull-up resistor to VOUT or VIN. the output voltage noise to levels close to that of the fixed output ADP7102. The circuit shown in Figure 70 adds two additional Power-good accuracy is 93.5% of the nominal regulator output components to the output voltage setting resistor divider. C voltage when this voltage is rising, with a 90% trip point when NR and R are added in parallel with R to reduce the ac gain of this voltage is falling. Regulator input voltage brownouts or glitches NR FB1 the error amplifier. R is chosen to be equal to R ; this limits trigger power no good signals if V falls below 90%. NR FB2 OUT the ac gain of the error amplifier to approximately 6 dB. The actual A normal power-down causes the power-good signal to go low gain is the parallel combination of R and R , divided by R . NR FB1 FB2 when V drops below 90%. OUT This ensures that the error amplifier always operates at greater Figure 68 and Figure 69 show the typical power-good rising and than unity gain. falling threshold over temperature. C is chosen by setting the reactance of C equal to R − R NR NR FB1 NR 6 at a frequency between 50 Hz and 100 Hz. This sets the frequency PG –40°C PG –5°C where the ac gain of the error amplifier is 3 dB down from PG +25°C 5 PG +85°C its dc gain. PG +125°C 4 VIN = 8V VIN VOUT VOUT = 5V G (V) 3 1CµINF + ADJ 40R.2FkBΩ1 +C10N0RnF +C1µOFUT P OFF ON 100kΩ EN/ RFB2 1R3NkRΩ 100kΩ 2 UVLO 13kΩ 100kΩ GND PG PG 1 09506-065 0 Figure 70. Noise Reduction Modification to Adjustable LDO 4.2 4.3 4.4 4.5 VOU4.T6 (V) 4.7 4.8 4.9 5.0 09506-063 The noise of the adjustable LDO can be found by using the Figure 68. Typical Power-Good Threshold vs. Temperature, VOUT Rising following formula, assuming the noise of a fixed output LDO is approximately 15 μV. 6 PG –40°C PG –5°C 5 PPPGGG +++1285525°°CC°C 15μV 1 1 /13kΩ 1/13kΩ1/40.2k     4 Based on the component values shown in Figure 70, the G (V) 3 ADP7102 has the following characteristics: P  DC gain of 4.09 (12.2 dB) 2  3 dB roll off frequency of 59 Hz  High frequency ac gain of 1.76 (4.89 dB) 1  Noise reduction factor of 1.33 (2.59 dB)  RMS noise of the adjustable LDO without noise reduction 0 4.2 4.3 4.4 4.5 VOU4.T6 (V) 4.7 4.8 4.9 5.0 09506-064  oRfM 27S .n8 oμiVse romf sth e adjustable LDO with noise reduction Figure 69. Typical Power-Good Threshold vs. Temperature, VOUT Falling (assuming 15 μV rms for fixed voltage option) of 19.95 μV rms Rev. E | Page 20 of 28

Data Sheet ADP7102 CURRENT LIMIT AND THERMAL OVERLOAD To guarantee reliable operation, the junction temperature of the PROTECTION ADP7102 must not exceed 125°C. To ensure that the junction temperature stays below this maximum value, the user must be The ADP7102 is protected against damage due to excessive aware of the parameters that contribute to junction temperature power dissipation by current and thermal overload protection changes. These parameters include ambient temperature, power circuits. The ADP7102 is designed to current limit when the dissipation in the power device, and thermal resistances between output load reaches 400 mA (typical). When the output load the junction and ambient air (θ ). The θ number is dependent exceeds 400 mA, the output voltage is reduced to maintain a JA JA on the package assembly compounds that are used and the amount constant current limit. of copper used to solder the package GND pins to the PCB. Thermal overload protection is included, which limits the Table 6 shows typical θ values of the 8-lead SOIC and 8-lead junction temperature to a maximum of 150°C (typical). Under JA LFCSP packages for various PCB copper sizes. Table 7 shows extreme conditions (that is, high ambient temperature and/or the typical Ψ values of the 8-lead SOIC and 8-lead LFCSP. high power dissipation) when the junction temperature starts to JB rise above 150°C, the output is turned off, reducing the output Table 6. Typical θJA Values current to zero. When the junction temperature drops below θ (°C/W) JA 135°C, the output is turned on again, and output current is Copper Size (mm2) LFCSP SOIC restored to its operating value. 251 165.1 167.8 Consider the case where a hard short from VOUT to ground 100 125.8 111 occurs. At first, the ADP7102 current limits, so that only 400 mA 500 68.1 65.9 is conducted into the short. If self heating of the junction is 1000 56.4 56.1 great enough to cause its temperature to rise above 150°C, 6400 42.1 45.8 thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and 1 Device soldered to minimum size pin traces. drops below 135°C, the output turns on and conducts 400 mA Table 7. Typical Ψ Values JB into the short, again causing the junction temperature to rise Model Ψ (°C/W) JB above 150°C. This thermal oscillation between 135°C and 150°C LFCSP 15.1 causes a current oscillation between 400 mA and 0 mA that SOIC 31.3 continues as long as the short remains at the output. The junction temperature of the ADP7102 is calculated from Current and thermal limit protections are intended to protect the following equation: the device against accidental overload conditions. For reliable T = T + (P × θ ) (2) operation, device power dissipation must be externally limited J A D JA so the junction temperature does not exceed 125°C. where: T is the ambient temperature. THERMAL CONSIDERATIONS A P is the power dissipation in the die, given by D In applications with low input to output voltage differential, the P = [(V − V ) × I ] + (V × I ) (3) ADP7102 does not dissipate much heat. However, in applications D IN OUT LOAD IN GND with high ambient temperature and/or high input voltage, the where: heat dissipated in the package may become large enough that it ILOAD is the load current. causes the junction temperature of the die to exceed the maximum I is the ground current. GND junction temperature of 125°C. V and V are input and output voltages, respectively. IN OUT When the junction temperature exceeds 150°C, the converter Power dissipation due to ground current is quite small and can enters thermal shutdown. It recovers only after the junction be ignored. Therefore, the junction temperature equation simplifies temperature has decreased below 135°C to prevent any permanent to the following: damage. Therefore, thermal analysis for the chosen application T = T + {[(V − V ) × I ] × θ } (4) J A IN OUT LOAD JA is very important to guarantee reliable performance over all As shown in Equation 4, for a given ambient temperature, input conditions. The junction temperature of the die is the sum of the to output voltage differential, and continuous load current, there ambient temperature of the environment and the temperature rise exists a minimum copper size requirement for the PCB to ensure of the package due to the power dissipation, as shown in that the junction temperature does not rise above 125°C. Figure 71 Equation 2. to Figure 78 show junction temperature calculations for different ambient temperatures, power dissipation, and areas of PCB copper. Rev. E | Page 21 of 28

ADP7102 Data Sheet 145 145 135 135 125 125 C) C) E (° 115 E (° 115 UR 105 UR 105 T T RA 95 RA 95 E E MP 85 MP 85 E E T 75 T 75 N N TIO 65 TIO 65 C C N 55 N 55 U U J 45 6400mm2 J 45 6400mm2 500mm2 500mm2 35 25mm2 35 25mm2 TJMAX TJMAX 25 25 0 0.2 0.4 0.T6OT0A.8L P1O.0WE1R. 2DIS1S.4IPA1T.I6ON1 (.W8)2.0 2.2 2.4 09506-066 0 0.2 0.4 0.T6OT0A.8L P1O.0WE1R. 2DIS1S.4IPA1T.I6ON1 (.W8)2.0 2.2 2.4 09506-069 Figure 71. LFCSP, TA = 25°C Figure 74. SOIC, TA = 25°C 140 140 130 130 C) 120 C) 120 E (° E (° UR 110 UR 100 AT AT ER 100 ER 110 P P M M TE 90 TE 90 N N CTIO 80 CTIO 80 N N U 70 U 70 J 6400mm2 J 6400mm2 60 52050mmmm22 60 52050mmmm22 500 0.2 0.4TOTA0L.6 POW0E.8R DIS1S.0IPATI1O.2N (W)1.4 TJ1M.6AX 1.8 09506-067 500 0.2 0.4TOTA0L.6 POW0E.8R DIS1S.0IPATI1O.2N (W)1.4 TJ1M.6AX 1.8 09506-070 Figure 72. LFCSP, TA = 50°C Figure 75. SOIC, TA = 50°C 145 145 135 135 C) C) RE (° 125 RE (° 125 ATU 115 ATU 115 R R MPE 105 MPE 105 ON TE 95 ON TE 95 CTI CTI UN 85 UN 85 J 6400mm2 J 6400mm2 75 500mm2 75 500mm2 25mm2 25mm2 650 0.1 0.2TO0T.A3L P0O.W4ER0 D.5ISSIP0.A6TION0. 7(W)0.8TJM0.A9X 1.0 09506-068 650 0.1 0.2TO0T.A3L P0O.4WER0 D.5ISSI0P.A6TION0. 7(W)0.8TJ0M.9AX 1.0 09506-071 Figure 73. LFCSP, TA = 85°C Figure 76. SOIC, TA = 85°C Rev. E | Page 22 of 28

Data Sheet ADP7102 140 In the case where the board temperature is known, use the thermal characterization parameter, ΨJB, to estimate the junction 120 temperature rise (see Figure 77 and Figure 78). Maximum junction T)J temperature (T) is calculated from the board temperature (T ) and E ( 100 J B R U power dissipation (P ) using the following formula: T D A R 80 E T = T + (P × Ψ ) (5) P J B D JB M TE 60 The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP N O package and 31.3°C/W for the 8-lead SOIC package. TI C 40 N 140 JU TB = 25°C TB = 50°C 20 TB = 65°C 120 TB = 85°C TJMAX URE (T)J 100 00 0.5 TO1.T0AL POW1.5ER DISS2.I0PATION2 (.W5) 3.0 3.5 09506-073 AT Figure 78. SOIC R 80 E P M E T 60 N O TI C 40 N JU TB = 25°C TB = 50°C 20 TB = 65°C TB = 85°C TJMAX 00 0.5 1.0 1.5TO2.T0AL2 .P5O3W.0ER3 D.5IS4S.I0PA4T.I5ON5 .(0W)5.5 6.0 6.5 7.0 09506-072 Figure 77. LFCSP Rev. E | Page 23 of 28

ADP7102 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP7102. However, as listed in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Use of 0805 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. 09506-075 Figure 80. Example SOIC PCB Layout 09506-074 Figure 79. Example LFCSP PCB Layout Rev. E | Page 24 of 28

Data Sheet ADP7102 OUTLINE DIMENSIONS 3.10 2.48 3.00 SQ 2.38 2.90 2.23 5 8 EXPOSED 1.74 PAD 1.64 0.50 1.49 0.40 IANRDEEXA 0.30 4 1 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR 0.80 0.80 MAX (R 0.2) 0.55 NOM 0.75 FOR PROPER CONNECTION OF 0.70 0.05 MAX THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS 0.08 SECTION OF THIS DATA SHEET. SEPALTAINNGE 0.30 0.50 BSC 0.20 REF 0.25 0.18 COMPLIANTTOJEDEC STANDARDS MO-229-WEED-4 02-05-2013-B Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-5) Dimensions shown in millimeters 5.00 3.098 4.90 4.80 0.356 8 5 6.20 4.00 6.00 3.90 5.80 2.41 3.80 0.457 1 4 FOR PROPER CONNECTION OF 1.27 BSC BOTTOM VIEW THE EXPOSED PAD, REFER TO 3.81 REF THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW SECTION OF THIS DATA SHEET. 1.75 1.65 0.50 45° 1.35 1.25 0.25 0.25 0.17 0.10 MAX SEATING PLANE 0.51 0.05 NOM 8° 1.04 REF 0.31 COPL0A.1N0ARITY 0° 10..2470 COMPLIANTTO JEDEC STANDARDS MS-012-AA 06-03-2011-B Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-2) Dimensions shown in millimeters Rev. E | Page 25 of 28

ADP7102 Data Sheet ORDERING GUIDE Temperature Output Package Package Model1 Range Voltage (V)2, 3 Description Option Branding ADP7102ACPZ-R7 −40°C to +125°C Adjustable 8-Lead LFCSP_WD CP-8-5 LHO ADP7102ACPZ-1.5-R7 −40°C to +125°C 1.5 8-Lead LFCSP_WD CP-8-5 LJV ADP7102ACPZ-1.8-R7 −40°C to +125°C 1.8 8-Lead LFCSP_WD CP-8-5 LJW ADP7102ACPZ-2.5-R7 −40°C to +125°C 2.5 8-Lead LFCSP_WD CP-8-5 LJZ ADP7102ACPZ-3.0-R7 −40°C to +125°C 3.0 8-Lead LFCSP_WD CP-8-5 LKO ADP7102ACPZ-3.3-R7 −40°C to +125°C 3.3 8-Lead LFCSP_WD CP-8-5 LK1 ADP7102ACPZ-5.0-R7 −40°C to +125°C 5 8-Lead LFCSP_WD CP-8-5 LK2 ADP7102ACPZ-9.0-R7 −40°C to +125°C 9 8-Lead LFCSP_WD CP-8-5 LLC ADP7102ARDZ-R7 −40°C to +125°C Adjustable 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-1.5-R7 −40°C to +125°C 1.5 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-1.8-R7 −40°C to +125°C 1.8 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-2.5-R7 −40°C to +125°C 2.5 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-3.0-R7 −40°C to +125°C 3.0 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-3.3-R7 −40°C to +125°C 3.3 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-5.0-R7 −40°C to +125°C 5 8-Lead SOIC_N_EP RD-8-2 ADP7102ARDZ-9.0-R7 −40°C to +125°C 9 8-Lead SOIC_N_EP RD-8-2 ADP7102CP-EVALZ 3.3 LFCSP Evaluation Board ADP7102RD-EVALZ 3.3 SOIC Evaluation Board ADP7102CPZ-REDYKIT LFCSP REDYKIT ADP7102RDZ-REDYKIT SOIC REDYKIT 1 Z = RoHS Compliant Part. 2 For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative. 3 The ADP7102CP-EVALZ and ADP7102RD-EVALZ evaluation boards are preconfigured with a 3.3 V ADP7102 Rev. E | Page 26 of 28

Data Sheet ADP7102 NOTES Rev. E | Page 27 of 28

ADP7102 Data Sheet NOTES ©2011–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09506-0-9/15(E) Rev. E | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADP7102ARDZ-3.0-R7 ADP7102ACPZ-3.3-R7 ADP7102ACPZ-R7 ADP7102ARDZ-R7 ADP7102ARDZ-1.5-R7 ADP7102ACPZ-9.0-R7 ADP7102ARDZ-9.0-R7 ADP7102ARDZ-3.3-R7 ADP7102ACPZ-1.8-R7 ADP7102ACPZ-3.0- R7 ADP7102ARDZ-5.0-R7 ADP7102ARDZ-2.5-R7 ADP7102ARDZ-1.8-R7 ADP7102ACPZ-1.5-R7 ADP7102ACPZ- 5.0-R7 ADP7102ACPZ-2.5-R7