Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs Data Sheet ADP5033 FEATURES TYPICAL APPLICATION CIRCUIT Main input voltage range: 2.3 V to 5.5 V ADP5033 TTwinoy ,8 1060- bmaAll ,b 2u mckm re ×g 2u lmatmor Ws aLnCdSP t wpoac 3k0a0g me A LDOs 25T..O35VV 4.7CµF1 VIN1 BUCK1 SVOWU1T1L1 1µH C5V80O0@UmTA1 Regulator accuracy: ±1.8% D EN1 PGND1 10µF Factory programmable VOUTx ENA ANO MODE 3 MmHozd beus ck operation with forced PWM and auto PWM/PSM OFFON ENB ACTIV. UVL EEENNN234 MODE PWMPSM/PWM BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V C2 VIN2 MODE SW2 L2 1µH VOUT2 LDO1/LDO2: output voltage range from 0.8 V to 5.2 V 4.7µF @ BUCK2 VOUT2 800mA LDO1/LDO2: low input supply voltage from 1.7 V to 5.5 V C6 EN2 PGND2 10µF LDO1/LDO2: high PSRR and low output noise APPLICATIONS 1T.7OV VIN3 EN3LDO1 VOUT3 VO@UT3 5.5V C3 (ANALOG) 300mA Power for processors, ASICS, FPGAs, and RF chipsets 1µF C7 1µF Portable instrumentation and medical devices VIN4 EN4 VOUT4 VOUT4 LDO2 @ Space constrained devices C4 (DIGITAL) 300mA 1µF AGND C1µ8F 09788-001 Figure 1. GENERAL DESCRIPTION The ADP5033 combines two high performance buck regulators The regulators in the ADP5033 are activated by the ENA and ENB and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm × pins. The specific channels controlled by ENA and ENB are set 2 mm WLCSP to meet demanding performance and board space by factory programming. A high voltage level applied to the enable requirements. pins activates the regulators. The default output voltages are factory programmable and can be set to a wide range of options. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. Table 1. Family Models When the MODE pin is set high, the buck regulators operate in Maximum forced PWM mode. When the MODE pin is set low, the buck Model Channels Current Package regulators operate in PWM mode when the load current is above ADP5023 2 Bucks, 1 LDO 800 mA, 300 mA LFCSP (CP-24-10) a predefined threshold. When the load current falls below a ADP5024 2 Bucks, 1 LDO 1.2 A, 300 mA LFCSP (CP-24-10) predefined threshold, the regulator operates in power save ADP5034 2 Bucks, 2 LDOs 1.2 A, 300 mA LFCSP (CP-24-10), TSSOP (RE-28-1) mode (PSM), improving the light load efficiency. ADP5037 2 Bucks, 2 LDOs 800 mA, 300 mA LFCSP (CP-24-10) The two bucks operate out of phase to reduce the input capacitor ADP5033 2 Bucks, 2 LDOs with 800 mA, 300 mA WLCSP (CB-16-8) requirement and noise. 2 EN pins ADP5040 1 Buck, 2 LDOs 1.2 A, 300 mA LFCSP (CP-20-10) The low quiescent current, low dropout voltage, and wide input ADP5041 1 Buck, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-20-10) voltage range of the ADP5033 LDO extend the battery life of Supervisory, Watchdog, portable devices. The ADP5033 LDOs maintain power supply Manual Reset ADP5133 2 Bucks with 2 ENx pins 800 mA WLCSP (CB-16-8) rejection greater than 60 dB for frequencies as high as 10 kHz ADP5134 2 Bucks, 2 LDOs with 1.2 A, 300 mA LFCSP (CP-24-10) while operating with a low headroom voltage. precision enable and power-good output Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADP5033 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Power Management Unit ........................................................... 15 Typical Application Circuit ............................................................. 1 BUCK1 and BUCK2 .................................................................. 16 General Description ......................................................................... 1 LDO1 and LDO2 ........................................................................ 17 Revision History ............................................................................... 2 Applications Information .............................................................. 18 Specifications ..................................................................................... 3 Buck External Component Selection ....................................... 18 General Specifications ................................................................. 3 LDO Capacitor Selection .......................................................... 20 BUCK1 and BUCK2 Specifications ........................................... 4 Power Dissipation and Thermal Considerations ....................... 21 LDO1 and LDO2 Specifications ................................................. 4 Buck Regulator Power Dissipation .......................................... 21 Input and Output Capacitor, Recommended Specifications ........ 5 Junction Temperature ................................................................ 22 Absolute Maximum Ratings ............................................................ 6 PCB Layout Guidelines .................................................................. 23 Thermal Resistance ...................................................................... 6 Typical Application Schematic ..................................................... 24 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 25 Pin Configuration and Function Descriptions ............................. 7 Ordering Guide .......................................................................... 26 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 3/2019—Rev. G to Rev. H Changes to Figure 36 Caption ...................................................... 13 Changes to Ordering Guide .......................................................... 26 Changes to Undervoltage Lockout Section ................................. 16 Moved Power Dissipation and Thermal Considerations Section .... 21 9/2014—Rev. F to Rev. G Changes to Buck Regulator Power Dissipation Section ............ 21 Changes to Page Layout ................................................................... 1 Updated Outline Dimensions ....................................................... 25 Changes to Table 1 ............................................................................ 1 Changes to Ordering Guide .......................................................... 25 Changes to Ordering Guide .......................................................... 26 1/2012—Rev. 0 to Rev. A 10/2013—Rev. E to Rev. F Changes to Features Section and General Description Section .... 1 Changes to VIN1 Undervoltage Lockout Parameter, Table 2 ..... 3 Changes to Output Characteristics Parameter, Table 2 ................ 4 Changes to Undervoltage Lockout Section ................................. 16 Changes to Output Characteristics Parameter, Table 3 and Moved Ordering Guide .................................................................. 26 Dropout Voltage Parameter, Table 3 ............................................... 4 Changes to Ordering Guide .......................................................... 26 Changes to Nominal Input and Output Capacitor Ratings Parameter, Table 4 ............................................................................. 5 9/2013—Rev. D to Rev. E Changes to Table 5 ............................................................................. 6 Changes to Table 1 ............................................................................ 1 Changed V = V = V = V = 5.0 V to V = V = V = IN1 IN2 IN3 IN4 IN1 IN2 IN3 Changes to Ordering Guide .......................................................... 25 V = 3.6 V .........................................................................................8 IN4 Changes to Figure 4 to Figure 8 ....................................................... 8 5/2013—Rev. C to Rev. D Change to Figure 15 Caption and Figure 17 Caption ................ 10 Added Table 1; Renumbered Sequentially .................................... 1 Changes Figure 19 and Figure 20 ................................................. 10 Changes to Ordering Guide .......................................................... 25 Changes to Figure 31 and Figure 32 ............................................ 12 Changes to Figure 33, Figure 37, and Figure 38 ......................... 13 1/2013—Rev. B to Rev. C Changes to Buck Regulator Power Dissipation Section ............ 15 Changes to Figure 9 .......................................................................... 9 Changes to LDO Regulator Power Dissipation Section and Changes to Ordering Guide .......................................................... 25 Junction Temperature Section ...................................................... 16 Changes to Undervoltage Lockout Section ................................. 18 10/2012—Rev. A to Rev. B Changes to LDO1 and LDO2 Section ......................................... 19 Changes to Features Section............................................................ 1 Changes to Output Capacitor Section ......................................... 20 Changes to Buck Output Voltage Accuracy Parameter, Table 2 ....... 4 Changes to Table 9 .......................................................................... 21 Changes to LDO Output Voltage Accuracy Parameter, Table 3 ....... 4 Change to Input and Output Capacitor Properties Section ..... 22 Changes to Figure 6 to Figure 8 ...................................................... 8 Changes to Ordering Guide .......................................................... 25 Changes to Figure 30 to Figure 32 ................................................ 12 5/2011—Revision 0: Initial Version Rev. H | Page 2 of 28

Data Sheet ADP5033 SPECIFICATIONS GENERAL SPECIFICATIONS V = V = V = V = 2.3 V to 5.5 V; V = V = 1.7 V to 5.5 V; T = −40°C to +125°C for minimum/maximum specifications, and IN1 IN2 IN3 IN4 IN3 IN4 J T = 25°C for typical specifications, unless otherwise noted. A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V , V 2.3 5.5 V IN1 IN2 THERMAL SHUTDOWN Threshold TS T rising 150 °C SD J Hysteresis TS 20 °C SD-HYS START-UP TIME1 BUCK1, LDO1, LDO2 t 250 µs START1 BUCK2 t 300 µs START2 ENA, ENB, MODE INPUTS Input Logic High V 1.1 V IH Input Logic Low V 0.4 V IL Input Leakage Current V 0.05 1 µA I-LEAKAGE STANDBY CURRENT All Channels Enabled I No load, no buck switching 108 175 µA STBY-NOSW All Channels Disabled I T = −40°C to +85°C 0.3 1 µA SHUTDOWN J VIN1 UNDERVOLTAGE LOCKOUT Low UVLO Input Voltage Rising UVLO 2.275 V VIN1RISE Low UVLO Input Voltage Falling UVLO 1.95 V VIN1FALL 1 Start-up time is defined as the time from VIN1 > UVLOVIN1RISE to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal levels. Rev. H | Page 3 of 28

ADP5033 Data Sheet BUCK1 AND BUCK2 SPECIFICATIONS V = V = 2.3 V to 5.5 V; T = −40°C to +125°C for minimum/maximum specifications, and T = 25°C for typical specifications, unless IN1 IN2 J A otherwise noted.1 Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Input Voltage Range V , V PWM mode, I = I = 0 mA to 800 mA 2.3 5.5 V IN1 IN2 LOAD1 LOAD2 OUTPUT CHARACTERISTICS Output Voltage Accuracy ∆V /V , ∆V /V PWM mode; I = I = 0 mA −1.8 +1.8 % OUT1 OUT1 OUT2 OUT2 LOAD1 LOAD2 Line Regulation (∆V /V )/∆V , PWM mode −0.05 %/V OUT1 OUT1 IN1 (∆V /V )/∆V OUT2 OUT2 IN2 Load Regulation (∆V /V )/∆I , I = 0 mA to 800 mA, PWM mode −0.1 %/A OUT1 OUT1 OUT1 LOAD (∆V /V )/∆I OUT2 OUT2 OUT2 PSM CURRENT THRESHOLD PSM to PWM Operation I 100 mA PSM OPERATING SUPPLY CURRENT MODE = ground BUCK1 Only I I = 0 mA, device not switching, all 44 μA IN LOAD1 other channels disabled BUCK2 Only I I = 0 mA, device not switching, all 55 μA IN LOAD2 other channels disabled BUCK1 and BUCK2 I I = I = 0 mA, device not switching, 67 μA IN LOAD1 LOAD2 LDO channels disabled SW CHARACTERISTICS SW On Resistance R PFET at VIN1 = 5 V 145 235 mΩ PFET R PFET at VIN1 = 3.6 V 180 295 mΩ PFET R NFET at VIN1 = 5 V 110 190 mΩ NFET R NFET at VIN1 = 3.6 V 125 220 mΩ NFET Current Limit I , I PFET switch peak current limit 1100 1350 mA LIMIT1 LIMIT2 ACTIVE PULL-DOWN R Channel disabled 75 Ω PDWN-B OSCILLATOR FREQUENCY f 2.5 3.0 3.5 MHz SW 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO1 AND LDO2 SPECIFICATIONS V = (V + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, V = (V + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; C = C = IN3 OUT3 IN4 OUT4 IN OUT 1 µF; T = −40°C to +125°C for minimum/maximum specifications, and T = 25°C for typical specifications, unless otherwise noted.1 J A Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V , V 1.7 5.5 V IN3 IN4 OPERATING SUPPLY CURRENT Bias Current per LDO2 I /I I = I = 0 µA 10 30 µA VIN3BIAS VIN4BIAS OUT3 OUT4 I = I = 10 mA 60 100 µA OUT3 OUT4 I = I = 300 mA 165 245 µA OUT3 OUT4 Total System Input Current I Includes all current into VIN1, VIN2, VIN3, and VIN4 IN LDO1 or LDO2 Only I = I = 0 µA, all other channels disabled 53 µA OUT3 OUT4 LDO1 and LDO2 Only I = I = 0 µA, buck channels disabled 74 µA OUT3 OUT4 OUTPUT CHARACTERISTICS Output Voltage Accuracy ∆V /V , 100 µA < I < 300 mA, 100 µA < I < 300 mA −1.8 +1.8 % OUT3 OUT3 OUT3 OUT4 ∆V /V OUT4 OUT4 Line Regulation (∆V /V )/∆V , I = I = 1 mA −0.03 +0.03 %/V OUT3 OUT3 IN3 OUT3 OUT4 (∆V /V )/∆V OUT4 OUT4 IN4 Load Regulation3 (∆V /V )/∆I , I = I = 1 mA to 300 mA 0.001 0.003 %/mA OUT3 OUT3 OUT3 OUT3 OUT4 (∆V /V )/∆I OUT4 OUT4 OUT4 Rev. H | Page 4 of 28

Data Sheet ADP5033 Parameter Symbol Test Conditions/Comments Min Typ Max Unit DROPOUT VOLTAGE4 V V = V = 5.2 V, I = I = 300 mA 50 mV DROPOUT OUT3 OUT4 OUT3 OUT4 V = V = 3.3 V, I = I = 300 mA 65 110 mV OUT3 OUT4 OUT3 OUT4 V = V = 2.5 V, I = I = 300 mA 85 mV OUT3 OUT4 OUT3 OUT4 V = V = 1.8 V, I = I = 300 mA 165 mV OUT3 OUT4 OUT3 OUT4 CURRENT-LIMIT THRESHOLD5 I , I 335 600 mA LIMIT3 LIMIT4 ACTIVE PULL-DOWN R Channel disabled 600 Ω PDWN-L POWER SUPPLY REJECTION RATIO PSRR Regulator LDO1 10 kHz, V = 3.3 V, V = 2.8 V, I = 1 mA 60 dB IN3 OUT3 OUT3 100 kHz, V = 3.3 V, V = 2.8 V, I = 1 mA 62 dB IN3 OUT3 OUT3 1 MHz, V = 3.3 V, V = 2.8 V, I = 1 mA 63 dB IN3 OUT3 OUT3 Regulator LDO2 10 kHz, V = 1.8 V, V = 1.2 V, I = 1 mA 54 dB IN4 OUT4 OUT4 100 kHz, V = 1.8 V, V = 1.2 V, I = 1 mA 57 dB IN4 OUT4 OUT4 1 MHz, V = 1.8 V, V = 1.2 V, I = 1 mA 64 dB IN4 OUT4 OUT4 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 This is the input current into VIN3/VIN4, which is not delivered to the output load. 3 Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS T = −40°C to +125°C, unless otherwise specified. A Table 5. Parameter Symbol Min Typ Max Unit NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2 Input Capacitor Rating C , C 4.7 40 µF MIN1 MIN2 BUCK1, BUCK2 Output Capacitor Rating C , C 10 40 µF MIN1 MIN2 LDO1, LDO21 Input and Output Capacitor Rating C , C 1.0 µF MIN3 MIN4 CAPACITOR ESR R 0.001 1 Ω ESR 1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics. Rev. H | Page 5 of 28

ADP5033 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Rating θ and Ψ are specified for the worst-case conditions, that is, a JA JB VIN1 to AGND −0.3 V to +6 V device soldered in a circuit board for surface-mount packages. VIN2 to VIN1 −0.3 V to +0.3 V Table 7. Thermal Resistance PGND1, PGND2 to AGND −0.3 V to +0.3 V Package Type θ Ψ Unit VIN3, VIN4, VOUT1, VOUT2, ENA, ENB, −0.3 V to JA JB MODE to AGND (VIN1 + 0.3 V) 16-Ball, 0.5 mm Pitch WLCSP 57 14 °C/W VOUT3 to AGND −0.3 V to (VIN3 + 0.3 V) ESD CAUTION VOUT4 to AGND −0.3 V to (VIN4 + 0.3 V) SW1 to PGND1 −0.3 V to (VIN1 + 0.3 V) SW2 to PGND2 −0.3 V to (VIN2 + 0.3 V) Storage Temperature Range −65°C to +150°C Operating Junction Temperature Range −40°C to +125°C Soldering Conditions JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. For detailed information on power dissipation, see the Power Dissipation and Thermal Considerations section. Rev. H | Page 6 of 28

Data Sheet ADP5033 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 3 4 VOUT3 VIN3 VIN4 VOUT4 A AGND MODE ENA ENB B VIN1 VOUT1VOUT2 VIN2 C PGND1 SW1 SW2 PGND2 D (BALNTLoO tS PtIoD V ESIE cDaWOleWN) 09788-002 Figure 2. Pin Configuration—View from the Top of the Die Table 8. Pin Function Descriptions Pin No. Mnemonic Description A1 VOUT3 LDO1 Output Voltage and Sensing Input. A2 VIN3 LDO1 Input Supply (1.7 V to 5.5 V, VIN4 ≤ VIN1 = VIN2). A3 VIN4 LDO2 Input Supply (1.7 V to 5.5 V, VIN3 ≤ VIN1 = VIN2). A3 VOUT4 LDO2 Output Voltage and Sensing Input. B1 AGND Analog Ground. B2 MODE BUCK1/BUCK2 Operating Mode. MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation. B3 ENA Regulator Enable Pin A, Active High. The regulators turned on with ENA are factory programmed. B4 ENB Regulator Enable Pin B, Active High. The regulators turned on with ENB are factory programmed. C1 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V) and UVLO Detection. Connect VIN1 to VIN2. C2 VOUT1 BUCK1 Output Voltage Sensing Input. C3 VOUT2 BUCK2 Output Voltage Sensing Input. C4 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1. D1 PGND1 Dedicated Power Ground for BUCK1. D2 SW1 BUCK1 Switching Node. D3 SW2 BUCK2 Switching Node. D4 PGND2 Dedicated Power Ground for BUCK2. Rev. H | Page 7 of 28

ADP5033 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = V = V = V = 3.6 V, T = 25°C, unless otherwise noted. IN1 IN2 IN3 IN4 A 3.310 140 3.305 –40°C 120 A) 3.300 µ NT ( 100 3.295 +25°C E NT CURR 80 V (V)OUT 3.290 E 60 3.285 C S E +85°C UI 40 3.280 Q 20 3.275 0 3.270 2.3 2.8 3.3INPUT 3V.O8LTAGE4 (.V3) 4.8 5.3 09788-139 0 0.1 0.2 0.3 IOU0T.4 (A) 0.5 0.6 0.7 0.8 09788-225 Figure 3. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V, Figure 6. BUCK1 Load Regulation Across Temperature, VIN = 4.2 V, VOUT2 = 1.8 V, VOUT3 = 1.2 V, VOUT4 = 3.3 V, All Channels Unloaded VOUT1 = 3.3 V, PWM Mode 1.812 T 1.810 SW –40°C 4 1.808 IOUT 2 +25°C V) 1.806 (UT O VOUT V 1.804 1 EN 1.802 +85°C 3 1.800 CCHH3125..0000VV BBWW CCHH4255.00.00VmAΩBBWW MT4101..02µ0s% ACH3 2.2V 09788-249 1.7980 0.1 0.2 0.3 IOU0T.4 (A) 0.5 0.6 0.7 0.8 09788-224 Figure 4. Buck1 Startup, VOUT1 = 1.8 V, IOUT1 = 5 mA Figure 7. BUCK2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT2 = 1.8 V, PWM Mode 0.808 T 0.807 SW 4 +25°C IOUT 0.806 2 –40°C V) (UT 0.805 O VOUT V 1 0.804 +85°C EN 0.803 3 0.802 CCHH31 25..0000VV BBWW CCHH42 55.00.00VmA Ω BBWW MT 4101..02µ0s% A CH3 2.2V 09788-248 0 0.1 0.2 0.3 IOU0T.4 (A) 0.5 0.6 0.7 0.8 09788-226 Figure 5. BUCK2 Startup, VOUT2 = 3.3 V, IOUT2 = 10 mA Figure 8. BUCK1 Load Regulation Across Temperature, VIN = 3.6 V, VOUT1 = 0.8 V, PWM Mode Rev. H | Page 8 of 28

Data Sheet ADP5033 100 100 90 90 80 80 70 70 %) %) Y ( 60 Y ( 60 C C EN 50 EN 50 CI CI FI 40 FI 40 F F E E 30 30 20 20 VIN = 2.4V VIN = 3.9V VIN = 3.6V 10 VIN = 4.2V 10 VIN = 4.5V 01 10 ILOAD (mA) 100 VIN = 5.51V000 09788-038 00.001 0.01 IOUT (A) 0.1 VIN = 5.5V1 09788-035 Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage, Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Auto Mode VOUT2 = 1.8 V, PWM Mode 100 100 90 90 80 80 70 70 %) %) EFFICIENCY ( 654000 EFFICIENCY ( 654000 30 30 20 20 VIN = 2.3V VIN = 3.9V VIN = 3.6V 10 VIN = 4.2V 10 VIN = 4.2V 00.001 0.01 IOUT (A) 0.1 VIN = 5.5V1 09788-039 00.001 0.01 IOUT (A) 0.1 VIN = 5.5V1 09788-034 Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage, Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode VOUT1 = 0.8 V, Auto Mode 100 100 90 90 80 80 70 70 EFFICIENCY (%) 654000 EFFICIENCY (%) 654000 30 30 20 VIN = 2.3V 20 VIN = 2.3V VIN = 3.6V VIN = 3.6V 10 VIN = 4.2V 10 VIN = 4.2V 00.001 0.01 IOUT (A) 0.1 VIN = 5.5V1 09788-036 00.001 0.01 IOUT (A) 0.1 VIN = 5.5V1 09788-065 Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage, Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, Auto Mode VOUT1 = 0.8 V, PWM Mode Rev. H | Page 9 of 28

ADP5033 Data Sheet 100 3.3 90 3.2 80 3.1 CIENCY (%) 765000 UENCY (MHz)32..09 EFFI 40 REQ2.8 F 30 2.7 20 +25°C 2.6 TA= +25°C 10 +85°C TA= –40°C 00.001 0.01 IOUT (A) 0.1 –40°C1 09788-062 2.50 0.2 0.4 IOU0T.6 (A) 0.8 T1A.0= +85°C1.2 09788-040 Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature, Figure 18. BUCK2 Switching Frequency vs. Output Current, Across VIN1 = 3.9 V, VOUT1 = 3.3 V, Auto Mode Temperature, VOUT2 = 1.8 V, PWM Mode 100 T 90 VOUT 80 1 70 %) ISW Y ( 60 C EN 50 2 CI FI 40 F SW E 30 20 +85°C 10 +25°C 4 –40°C 0 0.001 0.01 IOUT (A) 0.1 1 09788-063 CH1 50.0mV CCHH42 520.000mVA Ω MT 42.80.04µ0s% A CH2 240mA 09788-251 Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature, Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode VOUT2 = 1.8 V, Auto Mode 100 T 90 VOUT 80 1 70 %) Y ( 60 ISW C EN 50 2 CI FI 40 F E 30 SW 20 +85°C 10 +25°C 4 –40°C 00.001 0.01 IOUT (A) 0.1 1 09788-200 CH1 50.0mV BWCCHH42 520.000mVA Ω BW MT 42.80.04µ0s%A CH2 220mA 09788-250 Figure 17. BUCK1 Efficiency vs. Load Current, Across Temperature, Figure 20. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Auto Mode VOUT1 = 0.8 V, Auto Mode Rev. H | Page 10 of 28

Data Sheet ADP5033 T T VOUT 1 VIN ISW VOUT 2 1 SW SW 43 4 CH1 50mV CCHH42 520.000mVA Ω MT 42080.4n0s% A CH2 220mA 09788-027 CCHH13 510.0.00mVV CH4 2.00V MT 13.00.04m0%s A CH3 4.80V 09788-013 Figure 21. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode Figure 24. BUCK2 Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT2 = 1.8 V, PWM Mode T T VOUT SW 1 4 ISW 2 VOUT 1 SW IOUT 4 2 CH1 50mV CCHH42 520.000mVA Ω MT 42080.4n0s% A CH2 220mA 09788-026 CH1 50.0mV CCHH42 55.00.00VmA Ω MT 2600..00µ0s0µsA CH2 356mA 09788-016 Figure 22. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode Figure 25. BUCK1 Response to Load Transient, IOUT1 from 1 mA to 50 mA, VOUT1 = 3.3 V, Auto Mode T T SW VIN 4 VOUT VOUT 1 1 SW IOUT 3 2 CCHH13 510.0.00mVV CH4 2.00V MT 13.00.04m0%s A CH3 4.80V 09788-012 CH1 50.0mV CCHH42 55.00.00VmA Ω MT 2202..02µ0s%A CH2 379mA 09788-015 Figure 23. Buck1 Response to Line Transient, Input Voltage from 4.5 V to Figure 26. BUCK2 Response to Load Transient, IOUT2 from 1 mA to 50 mA, 5.0 V, VOUT1 = 3.3 V, PWM Mode VOUT2 = 1.8 V, Auto Mode Rev. H | Page 11 of 28

ADP5033 Data Sheet T SW EN 4 2 VOUT 1 VOUT IOUT 3 2 IIN 1 CH1 50.0mV CCHH42 52.0000mVA Ω MT 2200..04µ0s%A CH2 408mA 09788-017 CCHH31 11.0000mVA CH2 5.00V MT 4105.90.µ4s00µsA CH2 4.20V 09788-022 Figure 27. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA, Figure 30. LDO Startup, VOUT3 = 1.8 V VOUT1 = 3.3 V, Auto Mode 3.304 T 3.303 SW 3.302 4 3.301 VIN = 5.5V 3.300 1 VOUT (V)UT 3.299 VIN = 4.2V O V 3.298 VIN = 3.8V IOUT 3.297 3.296 2 3.295 3.294 CH1 100mV CCHH42 250.000mVA Ω MT 2109..02µ0s%A CH2 88.0mA 09788-018 0 0.1 IOUT (A) 0.2 0.3 09788-232 Figure 28. BUCK2 Response to Load Transient, IOUT2 from 20 mA to 180 mA, Figure 31. LDO Load Regulation Across Input Voltage, VOUT3 = 3.3 V VOUT2 = 1.8 V, Auto Mode 1.802 T 1.801 VOUT2 –40°C 1.800 2 SW1 1.799 1.798 V) 3 (UT 1.797 +25°C O V VOUT1 1.796 1.795 1 SW2 1.794 +85°C 1.793 4 1.792 CCHH31 55..0000VV CCHH42 55..0000VV MT 45000.0n0s% A CH4 1.90V 09788-066 0 0.1 IOUT (A) 0.2 0.3 09788-233 Figure 29. VOUT and SW Waveforms for BUCK1 and BUCK2 in PWM Mode Figure 32. LDO Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 1.8 V Showing Out-of-Phase Operation Rev. H | Page 12 of 28

Data Sheet ADP5033 3.0 IOUT = 10mA IOUT = 100µA T 2.5 IOUT = 1mA IOUT = 100mA IOUT = 150mA VIN 2.0 IOUT = 300mA V) (UT 1.5 VO VOUT 21 1.0 0.5 3 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.V8IN4 (.0V)4.2 4.4 4.6 4.8 5.0 5.2 5.4 09788-234 CCHH13 210.0.00mVV MT 12080.4µ0s% A CH3 4.80V 09788-014 Figure 33. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V Figure 36. LDO Response to Line Transient, Input Voltage from 4.5 V to 5 V, VOUT3 = 2.8 V 50 60 VIN = 5V 45 55 40 VIN = 3.3V µA) 35 50 RENT ( 30 E (µV) 45 R S OUND CU 2205 RMS NOI 40 GR 15 35 10 30 5 0 25 0 0.05 0.L10OAD CU0R.1R5ENT (A)0.20 0.25 09788-136 0.001 0.01 0.1 ILOAD1 (mA) 10 100 09788-255 Figure 34. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V Figure 37. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 2.8 V 65 T 60 VIN = 5V IOUT 55 VIN = 3.3V 2 µV) 50 E ( S OI 45 N 1 VOUT S M 40 R 35 30 25 CH1 100mV CH2 100mA Ω MT 4109..02µ0s%A CH2 52.0mA 09788-019 0.001 0.01 0.1 ILOAD1 (mA) 10 100 09788-256 Figure 35. LDO Response to Load Transient, IOUT3 from 1 mA to 80 mA, Figure 38. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 2.8 V VOUT3 = 3.0 V Rev. H | Page 13 of 28

ADP5033 Data Sheet 0 0 100µA 100µA –10 1mA 1mA 10mA –20 10mA –20 50mA 50mA 100mA 100mA –30 150mA –40 150mA B) –40 B) d d R ( –50 R ( –60 R R S S P –60 P –80 –70 –80 –100 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09788-050 –12010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09788-053 Figure 39. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V Figure 41. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2.8 V 0 0 100µA –10 1mA –20 10mA –20 50mA 100mA –30 –40 150mA B) B) –40 d d R ( –60 R ( –50 R R S S P P –60 –80 100µA –70 1mA 10mA –80 –100 50mA 100mA –90 150mA –12010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09788-051 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09788-052 Figure 40. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V Figure 42. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V Rev. H | Page 14 of 28

Data Sheet ADP5033 THEORY OF OPERATION VOUT1 VOUT2 ENBK1 75Ω 75Ω ENBK2 GM ERROR GM ERROR ADP5033 VDDA AMP AMP PWM PWM COMP COMP VIN1 SOFT START SOFT START VIN2 ILIMIT ILIMIT PSM PSM COMP COMP PWM/ PWM/ PSM PSM LOW CONTROL CONTROL LOW CURRENT BUCK1 BUCK2 CURRENT SW1 SW2 OSCILLATOR DRIVER AND DRIVER ANTISHOOT ANTAISNHDOOT SYSTEM THROUGH THROUGH UNDLEORCVKOOLUTTAGE OPMODE PGND2 PGND1 STHHUETRDMOAWLN SELYBMODE2 ENLDO1 600Ω A MODE LDO LDO UNDERVOLTAGE UNDERVOLTAGE LOCK OUT LOCK OUT ENA ENBK1 R1 R3 ENABLE ENBK2 AND MODE CONTROL ENLDO1 LDO LDO CONTROL CONTROL ENB ENLDO2 VDDA VDDA R2 600Ω ENLDO1 R4 VIN3 AGND VOUT3 VIN4 VOUT4 09788-003 Figure 43. Functional Block Diagram POWER MANAGEMENT UNIT The auto PWM/PSM mode transition is controlled independently for each buck regulator. The two bucks operate synchronized to The ADP5033 is a micropower management unit (µPMU) each other. combing two step-down (buck) dc-to-dc convertors and two low dropout linear regulators (LDO). The high switching When a regulator is turned on, the output voltage ramp is frequency and tiny 16-ball WLCSP package allow for a small controlled through a soft start circuit to avoid a large inrush power management solution. current due to the charging of the output capacitors. To combine these high performance regulators into the µPMU, Thermal Protection there is a system controller allowing them to operate together. In the event that the junction temperature rises above 150°C, The buck regulators can operate in forced PWM mode if the the thermal shutdown circuit turns off all the regulators. Extreme MODE pin is at a logic high level. In forced PWM mode, the junction temperatures can be the result of high current opera- buck switching frequency is always constant and does not change tion, poor circuit board design, or high ambient temperature. with the load current. If the MODE pin is at logic low, the A 20°C hysteresis is included so that when thermal shutdown switching regulators operate in auto PWM/PSM mode. In this occurs, the regulators do not return to operation until the on-chip mode, the regulators operate at fixed PWM frequency when the temperature drops below 130°C. When coming out of thermal load current is above the power saving current threshold. When shutdown, all regulators restart with soft start control. the load current falls below the power save current threshold, the regulator in question enters PSM where the switching occurs in bursts. The burst repetition is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. Rev. H | Page 15 of 28

ADP5033 Data Sheet Undervoltage Lockout Figure 44 shows the regulator activation timings for the ADP5033 when both enables are connected to VINx. Figure 44 also shows To protect against battery discharge, undervoltage lockout the active pull-down activation. (UVLO) circuitry is integrated in the system. If the input voltage on VIN1 drops below a typical 2.15 V UVLO threshold, all BUCK1 AND BUCK2 channels shut down. In the buck channels, both the power switch The two bucks use a fixed frequency and high speed current and the synchronous rectifier turn off. When the voltage on VIN1 mode architecture. The bucks operate with an input voltage of rises above the UVLO threshold, the part is enabled once more. 2.3 V to 5.5 V. Alternatively, the user can request a new device model with a Control Scheme UVLO set at a higher level, suitable for 5 V supply applications. The bucks operate with a fixed frequency, current mode PWM For these models, the device reaches the turn-off threshold when control architecture at medium to high loads for high efficiency the input supply drops to 3.65 V typical. To order a device with but shift to a PSM control scheme at light loads to lower the options other than the default options listed in the Ordering regulation power losses. When operating in fixed frequency Guide section, contact your local Analog Devices, Inc., sales or PWM mode, the duty cycle of the integrated switches is adjusted distribution representative. and regulates the output voltage. When operating in PSM at In case of a thermal or UVLO event, the active pull-down resistors light loads, the output voltage is controlled in a hysteretic (if factory enabled) are enabled to discharge the output capacitors manner, with higher output voltage ripple. During part of this quickly. The pull-down resistors remain engaged until the time, the converter is able to stop switching and enters an idle thermal fault event is no longer present or the input supply mode, which improves conversion efficiency. voltage falls below the V voltage level. The typical value of POR PWM Mode V is approximately 1 V. POR In PWM mode, the bucks operate at a fixed frequency of 3 MHz Enable/Shutdown set by an internal oscillator. At the start of each oscillator cycle, The ADP5033 has two enable pins (ENA and ENB). A high the PFET switch is turned on, sending a positive voltage across level applied to the enable pins enables a certain selection of the inductor. Current in the inductor increases until the current regulators defined by factory programming. For example, the sense signal crosses the peak inductor current threshold that ADP5033 can be factory programmed to enable BUCK1 and turns off the PFET switch and turns on the NFET synchronous LDO2 with ENA and BUCK2 and LDO1 with ENB. When both rectifier. This sends a negative voltage across the inductor, enables are low, all regulators are turned off. When both enable causing the inductor current to decrease. The synchronous pins are high, all regulators are turned on. All possible regulator rectifier stays on for the rest of the cycle. The buck regulates the combinations can be factory programmed to operate with the output voltage by adjusting the peak inductor current threshold. ENA and ENB pins. VIN1 VUVLO VPOR VOUT1 VOUT3 VOUT4 30µs (MIN) 30µs (MIN) VOUT2 50µs (MIN) 50µs (MIN) BUCK1, LDO1, LDO2 PULL-DOWNS PULL-BDUOCWKN2 09788-148 Figure 44. Regulators Sequencing on the ADP5033 (ENx = VINx) Rev. H | Page 16 of 28

Data Sheet ADP5033 PSM Current Limit The bucks smoothly transition to PSM operation when the load Each buck has protection circuitry to limit the amount of current decreases below the PSM current threshold. When either of positive current flowing through the PFET switch and the the bucks enters PSM, an offset is induced in the PWM regulation amount of negative current flowing through the synchronous level, which makes the output voltage rise. When the output rectifier. The positive current limit on the power switch limits voltage reaches a level approximately 1.5% above the PWM the amount of current that can flow from the input to the output. regulation level, PWM operation is turned off. At this point, The negative current limit prevents the inductor current from both power switches are off, and the buck enters an idle mode. reversing direction and flowing out of the load. The output capacitor discharges until the output voltage falls to 100% Duty Operation the PWM regulation voltage, at which point the device drives With a dropin input voltage or with an increase in load current, the inductor to make the output voltage rise again to the upper the buck may reach a limit where, even with the PFET switch on threshold. This process is repeated while the load current is 100% of the time, the output voltage drops below the desired below the PSM current threshold. output voltage. At this limit, the buck transitions to a mode where The ADP5033 has a dedicated MODE pin controlling the PSM the PFET switch stays on 100% of the time. When the input and PWM operation. A high logic level applied to the MODE conditions change again and the required duty cycle falls, the pin forces both bucks to operate in PWM mode. A logic level buck immediately restarts PWM regulation without allowing low sets the bucks to operate in auto PSM/PWM. overshoot on the output voltage. PSM Current Threshold Active Pull-Downs The PSM current threshold is set to 100 mA. The bucks employ a All regulators have optional, factory programmable, active pull- scheme that enables this current to remain accurately controlled, down resistors discharging the respective output capacitors when independent of input and output voltage levels. This scheme the regulators are disabled by the ENx pins or by a faulty condition. also ensures that there is very little hysteresis between the PSM The pull-down resistors are connected between VOUTx and current threshold for entry to and exit from the PSM. The PSM AGND. Active pull-downs are disabled when the regulators are current threshold is optimized for excellent efficiency over all turned on. The typical value of the pull-down resistor is 600 Ω for load currents. the LDOs and 75 Ω for the bucks. Figure 44 shows the activation Oscillator/Phasing of Inductor Switching timings for the active pull-down during regulator activation and deactivation. The ADP5033 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. LDO1 AND LDO2 Additionally, the ADP5033 ensures that when both bucks are in The ADP5033 contains two LDOs with low quiescent current PWM mode, they operate out of phase, whereby the BUCK2 PFET and low dropout voltage, and provides up to 300 mA of output starts conducting exactly half a clock period after the BUCK1 current. Drawing a low 25 μA quiescent current (typical) at no load PFET starts conducting. makes the LDO ideal for battery-operated portable equipment. Short-Circuit Protection Each LDO operates with an input voltage of 1.7 V to 5.5 V. The The bucks include frequency foldback to prevent output current wide operating range makes these LDOs suitable for cascading runaway on a hard short. When the voltage at the feedback pin configurations where the LDO supply voltage is provided from falls below half the target output voltage, indicating the possibility one of the buck regulators. of a hard short at the output, the switching frequency is reduced Each LDO also provides high power supply rejection ratio (PSRR), to half the internal oscillator frequency. The reduction in the low output noise, and excellent line and load transient response switching frequency allows more time for the inductor to with just a small 1 µF ceramic input and output capacitor. discharge, preventing a runaway of output current. LDO1 is optimized to supply analog circuits because it offers Soft Start better noise performance compared to LDO2. LDO1 should be The bucks have an internal soft start function that ramps the output used in applications where noise performance is critical. voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Rev. H | Page 17 of 28

ADP5033 Data Sheet APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Output Capacitor Trade-offs between performance parameters such as efficiency Higher output capacitor values reduce the output voltage ripple and transient response can be made by varying the choice of and improve load transient response. When choosing this value, external components in the applications circuit, as shown in it is also important to account for the loss of capacitance due to Figure 1. output voltage dc bias. Inductor Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied The high switching frequency of the ADP5033 bucks allows for voltage. Capacitors must have a dielectric adequate to ensure the selection of small chip inductors. For best performance, use the minimum capacitance over the necessary temperature range inductor values between 0.7 μH and 3 μH. Suggested inductors and dc bias conditions. X5R or X7R dielectrics with a voltage are shown in Table 9. rating of 6.3 V or 10 V are recommended for best performance. The peak-to-peak inductor current ripple is calculated using Y5V and Z5U dielectrics are not recommended for use with any the following equation: dc-to-dc converter because of their poor temperature and dc V ×(V −V ) bias characteristics. I = OUT IN OUT RIPPLE V ×f ×L The worst-case capacitance accounting for capacitor variation IN SW over temperature, component tolerance, and voltage is calculated where: using the following equation: f is the switching frequency. SW L is the inductor value. CEFF = COUT × (1 − TEMPCO) × (1 − TOL) The minimum dc current rating of the inductor must be greater where: than the inductor peak current. The inductor peak current is CEFF is the effective capacitance at the operating voltage. calculated using the following equation: TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. I I =I + RIPPLE PEAK LOAD(MAX) 2 In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. Inductor conduction losses are caused by the flow of current The tolerance of the capacitor (TOL) is assumed to be 10%, and through the inductor, which has an associated internal dc C is 9.2 μF at 1.8 V, as shown in Figure 45. resistance (DCR). Larger sized inductors have smaller DCR, OUT which may decrease inductor conduction losses. Inductor core Substituting these values in the equation yields losses are related to the magnetic permeability of the core material. C = 9.2 μF × (1 − 0.15) × (1 − 0.1) ≈ 7.0 μF EFF Because the bucks are high switching frequency dc-to-dc To guarantee the performance of the bucks, it is imperative that converters, shielded ferrite core material is recommended for the effects of dc bias, temperature, and tolerances on the behavior its low core losses and low EMI. of the capacitors be evaluated for each application. Table 9. Suggested 1.0 μH Inductors 12 Dimensions I DCR SAT Vendor Model (mm) (mA) (mΩ) 10 Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85 Murata LQM18FN1R0M00B 1.6 × 0.8 × 0.8 150 26 F) 8 µ Taiyo BRC1608T1R0M 1.6 × 0.8 × 0.8 520 180 E ( C Yuden AN 6 T Coilcraft EPL2014-102ML 2.0 × 2.0 × 1.4 900 59 CI A P TDK GLFR1608T1R0M-LR 1.6 × 0.8 × 0.8 230 80 CA 4 Coilcraft 0603LS-102 1.8 × 1.69 × 1.1 400 81 Toko MDT2520-CN 2.5 × 2.0 × 1.2 1350 85 2 00 1 2DC BIAS V3OLTAGE 4(V) 5 6 09788-004 Figure 45. Typical Capacitor Performance Rev. H | Page 18 of 28

Data Sheet ADP5033 The peak-to-peak output voltage ripple for the selected output The effective capacitance needed for stability, which includes capacitor and inductor values is calculated using the following temperature and dc bias effects, is a minimum of 7 µF and a equation: maximum of 40 µF. I V The buck regulators require 10 µF output capacitors to guarantee VRIPPLE =8×f RIP×PLCE ≈(2π×f )2IN×L×C stability and response to rapid load variations and to transition SW OUT SW OUT into and out of the PWM/PSM modes. In certain applications, Capacitors with lower equivalent series resistance (ESR) are where one or both buck regulators power a processor, the preferred to guarantee low output voltage ripple, as shown in operating state is known because it is controlled by software. the following equation: In this condition, the processor can drive the MODE pin V according to the operating state; consequently, it is possible to ESR ≤ RIPPLE COUT I reduce the output capacitor from 10 µF to 4.7 µF because the RIPPLE regulator does not expect a large load variation when working in PSM mode (see Figure 47). Table 10. Suggested 10 μF Capacitors Vendor Type Model Case Size Voltage Rating (V) Murata X5R GRM188R60J106 0603 6.3 TDK X5R C1608JB0J106K 0603 6.3 Panasonic X5R ECJ1VB0J106M 0603 6.3 Rev. H | Page 19 of 28

ADP5033 Data Sheet Input Capacitor applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature Higher value input capacitors help to reduce the input voltage range and dc bias conditions. X5R or X7R dielectrics with a voltage ripple and improve transient response. Maximum input rating of 6.3 V or 10 V are recommended for best performance. capacitor current is calculated using the following equation: Y5V and Z5U dielectrics are not recommended for use with any I ≥I VOUT(VIN −VOUT) LDO because of their poor temperature and dc bias characteristics. CIN LOAD(MAX) V IN Figure 46 depicts the capacitance vs. voltage bias characteristic To minimize supply noise, place the input capacitor as close to of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a the VINx pin of the buck as possible. As with the output capacitor, capacitor is strongly influenced by the capacitor size and voltage a low ESR capacitor is recommended. rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the The effective capacitance needed for stability, which includes X5R dielectric is about ±15% over the −40°C to +85°C temperature temperature and dc bias effects, is a minimum of 3 µF and a range and is not a function of package or voltage rating. maximum of 10 µF. A list of suggested capacitors is shown in 1.2 Table 11. Table 11. Suggested 4.7 μF Capacitors 1.0 Case Voltage Vendor Type Model Size Rating (V) F)0.8 µ Murata X5R GRM188R60J475ME19D 0402 6.3 E ( C Taiyo Yuden X5R JMK107BJ475 0402 6.3 AN0.6 T Panasonic X5R ECJ-0EB0J475M 0402 6.3 CI A P LDO CAPACITOR SELECTION CA0.4 Output Capacitor 0.2 The ADP5033 LDOs are designed for operation with small, space-saving ceramic capacitors, but function with most commonly uEsSeRd o cfa tphaec oituotrpsu at sc alopnacgi taosr caafrfeec itss ttahkee snta wbiiltihty tohfe t hEeS RL DvaOlu ceo. nTthroe l 00 1 D2C BIAS VO3LTAGE (V4) 5 6 09788-006 Figure 46. Capacitance vs. Voltage Characteristic loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended to ensure the stability of the ADP5033. Use the following equation to determine the worst-case capacitance Transient response to changes in load current is also affected by accounting for capacitor variation over temperature, component output capacitance. Using a larger value of output capacitance tolerance, and voltage: improves the transient response of the ADP5033 to large changes C = C × (1 − TEMPCO) × (1 − TOL) EFF BIAS in load current. where: Input Bypass Capacitor C is the effective capacitance at the operating voltage. BIAS Connecting a 1 µF capacitor from VIN3 and VIN4 to ground TEMPCO is the worst-case capacitor temperature coefficient. reduces the circuit sensitivity to printed circuit board (PCB) TOL is the worst-case component tolerance. layout, especially when long input traces or high source In this example, the worst-case temperature coefficient (TEMPCO) impedance is encountered. If greater than 1 µF of output over −40°C to +85°C is assumed to be 15% for an X5R dielectric. capacitance is required, increase the input capacitor to match it. The tolerance of the capacitor (TOL) is assumed to be 10%, and C is 0.85 μF at 1.8 V, as shown in Figure 46. Table 12. Suggested 1.0 μF Capacitors BIAS Case Voltage Substituting these values into the following equation, Vendor Type Model Size Rating (V) C = 0.85 μF × (1 − 0.15) × (1 − 0.1) ≈ 0.65 μF Murata X5R GRM155B30J105K 0402 6.3 EFF TDK X5R C1005JB0J105KT 0402 6.3 Therefore, the capacitor chosen in this example meets the Panasonic X5R ECJ0EB0J105K 0402 6.3 minimum capacitance requirement of the LDO over Taiyo Yuden X5R LMK105BJ105MV-F 0402 10.0 temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5033, it is imperative Input and Output Capacitor Properties that the effects of dc bias, temperature, and tolerances on the Use any good quality ceramic capacitors with the ADP5033 as behavior of the capacitors be evaluated for each application. long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and Rev. H | Page 20 of 28

Data Sheet ADP5033 POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5033 is a highly efficient micropower management BUCK REGULATOR POWER DISSIPATION unit (µPMU), and, in most cases, the power dissipated in the The power loss of the buck regulator is approximated by device is not a concern. However, if the device operates at high P = P + P (3) ambient temperatures and maximum loading condition, the LOSS DBUCK L junction temperature can reach the maximum allowable where: operating limit (125°C). P is the power dissipation on one of the ADP5033 buck DBUCK regulators. When the temperature exceeds 150°C, the ADP5033 turns off P is the inductor power losses. all the regulators, allowing the device to cool down. When the L die temperature falls below 130°C, the ADP5033 resumes The inductor losses are external to the device, and they do not normal operation. have any effect on the die temperature. This section provides guidelines to calculate the power dissi- The inductor losses are estimated (without core losses) by pated in the device and ensure that the ADP5033 operates P ≈ I 2 × DCR (4) L OUT1(RMS) L below the maximum allowable junction temperature. where: The efficiency for each regulator on the ADP5033 is given by DCR is the inductor series resistance. L P I is the rms load current of the buck regulator. η= OUT ×100% (1) OUT1(RMS) P IN r I =I × 1+ (5) where: OUT1(RMS) OUT1 12 η is the efficiency. where r is the normalized inductor ripple current P is the input power. IN POUT is the output power. r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) (6) Power loss is given by where: L is the inductance. P = P − P (2a) LOSS IN OUT f is the switching frequency. SW or D is the duty cycle. PLOSS = POUT (1− η)/η (2b) D = VOUT1/VIN1 (7) Power dissipation can be calculated in several ways. The most The ADP5033 buck regulator power dissipation, P , includes DBUCK intuitive and practical is to measure the power dissipated at the the power switch conductive losses, the switch losses, and the input and all the outputs. Perform the measurements at the transition losses of each channel. There are other sources of worst-case conditions (voltages, currents, and temperature). loss, but these are generally less significant at high output load The difference between input and output power is dissipated in currents, where the thermal limit of the application is. Equation 8 the device and the inductor. Use Equation 4 to derive the power captures the calculation that must be made to estimate the lost in the inductor and, from this, use Equation 3 to calculate power dissipation in the buck regulator. the power dissipation in the ADP5033 buck converter. P = P + P + P (8) DBUCK COND SW TRAN A second method to estimate the power dissipation uses the The power switch conductive losses are due to the output current, efficiency curves provided for the buck regulator, and the power I , flowing through the P-MOSFET and the N-MOSFET OUT1 lost on each LDO can be calculated using Equation 12. When power switches that have internal resistance, RDS and ON-P the buck efficiency is known, use Equation 2b to derive the total RDS . The amount of conductive power loss is found by ON-N power lost in the buck regulator and inductor, use Equation 4 to derive the power lost in the inductor, and then calculate the PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT1(RMS)2 (9) power dissipation in the buck converter using Equation 3. Add where RDS is approximately 0.2 Ω, and RDS is approxi- ON-P ON-N the power dissipated in the buck and in the two LDOs to find mately 0.16 Ω at 25°C junction temperature and VIN1 = VIN2 = the total dissipated power. 3.6 V. At VIN1 = VIN2 = 2.3 V, these values change to 0.31 Ω and Note that the buck efficiency curves are typical values and may 0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V, the values are not be provided for all possible combinations of V , V , and 0.16 Ω and 0.14 Ω, respectively. IN OUT IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDO provided by Equation 12. Rev. H | Page 21 of 28

ADP5033 Data Sheet Switching losses are associated with the current drawn by the JUNCTION TEMPERATURE driver to turn on and turn off the power devices at the switching In cases where the board temperature T is known, the thermal A frequency. The amount of switching power loss is given by resistance parameter, θ , can be used to estimate the junction JA PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) temperature rise. TJ is calculated from TA and PD using the formula where: CGATE-P is the P-MOSFET gate capacitance. TJ = TA + (PD × θJA) (14) C is the N-MOSFET gate capacitance. GATE-N The typical θ value for the 16-ball, 0.5 mm pitch WLCSP is JA For the ADP5033, the total of (CGATE-P + CGATE-N) is approxi- 57°C/W (see Table 7). A very important factor to consider is mately 150 pF. that θ is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per JA JEDEC standard, and real applications may use different sizes The transition losses occur because the P-channel power and layers. It is important to maximize the copper used to remove MOSFET cannot be turned on or off instantaneously, and the the heat from the device. Copper exposed to air dissipates heat SW node takes some time to slew from near ground to near better than copper used in the inner layers. The exposed pad V (and from V to ground). The amount of transition OUT1 OUT1 should be connected to the ground plane with several vias. loss is calculated by If the case temperature can be measured, the junction tempera- P = V × I × (t + t ) × f (11) TRAN IN1 OUT1 RISE FALL SW ture is calculated by where t and t are the rise time and the fall time of the RISE FALL T = T + (P × Ψ ) (15) switching node, SW. For the ADP5033, the rise and fall times of J C D JB SW are in the order of 5 ns. where T is the case temperature and Ψ is the junction-to- C JB board thermal resistance provided in Table 7. If the preceding equations and parameters are used for estimat- ing the converter efficiency, it must be noted that the equations When designing an application for a particular ambient do not describe all of the converter losses, and the parameter temperature range, calculate the expected ADP5033 power values given are typical numbers. The converter performance dissipation (P ) due to the losses of all channels by using the D also depends on the choice of passive components and board Equation 8 to Equation 13. From this power calculation, the layout; therefore, a sufficient safety margin should be included junction temperature, T, can be estimated using Equation 14. J in the estimate. The reliable operation of the converter and the two LDO regulators LDO Regulator Power Dissipation can be achieved only if the estimated die junction temperature of The power loss of an LDO regulator is given by the ADP5033 (Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) is highly affected by increas- P = [(V − V ) × I ] + (V × I ) (12) DLDO IN OUT LOAD IN GND ing the junction temperature. Additional information about where: product reliability can be found in the ADI Reliability Handbook, ILOAD is the load current of the LDO regulator. which can be found at www.analog.com/reliability_handbook. V and V are input and output voltages of the LDO, IN OUT respectively. I is the ground current of the LDO regulator. GND Power dissipation due to the ground current is small, and it can be ignored. The total power dissipation in the ADP5033 simplifies to P = P + P + P + P (13) D DBUCK1 DBUCK2 DLDO1 DLDO2 Rev. H | Page 22 of 28

Data Sheet ADP5033 PCB LAYOUT GUIDELINES Poor layout can affect ADP5033 performance, causing electro- • Maximize the size of ground metal on the component side magnetic interference (EMI) and electromagnetic compatibility to help with thermal dissipation. (EMC) problems, ground bounce, and voltage losses. Poor • Use a ground plane with several vias connecting to the layout can also affect regulation and stability. A good layout is component side ground to further reduce noise interfer- implemented using the following guidelines: ence on sensitive circuit nodes. • Place the inductor, input capacitor, and output capacitor • Connect VIN1 and VIN2 together close to the IC using close to the IC using short tracks. These components carry short tracks. high switching frequencies, and large tracks act as antennas. • Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Rev. H | Page 23 of 28

ADP5033 Data Sheet TYPICAL APPLICATION SCHEMATIC ADP5033 VCORE PROCESSOR L1 1µH SW1 VIN1 VCORE C1 VOUT1 4.7µF BUCK1 C5 PGND1 4.7µF ALWAYS ON ENA BK1 ON ACT BLDK12 MODE GPIO OFF ENB LD2 VIO VIN: VIN2 2.3V TO 5.5V C2 SW2 L2 1µH 4.7µF VIO VOUT2 BUCK2 C6 PGND2 4.7µF ANALOG SUBSYSTEM F(1R.7OVM M VINIO) C3 VIN3 LDO1 VOUT3 C7 VANA 1µF 1µF FRO(M1. 7VVC MORINE) C4 VIN4 LDO2 VOUT4 C8 VDIG 1µF 1µF AGND 09788-152 Figure 47. Processor System Power Management with PSM/PWM Control Rev. H | Page 24 of 28

Data Sheet ADP5033 OUTLINE DIMENSIONS 2.040 2.000 SQ 1.960 4 3 2 1 A BALLA1 IDENTIFIER 1.50 B REF C D 0.50 REF TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.390 0.660 0.360 0.600 SIDE VIEW 0.330 0.540 COPLANARITY 0.04 SEATING 0.360 0.270 PLANE 00..322800 00..224100 10-19-2012-B Figure 48. 16-Ball Wafer Level Chip Scale Package [WLCSP] Back-Coating Included (CB-16-8) Dimensions shown in millimeters Rev. H | Page 25 of 28

ADP5033 Data Sheet ORDERING GUIDE ENA Temperature Output Controlled Package Package Marking Model1 Range Voltage (V)2 Options Channels3 Description Option Code ADP5033ACBZ-1-R7 −40°C to VOUT1: 1.2 V, UVLO: low, BUCK2, 16-Ball WLCSP CB-16-8 LHX +125°C VOUT2: 3.3 V, pull-downs on LDO1 VOUT3: 2.8 V, buck channels VOUT4: 1.8 V only ADP5033ACBZ-2-R7 −40°C to VOUT1: 1.8 V, UVLO: low, BUCK1, 16-Ball WLCSP CB-16-8 LMD +125°C VOUT2: 2.8 V, pull-downs on BUCK2, VOUT3: 2.8 V, all channels LDO1 VOUT4: 3.0 V ADP5033ACBZ-3-R7 −40°C to VOUT1: 3.0 V, UVLO: low, BUCK1, 16-Ball WLCSP CB-16-8 LNC +125°C VOUT2: 1.2 V, pull-downs on LDO1, VOUT3: 1.8 V, all channels LDO2 VOUT4: 3.0 V ADP5033ACBZ-4-R7 −40°C to VOUT1: 0.9 V, UVLO: low, BUCK1, 16-Ball WLCSP CB-16-8 LNR +125°C VOUT2: 0.9 V, pull-downs BUCK2 VOUT3: 3.0 V, disabled VOUT4: 2.8 V ADP5033ACBZ-5-R7 −40°C to VOUT1: 3.3 V, UVLO: low, BUCK1 16-Ball WLCSP CB-16-8 LQ3 +125°C VOUT2: 1.8 V, pull-downs on VOUT3: 1.2 V, all channels VOUT4: 1.5 V ADP5033ACBZ-6-R7 −40°C to VOUT1: 1.8 V, UVLO: low, BUCK1, 16-Ball WLCSP CB-16-8 LQ5 +125°C VOUT2: 2.5 V, pull-downs on LDO1 VOUT3: 3.0 V, all channels VOUT4: 3.0 V ADP5033ACBZ-7-R7 −40°C to VOUT1: 1.1 V, UVLO: low, BUCK1 16-Ball WLCSP CB-16-8 LRB +125°C VOUT2: 1.8 V, pull-downs on VOUT3: 2.5 V, all channels VOUT4: 3.2 V ADP5033ACBZ-8-R7 −40°C to VOUT1: 2.8 V, UVLO: low, BUCK1, 16-Ball WLCSP CB-16-8 LRC +125°C VOUT2: 1.5 V, pull-downs on BUCK2, VOUT3: 2.8 V, all channels LDO2 VOUT4: 1.8 V ADP5033ACBZ-9-R7 −40°C to VOUT1: 1.1 V, UVLO: low, BUCK1 16-Ball WLCSP CB-16-8 LRD +125°C VOUT2: 1.8 V, pull-downs on VOUT3: 1.2 V, all channels VOUT4: 3.2 V ADP5033ACBZ-10- −40°C to VOUT1: 1.8 V, UVLO: low, BUCK1, 16-Ball WLCSP CB-16-8 LV6 R7 +125°C VOUT2: 3.3 V, pull-downs on LDO1 VOUT3: 1.8 V, all channels VOUT4: 3.3 V ADP5033ACBZ-11- −40°C to VOUT1: 1.2 V, UVLO: low, BUCK1, 16-Ball WLCSP CB-16-8 LV7 R7 +125°C VOUT2: 3.3 V, pull-downs on BUCK2 VOUT3: 1.8 V, all channels VOUT4: 2.5 V ADP5033-1-EVALZ Evaluation Board for ADP5033ACBZ- 1-R7 1 Z = RoHS Compliant Part. 2 For additional options, contact a local sales or distribution representative. Additional options available include the following: BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, or 0.9 V. LDO1 and LDO2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, or 0.8 V. UVLO: low or high. In addition, for BUCK1, BUCK2, LDO1, and LDO2, active pull-down resistor is programmable to be either enabled or disabled. 3 ENA activated channels (ENB controls the other channels). Rev. H | Page 26 of 28

Data Sheet ADP5033 NOTES Rev. H | Page 27 of 28

ADP5033 Data Sheet NOTES ©2011–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09788-0-3/19(H) Rev. H | Page 28 of 28