High Accuracy, Low I , anyCAP® Q Adjustable Low Dropout Regulator ADP3334 FEATURES FUNCTIONAL BLOCK DIAGRAM High Accuracy over Line and Load: (cid:1)0.9% @ 25(cid:2)C, (cid:1)1.8% over Temperature 500 mA Current Capability IN Q1 OUT Ultralow Dropout Voltage THERMAL ADP3334 Requires Only C = 1.0 (cid:3)F for Stability PROTECTION CC O anyCAP = Stable with Any Type of Capacitor FB (Including MLCC) DRIVER gm Current and Thermal Limiting Low Noise SD BAND GAP Low Shutdown Current: < 1.0 (cid:3)A (Typ) REF 2.6 V to 11 V Supply Range 1.5 V to 10 V Output Range GND –40(cid:2)C to +85(cid:2)C Ambient Temperature Range APPLICATIONS Cellular Phones TFT LCD Modules Camcorders, Cameras Networking Systems, DSL/Cable Modems Cable Set-Top Boxes DSP Supplies Personal Digital Assistants GENERAL DESCRIPTION The ADP3334 is available in three different package options: The ADP3334 is a member of the ADP333x family of precision 1.Excellent thermal capability, space saving 3 mm (cid:1) 3 mm LFCSP. low dropout anyCAP voltage regulators. The ADP3334 operates with an input voltage range of 2.6 V to 11 V and delivers a 2.Popular low profile MSOP-8. continuous load current up to 500 mA. The novel anyCAP 3.Traditional thermal enhanced SOIC-8. architecture requires only a very small 1 µF output capacitor for stability, and the LDO is insensitive to the capacitor’s equivalent ADP3334 series resistance (ESR). This makes the ADP3334 stable with any IN OUT capacitor, including ceramic (MLCC) types for space restricted applications. VIN IN OUT VOUT CIN R1 CNR COUT The ADP3334 achieves exceptional accuracy of ±0.9% at room 1(cid:3)F FB 1(cid:3)F temperature and ±1.8% over temperature, line, and load. The SD GND R2 dropout voltage of the ADP3334 is only 200 mV (typical) at OFF 500 mA. This device also includes a safety current limit, ther- ON mal overload protection, and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 µA. The Figure 1.Typical Application Circuit ADP3334 has low quiescent current of 90 µA (typical) in light load situations. REV.C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781/461-3113 © 2014 Analog Devices, Inc. All rights reserved.

ADP3334–SPECIFICATIONS1, 2, 3 (V = 6.0V, C = C = 1.0 (cid:3)F, T = –40(cid:2)C to +85(cid:2)C, unless otherwise noted.) IN IN OUT A Parameter Symbol Conditions Min Typ Max Unit OUTPUT Voltage Accuracy4 V V = V + 0.4 V to 11 V –0.9 +0.9 % OUT IN OUT(NOM) I = 0.1 mA to 500 mA L T = 25°C A V = V + 0.4 V to 11 V –1.8 +1.8 % IN OUT(NOM) I = 0.1 mA to 500 mA L T = 85°C A V = V + 0.4 V to 11 V –2.3 +2.3 % IN OUT(NOM) I = 0.1 mA to 500 mA L T = 150°C J Line Regulation4 V = V + 0.4 V to 11 V 0.04 mV/V IN OUT(NOM) I = 0.1 mA L T = 25°C A Load Regulation I = 0.1 mA to 500 mA 0.04 mV/mA L T = 25°C A Dropout Voltage V V = 98% of V DROP OUT OUT(NOM) I = 500 mA 200 400 mV L I = 300 mA 140 250 mV L I = 100 mA 60 140 mV L I = 1 mA 10 mV L Peak Load Current I V = V + 1 V 800 mA LDPK IN OUT(NOM) Output Noise V f = 10 Hz–100 kHz, C = 10 µF 27 µV rms NOISE L I = 500 mA, C = 10 nF L NR f = 10 Hz–100 kHz, C = 10 µF 45 µV rms L I = 500 mA, C = 0 nF L NR GROUND CURRENT5 In Regulation I I = 500 mA 4.5 10 mA GND L I = 300 mA 2.6 6 mA L I = 50 mA 0.5 1.5 mA L I = 0.1 mA 90 130 µA L In Dropout I V = V – 100 mV 150 450 µA GND IN OUT(NOM) I = 0.1 mA L In Shutdown I SD = 6 V, V = 11 V 0.9 3 µA GNDSD IN SHUTDOWN Threshold Voltage V LDO OFF 2.0 V THSD LDO ON 0.4 V SD Input Current ISD 0 £ SD £ 5 V 1.2 3 µA Output Current in Shutdown I SD = 2 V, V = 11 V 0.01 5 µA OSD IN NOTES 1All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. 2Ambient temperature of 85°C corresponds to a junction temperature of 125°C under pulsed full load test conditions. 3Application stable with no load. 4VIN = 2.6 V to 11 V for VOUT(NOM) £ 2.2 V. 5Ground current includes current through external resistors. Specifications subject to change without notice. –2– REV. C

ADP3334 ABSOLUTE MAXIMUM RATSINGS* PIN FUNCTION DESCRIPTIONS Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V Mnemonic Function Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited GND Ground Pin. Operating Ambient Temperature Range . . . . –40°C to +85°C SD Shutdown Control. Pulling this pin low Operating Junction Temperature Range . . . –40°C to +150°C turns on the regulator. Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C IN Regulator Input. (cid:2) 2-Layer SOIC-8 . . . . . . . . . . . . . . . . . . . . . . . . 122.3°C/W JA (cid:2) 4-Layer SOIC-8 . . . . . . . . . . . . . . . . . . . . . . . . . 86.6°C/W OUT Output. Bypass to ground with a 1.0 µF or JA (cid:2) 2-Layer LFCSP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W larger capacitor. JA (cid:2)JA 4-Layer LFCSP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W FB Feedback Input. FB should be connected to (cid:2)JA 2-Layer MSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W an external resistor divider that sets the (cid:2)JA 4-Layer MSOP-8 . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W output voltage. Lead Temperature Range (Soldering 6 sec) . . . . . . . . . . 300°C NC No Connection. *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATIONS OUT 1 8 IN OUT 1 8 IN GND 1 8 NC OUT 2 ADP3334ARM 7 IN OUT 2 ADP3334ACP 7 IN SD 2 ADP3334AR 7 FB TOP VIEW TOP VIEW FB 3 (Not to Scale) 6 SD FB 3 TOP VIEW* 6 SD IN 3 (Not to Scale) 6 OUT NC 4 5 GND NC 4 5 GND IN 4 5 OUT NC = NO CONNECT NC = NO CONNECT *PINS UNDERSIDE NC = NO CONNECT The EPAD should be connected to VIN. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3334 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3–

ADP3334–Typical Performance Characteristics 2.202 2.201 140 VOUT = 2.2V VOUT = 2.2V IL = 100(cid:3)A VOUT = 2.2V 2.201 IL = 0 2.200 VIN = 6V 120 OUTPUT VOLTAGE – V22222.....111219990987609 15300m0mAA OUTPUT VOLTAGE – V22222.....111119999976598 (cid:3)GROUND CURRENT – A160480000 IL = 0 2.195 500mA 2.194 20 2.194 2.193 0 2 4 6 8 10 12 0 100 200 300 400 500 0 2 4 6 8 10 12 INPUT VOLTAGE – V OUTPUT LOAD – mA INPUT VOLTAGE – V TPC 1. Line Regulation Output TPC 2. Output Voltage vs. TPC 3. Ground Current vs. Voltage vs. Supply Voltage Load Current Supply Voltage 5.0 0.5 8 4.0 VVIONU =T 6=V 2.2V 0.4 300mA0mA A7 IL = 500mA VVIONU =T 6=V 2.2V ROUND CURRENT – mA23..00 OUTPUT CHANGE – % 000...2301 500mA GROUND CURRENT – m65342 130000mmAA G1.0 500mA –0.1 1 50mA 0 0 0 –0.2 0 0 100 200 300 400 500 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 OUTPUT LOAD – mA JUNCTION TEMPERATURE – (cid:2)C JUNCTION TEMPERATURE – (cid:2)C TPC 4. Ground Current vs. TPC 5. Output Voltage Variation % TPC 6. Ground Current vs. Load Current vs. Junction Temperature Junction Temperature 250 AGE – mV210500 VOUT = 2.2V T VOLTAGE – V3221....0505 SRVDOL U ==T 4 G=.4 N2(cid:4)D.2V V – VOUT3210 COUT = 1(cid:3)F COUT = 10(cid:3)F T U OL TP1.0 4 V U V DROPOUT 10500 INPUT/O0.50 V – IN20 SRVDOL U ==T 4 G=.4 N2(cid:4)D.2V 1 2 3 4 200 400 600 800 TIME – s TIME – (cid:3)s 0 0 100 200 300 400 500 OUTPUT LOAD – mA TPC 7. Dropout Voltage vs. TPC 8. Power-Up/Power-Down TPC 9. Power-Up Response Output Current –4– REV. C

ADP3334 2.210 2.210 2.3 V V V – UT 2.200 – UT 2.200 – UT2.2 O O O V 2.190 V 2.190 V 2.1 VOUT = 2.2V VOUT = 2.2V 2.180 RL = 4.4(cid:4) 2.180 RL = 4.4(cid:4) CL = 1(cid:3)F CL = 10(cid:3)F 2.170 2.170 A400 V – VIN33..050000 V – VIN33..050000 I – mOUT2000 VCVIOLN U ==T 1 6=(cid:3)V 2F.2V 40 80 140 180 40 80 140 180 200 400 600 800 TIME – (cid:3)s TIME – (cid:3)s TIME – (cid:3)s TPC 10. Line Transient Response TPC 11. Line Transient Response TPC 12. Load Transient Response V 2.3 – 2.2 V T V – OUT 22..12 VOU 0 – VT 12 1(cid:3)F 10(cid:3)F 10(cid:3)F FULL SHORT OU 1(cid:3)F 3 800m(cid:4) V 0 SHORT A 400 2 VIN = 6V I – mOUT2000 VVCOILN U ==T 1 6=0V (cid:3)2.F2V I – AOUT 01 VIN = 4V V – VSD 02 RVOL U=T 4 =.4 2(cid:4).2V 200 400 600 800 200 400 600 800 200 400 600 800 TIME – (cid:3)s TIME – (cid:3)s TIME – (cid:3)s TPC 13. Load Transient Response TPC 14. Short Circuit Current TPC 15. Turn Off/On Response –20 160 100 RIPPLE REJECTION – dB–––––3456700000 VOCIULL T= = =5 102(cid:3)(cid:3).2FAVCILL = = 5 10(cid:3)0mFA CICLLL = == 5 110000(cid:3)(cid:3)mFFA (cid:3)RMS NOISE – V111420864000000 NILO =I S5E00 RmEAD WUNILCO I=TTI HS5IOOE0NILN0 UO Rm=TIE S0ADEm WUCV ARCOIN ETWTURHDIOIT UT= NHC= 1OT 20IUO.n0TNFV VOLTAGE NOISE SPECTRAL(cid:3)DENSITY – V/ Hz00.10.0111 CCNL R= =1 01(cid:3)0nFCCFNL R= =CC1 N(cid:3)L1 R0F= n =1F 00(cid:3)FCCIVNLL RO == U = 1T1 (cid:3)0 m=F A2.2V –80 IL = 50(cid:3)A 20 –90 0 IL = 0mA WITH NOISE REDUCTION 0.001 10 100 1k 10k 100k 1M 10M 0 10 20 30 40 50 10 100 1k 10k 100k 1M FREQUENCY – Hz CL – (cid:3)F FREQUENCY – Hz TPC 16. Power Supply Ripple TPC 17. RMS Noise vs. C TPC 18. Output Noise Density L Rejection (10 Hz to 100 kHz) REV. C –5–

ADP3334 THEORY OF OPERATION superior line noise rejection and very high regulator gain, which The new anyCAP LDO ADP3334 uses a single control loop for lead to excellent line and load regulation. An impressive ±1.8% regulation and reference functions. The output voltage is sensed accuracy is guaranteed over line, load, and temperature. by a resistive voltage divider consisting of R1 and R2 that is Additional features of the circuit include current limit and ther- varied to provide the available output voltage option. Feedback mal shutdown. is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. APPLICATION INFORMATION Output Capacitor INPUT OUTPUT As with any micropower device, output transient response is a ATTENUATION function of the output capacitance. The ADP3334 is stable with Q1 COMPENSATION(VBANDGAP/VOUT) R1 a wide range of capacitor values, types, and ESR (anyCAP). CAPACITORPTAT R3 D1 CLOAD A capacitor as low as 1 µF is all that is needed for stability; NOWNIIDNEVBEARNTDING gm VOS FB (a) larger capacitors can be used if high output current surges are DRIVER R4 PCTUARTRENT R2 RLOAD acnaptiaccipitaotresd .( ETShRe A(cid:1)D0P),3 s3u3c4h ias ss tmabulleti lwaiytehr ecxetrraemmice lcya lpoawci tEoSrsR ADP3334 (MLCC) or OSCON. Note that the effective capacitance of some capacitor types may fall below the minimum over the operating temperature range or with the application of a dc voltage. GND Input Bypass Capacitor Figure 2.Functional Block Diagram An input bypass capacitor is not strictly required but is advisable A very high gain error amplifier is used to control this loop. The in any application involving long input wires or high source amplifier is constructed in such a way that equilibrium pro- impedance. Connecting a 1 µF capacitor from IN to ground duces a large, temperature-proportional input, “offset voltage” reduces the circuit’s sensitivity to PC board layout. If a larger that is repeatable and very well controlled. The temperature- value output capacitor is used, then a larger value input capaci- proportional offset voltage is combined with the complementary tor is also recommended. diode voltage to form a “virtual band gap” voltage, implicit in Noise Reduction Capacitor the network although it never appears explicitly in the circuit. A noise reduction capacitor (C ) can be placed between the Ultimately, this patented design makes it possible to control NR output and the feedback pin to further reduce the noise by the loop with only one amplifier. This technique also improves 6 dB to 10dB (TPC 18). Low leakage capacitors in the 100 pF the noise characteristics of the amplifier by providing more to 1 nF range provide the best performance. Since the feedback flexibility on the trade-off of noise sources that leads to a low pin (FB) is internally connected to a high impedance node, any noise design. connection to this node should be carefully done to avoid noise The R1, R2 divider is chosen in the same ratio as the band gap pickup from external sources. The pad connected to this pin voltage to the output voltage. Although the R1, R2 resistor divider should be as small as possible, and long PC board traces are not is loaded by the diode D1 and a second divider consisting of R3 recommended. and R4, the values can be chosen to produce a temperature stable When adding a noise reduction capacitor, maintain a mini- output. This unique arrangement specifically corrects for the mum load current of 1 mA when not in shutdown. loading of the divider, thus avoiding the error resulting from base current loading in conventional circuits. It is important to note that as CNR increases, the turn-on time will be delayed. With C values of 1 nF, this delay may be The patented amplifier controls a new and unique noninverting NR on the order of several milliseconds. driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to ADP3334 achieve reduced sensitivity to the value, type, and ESR of the IN OUT load capacitance. VIN IN OUT VOUT Most LDOs place very strict requirements on the range of ESR CIN R1 CNR COUT values for the output capacitor because they are difficult to stabilize 1(cid:3)F FB 1(cid:3)F SD GND due to the uncertainty of load capacitance and resistance. More- R2 over, the ESR value, required to keep conventional LDOs stable, OFF changes depending on load and temperature. These ESR limita- ON tions make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. Figure 3.Typical Application Circuit With the ADP3334 anyCAP LDO, this is no longer true. It can Output Voltage be used with virtually any good quality capacitor, with no con- The ADP3334 has an adjustable output voltage that can be set straint on the minimum ESR. This innovative design allows the by an external resistor divider. The output voltage will be divided circuit to be stable with just a small 1 mF capacitor on the out- by R1 and R2 and then fed back to the FB pin. put. Additional advantages of the pole-splitting scheme include –6– REV. C

ADP3334 To have the lowest possible sensitivity of the output voltage to 3.0 temperature variations, it is important that the value of the parallel resistance of R1 and R2 be kept as close as possible to 50kW. 2.5 R R11¥+RR22 =50kW (1) OR – % 2.0 R Also, for the best accuracy over temperature, the feedback volt- ER 1.5 age should be set for 1.178 V: UT P T U 1.0 O Ê R2 ˆ V FB =VOUT ¥ËÁR1+R2¯˜ (2) 0.5 where V is the desired output voltage and V is the virtual OUT FB 0 band gap voltage. Note that V does not actually appear at the 0 2 3 4 5 6 FB Rp ERROR – % FB pin due to loading by the internal PTAT current. Figure 4.Output Voltage Error vs. Combining the above equations and solving for R1 and R2 gives Parallel Resistance Error the following formulas: The actual output voltage can be calculated using the following R1=50kW¥ÊÁVVOUTˆ˜ (3) equation. Ë FB ¯ ÊR1 ˆ R2= 50kW (4) VOUT =1.178V ¥ËÁR2 +1¯˜ (5) ÊÁ1-VVFB ˆ˜ V OUT =3.274V Ë OUT¯ So worst-case error will occur when R1 has a –1% tolerance and R2 has a +1% tolerance. Recalculating the output voltage, the Table I. Feedback Resistor Selection parallel resistance and error are: VOUT (V) R1 (1% Resistor) (k(cid:4)) R2 (1% Resistor) (k(cid:4)) Ê138.6 ˆ 1.5 63.4 232.0 VOUT =1.178V ¥ËÁ 79.5 +1¯˜ 1.8 76.8 147.0 2.2 93.1 107.0 VOUT =3.232V (6) 2.7 115.0 88.7 Ê3.232 ˆ 3.3 140.0 78.7 R esistor Divider Error =ËÁ 3.3 -1¯˜ ¥100%=-2.1% 5.0 210.0 64.9 10.0 422.0 56.2 R1¥R2 138.6¥79.5 RPARALLEL = R1+R2 =138.6+79.5 =50.51 kW (7) Using standard 1% values, as shown in Table I, will sacrifice Ê50.51 ˆ some output voltage accuracy. To estimate the overall output RPARALLEL Error = Á 50 -1˜¥100%=1.02% voltage accuracy, it is necessary to take into account all sources Ë ¯ of error. The accuracy given in the specifications table does not So, from the graph in Figure 4, the output voltage error is take into account the error introduced by the feedback resistor estimated to be an additional 0.25%. The error budget is divider ratio or the error introduced by the parallel combination 1.8% (the initial output voltage accuracy over temperature), of the feedback resistors. plus 2.1% (resistor divider error), plus 0.25% (parallel resis- The error in the parallel combination of the feedback resistors tance error) for a worst-case total of 4.15%. causes the reference to have a wider variation over temperature. Thermal Overload Protection To estimate the variation, calculate the worst-case error from The ADP3334 is protected against damage from excessive power 50 kW, and then use the graph in Figure 4 to estimate the dissipation by its thermal overload protection circuit, which limits additional change in the output voltage over the operating the die temperature to a maximum of 165°C. Under extreme temperature range. conditions (i.e., high ambient temperature and power dissipation) For example: where die temperature starts to rise above 165°C, the output current is reduced until the die temperature has dropped to a safe V = 5 V IN level. The output current is restored when the die temperature V = 3.3 V OUT is reduced. R1 = 140 kW, 1% R2 = 78.7 kW, 1% REV. C –7–

ADP3334 Current and thermal limit protections are intended to protect As an example, the patented thermal coastline lead frame design the device against accidental overload conditions. For normal of the ADP3334 uniformly minimizes the value of the dominant operation, device power dissipation should be externally limited portion of the thermal resistance. It ensures that heat is con- so that junction temperatures will not exceed 150°C. ducted away by all pins of the package. This yields a very low 86.6°C/W thermal resistance for the SOIC-8 package, without Calculating Junction Temperature any special board layout requirements, relying only on the normal Device power dissipation is calculated as follows: traces connected to the leads. This yields a 15% improvement in P D =(VIN -VOUT)ILOAD +(VIN)IGND (8) heat dissipation capability as compared to a standard SOIC-8 where I and I are load current and ground current, V package. The thermal resistance can be decreased by an addi- LOAD GND IN and V are input and output voltages, respectively. tional 10% by attaching a few square centimeters of copper area OUT to the IN or OUT pins of the ADP3334 package. Assuming I = 400 mA, I = 4 mA, V = 5.0 V and LOAD GND IN V = 2.8 V, device power dissipation is: It is not recommended to use solder mask or silkscreen on the OUT PCB traces adjacent to the ADP3334’s pins since it will increase P D =(5-2.8)400mA+5.0(4mA)=900mW (9) the junction-to-ambient thermal resistance of the package. As an example, the proprietary package used in the ADP3334 has a thermal resistance of 86.6°C/W, significantly lower than 2x VIAS, 0.250 a standard SOIC-8 package. Assuming a 4-layer board, the 35µm PLATING junction temperature rise above ambient temperature will be 0.73 approximately equal to: 0.30 D TJA=0.900W ¥86.6∞C/W =77.9∞C (10) 1.80 0.90 To limit the maximum junction temperature to 150°C, maxi- 2.36 mum allowable ambient temperature will be: 0.50 T AMAX =150∞C -77.9∞C/W =72.1∞C (11) The maximum power dissipation versus ambient temperature 1.40 for each package is shown in Figure 5. 1.90 3.36 3.5 Figure 6.3 mm x 3 mm LFCSP Pad Pattern 48(cid:2)C/W LFCSP 3.0 (Dimensions shown in millimeters) LFCSP Layout Considerations W – 2.5 The LFCSP package has an exposed die paddle on the bottom, N 62(cid:2)C/W LFCSP O which efficiently conducts heat to the PCB. In order to achieve SSIPATI 2.0 86(cid:2)C/W SOIC tchoen soipdteirmatuiomn pmerufsotr mbea ngicvee nfr otom t hthee l aLyFoCutS oPf pthaec kPaCgeB, .s Upescei atlhe R DI 1.5 122(cid:2)C/W SOIC following layout guidelines for the LFCSP package. E W O 1.0 1. The pad pattern is given in Figure 6. The pad dimension P should be followed closely for reliable solder joints while 0.5 158(cid:2)C/W MSOP maintaining reasonable clearances to prevent solder bridging. 220(cid:2)C/W MSOP 2. The thermal pad of the LFCSP package provides a low ther- 0 –20 0 20 40 60 80 mal impedance path (approximately 20°C/W) to the PCB. AMBIENT TEMPERATURE – (cid:2)C Therefore the PCB must be properly designed to effectively Figure 5.Power Derating Curve conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal Printed Circuit Board Layout Consideration path to the inner or bottom layers. See Figure 5 for the rec- All surface-mount packages rely on the traces of the PC board ommended via pattern. Note that the via diameter is small to to conduct heat away from the package. prevent the solder from flowing through the via and leaving In standard packages, the dominant component of the heat voids in the thermal pad solder joint. resistance path is the plastic between the die attach pad and the Note that the thermal pad is attached to the die substrate, so individual leads. In typical thermally enhanced packages, one or the thermal planes that the vias attach the package to must more of the leads are fused to the die attach pad, significantly be electrically isolated or connected to V . Do NOT con- decreasing this component. To make the improvement mean- IN nect the thermal pad to ground. ingful, however, a significant copper area on the PCB must be attached to these fused pins. –8– REV. C

ADP3334 3. The solder mask opening should be about 120 microns Use the following general guidelines when designing printed (4.7 mils) larger than the pad size resulting in a minimum circuit boards. 60 micron (2.4 mils) clearance between the pad and the 1. Keep the output capacitor as close as possible to the out- solder mask. put and ground pins. 4. The paste mask opening is typically designed to match the 2. Keep the input capacitor as close as possible to the input pad size used on the peripheral pads of the LFCSP package. and ground pins. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. 3. PC board traces with larger cross sectional areas will remove more heat from the ADP3334. For optimum heat transfer, The paste mask for the thermal pad needs to be designed for specify thick copper and use wide traces. the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the 4. Use additional copper layers or planes to reduce the size of the thermal pad, eliminating voids may not be possible. thermal resistance. When connecting to other layers, use multiple vias if possible. 5. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should Shutdown Mode Applying a TTL high signal to the shutdown (SD) pin or the be used. input pin will turn the output off. Pulling SD down to 0.4 V or A “No Clean” Type 3 solder paste should be used for mount- below or tying it to ground will turn the output on. In shutdown ing the LFCSP package. Also, a nitrogen purge during the mode, quiescent current is reduced to much less than 1 µA. reflow process is recommended. 6. The package manufacturer recommends that the reflow temperature should not exceed 220°C and the time above liquidus is less than 75 seconds. The preheat ramp should be 3°C/second or lower. The actual temperature profile depends on the board density and must determined by the assembly house as to what works best. REV. C –9–

ADP3334 Data Sheet OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 7. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 8. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. C | Page 10

Data Sheet ADP3334 1.84 3.10 1.74 3.00 SQ 2.90 1.64 0.50 BSC 5 8 PIN 1 INDEX EXPOSED 1.55 AREA PAD 1.45 0.50 1.35 0.40 0.30 4 1 PIN 1 TOP VIEW BOTTOM VIEW INDICATOR (R 0.15) 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO THE PIN CONFIGURATIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.30 0.08 PLANE 0.25 0.203 REF 0.C2O0MPLIANTTOJEDEC STANDARDS MO-229-WEED 12-07-2010-A Figure 9. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-13) Dimensions shown in millimeters ORDERING GUIDE Model1 Package Description Package Option Branding ADP3334ARZ 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADP3334ARZ-REEL 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADP3334ARZ-REEL7 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADP3334ACPZ-REEL7 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-13 LLA ADP3334ARMZ-REEL7 8-Lead Mini Small Outline Package [MSOP] RM-8 L1N 1 Z = RoHS Compliant Part. REVISION HISTORY 1/03—Rev. 0 to Rev. A Added 8-Lead LFCSP and 8-Lead MSOP Package ........ Universal 1/14—Rev. B to Rev. C Edits to product title ......................................................................... 1 Added EPAD Note ............................................................................ 3 Edits to Features ................................................................................. 1 Changes to Figure 9, Outline Dimensions .................................. 10 Edits to Applications ......................................................................... 1 Changes to Ordering Guide .......................................................... 11 Edits to General Description ........................................................... 1 3/03—Rev. A to Rev. B Removed pin numbers from Figure 1 ............................................. 1 Edits to Specifications ....................................................................... 2 Edits to Specifications ...................................................................... 2 Edits to Absolute Maximum Ratings .............................................. 3 Edits to Output Voltage ................................................................... 6 Edits to Ordering Guide ................................................................... 3 Added text to Output Voltage section ........................................... 7 Added pinouts to Pin Configurations ............................................ 3 Added Figure 4 .................................................................................. 7 Added text to Calculating Junction Temperature section ........... 8 Edits to Calculating Junction Temperature section ..................... 8 Added LFCSP Layout Considerations section .............................. 8 Renumbered Figures 5 and 6 .......................................................... 8 Added Figure 5 .................................................................................. 8 Updated 8-Lead SOIC Package ..................................................... 10 ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02610-0-1/14(C) Rev. C | Page 11