Triple, 200 mA, Low Noise, High PSRR Voltage Regulator Data Sheet ADP322/ADP323 FEATURES TYPICAL APPLICATION CIRCUITS Fixed (ADP322) and adjustable output (ADP323) options ADP322 VBIAS Bias voltage range (VBIAS): 2.5 V to 5.5 V 2.5V TO VBIAS LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V 5.5V +1µF Three 200 mA low dropout voltage regulators (LDOs) 1.8V TO VIN1/VIN2 16-lead, 3 mm × 3 mm LFCSP 5.5V +1µF LDO 1 VOUT1 ON Initial accuracy: ±1% EN1OFF EN LD1 +1µF Stable with 1 µF ceramic output capacitors VBIAS No noise bypass capacitor required LDO 2 VOUT2 ON 3 independent logic controlled enables EN2OFF EN LD2 +1µF Overcurrent and thermal protection VBIAS 1.8V TO VIN3 KeHy isgphe PciSfRicRa tions 5.5V +1µFEN3OFFON ENL LDDO3 3 VO+U1Tµ3F 76 dB PSRR up to 1 kHz 70 dB PSRR at 10 kHz GND 09288-001 60 dB PSRR at 100 kHz Figure 1. Typical Application Circuit for ADP322 40 dB PSRR at 1 MHz Low output noise 24 µV rms typical output noise at V = 1.2 V ADP323 VBIAS OUT 2.5V TO VBIAS 43 µV rms typical output noise at VOUT = 2.8 V 5.5V + 1µF Excellent transient response L81o50w 0µ µAds rt ofyappsoitcu tatul vrgnor olotuanng cdeir: c c1uu1rit0r e mntV a att n 2o0 l0o amdA, alolla LdD Os enabled 1.8V5 .T5OV VIN1/VIN2 +1µFEN1OFFON ENL LDDO1 1 FB1 VO+U1Tµ1F Guaranteed 200 mA output current per regulator VBIAS −40°C to +125°C junction temperature VOUT2 LDO 2 ON FB2 + EN2 1µF APPLICATIONS OFF EN LD2 VBIAS Mobile phones 1.8V TO VIN3 Digital cameras and audio devices 5.5V +1µF ON LDO 3 FB3 VO+UT3 Portable and battery-powered equipment EN3 1µF OFF EN LD3 PPoorstta dbcl-et om-decd irceagl udleavtiiocens GND 09288-053 Figure 2. Typical Application Circuit for ADP323 GENERAL DESCRIPTION The ADP322/ADP323 200 mA triple output LDOs combine high The ADP322/ADP323 are available in a miniature 16-lead, 3 mm × PSRR, low noise, low quiescent current, and low dropout voltage 3 mm LFCSP package and are stable with tiny 1 µF ±30% ceramic to extend the battery life of portable devices and are ideally suited output capacitors providing the smallest possible board area for for wireless applications with demanding performance and board a wide variety of portable power needs. space requirements. The ADP322 is available in output voltage combinations ranging The ADP322/ADP323 PSRR is greater than 60 dB for frequencies from 0.8 V to 3.3 V and offers overcurrent and thermal protection as high as 100 kHz while operating with a low headroom voltage. to prevent damage in adverse conditions. The ADP323 adjustable The ADP322/ADP323 offer much lower noise performance than triple LDO can be configured for any output voltage between competing LDOs without the need for a noise bypass capacitor. 0.5 V and 5 V with two resistors for each output. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADP322/ADP323 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Applications Information .............................................................. 17 Typical Application Circuits ............................................................ 1 ADIsimPower Design Tool ....................................................... 17 General Description ......................................................................... 1 Capacitor Selection .................................................................... 17 Revision History ............................................................................... 2 Undervoltage Lockout ............................................................... 18 Specifications ..................................................................................... 3 Enable Feature ............................................................................ 18 Input and Output Capacitor, Recommended Specifications .. 4 Noise Reduction of the ADP323 in Adjustable Mode ........... 19 Absolute Maximum Ratings ............................................................ 5 Current-Limit and Thermal Overload Protection ................. 20 Thermal Data ................................................................................ 5 Thermal Considerations ............................................................ 20 Thermal Resistance ...................................................................... 5 Printed Circuit Board Layout Considerations........................ 22 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 23 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 23 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 10/2018—Rev. D to Rev. E 9/2011—Rev. 0 to Rev. A Change to Figure 56 ....................................................................... 19 Added Figure 2, Renumbered Sequentially ................................... 1 Changes to Ordering Guide .......................................................... 23 Changes to Theory of Operation Section.................................... 15 Added Figure 45, Renumbered Sequentially .............................. 15 3/2017—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 21 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 9/2010—Revision 0: Initial Version 10/2015—Rev. B to Rev. C Changes to Ordering Guide .......................................................... 23 11/2014—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Table 1 ............................................................................ 3 Changes to Figure 30, Figure 31, Figure 32, and Figure 33; Added Figure 34; Renumbered Sequentially .............................. 12 Added Figure 35 and Figure 36; Changes to Figure 38, Figure 39, and Figure 40 ................................................................ 13 Added ADIsimPower Design Tool Section ................................. 17 Added Noise Reduction of the ADP323 in Adjustable Mode Section .............................................................................................. 19 Rev. E | Page 2 of 24

Data Sheet ADP322/ADP323 SPECIFICATIONS V /V = V = (V + 0.5 V) or 1.8 V (whichever is greater), V = 2.5 V, EN1, EN2, EN3 = V , I = I = I = 10 mA, IN1 IN2 IN3 OUT BIAS BIAS OUT1 OUT2 OUT3 C = C = C = C = 1 µF, and T = 25°C, unless otherwise noted. IN OUT1 OUT2 OUT3 A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit VOLTAGE RANGE Input Bias Voltage Range V T = −40°C to +125°C 2.5 5.5 V BIAS J Input LDO Voltage Range V /V /V T = −40°C to +125°C 1.8 5.5 V IN1 IN2 IN3 J CURRENT Ground Current with All I I = 0 µA 85 µA GND OUT Regulators On I = 0 µA, T = −40°C to +125°C 160 µA OUT J I = 10 mA 120 µA OUT I = 10 mA, T = −40°C to +125°C 220 µA OUT J I = 200 mA 250 µA OUT I = 200 mA, T = −40°C to +125°C 380 µA OUT J Bias Voltage Input Current I 66 µA BIAS T = −40°C to +125°C 140 µA J Shutdown Current I EN1 = EN2 = EN3 = GND 0.1 µA GND-SD EN1 = EN2 = EN3 = GND, T = −40°C to +125°C 2.5 µA J FEEDBACK INPUT CURRENT FB 0.01 µA IN VOLTAGE ACCURACY Output Voltage Accuracy V −1 +1 % OUT (ADP322) 100 µA < I < 200 mA, V = (V + 0.5 V) to 5.5 V, −2 +2 % OUT IN OUT T = −40°C to +125°C J Feedback Voltage Accuracy V 0.495 0.5 0.505 V FB (ADP323)1 100 µA < I < 200 mA, V = (V + 0.5 V) to 5.5 V, 0.490 0.510 V OUT IN OUT T = −40°C to +125°C J LINE REGULATION ∆V /∆V V = (V + 0.5 V) to 5.5 V 0.01 %/V OUT IN IN OUT V = (V + 0.5 V) to 5.5 V, T = −40°C to +125°C −0.03 +0.03 %/V IN OUT J LOAD REGULATION2 ∆V /∆I I = 1 mA to 200 mA 0.001 %/mA OUT OUT OUT I = 1 mA to 200 mA, T = −40°C to +125°C 0.005 %/mA OUT J DROPOUT VOLTAGE3 V V = 3.3 V mV DROPOUT OUT I = 10 mA 6 mV OUT I = 10 mA, T = −40°C to +125°C 9 mV OUT J I = 200 mA 110 mV OUT I = 200 mA, T = −40°C to +125°C 170 mV OUT J START-UP TIME4 T V = 3.3 V, all V initially off, enable any LDO 240 µs START-UP OUT OUT V = 0.8 V 100 µs OUT V = 3.3 V, one V initially on, enable second or 160 µs OUT OUT third LDO V = 0.8 V 20 µs OUT CURRENT LIMIT THRESHOLD5 I 250 360 600 mA LIMIT THERMAL SHUTDOWN Thermal Shutdown Threshold TS T rising 155 °C SD J Thermal Shutdown Hysteresis TS 15 °C SD-HYS Rev. E | Page 3 of 24

ADP322/ADP323 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit EN INPUT EN Input Logic High V 2.5 V ≤ V ≤ 5.5 V 1.2 V IH BIAS EN Input Logic Low V 2.5 V ≤ V ≤ 5.5 V 0.4 V IL BIAS EN Input Leakage Current V EN1 = EN2 = EN3 = V or GND 0.1 µA I-LEAKAGE IN EN1 = EN2 = EN3 = V or GND, 1 µA IN T = −40°C to +125°C J UNDERVOLTAGE LOCKOUT UVLO Input Bias Voltage (VBIAS) UVLO 2.45 V RISE Rising Input Bias Voltage (VBIAS) UVLO 2.0 V FALL Falling Hysteresis UVLO 180 mV HYS OUTPUT NOISE OUT 10 Hz to 100 kHz, V = 5 V, V = 3.3 V 50 µV rms NOISE IN OUT 10 Hz to 100 kHz, V = 5 V, V = 2.8 V 43 µV rms IN OUT 10 Hz to 100 kHz, V = 3.6 V, V = 2.5 V 40 µV rms IN OUT 10 Hz to 100 kHz, V = 3.6 V, V = 1.2 V 24 µV rms IN OUT 10 Hz to 100 kHz, V = 3.6 V, V = 0.5 V 14 µV rms IN OUT POWER SUPPLY REJECTION RATIO PSRR V = 1.8 V, V = 0.8 V, I = 100 mA IN OUT OUT 100 Hz 70 dB 1 kHz 70 dB 10 kHz 70 dB 100 kHz 60 dB 1 MHz 40 dB V = 3.3 V, V = 2.8 V, I = 100 mA IN OUT OUT 100 Hz 68 dB 1 kHz 62 dB 10 kHz 68 dB 100 kHz 60 dB 1 MHz 40 dB 1 Accuracy when VOUTx is connected directly to FBx. When the VOUTx voltage is set by external feedback resistors, the absolute accuracy in adjust mode depends on the tolerances of the resistors used. 2 Based on an end point calculation using 1 mA and 200 mA loads. 3 The dropout voltage specification applies only to output voltages greater than 1.8 V. Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. 4 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, that is, 2.7 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE1 C T = −40°C to +125°C 0.70 µF MIN A CAPACITOR ESR R T = −40°C to +125°C 0.001 1 Ω ESR A 1 The minimum input and output capacitance must be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs. Rev. E | Page 4 of 24

Data Sheet ADP322/ADP323 ABSOLUTE MAXIMUM RATINGS Junction to ambient thermal resistance (θ ) of the package is Table 3. JA based on modeling and calculation using a 4-layer board. The Parameter Rating junction to ambient thermal resistance is highly dependent on VIN1/VIN2, VIN3, VBIAS to GND −0.3 V to +6.5 V the application and board layout. In applications where high VOUT1, VOUT2, FB1, FB2 to GND −0.3 V to VIN1/VIN2 maximum power dissipation exists, close attention to thermal VOUT3, FB3 to GND −0.3 V to VIN3 board design is required. The value of θ can vary, depending EN1, EN2, EN3 to GND −0.3 V to +6.5 V JA on PCB material, layout, and environmental conditions. The Storage Temperature Range −65°C to +150°C specified values of θ are based on a 4-layer, 4 inch × 3 inch circuit Operating Junction Temperature Range −40°C to +125°C JA board. See JEDEC JESD 51-9 for detailed information on the Soldering Conditions JEDEC J-STD-020 board construction. For additional information, see the AN-617 Stresses at or above those listed under Absolute Maximum Application Note, MicroCSP™ Wafer Level Chip Scale Package. Ratings may cause permanent damage to the product. This is a Ψ is the junction to board thermal characterization parameter stress rating only; functional operation of the product at these JB with units of °C/W. Ψ of the package is based on modeling and or any other conditions above those indicated in the operational JB calculation using a 4-layer board. The JESD51-12, Guidelines for section of this specification is not implied. Operation beyond Reporting and Using Package Thermal Information, states that the maximum operating conditions for extended periods may thermal characterization parameters are not the same as thermal affect product reliability. resistances. Ψ measures the component power flowing through JB THERMAL DATA multiple thermal paths rather than a single path as in thermal Absolute maximum ratings apply individually only, not in resistance, θJB. Therefore, ΨJB thermal paths include convection combination. from the top of the package as well as radiation from the package, factors that make Ψ more useful in real-world applications. JB The ADP322/ADP323 triple LDO can be damaged when the Maximum junction temperature (T) is calculated from the board J junction temperature limits are exceeded. Monitoring ambient temperature (T ) and power dissipation (P ) using the following B D temperature does not guarantee that the junction temperature formula: (T) is within the specified temperature limits. In applications J with high power dissipation and poor thermal resistance, the TJ = TB + (PD × ΨJB) maximum ambient temperature may have to be derated. In See JEDEC JESD51-8 and JESD51-12 for more detailed infor- applications with moderate power dissipation and low printed mation about Ψ . JB circuit board (PCB) thermal resistance, the maximum ambient THERMAL RESISTANCE temperature can exceed the maximum limit as long as the junction temperature is within specification limits. θJA and ΨJB are specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. The junction temperature (T) of the device is dependent on the J ambient temperature (TA), the power dissipation of the device Table 4. (PD), and the junction to ambient thermal resistance of the package Package Type θJA ΨJB Unit (θJA). Maximum junction temperature (TJ) is calculated from 16-Lead, 3 mm × 3 mm LFCSP 49.5 25.2 °C/W the ambient temperature (TA) and power dissipation (PD) using the following formula: ESD CAUTION T = T + (P × θ ) J A D JA Rev. E | Page 5 of 24

ADP322/ADP323 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 2NE 3NE CNI CIN 6 5 4 3 1 1 1 1 EN1 1 12 GND VBIAS 2 11 NIC ADP322 VIN1/VIN2 3 10 VIN3 NIC 4 9 NIC 5 6 7 8 1 2 C 3 TU TU IN TU O O O V V V TOP VIEW (Not to Scale) N12..O NCTIOECNS =N NECOTT EINXTPEORSNEADL LPYA DC OTONN GERCOTUENDD. PLANE. 09288-002 Figure 3. ADP322 Pin Configuration Table 5. ADP322 Pin Function Descriptions Pin No. Mnemonic Description 1 EN1 Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For automatic startup, connect EN1 to VBIAS. 2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 µF or greater capacitor. 3 VIN1/VIN2 Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 µF or greater capacitor. 4 NIC Not Internally Connected. This pin is not connected internally. 5 VOUT1 Regulated Output Voltage 1. Connect a 1 µF or greater output capacitor between VOUT1 and GND. 6 VOUT2 Regulated Output Voltage 2. Connect a 1 µF or greater output capacitor between VOUT2 and GND. 7 NIC Not Internally Connected. This pin is not connected internally. 8 VOUT3 Regulated Output Voltage 3. Connect a 1 µF or greater output capacitor between VOUT3 and GND. 9 NIC Not Internally Connected. This pin is not connected internally. 10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 µF or greater capacitor. 11 NIC Not Internally Connected. This pin is not connected internally. 12 GND Ground Pin. 13 NIC Not Internally Connected. This pin is not connected internally. 14 NIC Not Internally Connected. This pin is not connected internally. 15 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to VBIAS. 16 EN2 Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For automatic startup, connect EN2 to VBIAS. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane. Rev. E | Page 6 of 24

Data Sheet ADP322/ADP323 2NE 3NE CIN CIN 6 5 4 3 1 1 1 1 EN1 1 12 GND VBIAS 2 11 NIC ADP323 VIN1/VIN2 3 10 VIN3 FB1 4 9 FB3 5 6 7 8 1 2 2 3 T T B T U U F U O O O V V V TOP VIEW (Not to Scale) N12..O NCTIOECNS =N NECOTT EINXTPEORSNEADL LPYA DC OTONN GERCOTUENDD. PLANE. 09288-054 Figure 4. ADP323 Pin Configuration Table 6. ADP323 Pin Function Descriptions Pin No. Mnemonic Description 1 EN1 Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For automatic startup, connect EN1 to VBIAS. 2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 µF or greater capacitor. 3 VIN1/VIN2 Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 µF or greater capacitor. 4 FB1 Connect the midpoint of the voltage divider from VOUT1 to GND to set VOUT1. 5 VOUT1 Regulated Output Voltage 1. Connect a 1 µF or greater output capacitor between VOUT1 and GND. 6 VOUT2 Regulated Output Voltage 2. Connect a 1 µF or greater output capacitor between VOUT2 and GND. 7 FB2 Connect the midpoint of the voltage divider from VOUT2 to GND to set VOUT2. 8 VOUT3 Regulated Output Voltage 3. Connect a 1 µF or greater output capacitor between VOUT3 and GND. 9 FB3 Connect the midpoint of the voltage divider from VOUT3 to GND to set VOUT3. 10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 µF or greater capacitor. 11 NIC Not Internally Connected. This pin is not connected internally. 12 GND Ground Pin. 13 NIC Not Internally Connected. This pin is not connected internally. 14 NIC Not Internally Connected. This pin is not connected internally. 15 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For automatic startup, connect EN3 to VBIAS. 16 EN2 Enable Input for Regulator 2. Drive EN3 high to turn on Regulator 2; drive it low to turn off Regulator 2. For automatic startup, connect EN2 to VBIAS. EP Exposed pad for enhanced thermal performance. Connect to copper ground plane. Rev. E | Page 7 of 24

ADP322/ADP323 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V /V = V =V = 4 V, V = 3.3 V, V = 1.8 V, V = 1.5 V, I = 10 mA, C = C = C = C = 1 µF, V is the IN1 IN2 IN3 BIAS OUT1 OUT2 OUT3 OUT IN OUT1 OUT2 OUT3 ENX enable voltage, T = 25°C, unless otherwise noted. A 3.33 1.820 LOAD = 1mA LOAD = 1mA LOAD = 5mA LOAD = 5mA LOAD = 10mA 1.815 LOAD = 10mA 3.32 LOAD = 50mA LOAD = 50mA LOAD = 100mA LOAD = 100mA LOAD = 200mA 1.810 LOAD = 200mA 3.31 1.805 V) V) (UT3.30 (UT1.800 O O V V 1.795 3.29 1.790 3.28 1.785 3.27 1.780 –40 –5 TJ2 (5°C) 85 125 09288-003 –40 –5 TJ2 (5°C) 85 125 09288-006 Figure 5. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 µF Figure 8. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 µF 3.320 1.820 3.315 1.815 V (V)OUT3.310 V (V)OUT1.810 3.305 1.805 3.3001 10 ILOAD (mA) 100 1000 09288-004 1.8001 10 ILOAD (mA) 100 1000 09288-007 Figure 6. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 µF Figure 9. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 µF 3.320 1.820 LOAD = 1mA LOAD = 1mA LOAD = 5mA LOAD = 5mA LOAD = 10mA LOAD = 10mA LOAD = 50mA LOAD = 50mA LOAD = 100mA LOAD = 100mA 3.315 LOAD = 200mA 1.815 LOAD = 200mA V) V) (UT3.310 (UT1.810 O O V V 3.305 1.805 3.300 1.800 3.6 3.8 4.0 4.2 4.4VIN 4(V.6) 4.8 5.0 5.2 5.4 09288-005 2.1 2.5 2.9 3.3 3V.I7N (V)4.1 4.5 4.9 5.3 09288-008 Figure 7. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 µF Figure 10. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 µF Rev. E | Page 8 of 24

Data Sheet ADP322/ADP323 1.520 140 LOAD = 1mA LOAD = 5mA 1.515 LOAD = 10mA 120 LOAD = 50mA LOAD = 100mA 1.510 LOAD = 200mA A) 100 µ 1.505 NT ( (V)UT1.500 URRE 80 O C V D 60 1.495 UN O 1.490 GR 40 LOAD = 1mA LOAD = 5mA 1.485 20 LLOOAADD == 1500mmAA LOAD = 100mA LOAD = 200mA 1.480 –40 –5 TJ2 (5°C) 85 125 09288-009 0 –40 –5 TJ2 (5°C) 85 125 09288-012 Figure 11. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 µF Figure 14. Ground Current vs. Junction Temperature, Single Output Loaded, VRIPPLE = 50 mV, COUT = 1 µF 1.510 120 100 1.508 A) T (µ 80 1.506 N (V)UT URRE 60 O C V1.504 ND U O 40 R G 1.502 20 1.500 0 1 10 ILOAD (mA) 100 1000 09288-010 1 10 ILOAD (mA) 100 1000 09288-013 Figure 12. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 µF Figure 15. Ground Current vs. Load Current, Single Output Loaded, VRIPPLE = 50 mV, COUT = 1 µF 1.510 120 LOAD = 1mA LOAD = 5mA LOAD = 10mA 1.508 LLOOAADD == 5100m0mAA 100 LOAD = 200mA A) V)1.506 ENT (µ 80 V (OUT1.504 D CURR 60 N U O 40 R G LOAD = 1mA 1.502 LOAD = 5mA 20 LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.500 1.80 2.20 2.60 3.00 3.40VIN 3(V.8)0 4.20 4.60 5.00 5.40 09288-011 01.8 2.2 2.6 3.0 3.4VIN (3V.)8 4.2 4.6 5.0 5.4 09288-014 Figure 13. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 µF Figure 16. Ground Current vs. Input Voltage, Single Output Loaded, VRIPPLE = 50 mV, COUT = 1 µF Rev. E | Page 9 of 24

ADP322/ADP323 Data Sheet 350 120 300 100 A) 250 D CURRENT (µ 125000 CURRENT (µA) 6800 GROUN 100 LOAD = 1mA BIAS 40 LOAD = 1mA LOAD = 5mA LOAD = 5mA LOAD = 10mA 20 LOAD = 10mA 50 LOAD = 50mA LOAD = 50mA LOAD = 100mA LOAD = 100mA LOAD = 200mA LOAD = 200mA 0 0 –40 –5 TJ2 (5°C) 85 125 09288-015 –40 –5 TJ2 (5°C) 85 125 09288-018 Figure 17. Ground Current vs. Junction Temperature, Figure 20. Bias Current vs. Junction Temperature, Single Output Loaded, All Outputs Loaded Equally, VRIPPLE = 50 mV, COUT = 1 µF VRIPPLE = 50 mV, COUT = 1 µF 300 100 90 250 80 A) T (µ 200 µA) 70 EN T ( 60 R N R E CU 150 RR 50 UND S CU 40 O 100 A GR BI 30 50 20 10 01 TOT1A0L LOAD CURRENT1 (0m0A) 1000 09288-016 01 10 ILOAD (mA) 100 1000 09288-019 Figure 18. Ground Current vs. Load Current, All Outputs Loaded Equally, Figure 21. Bias Current vs. Load Current, Single Output Loaded, VRIPPLE = 50 mV, COUT = 1 µF VRIPPLE = 50 mV, COUT = 1 µF 300 76 250 74 LOAD = 1mA LOAD = 5mA A) LOAD = 10mA ENT (µ 200 T (µA) 72 LLLOOOAAADDD === 512000m00mmAAA R N R E CU 150 RR 70 ROUND 100 BIAS CU 68 G LOAD = 1mA LOAD = 5mA 50 LOAD = 10mA 66 LOAD = 50mA LOAD = 100mA LOAD = 200mA 0 64 1.7 2.1 2.5 2.9 3.3VIN 3(V.7) 4.1 4.5 4.9 5.3 09288-017 2.5 2.9 3.3 3.7 VIN (4V.1) 4.5 4.9 5.3 09288-020 Figure 19. Ground Current vs. Input Voltage, All Outputs Loaded Equally, Figure 22. Bias Current vs. Input Voltage, Single Output Loaded, VRIPPLE = 50 mV, COUT = 1 µF VRIPPLE = 50 mV, COUT = 1 µF Rev. E | Page 10 of 24

Data Sheet ADP322/ADP323 0.9 350 3.6 3.8 0.8 4.2 300 4.4 WN CURRENT (µA) 0000....4567 45..85 ND CURRENT (µA) 122505000 O U SHUTD 00..23 GRO 100 LLOOAADD == 15mmAA LOAD = 10mA 0.1 50 LOAD = 50mA LOAD = 100mA LOAD = 200mA 0 0 –50 –25 0 TE2M5PERAT5U0RE (°C7)5 100 125 09288-021 3.10 3.15 3.20 3.25 V3IN.3 (0V) 3.35 3.40 3.45 3.50 09288-024 Figure 23. Shutdown Current vs. Temperature at Various Input Voltages, Figure 26. Ground Current vs. Input Voltage (in Dropout), VOUT1 = 3.3 V, VRIPPLE = 50 mV, COUT = 1 µF VRIPPLE = 50 mV, COUT = 1 µF 100 300 90 250 80 70 200 V) V) m 60 m T ( T ( OU 50 OU 150 P P O O R 40 R D D 100 30 20 50 10 01 10 LOAD (mA) 100 1000 09288-022 01 10 LOAD (mA) 100 1000 09288-025 Figure 24. Dropout Voltage vs. Load Current and Output Voltage, Figure 27. Dropout Voltage vs. Load Current and Output Voltage, VOUT1 = 3.3 V, VRIPPLE = 50 mV, COUT = 1 µF VOUT2 = 1.8 V, VRIPPLE = 50 mV, COUT = 1 µF 3.35 1.85 LOAD = 1mA LOAD = 5mA 3.30 LOAD = 10mA 1.80 LOAD = 50mA LOAD = 100mA 3.25 LOAD = 200mA 1.75 3.20 1.70 V (V)OUT3.15 V (V)OUT1.65 3.10 1.60 LOAD = 1mA 3.05 1.55 LOAD = 5mA LOAD = 10mA 3.00 1.50 LOAD = 50mA LOAD = 100mA LOAD = 200mA 2.953.10 3.15 3.20 3.25 VI3N. 3(0V) 3.35 3.40 3.45 3.50 09288-023 1.451.70 1.80 1.9V0IN (V) 2.00 2.10 09288-026 Figure 25. Output Voltage vs. Input Voltage (in Dropout), Figure 28. Output Voltage vs. Input Voltage (in Dropout), VOUT1 = 3.3 V, VRIPPLE = 50 mV, COUT = 1 µF VOUT2 = 1.8 V, VRIPPLE = 50 mV, COUT = 1 µF Rev. E | Page 11 of 24

ADP322/ADP323 Data Sheet 160 0 10mA 140 –10 120000mmAA –20 A) 120 µ –30 NT ( 100 RE B) –40 D CUR 80 SRR (d –50 UN 60 P –60 O GR 40 LOAD = 1mA –70 LOAD = 5mA LOAD = 10mA –80 20 LOAD = 50mA LOAD = 100mA –90 LOAD = 200mA 01.70 1.80 1V.9IN0 (V) 2.00 2.10 09288-027 –1001 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M 09288-029 Figure 29. Ground Current vs. Input Voltage (in Dropout), VOUT2 = 1.8 V, Figure 32. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VRIPPLE = 50 mV, COUT = 1 µF VIN = 4.3 V, VRIPPLE = 50 mV, COUT = 1 µF 0 0 10mA 10mA –10 120000mmAA –10 120000mmAA –20 –20 –30 –30 PSRR (dB) –––654000 PSRR (dB) –––654000 –70 –70 –80 –80 –90 –90 –1001 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M 09288-028 –1001 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M 09288-131 Figure 30. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V, Figure 33. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 2.8 V, VRIPPLE = 50 mV, COUT = 1 µF VIN = 3.8 V, VRIPPLE = 50 mV, COUT = 1 µF 0 0 10mA –10 1100m0mAA –10 120000mmAA 200mA –20 –20 –30 –30 B) –40 dB) –40 R (d –50 RR ( –50 R S PS –60 P –60 –70 –70 –80 –80 –90 –90 –1001 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M 09288-129 –1001 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M 09288-030 Figure 31. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V, Figure 34. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.5 V, VIN = 2.3 V, VRIPPLE = 50 mV, COUT = 1 µF VIN = 2.5 V, VRIPPLE = 50 mV, COUT = 1 µF Rev. E | Page 12 of 24

Data Sheet ADP322/ADP323 0 10k 10mA –10 120000mmAA 11..58VV –20 √Hz) 23..53VV V/ 1k n –30 Y ( T B) –40 NSI d E RR ( –50 AL D100 PS –60 TR C E –70 SP E 10 –80 OIS N –90 –1001 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M 09288-133 11 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M 09288-032 Figure 35. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.5 V, Figure 38. Output Noise Spectral Density, VIN = 5 V, ILOAD = 10 mA, VIN = 2.0 V, VRIPPLE = 50 mV, COUT = 1 µF VRIPPLE = 50 mV, COUT = 1 µF 0 50 10mA –10 100mA 200mA –20 40 –30 s) PSRR (dB) –––654000 NOISE (µV rm 2300 112...585VVV 3.3V –70 –80 10 –90 –1001 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M 09288-134 00.001 0.01 0L.1OAD CUR1RENT (mA1)0 100 1000 09288-033 Figure 36. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.2 V, Figure 39. 10 Hz to 100 kHz Output Noise vs. Load Current and Output Voltage, VIN = 2.2 V, VRIPPLE = 50 mV, COUT = 1 µF VIN = 5 V, VRIPPLE = 50 mV, COUT = 1 µF 0 50 1.8V/200mA 1V HEADROOM –10 11..88VV//11000mmAA 1.8V PSRR 1.2V/200mA 1.2 XTALK –20 1.2V/100mA 40 1.2V/10mA –30 PSRR (dB) –––654000 OISE (µV rms) 2300 1.5V N 1.8V –70 2.5V 3.3V –80 10 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09288-031 00.001 0.01 0L.1OAD CUR1RENT (mA1)0 100 1000 09288-138 Figure 37. Power Supply Rejection Ratio vs. Frequency, Figure 40. 100 Hz to 100 kHz Output Noise vs. Load Current and Output Voltage, Channel to Channel Crosstalk, VRIPPLE = 50 mV, COUT = 1 µF VIN = 5 V, VRIPPLE = 50 mV, COUT = 1 µF Rev. E | Page 13 of 24

ADP322/ADP323 Data Sheet ILOAD1 ILOAD3 1 1 2 VOUT1 VOUT3 2 VOUT2 3 4 VOUT3 CCHH13 11000mmVA ΩBBWW CCHH24 5100mmVV BBWW MT 4 09.µ8s% A CH1 44mA 09288-034 CH1 200mA ΩBW CH2 50mV BW MT 4 010µ.s2%A CH1 124mA 09288-037 Figure 41. Load Transient Response, Figure 44. Load Transient Response, ILOAD1 = 1 mA to 200 mA, ILOAD2 = ILOAD3 = 1 mA, CH1 = ILOAD1, ILOAD3 = 1 mA to 200 mA, COUT3 = 1 μF, CH1 = ILOAD3, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF CH2 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF ILOAD1 VIN 1 1 2 VOUT1 2 VOUT1 3 VOUT2 4 VOUT3 CH1 200mA ΩBW CH250mV BW MT 4 100µ.s2%A CH1 124mA 09288-035 CCHH13 11V0mV BBWW CCHH24 1100mmVV BBWW MT 1 1µ5s% A CH1 4.62V 09288-038 Figure 42. Load Transient Response, Figure 45. Line Transient Response, ILOAD1 = 1 mA to 200 mA, COUT1 = 1 μF, CH1 = ILOAD1, VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =100 mA, CH1 = VIN, CH2 = VOUT1, VRIPPLE = 50 mV, COUT = 1 µF CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF ILOAD2 VIN 1 1 2 VOUT1 VOUT2 VOUT2 2 3 4 VOUT3 CH1 200mA ΩBW CH250mV BW MT 4 100µ.s4%A CH1 84mA 09288-036 CCHH13 110VmV BBWW CCHH241100mmVV BBWW MT 2 1µ2s% A CH1 4.58V 09288-039 Figure 43. Load Transient Response, ILOAD2 = 1 mA to 200 mA, COUT2 = 1 μF, Figure 46. Line Transient Response, CH1 = ILOAD2, CH2 = VOUT2, VRIPPLE = 50 mV, COUT = 1 µF VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =1 mA, CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF Rev. E | Page 14 of 24

Data Sheet ADP322/ADP323 VENx VOUT1 1 VOUT2 VOUT3 2 CCHH13 15V00mV BBWW CCHH42 550000mmVV BBWW MT 1 1000.µ2s%A CH1 540mV 09288-040 Figure 47. Turn On Response, ILOAD1 = ILOAD2 = ILOAD3 =100 mA, CH1 = VENx (the Enable Voltage), CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF Rev. E | Page 15 of 24

ADP322/ADP323 Data Sheet THEORY OF OPERATION The ADP322/ADP323 triple LDO are low quiescent current, LDOs The output voltage can be set using the following formulas: that operate from 1.8 V to 5.5 V on VIN1/VIN2 and VIN3 and V = 0.5 V(1 + R1/R2) + (FB )(R1) provide up to 200 mA of current from each output. Drawing a low OUT IN 250 μA quiescent current (typical) at full load makes the ADP322/ VOUT2 = 0.5 V(1 + R3/R4) + (FBIN)(R3) ADP323 ideal for battery operated portable equipment. Shutdown V = 0.5 V(1 + R5/R6) + (FB )(R5) OUT3 IN current consumption is typically 100 nA. Optimized for use with The value of R1, R3, R5 must be less than 200 kΩ to minimize small 1 µF ceramic capacitors, the ADP322/ADP323 provide errors in the output voltage caused by the FBx pin input current. excellent transient performance. For example, when R1 and R2 each equal 200 kΩ, the output Internally, the ADP322 consists of a reference, three error voltage is 1.0 V. The output voltage error introduced by the FBx amplifiers, three feedback voltage dividers, and three PMOS pin input current is 2 mV or 0.20%, assuming a typical FBx pin pass transistors. Output current is delivered via the PMOS pass input current of 10 nA at 25°C. device, which is controlled by the error amplifier. The error The ADP322 is available in multiple output voltage options amplifier compares the reference voltage with the feedback voltage ranging from 0.8 V to 3.3 V. from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is The ADP322/ADP323 use the EN1/EN2 and EN3 pins to enable pulled lower, allowing more current to flow and increasing the and disable the VOUT1/VOUT2/VOUT3 pins under normal output voltage. If the feedback voltage is higher than the reference operating conditions. When the EN1/EN2 and EN3 pins are high, voltage, the gate of the PMOS device is pulled higher, allowing VOUT1/VOUT2/VOUT3 turn on; when the EN1/EN2 and EN3 less current to flow and decreasing the output voltage. pins are low, VOUT1/VOUT2/VOUT3 turn off. For automatic startup, the EN1/EN2 and EN3 pins can be tied to VBIAS. VIN1/VIN2 VOUT1 ADP323 + VBIAS VUOVLILTNOATG PEARERNOSND/TAC TELUHC RBETRIRAEMSNATLS, OVERCURRENT 0R.E5VF– 2.5V5.T5OV +1µF VBIAS VBIAS SHUTDOWN VOUT2 EN1 VOUT1 1.8VTO VIN1/VIN2 VOUT1 EN2 SHVUOTDUOT2WN OVERCURRENT +– 5.5V +1µFEN1OFFON ENL LDDO1 1 FB1 R1 +1µF EN3 SHVUOTDUOT3WN 0R.E5VF VBIAS R2 VOUT2 VIN3 VOUT3 EN2 ON LDO 2 FB2 R3 +1µF GND + OFF EN LD2 OVERCURRENT – R4 VBIAS Figure 48. ADP322 Internal Block Diag0R.Er5aVFm 09288-041 1.8V5.T5OV +1µFEN3OVFIFNO3N ENL LDDO3 3 FB3 R5 VO+U1Tµ3F R6 Tvohleta AgeD dPi3v2id3 edrisf faerres ifnrtoemrn tahlley AdDiscPo3n2n2 eecxtceedp at nind tthhaet fteheed boauctpku t GND 09288-145 inputs of the error amplifiers are brought out for each output. Figure 50. ADP323 Application Circuit Diagram VIN1/VIN2 VOUT1 + FB1 INTERNAL BIAS OVERCURRENT – VBIAS VUOVLLTOAG AENSD/C TUHRERREMNATLS, 0.5V PROTECT REF SHUTDOWN VOUT2 EN1 VOUT1 EN2 SHVUOTDUOT2WN OVERCURRENT +– FB2 EN3 SHVUOTDUOT3WN 0R.E5VF VIN3 VOUT3 GND + FB3 OVERCURRENT – 0R.E5VF 09288-055 Figure 49. ADP323 Internal Block Diagram Rev. E | Page 16 of 24

Data Sheet ADP322/ADP323 APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL Input Bypass Capacitor The ADP323 is supported by the ADIsimPower design tool set. Connecting a 1 µF capacitor from VIN1/VIN2, VIN3, and ADIsimPower is a collection of tools that produce complete VBIAS to GND reduces the circuit sensitivity to the PCB layout, power designs optimized for a specific design goal. The tools especially when long input traces or high source impedance is enable the user to generate a full schematic, bill of materials, encountered. If an output capacitance greater than 1 µF is and calculate performance in minutes. ADIsimPower can required, the input capacitor can be increased to match it. optimize designs for cost, area, efficiency, and parts count, Input and Output Capacitor Properties taking into consideration the operating conditions and limitations Any good quality ceramic capacitor can be used with the ADP322/ of the IC and all real external components. For more information ADP323, as long as the capacitor meets the minimum capacit- about, and to obtain ADIsimPower design tools, visit ance and maximum ESR requirements. Ceramic capacitors are www.analog.com/ADIsimPower. manufactured with a variety of dielectrics, each with a different CAPACITOR SELECTION behavior over temperature and applied voltage. Capacitors must Output Capacitor have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R The ADP322/ADP323 are designed for operation with small, or X7R dielectrics with a voltage rating of 6.3 V or 10 V are space-saving ceramic capacitors, but the devices function with recommended. Y5V and Z5U dielectrics are not recommended most commonly used capacitors as long as care is taken with the due to their poor temperature and dc bias characteristics. effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum Figure 52 depicts the capacitance vs. voltage bias characteristic of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a to ensure the stability of the ADP322/ADP323. capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or with a higher Transient response to changes in load current is also affected by voltage rating exhibits better stability. The temperature variation output capacitance. Using a larger value of output capacitance of the X5R dielectric is about ±15% over the −40°C to +85°C improves the transient response of the ADP322/ADP323 to large temperature range and is not a function of the package or changes in the load current. Figure 51 shows the transient voltage rating. response for an output capacitance value of 1 µF. 1.2 ILOAD1 1.0 1 F) 0.8 µ E ( C N 2 VOUT1 TA 0.6 CI A P CA 0.4 VOUT2 3 4 VOUT3 0.2 CCHH31 1100m0mVAΩBBWW CCHH24 5100mmVV BBWW MT 4 09µ.8s% A CH1 44mA 09288-042 00 2 V4OLTAGE (V6) 8 10 09288-043 Figure 51. Output Transient Response, Figure 52. Capacitance vs. Voltage Bias Characteristic ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA, ILOAD3 = 1 mA, CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 Rev. E | Page 17 of 24

ADP322/ADP323 Data Sheet Use Equation 1 to determine the worst case capacitance, As shown in Figure 53, the ENx pin has built in hysteresis. This accounting for capacitor variation over temperature, compo- prevents on/off oscillations that can occur due to noise on the nent tolerance, and voltage. ENx pin as it passes through the threshold points. C = C × (1 − TEMPCO) × (1 − TOL) (1) The active/inactive thresholds of the ENx pin are derived from EFF BIAS the V voltage. Therefore, these thresholds vary with changing where: BIAS input voltage. Figure 54 shows typical ENx active/ inactive C is the effective capacitance at the operating voltage. BIAS thresholds when the input voltage varies from 2.5 V to 5.5 V TEMPCO is the worst case capacitor temperature coefficient. (note that V is the enable voltage). TOL is the worst case component tolerance. ENx 1.00 In this example, TEMPCO over −40°C to +85°C is assumed to 0.95 be 15% for an X5R dielectric. TOL is assumed to be 10%, and C is 0.94 μF at 1.8 V (from the graph in Figure 52). 0.90 BIAS S D0.85 Substituting these values into Equation 1 yields L O H0.80 CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF RES VENx RISE VENxFALL H0.75 Therefore, the capacitor chosen in this example meets the E T L0.70 minimum capacitance requirement of the LDO over temperature B A and tolerance at the chosen output voltage. EN0.65 0.60 To guarantee the performance of the ADP322/ADP323 triple 0.55 LDO, it is imperative that the effects of dc bias, temperature, afonrd e taoclhe raapnpcleisc aotnio tnh.e behavior of the capacitors be evaluated 0.502.5 3.0 3.5INPUT VO4.L0TAGE (V4).5 5.0 5.5 09288-045 UNDERVOLTAGE LOCKOUT Figure 54. Typical ENx Pins Thresholds vs. Input Voltage The ADP322/ADP323 have an internal undervoltage lockout The ADP322/ADP323 use an internal soft start to limit the circuit that disables all inputs and the output when the input inrush current when the output is enabled. The start-up time voltage bias, VBIAS, is less than approximately 2.2 V. This ensures for the 2.8 V option is approximately 220 µs from the time the that the inputs of the ADP322/ADP323 and the output behave ENx active threshold is crossed to when the output reaches 90% in a predictable manner during power-up. of its final value. The start-up time is somewhat dependent on the output voltage setting and increases slightly as the output ENABLE FEATURE voltage increases. The ADP322/ADP323 use the ENx pins to enable and disable the VOUTx pins under normal operating conditions. Figure 53 shows that, when a rising voltage on ENx crosses the active VENx VOUT1 threshold, VOUTx turns on. When a falling voltage on ENx crosses the inactive threshold, VOUTx turns off. 1 1.4 VOUT2 1.2 VOUT @ 4.5VIN VOUT3 1.0 0.8 V) (OUT 0.6 2 V 0.4 CCHH13 15V00mV BBWW CCHH42 550000mmVV BBWW MT 1 1000.µ2s%A CH1 540mV 09288-046 0.2 Figure 55. Typical Start-Up Time, ILOAD1 = ILOAD2 = ILOAD3 = 100 mA, CH1 = VENx (the Enable Voltage), CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 0 0.4 0.5 0.6 EN0A.7BLE V0O.8LTAGE0. 9(V) 1.0 1.1 1.2 09288-044 Figure 53. Typical ENx Pin Operation Rev. E | Page 18 of 24

Data Sheet ADP322/ADP323 NOISE REDUCTION OF THE ADP323 IN The noise of the adjustable LDO is found by using the following ADJUSTABLE MODE formula, assuming the noise of the 500 mV output is approxi- mately 14 μV. The adjustable LDO circuit can be modified to reduce the output voltage noise to levels close to that of the 500 mV output ADP323. Noise = 14 μV × (RPAR + R2)/R2 (1) The circuit shown in Figure 56 adds two additional components where R is a parallel combination of R1 and RNR. PAR to the output voltage setting resistor divider. CNR and RNR are Based on the component values shown in Figure 56, the ADP323 added in parallel with R1 to reduce the ac gain of the error has the following characteristics: amplifier. RNR is chosen to be small with respect to R2. If RNR is 1% to 10% of the value of R2, the minimum ac gain of the error • DC gain of 5 (13.98 dB) amplifier is approximately 0.1 dB to 0.8 dB. The actual gain is • 3 dB roll-off frequency of 0.79 Hz determined by the parallel combination of RNR and R1. This • High frequency ac gain of 1.02 (0.17 dB) gain ensures that the error amplifier always operates at slightly • Theoretical noise reduction factor of 4.9 (13.8 dB) greater than unity gain. • Measured rms noise of the adjustable LDO without noise CNR is chosen by setting the reactance of CNR equal to R1 − RNR reduction is 39.5 µV rms at a frequency between 1 Hz and 50 Hz. This setting places the • Measured rms noise of the adjustable LDO with noise frequency where the ac gain of the error amplifier is 3 dB down reduction is 14.4 µV rms from its dc gain. • Measured noise reduction of approximately 8.8 dB ADP323 VBIAS 2.5V TO VBIAS 5.5V + 1µF 3.0V TO VIN1/VIN2 VOUT1 = 1.5V 5.5V + LDO 1 R1 1µFEN1OFFON EN LD1 FB1 RNR1100kΩ 1µF 1kΩ VBIAS R2 CNR1 50kΩ 1µF VOUT2 = 2.5V LDO 2 ON R3 EN2OFF EN LD2 FB2 200kΩ 1µF RNR2 1kΩ VBIAS R4 CNR2 50kΩ 1µF VOUT3 = 3.3V 3.8V5 .T5OVVIN3 + LDO 3 R5 1µF ON EN LD3 FB3 200kΩ 1µF EN3 RNR3 OFF 1kΩ R6 CNR3 GND 35.7kΩ 1µF 09288-156 Figure 56. Noise Reduction Modification Rev. E | Page 19 of 24

ADP322/ADP323 Data Sheet Note that the measured noise reduction is less than the theoretical Consider the case where a hard short from VOUTx to GND noise reduction. Figure 57 shows the noise spectral density of an occurs. At first, the ADP322/ADP323 limits current so that only adjustable ADP323 set to 500 mV and 2.5 V with and without the 300 mA is conducted into the short. If self heating of the junction noise reduction network. The output noise with the noise reduction is great enough to cause its temperature to rise above 155°C, network is approximately the same for both voltages, especially thermal shutdown activates, turning off the output and reducing beyond 10 Hz. The noise of the 500 mV and 2.5 V outputs without the output current to zero. As the junction temperature cools the noise reduction network differs by a factor of 5 up to approxi- and drops below 140°C, the output turns on and conducts 300 mA mately 10 kHz. Above 20 kHz, the closed loop gain of the error into the short, again causing the junction temperature to rise amplifier is limited by its open loop gain characteristic. Therefore, above 155°C. This thermal oscillation between 140°C and 155°C the noise contribution from 20 kHz to 100 kHz is less than what causes a current oscillation between 0 mA and 300 mA that it can be if the error amplifier had infinite bandwidth. This is continues as long as the short remains at the output. also the reason why the noise is less than what might be expected Current and thermal limit protections are intended to protect simply based on the dc gain, that is, 39.5 µV rms vs. 70 µV rms. the device against accidental overload conditions. For reliable 10k operation, device power dissipation must be externally limited so that junction temperatures do not exceed 125°C. 2.5VWITHNR Hz) 25.050VmWVITHOUTNR THERMAL CONSIDERATIONS √ V/ 1k Y (n In most applications, the ADP322/ADP323 do not dissipate a lot SIT of heat due to high efficiency. However, in applications with a high N E ambient temperature and high supply voltage to output voltage D L 100 differential, the heat dissipated in the package is large enough A R T that it can cause the junction temperature of the die to exceed C E the maximum junction temperature of 125°C. P S SE 10 When the junction temperature exceeds 155°C, the converter OI N enters thermal shutdown. It recovers only after the junction temperature decreases below 140°C to prevent any permanent 1 damage. Therefore, thermal analysis for the chosen application 1 10 100 FRE1kQUENC1Y0 k(Hz) 100k 1M 10M 09288-157 icso vnedriyti iomnsp.o Trhtaen jtu tnoc gtiuoanr atnemtepe errealitaubrlee o pfe trhfoe rdmiea insc teh oev seurm al lo f Figure 57. 500 mV and 2.5 V Output Voltage with and Without Noise the ambient temperature of the environment and the temperature Reduction Network rise of the package due to the power dissipation, as shown in CURRENT-LIMIT AND THERMAL OVERLOAD Equation 2. PROTECTION To guarantee reliable operation, the junction temperature of the The ADP322/ADP323 are protected against damage due to ADP322/ADP323 must not exceed 125°C. To ensure that the excessive power dissipation by current and thermal overload junction temperature stays below this maximum value, the user protection circuits. The ADP322/ADP323 are designed to must be aware of the parameters that contribute to junction current limit when the output load reaches 300 mA (typical). temperature changes. These parameters include ambient tem- When the output load exceeds 300 mA, the output voltage is perature, power dissipation in the power device, and thermal reduced to maintain a constant current limit. resistances between the junction and ambient air (θ ). The θ JA JA Thermal overload protection is built in, which limits the number is dependent on the package assembly compounds used junction temperature to a maximum of 155°C (typical). Under and the amount of copper to which the GND pins of the package extreme conditions (that is, high ambient temperature and are soldered on the PCB. Table 7 shows typical θJA values for the power dissipation) when the junction temperature starts to ADP322/ADP323 for various PCB copper sizes. rise above 155°C, the output is turned off, reducing the output Table 7. Typical θ Values current to zero. When the junction temperature drops below JA Copper Size (mm2) ADP322/ADP323 Triple LDO (°C/W) 140°C, the output is turned on again and the output current JEDEC1 49.5 is restored to its nominal value. 100 83.7 500 68.5 1000 64.7 1 Device soldered to JEDEC standard board. Rev. E | Page 20 of 24

Data Sheet ADP322/ADP323 The junction temperature of the ADP322/ADP323 can be 140 calculated from the following equation: 120 C) wherTe:J = TA + (PD × θJA) (2) E, T (°J100 R U TA is the ambient temperature. AT 80 R P is the power dissipation in the die, given by E D P M E 60 PD = Σ[(VIN − VOUT) × ILOAD] + Σ(VIN × IGND) (3) N T O where: TI 40 C 1000mm2 IILOAD i sis t hthee g lrooaudn cdu crruernret.n t. JUN 20 51500000mmmmmm222 GND JEDEC PVoINw aenrd d VissOiUpTa atrioe nin dpuuet taon gdr oouutnpdu tc uvorrletangte iss, qreusiptee csmtivaellly a. nd 00 0.2 TOTA0L.4 POWER0 D.6ISSIPATI0O.8N (W) 1.T0J MAX 1.2 09288-048 can be ignored. Therefore, the junction temperature equation Figure 59. Junction Temperature vs. Total Power Dissipation, TA = 50°C simplifies to 140 T = T + {Σ[(V − V ) × I ] × θ } (4) J A IN OUT LOAD JA As shown in Equation 4, for a given ambient temperature, input C) 120 etox iostust pa umt vinoilmtaugem d cifofeprpeenrt isaizl,e a rnedq uciornemtineunot ufos rl othade PcuCrBre tnot ,e tnhseurree RE, T (°J100 U that the junction temperature does not rise above 125°C. Figure 58 AT 80 R to Figure 61 show junction temperature calculations for different PE M ambient temperatures, total power dissipation, and areas of TE 60 N PCB copper. O TI 40 C 1000mm2 In cases where the board temperature is known, the thermal UN 500mm2 characterization parameter, ΨJB, can be used to estimate the J 20 51000mmmm22 JEDEC junction temperature rise. TJ is calculated from TB and PD using 0 TJ MAX the formula 0 0.2 TOTA0L.4 POWER0 D.6ISSIPATI0O.8N (W) 1.0 1.2 09288-049 T = T + (P × Ψ ) (5) J B D JB Figure 60. Junction Temperature vs. Total Power Dissipation, TA = 85°C The typical Ψ value for the 16-lead, 3 mm × 3 mm LFCSP is JB 140 25.2°C/W. 140 C) 120 ATURE, T (°C)J11028000 EMPERATURE, T (°J1068000 ER N T P O N TEM 60 UNCTI 40 JUNCTIO 24000 1515JT0000EJ 000mDM0mmEmmAmmC2Xm222 J 2000 0.2 0.4TOTA0L.6 POW0E.8R DIS1S.0IPATI1O.2N (W)1.4 TTTTBBBJ 1M===.6 A258X505°°°CCC1.8 09288-050 0 0.2 TOTA0L.4 POWER0 D.6ISSIPATI0O.8N (W) 1.0 1.2 09288-047 Figure 61. Junction TemBopaerradt Tuerme vpse. rTaottuarle P ower Dissipation and Figure 58. Junction Temperature vs. Total Power Dissipation, TA = 25°C Rev. E | Page 21 of 24

ADP322/ADP323 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP322/ ADP323. However, as can be seen from Table 7, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VINx and GND pins. Place the output capacitors as close as possible to the VOUTx and GND pins. Use 0402 or 0603 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited. 09288-051 Figure 62. Example of PCB Layout, Top Side 09288-052 Figure 63. Example of PCB Layout, Bottom Side Rev. E | Page 22 of 24

Data Sheet ADP322/ADP323 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 3.10 0.30 3.00 SQ 0.23 PIN 1 INDICATOR 2.90 0.18 AREA 0.50 13 16 PI(SNIENDE I1CDAETTAOIRLAA)REAOPTIONS BSC 12 1 1.75 EXPOSED 1.60 SQ PAD 1.45 9 4 0.50 8 5 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 SIDE VIEW THE EXPOSED PAD, REFER TO 0.70 0.05 MAX THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF PKG-005138 COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6 08-24-2018-E Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Temperature Output Voltage (V)2 Package Marking Model1 Range VOUT1 VOUT2 VOUT3 Package Description Option Code ADP322ACPZ-115-R7 −40°C to +125°C 3.3 V 2.8 V 1.8 V 16-Lead LFCSP CP-16-22 LGU ADP322ACPZ-135-R7 −40°C to +125°C 3.3 V 2.5 V 1.8 V 16-Lead LFCSP CP-16-22 LGT ADP322ACPZ-145-R7 −40°C to +125°C 3.3 V 2.5 V 1.2 V 16-Lead LFCSP CP-16-22 LJC ADP322ACPZ-155-R7 −40°C to +125°C 3.3 V 1.8 V 1.5 V 16-Lead LFCSP CP-16-22 LGS ADP322ACPZ-165-R7 −40°C to +125°C 3.3 V 1.8 V 1.2V 16-Lead LFCSP CP-16-22 LLX ADP322ACPZ-175-R7 −40°C to +125°C 2.8 V 1.8 V 1.2 V 16-Lead LFCSP CP-16-22 LGR ADP322ACPZ-189-R7 −40°C to +125°C 2.5 V 1.8 V 1.2 V 16-Lead LFCSP CP-16-22 LJD ADP323ACPZ-R7 −40°C to +125°C Adjustable Adjustable Adjustable 16-Lead LFCSP CP-16-22 LGQ ADP323CP-EVALZ Evaluation board 1 Z = RoHS Compliant Part. 2 For additional voltage options, contact a local sales or distribution representative. Rev. E | Page 23 of 24

ADP322/ADP323 Data Sheet NOTES ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09288-0-10/18(E) Rev. E | Page 24 of 24