TFT LCD Panel Power Module ADP3041 FEATURES FUNCTIONAL BLOCK DIAGRAM 600 kHz PWM Frequency Fully Integrated 1.5 A Power Switch COMP IN 3% Output Regulation Accuracy ERROR ADP3041 Simple Compensation AMP REF Small Inductor and MLC Capacitors gm BIAS FB 300 (cid:1)A Quiescent Supply Current 90% Efficiency F/F SW Undervoltage Lockout R Q 5 Buffers RAMP GEN S DRIVER TSSOP 20-Lead Package COMPARATOR Pb-Free Part NC OSC APPLICATIONS TFT LCD Bias Supplies SD CURRENT SENSE GENERAL DESCRIPTION SS SOFT START AMPLIFIER PGND The ADP3041 is a fixed frequency, PWM step-up dc-to-dc AVCC switching regulator with five buffers capable of 12 V boosted output voltage in a TSSOP 20-lead package. It provides high VCMI VCMO efficiency, low noise operation, and excellent dynamic response, and is easy to use. The high switching frequency allows for small, cost-saving, external inductive and capacitive components. The G1I G1O ADP3041 operates in PWM current mode. The current limit and the power switch are integrated completely on-chip. G2I G2O Capable of operating from 2.5 V to 5.5 V input, the ADP3041 is ideal for thin-film transistor (TFT) liquid crystal display (LCD) module applications, where local point-of-use power G3I G3O regulation is required. Supporting output voltages down to 4.5 V, the ADP3041 is ideal to generate today’s low voltage rails, pro- viding the optimal solution in its class for delivering power G4I G4O efficiently, responsively, and simply with minimal printed circuit board area. The ADP3041 integrates five buffers. Each buffer can deliver 35 mA output current and has rail-to-rail input and output AGND capability. REV.D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

ADP3041–SPECIFICATIONS1 (V = 3.3 V, T = –40(cid:2)C to +85(cid:2)C, unless otherwise noted.) IN A Parameter Symbol Conditions Min Typ Max Unit SUPPLY Input Voltage V 2.5 3.3 5.5 V IN Operating Current2 I f = 600 kHz, No Load, 1 5 mA QSW AVCC = Open Quiescent Current I Not Switching, AVCC = Open 270 500 µA Q Shutdown Current I AVCC = Open 10 µA SD ERROR AMPLIFIER Feedback Voltage Accuracy V 1.215 1.233 1.251 V FB Line Regulation V = 2.5 V to 5.5 V –0.15 +0.15 %/V IN FB Bias Current 100 nA Overall Regulation Line, Temperature –3 +3 % OUTPUT SWITCH On Resistance R At 1.5 A, V = 3.3 V 300 mΩ DS (ON) IN Output Load Current I Continuous Operation, LOAD V = 3.3 V, V = 10V 300 mA IN OUT Leakage Current V = 12 V, SD = 0 V 5 µA SWITCH Efficiency I = 200 mA, V = 10 V 90 % LOAD OUT I = 100 mA, V = 10 V 90 % LOAD OUT OSCILLATOR Oscillator Frequency f 0.4 0.6 0.9 MHz OSC Maximum Duty Cycle D COMP= Open, FB = 1 V 80 90 % MAX Minimum Duty Cycle D COMP= Open, FB = 1 V 40 % MIN SOFT START Charge Current V = 3.3 V, C = 1 nF 2.5 µA SS SS SHUTDOWN Input Voltage Low 0.8 V Input Voltage High 2.2 V CURRENT LIMIT Peak Switch Current I 1.5 1.8 A CL COMPENSATION Transconductance g 100 µA/V m Gain A 1000 V/V V UNDERVOLTAGE LOCKOUT UVLO Threshold 2.2 2.4 2.5 V UVLO Hysteresis 130 mV OUTPUT Voltage Range V V = 2.5 V to 5.5 V 4.5 12 V OUT IN Load Regulation I = 10 mA to 150 mA, LOAD V = 10 V 0.05 mV/mA OUT –2– REV. D

ADP3041 Parameter Symbol Conditions Min Typ Max Unit BUFFER INPUT CHARACTERISTICS Offset Voltage V 2 10 mV OS Offset Voltage Drift (cid:1)V /(cid:1)T –40°C ≤ T ≤ +85°C 5 µV/°C OS A Input Bias Current I 80 600 nA B –40°C ≤ T ≤ +85°C 800 nA A Input Voltage Range –0.5 V + 0.5 V S Input Impedance Z 400 kΩ IN Input Capacitance C 1 pF IN OUTPUT CHARACTERISTICS Output Voltage High V I = 100 µA V – 0.005 V OH L S V = 12 V, I = 5 mA 11.85 11.94 V S L –40°C ≤ T ≤ +85°C 11.75 V A V = 4.5 V, I = 5 mA 4.2 4.38 V S L –40°C ≤ T ≤ +85°C 4.1 V A Output Voltage Low V I = 100 µA 5 mV OL L V = 12 V, I = 5 mA 42 150 mV S L –40°C ≤ T ≤ +85°C 250 mV A V = 4.5 V, I = 5 mA 95 300 mV S L 400 mV Continuous Output Current I 35 mA OUT Peak Output Current I V = 12 V 250 mA PK S TRANSFER CHARACTERISTICS Gain AVCL R = 2 kΩ 0.995 0.9985 1.005 V/V L –40°C ≤ T ≤ +85°C 0.995 0.9985 1.005 V/V A Gain Linearity NL R = 2 kΩ, L V = 0.5 to (V – 0.5 V) 0.01 % O S POWER SUPPLY Supply Voltage V 4.5 12 V S Power Supply Rejection Ratio PSRR V = 4 V to 12 V, S –40°C ≤ T ≤ +85°C 70 90 dB A Supply Current/Amplifier I V = V /2, No Load 780 1000 µA SY O S –40°C ≤ T ≤ +85°C 1.2 mA A DYNAMIC PERFORMANCE Slew Rate SR R = 10 kΩ, C = 200 pF 4.5 8 V/µs L L Bandwidth BW –3 dB, R = 10 kΩ, C = 10 pF 8 MHz L L Phase Margin (cid:2)m R = 10 kΩ, C = 10 pF 65 Degrees L L NOISE PERFORMANCE Voltage Noise Density e f = 1 kHz 27 nV/√Hz n e f = 10 kHz 25 nV/√Hz n Current Noise Density i f = 10 kHz 0.8 pA/√Hz n NOTES 1All limits at temperature extremes are guaranteed via correlation and characterization using standard Statistical Quality Control (SQC). 2This is the average current while switching. Specifications subject to change without notice. REV. D –3–

ADP3041 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to + 6 V Buffer Input Voltage . . . . . . . . . . . . . –0.5 V to AVCC + 0.5 V SW Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 V SW 1 20 PGND COMP Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +2.5 V IN 2 19 AGND FB Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +1.3 V SD 3 18 FB SD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +6 V NC 4 17 COMP PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±200 mV AVCC 5 ADP3041 16 SS Operating Ambient Temperature Range . . . . .–40°C to +85°C VCMI 6 TOP VIEW 15 VCMO Operating Junction Temperature Range . . . .–40°C to +125°C G1I 7 (Not to Scale)14 G1O Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C G2I 8 13 G2O (cid:3) 2-Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W JA G3I 9 12 G3O (cid:3) 4-Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W LJeAad Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C G4I 10 11 G4O NC = NO CONNECT *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE PIN FUNCTION DESCRIPTIONS Temperature Voltage Package Pin No. Mnemonic Function Model Range Output Option 1 SW Switching Output ADP3041ARU –40°C to +85°C 4.5 V to 12 V TSSOP-20 2 IN Main Power Supply Input ADP3041ARUZ* –40°C to +85°C 4.5 V to 12 V TSSOP-20 3 SD Shutdown Input *Z = Pb-free part. 4 NC No Connection D1 5 AVCC Buffers Power Supply Input R1 COUT 6 VCMI VCOM Buffer Input L1 7 G1I Gamma 1 Buffer Input R2 SW PGND 8 G2I Gamma 2 Buffer Input ADP3041 VIN IN AGND 9 G3I Gamma 3 Buffer Input CIN RSD 10 G4I Gamma 4 Buffer Input SD FB RC CC 11 G4O Gamma 4 Buffer Output NC COMP 12 G3O Gamma 3 Buffer Output CSS AVCC SS 13 G2O Gamma 2 Buffer Output VCMI VCMO 14 G1O Gamma 1 Buffer Output 15 VCMO VCOM Buffer Output G1I G1O 16 SS Soft Start Capacitor Timer Set G2I G2O 17 COMP Compensation Input G3I G3O 18 FB Feedback Voltage Sense Input G4I G4O 19 AGND Analog Signal Ground 20 PGND Ground Return for Power Transistor Figure 1. Typical Application CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3041 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. D

Typical Performance Characteristics–ADP3041 100 0 90 TA = 25(cid:2)C VCM = VS/2 4.5V < VS < 16V –50 80 VS = 16V A) ers) 70 T (n –100 mplifi 60 RREN –150 NTITY (A 5400 BIAS CU –200 VS = 4.5V QUA 30 PUT –250 N I 20 –300 10 0 –350 –12 –9 –6 –3 0 3 6 9 12 –40 25 85 INPUT OFFSET VOLTAGE (mV) TEMPERATURE ((cid:2)C) TPC 1. Input Offset Voltage Distribution TPC 4. Input Bias Current vs. Temperature 300 5 4.5V < VS < 16V 4 250 A) 3 n s) T ( 2 plifier 200 RREN 1 TITY (Am 150 FSET CU –10 VS = 4.5V VS = 16V N F QUA 100 UT O –2 P IN –3 50 –4 0 –5 0 10 20 30 40 50 60 70 80 90 100 –40 25 85 TCVOS ((cid:1)V/(cid:2)C) TEMPERATURE ((cid:2)C) TPC 2. Input Offset Voltage Drift Distribution TPC 5. Input Offset Current vs. Temperature 0 15.96 4.46 VCM = VS/2 15.95 ILOAD = 5mA 4.45 –0.25 VS = 16V V) V) 15.94 4.44 OLTAGE (m –0.50 VS = 16V GE SWING ( 1155..9932 44..4432 T V –0.75 TA 15.91 4.41 E L FS VO 15.90 4.40 UT OF –1.00 TPUT 15.89 VS = 4.5V 4.39 NP VS = 4.5V OU 15.88 4.38 I –1.25 15.87 4.37 –1.50 15.86 4.36 –40 25 85 –40 25 85 TEMPERATURE ((cid:2)C) TEMPERATURE ((cid:2)C) TPC 3. Input Offset Voltage vs. Temperature TPC 6. Output Voltage Swing vs. Temperature REV. D –5–

ADP3041 150 0.85 135 ILOAD = 5mA VCM = VS/2 A) 0.80 V) 120 m NG (m 105 FIER ( 0.75 VS = 16V SWI 90 MPLI AGE 75 VS = 4.5V NT/A 0.70 T VOLT 60 CURRE 0.65 OUTPU 4350 VS = 16V UPPLY 0.60 VS = 4.5V S 15 0 0.55 (cid:3)40 25 85 (cid:3)40 25 85 TEMPERATURE ((cid:2)C) TEMPERATURE ((cid:2)C) TPC 7. Output Voltage Swing vs. Temperature TPC 10. Supply Current/Amplifier vs. Temperature (Small Signal) 0.9999 8 4V.O5UVT < = V 0S.5 <V 1 T6OV 15V 7 VS = 16V RCLL == 1200k0p(cid:4)F RL = 2k(cid:4) 6 N ERROR (V/V) 0.9997 (cid:1)W RATE (V/s) 45 VS = 4.5V GAI SLE 3 2 RL = 600(cid:4) 0.9995 1 (cid:3)40 25 85 –40 25 85 TEMPERATURE ((cid:2)C) TEMPERATURE ((cid:2)C) TPC 8. Voltage Gain vs. Temperature TPC 11. Slew Rate vs. Temperature 1k 1.1 TA = 25(cid:2)C 1.0 TAAV == 215C A) VO = VS/2 m 0.9 E (mV)100 VS = 4.5V LIFIER ( 0.8 G P 0.7 A M VOLT 10 VS = 16V NT/A 0.6 PUT RRE 0.5 T U U C O LY 0.4 P 1 UP 0.3 S 0.2 0.1 0.1 0.001 0.01 0.1 1 10 100 0 2 4 6 8 10 12 14 16 18 LOAD CURRENT (mA) SUPPLY VOLTAGE (V) TPC 9. Output Voltage to Supply Rail vs. Load Current TPC 12. Supply Current/Amplifier vs. Supply Voltage –6– REV. D

ADP3041 10 18 5 1k(cid:4) 16 0 10k(cid:4) TA = 25(cid:2)C 14 VS = 16V –5 p) AV = +1 N (dB) ––1150 TVVCAISLN = === 2 (cid:5)455080(cid:2)pVmCFV rms 560(cid:4) WING (V p- 1102 DRILS =T O10RkT(cid:4)ION < 1% GAI –20 AV = +1 150(cid:4) UT S 8 P T 6 –25 U O –30 4 –35 2 –40 0 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) TPC 13. Resistive Loading vs. Frequency Response TPC 16. Closed-Loop Output Swing vs. Frequency 25 160 2105 RTVVAISLN = === 2 (cid:5)155080(cid:2)kVmC(cid:4)V rms O (dB) 114200 TVAS == 2156(cid:2)VC 10 AV = +1 RATI 100 N AIN (dB) 05 50pF REJECTIO 8600 +PSRR G –5 LY 40 P (cid:3)PSRR –10 UP 20 –15 1040pF 100pF ER S 0 W 540pF O –20 P –20 –25 –40 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) TPC 14. Capacitive Loading vs. Frequency Response TPC 17. Power Supply Rejection Ratio vs. Frequency, V = 16 V S 500 160 450 dB) 140 TVAS == 245.5(cid:2)VC 400 O ( 120 ATI 350 R 100 (cid:4)ANCE () 320500 VS = 4.5V EJECTION 8600 (cid:3)+PPSSRRRR D R MPE 200 PLY 40 I P 150 U 20 S R 100 E 0 W O 50 VS = 16V P –20 0 –40 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) TPC 15. Closed-Loop Output Impedance vs. Frequency TPC 18. Power Supply Rejection Ratio vs. Frequency, V = 4.5 V S REV. D –7–

ADP3041 1k 100 TA = 25(cid:2)C TA = 25(cid:2)C 4.5V ≤ VS ≤ 16V 90 VS = 4.5V Hz) 80 VVCINM = = 1 20.02m5VV p-p √V/ 70 AV = +1 SITY (n 100 OT (%) 60 RL = 10k(cid:4) N O E DE RSH 50 S E 40 NOI 10 OV –OS +OS E 30 G A LT 20 O V 10 1 0 10 100 1k 10k 10 100 1k FREQUENCY (Hz) LOAD CAPACITANCE (pF) TPC 19. Voltage Noise Density vs. Frequency TPC 22. Small Signal Overshoot vs. Load Capacitance, V = 4.5 V S 20 15 0 4T.A5 V= <25 V(cid:2)SC < 16V TVAS == 2(cid:5)58(cid:2)VC ON (dB) ––4200 (cid:5)0V TO V 105 RL = 10k(cid:4) EPARATI ––8600 G FROM 0 OVERSHOOT SETTLING TO 0.1% S N L –100 WI ANNE –120 UT S –5 H P C –140 UT UNDERSHOOT SETTLING TO 0.1% O –10 –160 –180 –15 100 1k 10k 100k 1M 10M 100M 0 0.5 1.0 1.5 2.0 SETTLING TIME ((cid:1)s) FREQUENCY (Hz) TPC 20. Channel Separation vs. Frequency TPC 23. Step Size vs. Settling Time 100 0 TA = 25(cid:2)C TA = 25(cid:2)C 90 VS = 16V 0 VS = 16V 80 VVCINM = = 1 80V0mV p-p 0 ARVL == 1+01k(cid:4) 70 AV = +1 CL = 300pF HOOT (%) 6500 RL = 10k(cid:4) E (2V/DIV) 00 S G R A OVE 40 –OS VOLT 0 30 +OS 0 20 0 10 0 0 10 100 1k 0 0 0 0 0 0 0 0 0 TIME (2(cid:1)s/DIV) LOAD CAPACITANCE (pF) TPC 21. Small Signal Overshoot vs. Load Capacitance, TPC 24. Large Signal Transient Response, V = 16 V S V = 16 V S –8– REV. D

ADP3041 0 0 TA = 25(cid:2)C TA = 25(cid:2)C 0 VS = 4.5V 0 VS = 4.5V AV = +1 AV = +1 0 RL = 10k(cid:4) 0 RL = 10k(cid:4) V/DIV) 0 CL = 300pF mV/DIV) 0 CL = 100pF GE (1 0 E (50 0 A G OLT 0 LTA 0 V O V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME (2(cid:1)s/DIV) TIME (1(cid:1)s/DIV) TPC 25. Large Signal Transient Response, VS = 4.5 V TPC 27. Small Signal Transient Response, VS = 4.5 V 0 0 V) 00 CTVARASVLL ===== 2111+56001(cid:2)Vk0C(cid:4)pF 00 TVARASVL ==== 211+5601(cid:2)VkC(cid:4) V/DI 0 DIV) 0 m V/ 0 3 E (5 0 GE ( 0 G A LTA 0 OLT 0 O V V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME (1(cid:1)s/DIV) TIME (40(cid:1)s/DIV) TPC 26. Small Signal Transient Response, VS = 16 V TPC 28. No Phase Reversal REV. D –9–

ADP3041 THEORY OF OPERATION to be equal and opposite to maintain steady state, one can say Switching Regulator that t × V will equal t × (V – V ), if we neglect the effect 1 IN 2 OUT IN The ADP3041 is a boost converter driver that stores energy of resistance in the inductor and switch and the forward voltage from an input voltage in an inductor and delivers that energy, drop of the diode. From this equality one can derive t /T = 1 – 1 augmented by the input, to a load at a higher output voltage. It V /V , where T is the period of a cycle, t + t . This result IN OUT 1 2 includes a voltage reference and an error amplifier to com- gives us the switch duty ratio, t /T, in terms of the input and 1 pare some fraction of the load voltage to the reference and to output voltages. amplify any difference between them. The amplified error In practice, the duty ratio needs to be slightly higher than this signal is compared to a dynamic signal produced by an inter- calculation. Because of series resistance in the inductor and the nal ramp generator incorporating switch current feedback. The switch, the voltage across the actual inductance is somewhat less comparator output timing sets the duty ratio of a switch driv- than the applied V , and the actual output voltage is less than ing the inductor to maintain the desired output voltage. IN our approximation by the amount of the diode forward voltage Referring to Figure 1, a typical application powers both the IC drop. However, the feedback control within the ADP3041 adjusts and the inductor from the same input voltage. The on-chip the duty ratio to maintain the output voltage. Changes in MOSFET is driven on, pulling the SW pin close to PGND. The load current and input voltage are also accommodated by the resulting voltage across the inductor causes its current to increase feedback control. approximately linearly, with respect to time. Changes in load current alone require a change in duty ratio in When the MOSFET switch is turned off, the inductor current order to change the average inductor current. Once the inductor cannot drop to zero, and so this current drives the SW node current adapts to the new load current, the duty ratio should capacitance rapidly positive until the diode becomes forward return to nearly its original value, as one can see from the biased. The inductor current now begins to charge the load duty cycle calculation, which depends on input and output capacitor, causing a slight increase in output voltage. Generally, voltages but not on current. Increasing the switch duty ratio the load capacitor is made large enough that this increase is very initially reduces the output voltage until the average inductor small during the time the switch is off. During this time, inductor current increases enough to offset the reduction of the t 2 current is also delivered to the load. In steady state operation, interval. By limiting the duty ratio, one can prevent this effect the inductor current exceeds the load current, and the excess is from regeneratively increasing the duty ratio to 100%, which what charges the load capacitor. The inductor current falls would cause the output to fall and the switch current to rise during this time, though not necessarily to zero. without limit. The duty ratio is limited to about 80% by the design of the oscillator and an additional flip-flop reset. During the next cycle, initiated by the on-chip oscillator, the switch is again turned on so that the inductor current is ramped A comparator compares the current sense amplifier output to a up again. The charge on the load capacitor provides load current factory set limit that resets the flip-flop, turning off the switch. during that interval. The remainder of the chip is arranged to This prevents runaway or overload conditions from damaging control the duty ratio of the switch to maintain a chosen output the switch and reflecting fault overloads back to the input. Of voltage despite changes in input voltage or load current. course, the load is directly connected to the input by way of the diode and inductor, so protection against short circuited loads The output voltage is scaled down by a resistor voltage divider must be done at the power input. and presented to the g amplifier. This amplifier operates on m the difference between an on-chip reference and the voltage at The g amplifier has high voltage gain to ensure the output m the FB pin so as to bring them to balance. This is when the voltage accuracy and invariance with load and input voltage. output voltage equals the reference voltage multiplied by the However, because it is a g amplifier with a specified current m resistor voltage divider ratio. response to input signal voltages, its high frequency response can be controlled by the compensation impedance. This permits The g amplifier drives an internal comparator, which has at its m the high frequency gain of the g amplifier to be optimized for other input a positive-going ramp produced by the oscillator m the best compromise between speed of response and frequency and modified by the current sense amplifier. The MOSFET stability. switch is turned on as the modified ramp voltage rises. When this voltage exceeds the output of the g amplifier, the compara- The stable closed-loop bandwidth of the system can be extended m tor turns off the switch by resetting the flip-flop previously set by the current feedback shown. A signal representing the magni- by the oscillator. The output of the flip-flop is buffered by a high tude of the switch current is added to the ramp. This dynamically current driver, which turned on the MOSFET switch at the reduces the duty ratio as the current in the inductor increases, beginning of the oscillator cycle. until the g amplifier restores it, improving the closed-loop m frequency stability. In the steady state with constant load and input voltage, the current in the inductor cycles around some average current Soft Start level. The increasing ramp of current depends on input voltage The soft start pin can load the COMP pin, forcing a low duty and t , the switch-on time, while the decreasing ramp depends cycle when its voltage is low. A capacitor on SS initially holds 1 on the difference between the input and output voltage and t , the pin low; however, a small internal current charges the 2 the remainder of the cycle. For the peaks of these two ramps capacitor, causing SS to rise after SD goes high. As it rises, –10– REV. D

ADP3041 COMP is allowed to rise slowly until the control loop limits the by 5 mA. This resistance should be placed in series with the voltage to that required for regulation. SS continues to rise and input exposed to an overvoltage. no longer affects COMP once soft start is complete. Output Phase Reversal When SD goes low, an internal switch discharges the SS The buffer family is immune to phase reversal. Although the capacitor to return its voltage to zero for soft restart. device’s output does not change phase, large currents due to input overvoltage could damage the device. In applications Because of the large current that flows into the main MOSFET where the possibility of an input voltage exceeding the supply switch, it is provided with a separate PGND return to the nega- voltage exists, overvoltage protection should be used as described tive supply terminal to avoid corrupting the small-signal return, in the previous section. GND, that can be used as a sense line at the output load point. Buffers APPLICATION INFORMATION This family of buffers is designed to drive large capacitive loads Output Voltage in LCD applications. Each has high output current drive and The ADP3041 operates with an adjustable output from V to IN rail-to-rail input/output operation and can be powered from a 12 V. The output voltage is fed back to the ADP3041 via resis- single 12 V supply. They are also intended for other applications tor dividers R1 and R2 (Figure 1). The feedback voltage is where low distortion and high output current drive are needed. 1.233 V, so the output voltage is set by the formula Input Overvoltage Protection  R1 As with any semiconductor device, whenever the input exceeds V =1.233V ×1+  (1) OUT  R2 either supply voltage, attention needs to be paid to the input overvoltage characteristics. As an overvoltage occurs, the ampli- Because the feedback bias current is 100 nA maximum, R2 may fier could be damaged, depending on the voltage level and the have a value up to 100 kΩ with minimum error due to the bias magnitude of the fault current. When the input voltage exceeds current. either supply by more than 0.6 V, the internal pin junctions Inductor Selection allow current to flow from the input to the supplies. For most applications, the inductor used with the ADP3041 This input current is not inherently damaging to the device as should be in the range of 1 µH to 22 µH. Several inductor long as it is limited to 5 mA or less. If a condition exists using manufacturers are listed in Table I. When selecting an inductor, the buffers where the input exceeds the supply more than 0.6 V, it is important to make sure that the inductor used with the a series external resistor should be added. The size of the resis- ADP3041 is able to handle a peak current without saturation, and tor can be calculated by using the maximum overvoltage divided that the peak current is below the current limit of the ADP3041. Table I. Inductor Manufacturers Part L (µH) Max DCR (mΩ) Height (mm) Vendor CMD4D11-4R7M 4.7 166 1.1 Sumida CCDRH5D18-100 10 124 2.0 847-545-6700 CR43-4R7 4.7 109 3.5 www.sumida.com CR43-100 10 182 3.5 DS1608-472 4.7 60 2.9 Coilcraft DS1608-103 10 75 2.9 847-639-6400 www.coilcraft.com D52LC-4R7M 4.7 84 2.0 Toko D52LC-100M 10 137 2.0 847-297-0070 www.tokoam.com REV. D –11–

ADP3041 As a rule, powdered iron cores saturate softly, whereas ferrite cores When selecting an output capacitor, make sure that the ripple saturate abruptly. Open drum core inductors tend to saturate current rating is sufficient to cover the rms switching current gradually and are low cost and small in size, making these of the ADP3041. The ripple current in the output capacitor is types of inductors attractive in many applications. However, given by care must be exercised in their placement because they have high magnetic fields. In applications that are sensitive to mag- I (C )=I VOUT –VIN (7) netic fields, shielded geometrics are recommended. RMS OUT OUT V IN In addition, inductor losses must be considered. Both core and Multilayer ceramic capacitors are a good choice since they have copper losses contribute to loss in converter efficiency. To mini- low ESR, high ripple current rating, and a very small package mize core losses, look for inductors rated for operation at high size. Tantalum or OS-CON capacitors can be used; however, switching frequencies. To minimize copper losses, it is best to they have a larger package size and higher ESR. Table II lists use low dc resistance inductors. Typically, it is best to use an some capacitor manufacturers. Consult the manufacturer for inductor with a dc resistance lower than 20 mΩ per µH. more information. The inductor value can be estimated using ( ) Table II. Capacitor Manufacturers L= V –V ×M (2) OUT IN SLOPE Vendor Phone No. Web Address where M is the scaling factor for the proper slope compensation. SLOPE AVX 843-448-9411 www.avxcorp.com 1.456 MSLOPE = f (3) MSaunryaota 747008--473469--19370104 wwwwww..msaunryaotvai.dceoom.com SW Taiyo Yuden 858-554-0755 www.t-yuden.com Choose the closest standard inductor value as a starting point. The corresponding peak inductor current can then be calculated. Diode Selection ( ) In specifying a diode, consideration must be given to speed, IL(PEAK)=IOUT ×VVOUT + 12VINL××VVOUT×–VfIN  (4) faonrdw tahred bcruerarkendto,w fonr wvoalrtdag veo. lTtahgee odurotppu, tr edvieordsee slehaokualgde b ceu rraretendt, to IN OUT S handle the maximum output current. If the output can be sub- It is recommended to try several different inductor values, sizes, jected to accidental short circuits, then the diode must be rated to and types to find the best inductor for the application. In gen- handle currents up to the current limit of the ADP3041. The eral, large inductor values lead to lower ripple current, less breakdown rating of the diode must exceed the output voltage. A output noise, and either larger size or higher dc resistance. high speed diode with low forward drop and low leakage will help Conversely, low inductor values lead to higher ripple current, improve the efficiency of the converter by lowering the losses of more noise, and either smaller size or lower dc resistance. The the diode. Schottky diodes are recommended. final inductor selection should be based on the best trade-off of Loop Compensation size, cost, and performance. Like most current programmed PWM converters, the ADP3041 Capacitor Selection needs compensation to maintain stability over the operating The ADP3041 requires an input capacitor to reduce the switching conditions of the particular application. For operation at duty ripple and noise on the IN pin. The value of the input capaci- cycles above 50%, the choice of inductor is critical in maintain- tor depends on the application. For most applications, a minimum ing stability. If the slope of the inductor current is too small or of 10 µF is required. For applications that are running close to too large, the circuit will be unstable. See the Inductor Selection current limit or that have large transient loads, input capacitors section for more information on choosing the proper inductor. in the range of 22 µF to 47 µF are required. The ADP3041 provides a pin (COMP) for compensating the The selection of the output capacitor also depends on the voltage feedback loop. This is done by connecting a series R application. Given the allowable output ripple voltage, (cid:1)V , C OUT network from the COMP pin to GND (see Figure 2). For most the criteria for selecting the output capacitor can be calcu- applications, the compensation resistor, R , should be in the C lated using range of 5 kΩ < R < 400 kΩ, and the compensation capacitor, C  (V –V )  CC, in the range of 100 pF < CC < 10 nF. Further details for COUT ≥8×IOUT f ×VOUT ×∆INV  (5) selecting the compensation components follow. S OUT OUT ∆V ESRCOUT ≤ I (PEOAUTK) (6) L –12– REV. D

ADP3041 ERROR So the compensation resistor, R , can be calculated by deter- C AMP mining the open-loop gain at the crossover frequency, f , and COMP C REF setting R to adjust the closed-loop gain to zero. The open-loop gm C FB gain can be approximated (in dB) by RCCC C2 G (f )=20logVIN ×RLOAD–20log 1+ fC 2 OC C V ×0.65   f   (12) OUT  P1  1 R = The boost reFgiugluatroer 2in. tCroodmucpees nas raigtihot nh aClfo pmlapnoe n(RenHtPs) zero. This C g × VFB ×10GO2C0(fC) (13) m V zero behaves like a zero with respect to the gain but behaves OUT like a pole with respect to phase. As a result, the RHP zero can Once the value of the compensation resistor is determined, the cause instability of the control loop if the bandwidth (in Hertz) value of the compensation capacitor, C , can be calculated. The C of the loop includes it. compensation capacitor sets up a zero to cancel out the pole created by the output load, f . Since the load pole position ( )  V 2 R varies with load current, the comP1pensation zero should be located fZ RHP =VOIUNT ×2πLO×ADL (8) aopnper hoxailmf tahtee lcy rfoosusro vtiemr efsr etqhue ewnocrys,t -1c/a2s e× lfoa,d w phoicleh, e4v e×r fiPs1 ,l oowr aetr. C Note that the RHP zero is dependant on the load. To optimize The frequency of the compensation zero is located at the compensation, a nominal load must be chosen. Typically, 1 clohaodo wsionrgk sa wn eRllL; ObAuDt mthaakte i ssu hrae ltfhwaat yt hbise tlwoaede nis nenoo luogahd taon edn sfuurlel fZC = 2×π×R ×C (14) C C CCM operation. The critical value of load resistance, R , for CRIT So, the value of C can be calculated using CCM is given by C 1 R = 2×L× fSW CC = 2×π× f ×R (15) CRIT  V  V 2 (9) ZC C 1– IN  IN  If the output capacitor selected has a high ESR value, it may be  V V  OUT OUT necessary to add another pole to cancel the zero introduced by So for the nominal load resistance R , use the half load the capacitor’s ESR. The ESR zero location is determined by LOAD resistance or R , whichever is lower. CRIT ( ) 1 To make sure the RHP zero does not cause stability problems, fZ ESR = 2×π×R ×C (16) the control loop bandwidth should be set at around 1/8 the ESR OUT frequency (in Hertz) of the RHP zero. So, a high frequency pole should be placed to cancel the ESR zero or at half the switching frequency, whichever is lower. By 1 ( ) f = × f RHP (10) placing a pole at half the switching frequency, the high fre- C 8 Z quency gain is rolled off for better phase margin. Note that the where f is the crossover frequency. high frequency pole must be at least a decade above the com- C pensation zero in order for the compensation to work properly. Another frequency of interest is the pole caused by the output If this is not the case, the high frequency pole should not be used. load and output capacitor. This frequency (in Hertz) is calcu- lated using C C2= ( C ) fP1 = 2π×R 1 ×C (11) 1+ 2π× fP(HF) ×RC ×CC (17) LOAD OUT After all the compensation components have been selected, the Note that the frequency varies with load current. Again, use the best check for stability and response time is to observe the tran- nominal load resistance for the calculation. sient performance of the ADP3041. Adjust R and C as necessary C C to optimize the transient response. Increasing R increases C REV. D –13–

ADP3041 the high frequency gain. Increasing C decreases the compensa- as possible. Use the following general guidelines when designing C tion zero frequency, which increases the stability but slows the printed circuit boards (see Figure 1): transient response. 1. Keep C close to the IN pin of the ADP3041. IN Shutdown 2. Keep the high current path from C through L1 to the SW The ADP3041 shuts down to reduce the supply current to a 10 µA IN pin and PGND pin as short as possible. maximum when the shutdown pin is pulled low. In this mode, the internal reference, error amplifier, comparator, biasing cir- 3. Similarly, keep the high current path from CIN through L1, cuitry, and the internal MOSFET switch are turned off. Note D1, and COUT as short as possible. that the output is still connected to the input via the inductor 4. Keep high current traces as short and wide as possible. and Schottky diode when in shutdown. 5. Place the feedback resistors as close to the FB pin as possible Layout Procedure to prevent noise pickup. To get high efficiency, good regulation, and stability, a good 6. Place the compensation components as close to the COMP printed circuit board layout is required. It is strongly recom- pin as possible. mended that the evaluation board layout be followed as closely 7. Avoid routing noise sensitive traces near the high current traces and components. –14– REV. D

ADP3041 OUTLINE DIMENSIONS 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 80(cid:2)(cid:2) 0.60 COPLANARITY 0.19 SEATING 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153AC REV. D –15–

ADP3041 Revision History Location Page 12/03—Data Sheet changed from REV. C to REV. D. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Updated formatting of Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 D) Change to TPC 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 03( 2/ Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 –1 0 – Changes to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 61 3 3 5/03—Data Sheet changed from REV. B to REV. C. 0 C Replaced all TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 10/02—Data Sheet changed from REV. A to REV. B. Updated Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Removed RT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 –16– REV. D