Dual, 200 mA, Low Noise, High PSRR Voltage Regulator Data Sheet ADP220/ADP221 FEATURES TYPICAL APPLICATION CIRCUITS Input voltage range: 2.5 V to 5.5 V 1 2 MDuinaila itnudreep 6e-nbdalel,n 1t .200 m0 mm A× l1o.5w m drmo pWoLuCtS vPo altnadg e6 -rbeaglul lators OFFON A EN1 VOUT1 VOUT1 = 2.8V bumped bare die 1µF Initial accuracy: ±1% Stable with 1 µF ceramic output capacitors B VIN = 3.3V GND VIN No noise bypass capacitor required 1µF Two independent logic controlled enables TOP VIEW (Not to Scale) Overcurrent and thermal protection AKecHtyi ivsgeph eo PcuiSftRipcRua tt ipounlsl -down (ADP221) OFFON C EN2 VOUT2 1VµOFUT2 = 2.8V 07572-001 Figure 1. Typical Application Circuit 76 dB PSRR up to 1 kHz 70 dB PSRR at 10 kHz 60 dB PSRR at 100 kHz 40 dB PSRR at 1 MHz VIN VOUT1 Low output noise 60Ω 27 µV rms typical output noise at V = 1.2 V OUT THERMAL CURRENT 50 µV rms typical output noise at V = 2.8 V SHUTDOWN LIMIT OUT Excellent transient response Low dropout voltage: 150 mV @ 200 mA load EN1 CONTROL 60 µA typical ground current at no load, both LDOs enabled LOGIC REFERENCE ADP221 AND ONLY 100 µs fast turn-on circuit EN2 ENABLE Guaranteed 200 mA output current per regulator −40°C to +125°C junction temperature ADP220 CURRENT APPLICATIONS LIMIT GND 60Ω Mobile phones Digital cameras and audio devices VOUT2 07572-002 Portable and battery-powered equipment Figure 2. Block Diagram of the ADP220/ADP221 Portable medical devices Post dc-to-dc regulation GENERAL DESCRIPTION The 200 mA dual output ADP220/ADP221 combine high PSRR, without the need for a noise bypass capacitor. The ADP221 also low noise, low quiescent current, and low dropout voltage in a includes an active pull-down to quickly discharge output loads. voltage regulator ideally suited for wireless applications with The ADP220/ADP221 are available in a miniature 6-ball demanding performance and board space requirements. WLCSP package and 6-ball bumped bare die and is stable with The low quiescent current, low dropout voltage, and wide input tiny 1 µF ± 30% ceramic output capacitors, resulting in the smallest voltage range of the ADP220/ADP221 extend the battery life of possible board area for a wide variety of portable power needs. portable devices. The ADP220/ADP221 maintain power supply The ADP220/ADP221 are available in many output voltage rejection greater than 60 dB for frequencies as high as 100 kHz combinations, ranging from 0.8 V to 3.3 V, and offer overcur- while operating with a low headroom voltage. The ADP220 rent and thermal protection to prevent damage in adverse offers much lower noise performance than competing LDOs conditions. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADP220/ADP221 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 Typical Application Circuits ............................................................ 1 Applications Information .............................................................. 12 General Description ......................................................................... 1 Capacitor Selection .................................................................... 12 Revision History ............................................................................... 2 Undervoltage Lockout ............................................................... 13 Specifications ..................................................................................... 3 Enable Feature ............................................................................ 13 Input and Output Capacitor, Recommended Specifications .. 4 Current-Limit and Thermal Overload Protection ................. 14 Absolute Maximum Ratings ............................................................ 5 Thermal Considerations ............................................................ 14 Thermal Data ................................................................................ 5 Printed Circuit Board (PCB) Layout Considerations ................ 16 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 17 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 18 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 1/13—Rev. G to Rev. H 1/10—Rev. B to Rev. C Changes to Undervoltage Lockout Input Voltage Rising Changes to Figure 24 ...................................................................... 10 Parameter and Undervoltage Lockout Input Voltage Falling Parameter, Table 1 ............................................................................. 3 10/09—Rev. A to Rev. B Changes to Features Section ............................................................ 1 11/12—Rev. F to Rev. G Changes to Table 3 and Table 4........................................................ 5 Added 6-Ball Bumped Bare Die (CD-6-7) ...................... Universal Changes to Figure 4, Figure 6, Figure 7, and Figure 9 .................. 7 Change to Undervoltage Lockout Input Voltage Rising Changes to Figure 10 and Figure 12 ............................................... 8 Parameter, Table 1 ............................................................................. 3 Changes to Figure 17 ......................................................................... 9 Updated Outline Dimensions ....................................................... 17 Changes to Figure 25 ...................................................................... 10 Moved Ordering Guide .................................................................. 18 Changes to Enable Feature Section and Figure 32 ..................... 13 Changes to Current-Limit and Thermal Overland Protection 4/12—Rev. E to Rev. F Section and Thermal Considerations Section ............................ 14 Changes to Ordering Guide .......................................................... 17 Changes to Ordering Guide .......................................................... 17 11/10—Rev. D to Rev. E 3/09—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 17 Changes to Figure 15 ......................................................................... 8 Changes to Figure 16 ......................................................................... 9 5/10—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 17 Changes to Figure 1 .......................................................................... 1 Changes to Ordering Guide .......................................................... 17 10/08—Revision 0: Initial Version Rev. H | Page 2 of 20

Data Sheet ADP220/ADP221 SPECIFICATIONS V = (V + 0.5 V) or 2.5 V (whichever is greater), EN1 = EN2 = V , I = I = 10 mA, C = C = C = 1 µF, T = 25°C, IN OUT IN OUT1 OUT2 IN OUT1 OUT2 A unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit INPUT VOLTAGE RANGE V T = −40°C to +125°C 2.5 5.5 V IN J OPERATING SUPPLY CURRENT WITH I I = 0 µA 60 µA GND OUT BOTH REGULATORS ON I = 0 µA, T = −40°C to +125°C 120 µA OUT J I = 10 mA 70 µA OUT I = 10 mA, T = −40°C to +125°C 140 µA OUT J I = 200 mA 120 µA OUT I = 200 mA, T = −40°C to +125°C 220 µA OUT J SHUTDOWN CURRENT I EN1= EN2 = GND 0.1 µA GND-SD EN1= EN2 = GND, T = −40°C to +125°C 2 µA J FIXED OUTPUT VOLTAGE ACCURACY V −1 +1 % OUT 100 µA < I < 200 mA, V = (V + 0.5 V) to −2 +2 % OUT IN OUT 5.5 V, T = −40°C to +125°C J LINE REGULATION ∆V /∆V V = (V + 0.5 V) to 5.5 V 0.01 %/V OUT IN IN OUT V = (V + 0.5 V) to 5.5 V, T = −40°C to +125°C −0.03 +0.03 %/V IN OUT J LOAD REGULATION1 ∆V /∆I I = 1 mA to 200 mA 0.001 %/mA OUT OUT OUT I = 1 mA to 200 mA, T = −40°C to +125°C 0.003 %/mA OUT J DROPOUT VOLTAGE2 V V = 3.3 V mV DROPOUT OUT I = 10 mA 7.5 mV OUT I = 10 mA, T = −40°C to +125°C 12 mV OUT J I = 200 mA 150 mV OUT I = 200 mA, T = −40°C to +125°C 230 mV OUT J START-UP TIME3 t V = 3.3 V, both initially off, enable one 240 µs START-UP OUT V = 0.8 V, both initially off, enable one 100 µs OUT V = 3.3 V, one initially on, enable second 180 µs OUT V = 0.8 V, one initially on, enable second 20 µs OUT ACTIVE PULL-DOWN RESISTANCE t V = 2.8 V, R = ∞, C = 1 μF, ADP221 only 80 Ω SHUTDOWN OUT LOAD OUT CURRENT-LIMIT THRESHOLD4 I 240 300 440 mA LIMIT THERMAL SHUTDOWN Thermal Shutdown Threshold TS T rising 155 °C SD J Thermal Shutdown Hysteresis TS 15 °C SD-HYS EN INPUT EN Input Logic High V 2.5 V ≤ V ≤ 5.5 V 1.2 V IH IN EN Input Logic Low V 2.5 V ≤ V ≤ 5.5 V 0.4 V IL IN EN Input Leakage Current V EN1 = EN2 = V or GND 0.1 µA I-LEAKAGE IN EN1 = EN2 = V or GND, T = −40°C to +125°C 1 µA IN J UNDERVOLTAGE LOCKOUT UVLO Input Voltage Rising UVLO 2.45 V RISE Input Voltage Falling UVLO 2.2 2.35 V FALL Hysteresis UVLO 100 mV HYS OUTPUT NOISE OUT 10 Hz to 100 kHz, V = 5 V, V = 3.3 V 56 µV rms NOISE IN OUT 10 Hz to 100 kHz, V = 5 V, V = 2.8 V 50 µV rms IN OUT 10 Hz to 100 kHz, V = 3.6 V, V = 2.5 V 45 µV rms IN OUT 10 Hz to 100 kHz, V = 3.6 V, V = 1.2 V 27 µV rms IN OUT Rev. H | Page 3 of 20

ADP220/ADP221 Data Sheet Parameter Symbol Conditions Min Typ Max Unit POWER SUPPLY REJECTION RATIO PSRR V = 2.5 V, V = 0.8 V, I = 100 mA IN OUT OUT 100 Hz 76 dB 1 kHz 76 dB 10 kHz 70 dB 100 kHz 60 dB 1 MHz 40 dB V = 3.8 V, V = 2.8 V, I = 100 mA IN OUT OUT 100 Hz 68 dB 1 kHz 68 dB 10 kHz 68 dB 100 kHz 60 dB 1 MHz 40 dB 1 Based on an end-point calculation using 1 mA and 200 mA loads. 2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.5 V. 3 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Conditions Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE1 C T = −40°C to +125°C 0.70 µF MIN A CAPACITOR ESR R T = −40°C to +125°C 0.001 1 Ω ESR A 1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with LDOs. Rev. H | Page 4 of 20

Data Sheet ADP220/ADP221 ABSOLUTE MAXIMUM RATINGS Junction-to-ambient thermal resistance (θ ) of the package is Table 3. JA based on modeling and calculation using a 4-layer board. The Parameter Rating junction-to-ambient thermal resistance is highly dependent VIN to GND –0.3 V to +6.5 V on the application and board layout. In applications where high VOUT1, VOUT2 to GND –0.3 V to VIN maximum power dissipation exists, close attention to thermal EN1, EN2 to GND –0.3 V to +6.5 V board design is required. The value of θ may vary, depending Storage Temperature Range –65°C to +150°C JA on PCB material, layout, and environmental conditions. The Operating Junction Temperature Range –40°C to +125°C specified values of θ are based on a four-layer, 4 inch × 3 inch, Soldering Conditions JEDEC J-STD-020 JA circuit board. Refer to JEDEC JESD 51-9 for detailed informa- tion on the board construction. For additional information, Stresses above those listed under Absolute Maximum Ratings see the AN-617 Application Note, MicroCSPTM Wafer Level Chip may cause permanent damage to the device. This is a stress Scale Package. rating only; functional operation of the device at these or any other conditions above those indicated in the operational ΨJB is the junction-to-board thermal characterization parameter section of this specification is not implied. Exposure to absolute with units of °C/W. ΨJB of the package is based on modeling and maximum rating conditions for extended periods may affect calculation using a 4-layer board. The JESD51-12, Guidelines device reliability. for Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as THERMAL DATA thermal resistances. Ψ measures the component power flowing JB Absolute maximum ratings apply individually only, not in through multiple thermal paths rather than a single path as in combination. thermal resistance, θ . Therefore, Ψ thermal paths include JB JB The ADP220/ADP221 can be damaged when the junction convection from the top of the package as well as radiation temperature limits are exceeded. Monitoring ambient temper- from the package. Factors that make ΨJB more useful in real- ature does not guarantee that the junction temperature (TJ) world applications. Maximum junction temperature (TJ) is is within the specified temperature limits. In applications calculated from the board temperature (TB) and power with high power dissipation and poor thermal resistance, the dissipation (PD) using the following formula: maximum ambient temperature may have to be derated. In T = T + (P × Ψ ) J B D JB applications with moderate power dissipation and low PCB Refer to JEDEC JESD51-8 and JESD51-12 for more detailed thermal resistance, the maximum ambient temperature can information on Ψ . JB exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (T) of J THERMAL RESISTANCE the device is dependent on the ambient temperature (T ), the A power dissipation of the device (PD), and the junction-to-ambient θJA and ΨJB are specified for the worst-case conditions, that is, a thermal resistance of the package (θ ). Maximum junction device soldered in a circuit board for surface-mount packages. JA temperature (T) is calculated from the ambient temperature J Table 4. (T ) and power dissipation (P ) using the following formula: A D Package Type θ Ψ Unit JA JB TJ = TA + (PD × θJA) 6-Ball, 0.5 mm Pitch WLCSP 260 43.8 °C/W 6-Ball Bumped Bare Die 260 43.8 °C/W ESD CAUTION Rev. H | Page 5 of 20

ADP220/ADP221 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 A EN1 VOUT1 B GND VIN C EN2 VOUT2 (BALNTLoO tS PtIoD V ESIE cDaWOleWN) 07572-003 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description A1 EN1 Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For automatic startup, connect EN1 to VIN. B1 GND Ground Pin. C1 EN2 Enable Input for Regulator 2. Drive EN2 high to turn on Regulator 2; drive it low to turn off Regulator 2. For automatic startup, connect EN2 to VIN. A2 VOUT1 Regulated Output Voltage 1. Connect a 1 µF or greater output capacitor between VOUT1 and GND. B2 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor. C2 VOUT2 Regulated Output Voltage 2. Connect a 1 µF or greater output capacitor between VOUT2 and GND. Rev. H | Page 6 of 20

Data Sheet ADP220/ADP221 TYPICAL PERFORMANCE CHARACTERISTICS V = 3.3 V, V = V = 2.8 V, I = 10 mA, C = C = C = 1 µF, T = 25°C, unless otherwise noted. IN OUT1 OUT2 OUT IN OUT1 OUT2 A 2.85 140 ILOAD = 10µA ILOAD = 100µA 120 2.83 ILOAD = 1mA ILOAD = 10mA TAGE (V) 2.81 IILLOOAADD == 120000mmAA RENT (µA) 10800 OL UR V C OUTPUT 2.79 GROUND 6400 IILLOOAADD == 1100µ0µAA 2.77 IILLOOAADD == 11m0mAA 20 ILOAD = 100mA ILOAD = 200mA 2.75 0 –40 JU–N5CTION TEM25PERATURE8 (5°C) 125 07572-004 –40 JU–N5CTION TEM25PERATURE8 (5°C) 125 07572-007 Figure 4. Output Voltage vs. Junction Temperature Figure 7. Ground Current vs. Junction Temperature, Single Output Loaded 2.85 120 VOUT = 2.8V VOUT = 2.8V 2.83 VTAIN == 235.°3CV 100 VTAIN == 235.°3CV AGE (V) 2.81 ENT (µA) 80 T R OL UR 60 V C UTPUT 2.79 OUND 40 O R G 2.77 20 2.75 0 0.01 0.1 LOA1D CURRENT1 0(mA) 100 1k 07572-005 0.01 0.1 LOA1D CURRENT1 0(mA) 100 1k 07572-008 Figure 5. Output Voltage vs. Load Current Figure 8. Ground Current vs. Load Current, Single Output Loaded 2.85 120 VOUT = 2.8V ILOAD = 10µA 2.83 TA = 25°C IILLOOAADD == 110m0AµA 100 ILOAD = 10mA AGE (V) 2.81 IILLOOAADD == 120000mmAA ENT (µA) 80 T R OL UR 60 V C OUTPUT 2.79 GROUND 40 IIILLLOOOAAADDD === 11100mµ0AµAA 2.77 ILOAD = 10mA 20 ILOAD = 100mA ILOAD = 200mA 2.75 0 3.3 3.5 3.7 3.9 I4N.1PUT4 V.3OLT4A.5GE 4(V.7) 4.9 5.1 5.3 5.5 07572-006 3.3 3.5 3.7 3.9 I4N.1PUT4 V.3OLT4A.5GE 4(V.7) 4.9 5.1 5.3 5.5 07572-009 Figure 6. Output Voltage vs. Input Voltage Figure 9. Ground Current vs. Input Voltage, Single Output Loaded Rev. H | Page 7 of 20

ADP220/ADP221 Data Sheet 160 0.9 3.3V 140 0.8 3.6V 4.0V A) 120 µA) 0.7 44..39VV NT (µ 100 ENT ( 0.6 5.5V E R R R 0.5 R U U 80 C D C WN 0.4 GROUN 6400 IIILLLOOOAAADDD = == 1 1100m0µµAAA SHUTDO 00..32 ILOAD = 10mA 20 ILOAD = 100mA 0.1 ILOAD = 200mA 0 –40 JU–N5CTION TEM25PERATURE8 (5°C) 125 07572-010 0–50 –25 0 T2E5MPERA50TURE (7°5C) 100 125 07572-013 Figure 10. Ground Current vs. Junction Temperature, Both Outputs Loaded Figure 13. Shutdown Current vs. Temperature at Various Input Voltages 140 250 2.5V VOUT = 2.8V 2.8V 120 VIN = 3.3V 3.3V TA = 25°C 200 A) 100 mV) RENT (µ 80 TAGE ( 150 UR OL C V GROUND 6400 DROPOUT 100 50 20 00.01 0.1 LOAD1 CURRRENT10 (mA) 100 1k 07572-011 01 1L0OAD CURRENT (m1A0)0 1k 07572-014 Figure 11. Ground Current vs. Load Current, Both Outputs Loaded Figure 14. Dropout Voltage vs. Load Current and Output Voltage 140 2.90 2.85 120 2.80 RENT (µA) 10800 TAGE (V) 22..7750 UR OL 2.65 C V GROUND 6400 IIILLLOOOAAADDD === 11100mµ0AµAA OUTPUT 22..6505 IILLOOAADD == 15mmAA ILOAD = 10mA 2.50 ILOAD = 10mA 20 ILOAD = 100mA ILOAD = 50mA ILOAD = 200mA 2.45 ILOAD = 100mA ILOAD = 200mA 0 2.40 3.3 3.5 3.7 3.9 I4N.1PUT4 V.3OLT4A.5GE 4(V.7) 4.9 5.1 5.3 5.5 07572-012 2.6 2.7 INP2U.8T VOLTAG2E.9 (V) 3.0 3.1 07572-015 Figure 12. Ground Current vs. Input Voltage, Both Outputs Loaded Figure 15. Output Voltage vs. Input Voltage (In Dropout) Rev. H | Page 8 of 20

Data Sheet ADP220/ADP221 180 –10 VRIPPLE = 50mV 200mA 160 –20 VIN = 2.5V 100mA VOUT = 0.8V 10mA 140 –30 COUT = 1µF 1mA A) 100µA µ –40 T ( 120 URREN 100 R (dB) ––5600 ND C 80 PSR –70 U O 60 GR 40 IIILLLOOOAAADDD === 151mm0mAAA ––8900 ILOAD = 50mA 20 ILOAD = 100mA –100 ILOAD = 200mA 02.6 2.7 INP2U.8T VOLTAG2E.9 (V) 3.0 3.1 07572-016 –11010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 07572-019 Figure 16. Ground Current vs. Input Voltage (In Dropout) Figure 19. Power Supply Rejection Ratio vs. Frequency, 0.8 V –10 0 VRIPPLE = 50mV 200mA 3.3V/200mA 0.8V/200mA 1.8V/200mA –20 VIN = 3.8V 100mA –10 VOUT = 2.8V 10mA 3.3V/100µA 0.8V/100µA 1.8V/100µA –30 COUT = 2.2µF 1mA –20 100µA –40 –30 B) –50 B) –40 d d R ( –60 R ( –50 R R S S P –70 P –60 –80 –70 –90 –80 –100 –90 –11010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 07572-017 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 07572-020 Figure 17. Power Supply Rejection Ratio vs. Frequency, 2.8 V Figure 20. Power Supply Rejection Ratio vs. Frequency, at Various Output Voltages and Load Currents 0 10 VRIPPLE = 50mV 200mA 3.3V µV/ Hz –10 VIN = 4.3V 100mA 2.8V µV/ Hz VOUT = 3.3V 10mA Hz) 0.8V µV/ Hz –20 COUT = 1µF 11m00AµA µV/ –30 UM ( 1 R SRR (dB) ––4500 E SPECT P –60 OIS N 0.1 –70 T U P –80 UT O –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 07572-018 0.0110 100 FREQUE1NkCY (Hz) 10k 100k 07572-021 Figure 18. Power Supply Rejection Ratio vs. Frequency, 3.3 V Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA Rev. H | Page 9 of 20

ADP220/ADP221 Data Sheet 60 T VIN = 4V TO 5V, ILOAD1 = 200mA, ILOAD2 = 100mA 50 VIN VOUT1 40 s) 2 m V r E (µ 30 S OI N 20 VOUT2 3.3V 13 2.8V 10 1.8V 0.8V 0 0.001 0.01 0L.1OAD CUR1RENT (mA1)0 100 1k 07572-022 CCHH31 51..0000mVVBWBWCH2 5.00mV TB W13.6M0%20.0μs A CH1 4.46V 07572-025 Figure 22. Output Noise vs. Load Current and Output Voltage, VIN = 5 V Figure 25. Line Transient Response, VIN = 4 V to 5 V, ILOAD1 = 200 mA, ILOAD2 = 100 mA CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2 T ILOAD1 ILOAD1 = 1mA TO 200mA, ILOAD2 = 1mA T VIN = 4V TO 5V, ILOAD1 = 200mA, ILOAD2 = 1mA VIN 1 VOUT1 2 2 VOUT1 1 3 3 VOUT2 VOUT2 CCHH31 1200.00mmAV ΩBBWWCH2 50.0mVT B 1W0.0M0%40.0μsA CH1 132mA 07572-023 CCHH31 51..0000mVVBWBWCH2 5.00mV TB W10M.0200%.0μs A CH1 4.46V 07572-026 Figure 23. Load Transient Response, Figure 26. Line Transient Response ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA VIN = 4 V to 5 V, ILOAD1 = 200 mA, ILOAD2 = 1 mA CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2 CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2 T T ILOAD1 1 1 ILOAD1 = 1mA TO 200mA, ILOAD2 = 100mA 2 VOUT1 2 3 3 VOUT2 CCHH31 1200.00mmAV ΩBBWWCH2 50.0mVT B 1W0.0M0%40.0μsA CH1 132mA 07572-024 CCHH31 25..0000VV BBWW CH2 2.00V BWT 9.8M04%0.0μs A CH1 2.10V 07572-027 Figure 24. Load Transient Response, Figure 27. Shutdown Response, ADP221 ILOAD1 = 1 mA to 200 mA, ILOAD2 = 100 mA, CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2 Rev. H | Page 10 of 20

Data Sheet ADP220/ADP221 THEORY OF OPERATION The ADP220/ADP221 are low quiescent current, low dropout Internally, the ADP220/ADP221 consist of a reference, two error linear regulators that operate from 2.5 V to 5.5 V and provide amplifiers, two feedback voltage dividers, and two PMOS pass up to 200 mA of current from each output. Drawing a low 120 μA transistors. Output current is delivered via the PMOS pass device, quiescent current (typical) at full load makes the ADP220/ which is controlled by the error amplifier. The error amplifier ADP221 ideal for battery-operated portable equipment. Shut- compares the reference voltage with the feedback voltage from down current consumption is typically 100 nA. the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device Optimized for use with small 1 µF ceramic capacitors, the is pulled lower, allowing more current to flow and increasing ADP220/ADP221 provide excellent transient performance. the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to flow and decreasing the output voltage. VIN VOUT1 60Ω The ADP221 also includes an active pull-down circuit to rapidly THERMAL CURRENT discharge the output load capacitance when each output is SHUTDOWN LIMIT disabled. The ADP220/ADP221 are available in multiple output voltage EN1 CONTROL options ranging from 0.8 V to 3.3 V. The ADP220/ADP221 use LOGIC REFERENCE ADP221 AND ONLY the EN1/EN2 pins to enable and disable the VOUT1/VOUT2 EN2 ENABLE pins under normal operating conditions. When EN1/EN2 are high, VOUT1/VOUT2 turn on; when EN1/EN2 are low, VOUT1/ ADP220 CURRENT VOUT2 turn off. For automatic startup, EN1/EN2 can be tied LIMIT to VIN. GND 60Ω VOUT2 07572-028 Figure 28. Internal Block Diagram Rev. H | Page 11 of 20

ADP220/ADP221 Data Sheet APPLICATIONS INFORMATION CAPACITOR SELECTION Input Bypass Capacitor Output Capacitor Connecting a 1 µF capacitor from VIN to GND reduces the circuit sensitivity to the PCB layout, especially when long input The ADP220/ADP221 are designed for operation with small, traces or high source impedance are encountered. If an output space-saving ceramic capacitors, but the parts function with capacitance greater than 1 µF is required, the input capacitor most commonly used capacitors as long as care is taken with should be increased to match it. regards to the effective series resistance (ESR) value. The ESR of the output capacitor affects stability of the LDO control loop. Input and Output Capacitor Properties A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less Any good quality ceramic capacitor can be used with the ADP220/ is recommended to ensure stability of the ADP220/ADP221. ADP221, as long as the capacitor meets the minimum capacit- Transient response to changes in load current is also affected by ance and maximum ESR requirements. Ceramic capacitors are output capacitance. Using a larger value of output capacitance manufactured with a variety of dielectrics, each with a different improves the transient response of the ADP220/ADP221 to large behavior over temperature and applied voltage. Capacitors must changes in the load current. Figure 29 and Figure 30 show the have an adequate dielectric to ensure the minimum capacitance transient responses for output capacitance values of 1 µF and over the necessary temperature range and dc bias conditions. 4.7 µF, respectively. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, T ILOAD1 due to their poor temperature and dc bias characteristics. Figure 31 depicts the capacitance vs. voltage bias characteristic 1 of an 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage ILOAD1 = 1mA TO 200mA, ILOAD2 = 1mA rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C tempera- 2 VOUT1 ture range and is not a function of the package or voltage rating. 3 1.2 VOUT2,COUT = 1µF CCHH31 1200.00mmAV ΩBBWWCH2 50.0mVT B 2W6.6M02%00nsA CH1 132mA 07572-029 1.0 Figure 29. Output Transient Response F) 0.8 µ ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA E ( CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2, COUT = 1 µF NC A 0.6 T CI A P T ILOAD1 CA 0.4 0.2 1 ILOAD1 = 1mA TO 200mA, ILOAD2 = 1mA 00 2 V4OLTAGE (V6) 8 10 07572-031 Figure 31. Capacitance vs. Voltage Bias Characteristic 2 VOUT1 3 VOUT2,COUT = 4.7µF CCHH31 1200.00mmAV ΩBBWWCH2 50.0mVT B 1W1.4M01%.00µsA CH1 132mA 07572-030 Figure 30. Output Transient Response ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2, COUT = 4.7 µF Rev. H | Page 12 of 20

Data Sheet ADP220/ADP221 Equation 1 can be used to determine the worst-case capacitance As shown in Figure 32, the ENx pins have built-in hysteresis. accounting for capacitor variation over temperature, compo- This prevents on/off oscillations that can occur due to noise on nent tolerance, and voltage. the ENx pins as it passes through the threshold points. C = C × (1 − TEMPCO) × (1 − TOL) (1) The active/inactive thresholds of the ENx pins are derived from EFF BIAS the VIN voltage. Therefore, these thresholds vary with changing where: input voltage. Figure 33 shows typical ENx active/inactive thresh- C is the effective capacitance at the operating voltage. BIAS olds when the input voltage varies from 2.5 V to 5.5 V. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. 1.00 In this example, TEMPCO over −40°C to +85°C is assumed to 0.95 be 15% for an X5R dielectric. TOL is assumed to be 10%, and CBIAS is 0.94 μF at 1.8 V from the graph in Figure 31. V) 0.90 D ( EN ACTIVE Substituting these values into Equation 1 yields L O 0.85 H S CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF HRE 0.80 T EN INACTIVE Therefore, the capacitor chosen in this example meets the S N 0.75 minimum capacitance requirement of the LDO over PI x N temperature and tolerance at the chosen output voltage. E 0.70 To guarantee the performance of the ADP220/ADP221, it is 0.65 imperative that the effects of dc bias, temperature, and toler- 0.60 aapnpcelisc aotnio tnh.e behavior of the capacitors be evaluated for each 2.5 3.0 3.5INPUT VO4.L0TAGE (V4).5 5.0 5.5 07572-033 Figure 33. Typical ENx Pins Thresholds vs. Input Voltage UNDERVOLTAGE LOCKOUT The ADP220/ADP221 utilize an internal soft start to limit the The ADP220/ADP221 have an internal undervoltage lockout inrush current when the output is enabled. The start-up time circuit that disables all inputs and the output when the input for the 2.8 V option is approximately 220 µs from the time the voltage is less than approximately 2.2 V. This ensures that the ENx active threshold is crossed to when the output reaches 90% inputs of the ADP220/ADP221 and the output behave in a of its final value. The start-up time is somewhat dependent on predictable manner during power-up. the output voltage setting and increases slightly as the output ENABLE FEATURE voltage increases. The ADP220/ADP221 use the ENx pins to enable and disable the VOUTx pins under normal operating conditions. Figure 32 T shows a rising voltage on ENx crossing the active threshold, then V turns on. When a falling voltage on ENx crosses the OUTx 1 inactive threshold, V turns off. OUTx T VOUTx 2 ENx 3 CCHH31 25..0000VVBBWW CH2 2.00VBWT 9.M804%0.0µs A CH1 2.10V 07572-034 Figure 34. Typical Start-Up Time 1 CH1 500mVBW CH2 500mVBTW 27M.4100%.0ms A CH2 1.76V 07572-032 Figure 32. Typical ENx Pin Operation Rev. H | Page 13 of 20

ADP220/ADP221 Data Sheet CURRENT-LIMIT AND THERMAL OVERLOAD To guarantee reliable operation, the junction temperature of PROTECTION the ADP220/ADP221 must not exceed 125°C. To ensure that the junction temperature stays below this maximum value, the The ADP220/ADP221 are protected against damage due to user needs to be aware of the parameters that contribute to junction excessive power dissipation by current and thermal overload temperature changes. These parameters include ambient tem- protection circuits. The ADP220/ADP221 are designed to perature, power dissipation in the power device, and thermal current limit when the output load reaches 300 mA (typical). resistances between the junction and ambient air (θ ). The θ When the output load exceeds 300 mA, the output voltage is JA JA number is dependent on the package assembly compounds used reduced to maintain a constant current limit. and the amount of copper to which the GND pins of the package Thermal overload protection is built-in, which limits the are soldered on the PCB. Table 6 shows typical θ values for the JA junction temperature to a maximum of 155°C (typical). Under ADP220/ADP221 for various PCB copper sizes. extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to Table 6. Typical θJA Values rise above 155°C, the output is turned off, reducing the output Copper Size (mm2) ADP220/ADP221 (°C/W) current to zero. When the junction temperature drops below 01 200 140°C, the output is turned on again and the output current 50 119 is restored to its nominal value. 100 118 300 115 Consider the case where a hard short from VOUTx to GND 500 113 occurs. At first, the ADP220/ADP221 current limit, so that only 300 mA is conducted into the short. If self-heating of the junction 1 Device soldered to minimum size pin traces. is great enough to cause its temperature to rise above 155°C, thermal shutdown activates, turning off the output and reducing The junction temperature of the ADP220/ADP221 can be the output current to zero. As the junction temperature cools calculated from the following equation: and drops below 140°C, the output turns on and conducts 300 mA T = T + (P × θ ) (2) J A D JA into the short, again causing the junction temperature to rise where: above 155°C. This thermal oscillation between 140°C and T is the ambient temperature. 155°C causes a current oscillation between 0 mA and 300 mA A P is the power dissipation in the die, given by that continues as long as the short remains at the output. D P = Σ[(V − V ) × I ] + Σ(V × I ) (3) Current and thermal limit protections are intended to protect D IN OUT LOAD IN GND the device against accidental overload conditions. For reliable where: operation, device power dissipation must be externally limited ILOAD is the load current. so that junction temperatures do not exceed 125°C. IGND is the ground current. V and V are input and output voltages, respectively. THERMAL CONSIDERATIONS IN OUT Power dissipation due to ground current is quite small and In most applications, the ADP220/ADP221 do not dissipate can be ignored. Therefore, the junction temperature equation much heat due to high efficiency. However, in applications with simplifies to a high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large TJ = TA + {Σ[(VIN − VOUT) × ILOAD] × θJA} (4) enough that it can cause the junction temperature of the die As shown in Equation 4, for a given ambient temperature, to exceed the maximum junction temperature of 125°C. input-to-output voltage differential, and continuous load When the junction temperature exceeds 155°C, the converter current, there exists a minimum copper size requirement enters thermal shutdown. It recovers only after the junction for the PCB to ensure the junction temperature does not rise temperature has decreased below 140°C to prevent any permanent above 125°C. Figure 35 to Figure 39 show junction temperature damage. Therefore, thermal analysis for the chosen application calculations for different ambient temperatures, total power is very important to guarantee reliable performance over all dissipation, and areas of PCB copper. conditions. The junction temperature of the die is the sum of In cases where the board temperature is known, the thermal the ambient temperature of the environment and the tempera- characterization parameter, Ψ , can be used to estimate the JB ture rise of the package due to the power dissipation, as shown junction temperature rise. T is calculated from T and P using J B D in Equation 2. the formula T = T + (P × Ψ ) (5) J B D JB The typical Ψ value for the 6-ball WLCSP is 43.8°C/W. JB Rev. H | Page 14 of 20

Data Sheet ADP220/ADP221 145 135 135 125 C) C) 125 E (° 115 E (° UR 105 UR T T RA 95 RA 115 E E MP 85 MP E E T 75 T N N 105 TIO 65 TIO C C N 55 N JU 500mm2 JU 95 500mm2 45 50mm2 50mm2 35 0mm2 0mm2 TJMAX TJMAX 25 85 0 0.1 0.2TO0T.A3L P0O.4WER0 D.5ISSI0P.A6TIO0N.7 (W)0.8 0.9 1.0 07572-035 0 0.1 0.2TO0T.A3L P0O.4WER0 D.5ISSI0P.A6TIO0N.7 (W)0.8 0.9 1.0 07572-038 Figure 35. Junction Temperature vs. Total Power Dissipation, TA = 25°C Figure 38. Junction Temperature vs. Total Power Dissipation, TA = 85°C 140 140 130 120 E (°C) 120 E (°C) 100 UR 110 UR T T A A ER 100 ER 80 P P M M TE 90 TE 60 N N TIO 80 TIO NC NC 40 TB = 25°C JU 70 500mm2 JU TB = 50°C 50mm2 20 TB = 65°C 60 0mm2 TB = 85°C TJMAX TJMAX 50 0 0 0.1 0.2TO0T.A3L P0O.4WER0 D.5ISSI0P.A6TIO0N.7 (W)0.8 0.9 1.0 07572-036 0 0.2 0.4 0T.6OTA0L.8 PO1W.0ER1 D.2ISS1I.P4AT1IO.6N (1W.8) 2.0 2.2 2.4 07572-039 Figure 36. Junction Temperature vs. Total Power Dissipation, TA = 50°C Figure 39. Junction Temperature vs. Total Power Dissipation and Board Temperature 145 135 C) E (° 125 R U T 115 A R E MP 105 E T ON 95 TI C N 85 JU 500mm2 50mm2 75 0mm2 TJMAX 65 0 0.1 0.2TO0T.A3L P0O.4WER0 D.5ISSI0P.A6TIO0N.7 (W)0.8 0.9 1.0 07572-037 Figure 37. Junction Temperature vs. Total Power Dissipation, TA = 65°C Rev. H | Page 15 of 20

ADP220/ADP221 Data Sheet PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP220/ADP221. However, as shown in Table 6, a point of diminishing returns eventually is reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitors as close as possible to the VOUT1, VOUT2, and GND pins. Use 0402 or 0603 size capacitors and resistors to achieve the smallest possible footprint solution on boards where area is limited. 07572-040 Figure 40. Example of PCB Layout, Top Side 07572-041 Figure 41. Example of PCB Layout, Bottom Side Rev. H | Page 16 of 20

Data Sheet ADP220/ADP221 OUTLINE DIMENSIONS 1.000 0.950 0.900 2 1 A BALLA1 IDENTIFIER 1.500 1.00 1.450 REF B 1.400 C 0.50 BSC TOP VIEW (BALL SIDE DOWN) 0.50 BSC 0.380 BOTTOM VIEW 0.675 0.355 (BALL SIDE UP) 0.595 SIDE VIEW 0.330 0.515 COPLANARITY 0.075 SEATING 0.345 0.270 PLANE 00..229455 00..224100 11-08-2012-B Figure 42. 6-Ball Wafer Level Chip Scale Package [WLCSP] (CB-6-2) Dimensions show in millimeters 1.00 0.96 0.92 2 1 A IDEBNATLIFLIEAR1 1.50 1.00 1.46 REF 1.42 B 0.50 REF C TOP VIEW (BALL SIDE DOWN) 0.50 REF BOTTOM VIEW (BALL SIDE UP) 0.330 0.225 NOM END VIEW 0.315 0.300 COPLANARITY 0.05 NOM SEATING PLANE 000...211074000 0.09 NOM 08-15-2012-A Figure 43. 6-Ball Bumped Bare Die Sales [BUMPED_CHIP] (CD-6-7) Dimensions show in millimeters Rev. H | Page 17 of 20

ADP220/ADP221 Data Sheet ORDERING GUIDE Temperature V /V Package OUT1 OUT2 Model1 Range Output Voltage (V)2 Package Description Option Branding ADP220ACBZ-1118R7 −40°C to +125°C 1.1/1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LFY ADP220ACBZ-1812R7 −40°C to +125°C 1.8/1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LEK ADP220ACBZ-1827R7 −40°C to +125°C 1.8/2.7 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LEH ADP220ACBZ-2623R7 −40°C to +125°C 2.6/2.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LGD ADP220ACBZ-26235R7 −40°C to +125°C 2.6/2.35 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L9L ADP220ACBZ-2812R7 −40°C to +125°C 2.8/1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8W ADP220ACBZ-2818R7 −40°C to +125°C 2.8/1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LEL ADP220ACBZ-2827R7 −40°C to +125°C 2.8/2.7 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8X ADP220ACBZ-2828R7 −40°C to +125°C 2.8/2.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8Y ADP220ACBZ275275R7 −40°C to +125°C 2.75/2.75 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L8Z ADP220ACBZ-3033R7 −40°C to +125°C 3.0/3.3 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LH4 ADP220ACBZ-1212R7 −40°C to +125°C 1.2/1.2 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LLT ADP220ACBZ-2525R7 −40°C to +125°C 2.5/2.5 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LLU ADP221ACBZ2828-R7 −40°C to +125°C 2.8/2.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 L90 ADP221ACBZ-1818-R7 −40°C to +125°C 1.8/1.8 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6-2 LJ0 ADP221ACDZ-1818-R7 −40°C to +125°C 1.8/1.8 6-Ball Bumped Bare Die Sales [Bump Chip] CD-6-7 LJ0 ADP220-2828-EVALZ −40°C to +125°C 2.8/2.8 2.8 V/2.8 V Evaluation Board ADP221-2828-EVALZ −40°C to +125°C 2.8/2.8 2.8 V/2.8 V with Output Discharge Evaluation Board 1 Z = RoHS Compliant Part. 2 For additional voltage options, contact a local Analog Devices sales or distribution representative. Rev. H | Page 18 of 20

Data Sheet ADP220/ADP221 NOTES Rev. H | Page 19 of 20

ADP220/ADP221 Data Sheet NOTES ©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07572-0-1/13(H) Rev. H | Page 20 of 20