Synchronous Current-Mode with Constant On-Time, PWM Buck Controller Data Sheet ADP1872/ADP1873 FEATURES TYPICAL APPLICATIONS CIRCUIT Power input voltage as low as 2.75 V to 20 V VIN = 2.75V TO 20V Bias supply voltage range: 2.75 V to 5.5 V M0.6in Vim reufmer eonuctpe uvto vltoalgtaeg wei:t 0h. 6± V1. 0% accuracy RCCC CC2 AADDPVPI11N887723/ CIN Supports all N-channel MOSFET power stages COMP/EN BST Available in 300 kHz, 600 KHz, and 1.0 MHz options VOUT RTOP FB DRVH CBST Q1L VOUT No current-sense resistor required RBOT + GND SW COUT Power saving mode (PSM) for light loads (ADP1873 only) CVDD2 Q2 VDD DRVL Resistor-programmable current-sense gain VDD T=O 2 .57.55VV PGND RRES LOAD TShheorrmt-cailr ocuvietr ploraodte pcrtoiotne ction CVDD 5A 08297-001 Precision enable input Figure 1. Integrated bootstrap diode for high-side drive 100 140 µA shutdown supply current VDD = 5.5V, VIN = 5.5V (PSM) VDD = 5.5V, VIN = 5.5V 95 Starts into a precharged load 90 Small, 10-lead MSOP package 85 APPLICATIONS %) 80 VDD = 5.5V, VIN = 13.0V (PSM) Y ( Telecom and networking systems ENC 75 VDD = 5.5V, VIN = 16.5V (PSM) Mid to high end servers CI 70 FI Set-top boxes EF 65 TA = 25°C DSP core power supplies 60 VOUT = 1.8V fSW = 300kHz 55 WURTH INDUCTOR: 744325120, L = 1.2µH, DCR = 1.8mΩ 50 INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 45100 1LkOAD CURRENT (m1A0)k 100k 08297-002 Figure 2. ADP1872 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz) GENERAL DESCRIPTION The ADP1872/ADP1873 are versatile current-mode, synchronous Available in three frequency options (300 kHz, 600 kHz, and step-down controllers that provide superior transient response, 1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are optimal stability, and current limit protection by using a constant well suited for a wide range of applications. These ICs not only on-time, pseudo-fixed frequency with a programmable current- operate from a 2.75 V to 5.5 V bias supply, but can also accept a sense gain, current-control scheme. In addition, these devices offer power input as high as 20 V. optimum performance at low duty cycles by using valley current- In addition, an internally fixed, soft start period is included to limit mode control architecture. This allows the ADP1872/ADP1873 input in-rush current from the input supply during startup and to drive all N-channel power stages to regulate output voltages to provide reverse current protection during soft start for a pre- as low as 0.6 V. charged output. The low-side current-sense, current-gain scheme The ADP1873 is the power saving mode (PSM) version of the and integration of a boost diode, along with the PSM/forced pulse- device and is capable of pulse skipping to maintain output width modulation (PWM) option, reduce the external part count regulation while achieving improved system efficiency at light and improve efficiency. loads (see the Power Saving Mode (PSM) Version (ADP1873) The ADP1872/ADP1873 operate over the −40°C to +125°C section for more information). junction temperature range and are available in a 10-lead MSOP. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.

ADP1872/ADP1873 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timer Operation ........................................................................ 21 Applications ....................................................................................... 1 Pseudo-Fixed Frequency ........................................................... 22 Typical Applications Circuit ............................................................ 1 Applications Information .............................................................. 23 General Description ......................................................................... 1 Feedback Resistor Divider ........................................................ 23 Revision History ............................................................................... 2 Inductor Selection ...................................................................... 23 Specifications ..................................................................................... 3 Output Ripple Voltage (ΔV ) .................................................. 23 RR Absolute Maximum Ratings ............................................................ 5 Output Capacitor Selection ....................................................... 23 Thermal Resistance ...................................................................... 5 Compensation Network ............................................................ 24 Boundary Condition .................................................................... 5 Efficiency Consideration ........................................................... 25 ESD Caution .................................................................................. 5 Input Capacitor Selection .......................................................... 26 Pin Configuration and Function Descriptions ............................. 6 Thermal Considerations ............................................................ 27 Typical Performance Characteristics ............................................. 7 Design Example .......................................................................... 27 ADP1872/ADP1873 Block Digram .............................................. 17 External Component Recommendations .................................... 30 Theory of Operation ...................................................................... 18 Layout Considerations ................................................................... 32 Startup .......................................................................................... 18 IC Section (Left Side of Evaluation Board) ............................. 37 Soft Start ...................................................................................... 18 Power Section ............................................................................. 37 Precision Enable Circuitry ........................................................ 18 Differential Sensing .................................................................... 37 Undervoltage Lockout ............................................................... 18 Typical Application Circuits ......................................................... 38 Thermal Shutdown ..................................................................... 18 Dual-Input, 300 kHz High Current Application Circuit ...... 38 Programming Resistor (RES) Detect Circuit .......................... 19 Single-Input, 600 kHz Application Circuit ............................. 38 Valley Current-Limit Setting .................................................... 19 Dual-Input, 300 kHz High Current Application Circuit ...... 39 Hiccup Mode During Short Circuit ......................................... 20 Outline Dimensions ....................................................................... 40 Synchronous Rectifier ................................................................ 21 Ordering Guide .......................................................................... 40 Power Saving Mode (PSM) Version (ADP1873) .................... 21 REVISION HISTORY 7/12—Rev. A to Rev. B Changes to Table 9 .......................................................................... 31 Changes to Figure 82 ...................................................................... 32 Changed R = 15 mΩ/100 kΩ Valley Current Level Value from ON Changes to Figure 83 ...................................................................... 33 7.5 to 3.87; Table 6 .......................................................................... 20 Changes to Figure 84 ...................................................................... 34 Changes to Ordering Guide .......................................................... 40 Changes to Figure 85 ...................................................................... 35 3/10—Rev. 0 to Rev. A Changes to Figure 86 ...................................................................... 36 Changes to Figure 1 .......................................................................... 1 Changes to Differential Sensing Section and Figure 88 ............ 37 Changes to Table 1 ............................................................................ 3 Changes to Figure 89 and Figure 90............................................. 38 Changes to Table 2 ............................................................................ 5 Changes to Figure 91 ...................................................................... 39 Changes to Figure 59 Caption and Figure 60 Caption .............. 16 Updated Outline Dimensions ....................................................... 40 Changes to Figure 64 ...................................................................... 17 10/09—Revision 0: Initial Version Changes to Timer Operation Section .......................................... 22 Changes to Table 7 .......................................................................... 23 Changes to Inductor Section ......................................................... 28 Rev. B | Page 2 of 40

Data Sheet ADP1872/ADP1873 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V, BST − SW = 5 V, VIN = 13 V. The specifications are valid for T = −40°C to +125°C, unless otherwise specified. J Table 1. Parameter Symbol Conditions Min Typ Max Unit POWER SUPPLY CHARACTERISTICS High Input Voltage Range VIN ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) 2.75 12 20 V ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) 2.75 12 20 V ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz) 3.0 12 20 V Low Input Voltage Range VDD C = 1 µF to PGND, C = 0.22 µF to GND IN IN ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) 2.75 5 5.5 V ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) 2.75 5 5.5 V ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz) 3.0 5 5.5 V Quiescent Current I + I FB = 1.5 V, no switching 1.1 mA Q_DD Q_BST Shutdown Current IDD, SD + IBST, SD COMP/EN < 285 mV 140 215 µA Undervoltage Lockout UVLO Rising VDD (See Figure 34 for temperature variation) 2.65 V UVLO Hysteresis Falling VDD from operational state 190 mV SOFT START Soft Start Period See Figure 57 3.0 ms ERROR AMPLIFER FB Regulation Voltage V T = 25°C 600 mV FB J T = −40°C to +85°C 595.5 600 605.4 mV J T = −40°C to +125°C 594.2 600 606.5 mV J Transconductance G 300 515 730 µs M FB Input Leakage Current I FB = 0.6 V, COMP/EN = released 1 50 nA FB, LEAK CURRENT-SENSE AMPLIFIER GAIN Programming Resistor (RES) RES = 47 kΩ ± 1% 2.7 3 3.3 V/V Value from DRVL to PGND RES = 22 kΩ ± 1% 5.5 6 6.5 V/V RES = none 11 12 13 V/V RES = 100 kΩ ± 1% 22 24 26 V/V SWITCHING FREQUENCY Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation1 ADP1872ARMZ-0.3/ 300 kHz ADP1873ARMZ-0.3 (300 kHz) On-Time VIN = 5 V, V = 2 V, T = 25°C 1120 1200 1280 ns OUT J Minimum On-Time VIN = 20 V 145 190 ns Minimum Off-Time 84% duty cycle (maximum) 320 385 ns ADP1872ARMZ-0.6/ 600 kHz ADP1873ARMZ-0.6 (600 kHz) On-Time VIN = 5 V, V = 2 V, T = 25°C 500 520 580 ns OUT J Minimum On-Time VIN = 20 V, V = 0.8 V 82 110 ns OUT Minimum Off-Time 65% duty cycle (maximum) 320 385 ns ADP1872ARMZ-1.0/ 1.0 MHz ADP1873ARMZ-1.0 (1.0 MHz) On-Time VIN = 5 V, V = 2 V, T = 25°C 285 312 340 ns OUT J Minimum On-Time VIN = 20 V 60 85 ns Minimum Off-Time 45% duty cycle (maximum) 320 385 ns Rev. B | Page 3 of 40

ADP1872/ADP1873 Data Sheet Parameter Symbol Conditions Min Typ Max Unit OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance I = 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2 3.5 Ω SOURCE Output Sink Resistance I = 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.8 2 Ω SINK Rise Time2 t BST − SW = 4.4 V, C = 4.3 nF (see Figure 59) 25 ns r, DRVH IN Fall Time2 t BST − SW = 4.4 V, C = 4.3 nF (see Figure 60) 11 ns f, DRVH IN Low-Side Driver Output Source Resistance I = 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.7 3 Ω SOURCE Output Sink Resistance I = 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.75 2 Ω SINK Rise Time2 t VDD = 5.0 V, C = 4.3 nF (see Figure 60) 18 ns r, DRVL IN Fall Time2 t VDD = 5.0 V, C = 4.3 nF (see Figure 59) 16 ns f, DRVL IN Propagation Delays DRVL Fall to DRVH Rise2 t BST − SW = 4.4 V (see Figure 59) 22 ns tpdh, DRVH DRVH Fall to DRVL Rise2 t BST − SW = 4.4 V (see Figure 60) 24 ns tpdh, DRVL SW Leakage Current I BST = 25 V, SW = 20 V, VDD = 5.5 V 110 µA SW, LEAK Integrated Rectifier Channel Impedance I = 10 mA 22 Ω SINK PRECISION ENABLE THRESHOLD Logic High Level VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V 235 285 330 mV Enable Hysteresis VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V 35 mV COMP VOLTAGE COMP Clamp Low Voltage V From disable state, release COMP/EN pin to enable 0.47 V COMP (LOW) device (2.75 V ≤ VDD ≤ 5.5 V) COMP Clamp High Voltage V (2.75 V ≤ VDD ≤ 5.5 V) 2.55 V COMP (HIGH) COMP Zero Current Threshold V (2.75 V ≤ VDD ≤ 5.5 V) 1.15 V COMP_ZCT THERMAL SHUTDOWN T TMSD Thermal Shutdown Threshold Rising temperature 155 °C Thermal Shutdown Hysteresis 15 °C Hiccup Current Limit Timing 6 ms 1 The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF and upper- and lower-side MOSFETs being Infineon BSC042N03MS G. 2 Not automatic test equipment (ATE) tested. Rev. B | Page 4 of 40

Data Sheet ADP1872/ADP1873 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply individually only, not in Table 2. combination. Unless otherwise specified, all other voltages are Parameter Rating referenced to PGND. VDD to GND −0.3 V to +6 V VIN to PGND −0.3 V to +28 V THERMAL RESISTANCE FB, COMP/EN to GND −0.3 V to (VDD + 0.3 V) θ is specified for the worst-case conditions, that is, a device JA DRVL to PGND −0.3 V to (VDD + 0.3 V) soldered in a circuit board for surface-mount packages. SW to PGND −0.3 V to +28 V SW to PGND −2 V pulse (20 ns) Table 3. Thermal Resistance BST to SW −0.6 V to (VDD + 0.3 V) Package Type θJA Unit BST to PGND −0.3 V to +28 V θ (10-Lead MSOP) JA DRVH to SW −0.3 V to VDD 2-Layer Board 213.1 °C/W PGND to GND ±0.3 V 4-Layer Board 171.7 °C/W Operating Junction Temperature −40°C to +125°C Range Storage Temperature Range −65°C to +150°C BOUNDARY CONDITION Soldering Conditions JEDEC J-STD-020 In determining the values given in Table 2 and Table 3, natural Maximum Soldering Lead 300°C convection was used to transfer heat to a 4-layer evaluation board. Temperature (10 sec) ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 5 of 40

ADP1872/ADP1873 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 10 BST COMP/EN 2 ADP1872 9 SW FB 3 TOP VIEW 8 DRVH GVDNDD 45 (Not to Scale) 76 PDGRVNLD 08297-003 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VIN High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. 2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC. 3 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. 4 GND Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations Section). 5 VDD Bias Voltage Supply for the ADP1872/ADP1873 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 µF directly from this pin to PGND and a 0.1 µF across VDD and GND are recommended. 6 DRVL Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see Figure 68). 7 PGND Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET. 8 DRVH Drive Output for the External Upper Side, N-Channel MOSFET. 9 SW Switch Node Connection. 10 BST Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VDD and BST for increased gate drive capability. Rev. B | Page 6 of 40

Data Sheet ADP1872/ADP1873 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 9905 VDVVDDI N=D = 5= .1 556V..5,5 VVV,I N(P =S 1M3)V (PSM) VDD = 5.5V, VIN = 5.5V 9905 VDDV =D D5 .=5 V5,. 5VVIN, V=I N1 3=V 5 (.P5VS M(P)SM)VDD = 5.5V, VIN = 5.5V 85 85 80 80 75 Y (%) 7705 V(VPDINSD M= = )5 5.5.5VV, VDD = 5V.5DVD, =VI N3 .=6 V1,3 VVIN = 5.5V Y (%) 6750 V(VPDINSD M= = )1 56..55VV, VDD = 5.5V, VIN = 13VVDD = 3.6V, VIN = 5.5V FICIENC 6605 VDVDD =D 5=. 53V.6, VV,I NV I=N 1=6 1.53VV FICIENC 556050 VDD = 5.5V, VIN = 16.5V EF 55 VDD = 3.6V, VIN = 16.5V EF 45 50 40 45 35 30 40 WURTH IND: 744355147, L = 0.47µH, DCR: 0.80mΩ 25 WURTH IND: 744355147, L = 0.47µH, DCR: 0.80mΩ 35 INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 20 INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 30 TA = 25°C 15 TA = 25°C 100 1LkOAD CURRENT (m1A0)k 100k 08297-004 100 1LkOAD CURRENT (m1A0)k 100k 08297-007 Figure 4. Efficiency—300 kHz, VOUT = 0.8 V Figure 7. Efficiency—600 kHz, VOUT = 0.8 V 100 100 95 VDD = 5.5V, VIN = 5.5V (PSM) VDD = 5.5V, VIN = 5.5V 95 VDD = 5.5V, = VIN = 5.5(PSM) VDD = 5.5V, VIN = 5.5V 90 90 85 85 7850 VDD = 5.5V, VIN = 16.5V (PSM) 7850 VDD = 5.5V, VIN = 16.5V Y (%) 70 VDD = 5.5V, VIN = 16.5V Y (%) 70 VDD = 5.5V, VIN = 16.5V (PSM) C 65 C 65 FFICIEN 5650 VDDV =D D3 .=6 V5,. 5VVIN, V=I N3 .=6 V13V (PSM) FFICIEN 5650 VDD = 5.5V, VIN = 13V (PSM) E 50 E 50 45 VDD = 5.5V, VIN = 13V 45 VDD = 3.6V, VIN = 5.5V 40 VDD = 3.6V, VIN = 5.5V 40 VDD = 5.5V, VIN = 13V 35 WURTH IND: 744325120, L = 1.2µH, DCR: 1.8mΩ 35 WURTH IND: 744325120, L = 1.2µH, DCR: 1.8mΩ 30 INFINEON FETS: BSC042N03MS G (UPPER/LOWER) 30 INFINEON FETS: BSC042N03MS G (UPPER/LOWER) TA = 25°C TA = 25°C 25 25 100 1LkOAD CURRENT (m1A0)k 100k 08297-005 100 1LkOAD CURRENT (m1A0)k 100k 08297-008 Figure 5. Efficiency—300 kHz, VOUT = 1.8 V Figure 8. Efficiency—600 kHz, VOUT = 1.8 V 100 100 95 VDD = 5.5V, VIN = 16.5V (PSM) 95 VVDIND = = 1 53.V5 V(P,SM) VDD = 3.6V,VIN = 13V 90 90 85 85 80 80 VDD = 5.5V, VIN = 13V %) 75 VVDIND = = 1 56.V5V, %) 75 VDD = 5.5V, VIN = 16.5V (PSM) Y ( 70 (PSM) Y ( 70 VDD = 3.6V, VIN = 16.5V C C EN 65 EN 65 FICI 60 VDD = 2.7V VDD = 3.6V VDD = 5.5V FICI 60 VDD = 5.5V, VIN = 16.5V EF 55 13VIN 13VIN 13VIN EF 55 50 16.5VIN 16.5VIN 16.5VIN 50 45 45 40 40 WURTH IND: 7443551200, L = 2µH, DCR: 2.6mΩ WURTH IND: 7443551200, L = 2µH, DCR: 2.6mΩ 35 INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 35 INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 30 TA = 25°C 30 TA = 25°C 100 1LkOAD CURRENT (m1A0)k 100k 08297-006 100 1LkOAD CURRENT (m1A0)k 100k 08297-009 Figure 6. Efficiency—300 kHz, VOUT = 7 V Figure 9. Efficiency—600 kHz, VOUT = 5 V Rev. B | Page 7 of 40

ADP1872/ADP1873 Data Sheet 100 0.8030 95 VDD = 5.5V,V VDIDN == 51.35VV ,(PSM) VDD = 5.5V, VIN = 5.5V 0.8025 90 VIN = 5.5V (PSM) 0.8020 85 0.8015 80 EFFICIENCY (%) 45566775050505 V(VPDINSD M= = )1 56..55VV, VDD = V3D.V6DVD =D, V5=I.N 55 V=.5, V5V.,I5 NVV I=N 1=3 1V6.5V UTPUT VOLTAGE (V)000000......888777000999100998050505 VIN = ++112325V5°C°C VIN = 1++612.2555°VC°C O0.7980 –40°C –40°C 40 35 VDD = 3.6V, VIN = 3.6V 0.7975 30 WURTH IND: 744303012, L = 0.12µH, DCR: 0.33mΩ 0.7970 VIN = +51.52V5°C 25 INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 0.7965 +25°C 20 TA = 25°C 0.7960 –40°C 100 1LkOAD CURRENT (m1A0)k 100k 08297-010 0 2000 4000 L6O0A00D CU8R00R0ENT1 0(,m00A0) 12,000 14,000 16,000 08297-013 Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V 100 1.821 95 VVDIND = = 1 56..55VV, (PSM)VDD = 5.5V, VIN = 5V (PSM) 90 1.816 85 %) 778050 V(VPDINSD M= = )1 53.V5V, VVDDDD == 53..56VV,, VVIINN == 1136V.5V VVDIND = = 5 5V.5V, GE (V) 1.811 FICIENCY ( 566505 VDD =V 5D.D5 V=, 3V.I6NV =, V1I3NV = 16.5V UT VOLTA 11..880061 F 50 P E T 45 U O 1.796 40 3305 WURTH IND: 744303022, L = 0.22µH, DCR: 0.33mΩ 1.791 VIN = +51.52V5°C VIN = +1132V5°C VIN = 1+61.255V°C 25 INFINEON FETs: BSC042N03MS G (UPPER/LOWER) +25°C +25°C +25°C 20 TA = 25°C 1.786 –40°C –40°C –40°C 100 1LkOAD CURRENT (m1A0)k 100k 08297-011 0 1500 3000 4500LO6A0D00 CU7R5R00ENT90 (0m0A1)0,50012,00013,50015,000 08297-014 Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V 100 7.000 95 VDD = 5.5V, VIN = 5V (PSM)VDD = 5.5V, VIN = 16.5V (PSM) VDD = 3.6V, VIN = 13V 90 6.995 VDD = 3.6V, VIN = 16.5V 85 6.990 80 %) 7705 VVDIND = = 1 53VV, GE (V) 6.985 FICIENCY ( 566505 VDD = 5V, VIN = 16.5V UT VOLTA 66..997850 F 50 P E 45 UT 6.970 O 40 6.965 35 232005 WITNAUF I=RN T2EH5O° ICNN DFE: T74s4: 3B2S5C07024,2 NL 0=3 M0.S72 Gµ H(U, DPCPERR: /1L.6O5WmEΩR) 66..995650 ++–412025°5°CC°C VVDDDD == 55..55VV,, VVIINN == 1136V.5V 100 LOAD CUR1RkENT (mA) 10k 08297-012 0 1000 2000 3000LO4A0D00 CU5R00R0EN6T0 0(m0A7)000 8000 900010,000 08297-015 Figure 12. Efficiency—1.0 MHz, VOUT = 4 V Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V Rev. B | Page 8 of 40

Data Sheet ADP1872/ADP1873 1.801 1.810 1.800 1.809 1.799 1.808 1.798 1.807 E (V) 1.797 E (V) 1.806 G G 1.805 A 1.796 A LT LT 1.804 O 1.795 O UT V 1.794 UT V 1.803 P P 1.802 OUT 1.793 OUT 1.801 1.792 1.800 1.791 VIN = 5.5V VIN = 13V VIN = 16.5V 1.799 VIN = 5.5V VIN = 13V VIN = 16.5V +125°C +125°C +125°C +125°C +125°C +125°C 1.790 +25°C +25°C +25°C 1.798 +25°C +25°C +25°C –40°C –40°C –40°C –40°C –40°C –40°C 1.7890 1500 3000 4500LO6A0D00 CU7R5R00ENT90 (0m0A1)0,50012,00013,50015,000 08297-016 1.7970 1500 3000 4500LO6A0D00 CU7R5R00ENT90 (0m0A1)0,50012,00013,50015,000 08297-019 Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V 5.044 4.050 5.042 4.045 4.040 5.040 4.035 5.038 4.030 E (V) 5.036 E (V) 4.025 G G 4.020 TA 5.034 TA 4.015 L L O 5.032 O 4.010 V V UT 5.030 UT 4.005 P P 4.000 OUT 5.028 OUT 3.995 5.026 3.990 5.024 3.985 VIN = 13V VIN = 16.5V 5.022 ++–412025°5°CC°C VVDDDD == 55..55VV,, VVIINN == 1136V.5V 33..998705 ++–412025°5°CC°C +–+421052°°5CC°C 5.0200 1000 2000 3000LO4A0D00 CU5R00R0EN6T0 0(m0A7)000 8000 900010,000 08297-017 3.9700 800 1600 2400LO3A2D00 CU4R00R0EN4T8 0(m0A5)600 6400 7200 8000 08297-020 Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 5 V Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 4 V 0.807 0.6030 VIN = 5.5V 0.806 +125°C 0.6025 +25°C –40°C 0.6020 0.805 GE (V) 0.804 AGE (V)00..66001105 A T LT 0.803 OL0.6005 O V T V 0.802 CK 0.6000 U A OUTP 0.801 FEEDB00..55999905 0.800 0.799 VIN = ++121325V5°C°C VIN = 1++612.2555°VC°C 00..55998805 VVDDDD == 23..76VV,, VVIINN == 23..76VV, T3O.6 V16.5V –40°C –40°C VDD = 5.5V, VIN = 5.5V, 13V, 16.5V 0.7980 2000 4000 L6O0A00D CU8R00R0ENT1 0(,m00A0) 12,000 14,000 16,000 08297-018 0.597–540.0 –7.5 TE25M.0PERATUR5E7 .(5°C) 90.0 122.5 08297-021 Figure 18. Output Voltage Accuracy—1 MHz, VOUT = 0.8 V Figure 21. Feedback Voltage vs. Temperature Rev. B | Page 9 of 40

ADP1872/ADP1873 Data Sheet 335 340 VDD = 5.5V +125°C NO LOAD VIN = 5.5V +125°C 325 VDD = 3.6V +–4205°°CC 325 VIN = 13V +–4205°°CC VIN = 16.5V 315 310 305 295 Hz) 295 Hz) CY (k 285 CY (k 280 N N 265 UE 275 UE REQ 265 REQ 250 F F 235 255 245 220 235 205 22510.8 11.0 11.2 11.4 11.6 11.8V1IN2 .(0V)12.2 12.4 12.6 12.8 13.0 13.2 08297-022 1900 2000 4000 L6O0A00D CU8R00R0ENT1 0(m,00A0) 12,000 14,000 16,000 08297-025 Figure 22. Switching Frequency vs. High Input Voltage, Figure 25. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V 300 kHz, ±10% of 12 V 650 360 VDD = 5.5V +125°C NO LOAD VIN = 5.5V +125°C VDD = 3.6V +–4205°°CC 350 VIN = 13V +–4205°°CC VIN = 16.5V 600 340 330 Hz) Hz) Y (k 550 Y (k 320 C C N N 310 E E U U EQ 500 EQ 300 R R F F 290 450 280 270 40010.8 11.0 11.2 11.4 11.6 11.8V1IN2 .(0V)12.2 12.4 12.6 12.8 13.0 13.2 08297-023 2600 2000 4000 6000LO8A0D00 CU10R,0R0E0N1T2, 0(m00A1)4,00016,00018,00020,000 08297-026 Figure 23. Switching Frequency vs. High Input Voltage, Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V 600 kHz, VOUT = 1.8 V, ±10% of 12 V 1000 358 950 VVDDDD == 53..56VV ++–412025°5°CC°C NO LOAD 335504 VVIINN == 1136V.5V ++–412025°5°CC°C 346 900 342 338 Hz) 850 Hz) 334 CY (k 800 CY (k 332360 N N E E 322 U 750 U Q Q 318 E E R R 314 F 700 F 310 650 306 302 600 298 294 55010.8 11.0 11.2 11.4 11.6 11.8V1IN2 .(0V)12.2 12.4 12.6 12.8 13.0 13.2 08297-024 2900 800 1600 2400 320L0O4A0D00 C4U8R00RE56N0T0 (6m40A0)7200 8000 8800 9600 08297-027 Figure 24. Switching Frequency vs. High Input Voltage, Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 7 V 1.0 MHz, ±10% of 12 V Rev. B | Page 10 of 40

Data Sheet ADP1872/ADP1873 700 1300 664700 VVIINN == 51.35VV ++–421025°5°CC°C 1125 VVIINN == 51.35VV ++–421025°5°CC°C 610 VIN = 16.5V 1150 VIN = 16.5V 580 1075 550 Hz) 520 Hz)1000 k k Y ( 490 Y ( 925 C 460 C N N 850 E 430 E U U Q 400 Q 775 E E FR 370 FR 700 340 310 625 280 550 250 475 220 1900 2000 4000 L6O0A00D CU8R00R0ENT1 0(,m00A0) 12,000 14,000 16,000 08297-028 4000 2000 4000 L6O0A00D CU8R00R0ENT1 0(,m00A0) 12,000 14,000 16,000 08297-031 Figure 28. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V Figure 31. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V 877179555 VVVIIINNN === 511.365V.V5V 11347550 VVVIIINNN === 511.365V.V5V 755 1300 735 1225 MIN-OFF TIME FREQUENCY (kHz) 566666791357915555555 FREQUENCY (kHz)111001890755205005 ENCROACHMENT 575 775 555 700 4559135550 2000 4000 6000LO8A0D00 CU10R,0R0E0N1T2, 0(0m0A1)4,00016,0001++–8,41200250°5°0CC°2C0,000 08297-029 5652050 2000 4000 6000LO8A0D00 CU10R,0R0E0N1T2, 0(0m0A1)4,00016,0001++–8,41200250°5°0CC°2C0,000 08297-032 Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V Figure 32. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V 760958 VVIINN == 1136V.5V ++–412025°5°CC°C 11445000 VVIINN == 1163.V5V ++–421025°5°CC°C 691 684 1350 677 FREQUENCY (kHz) 666666765443036925 FREQUENCY (kHz)1111322105050000 628 621 1100 614 1050 607 6000 800 1600 2400 320L0O4A0D00 C4U8R00RE56N0T0 (6m40A0)7200 8000 8800 9600 08297-030 10000 800 1600 2400LO3A2D00 CU4R00R0EN4T8 0(m0A5)600 6400 7200 8000 08297-033 Figure 30. Frequency vs. Load Current, 600 kHz, VOUT =5 V Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 4 V Rev. B | Page 11 of 40

ADP1872/ADP1873 Data Sheet 2.658 680 VDD = 2.7V 2.657 630 VDD = 3.6V VDD = 5.5V 580 2.656 ns) 530 2.655 E ( O (V)2.654 FF-TIM 448300 L O UV2.653 M U 380 M 2.652 NI MI 330 2.651 280 2.650 230 2.649–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 08297-034 180–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 08297-037 Figure 34. UVLO vs. Temperature Figure 37. Minimum Off-Time vs. Temperature 100 680 VDD = 2.7V +125°C +125°C 95 VDD = 3.6V +–4205°°CC 630 +–4205°°CC 90 VDD = 5.5V 580 CYCLE (%) 788505 TIME (ns) 543800 Y F- UT 70 OF 430 M D 65 UM 380 U M AXIM 60 MINI 330 M 55 280 50 45 230 40300 400 500 FRE6Q00UENCY7 0(0kHz) 800 900 1000 08297-035 1802.7 3.1 3.5 3.9VDD (V4).3 4.7 5.1 5.5 08297-038 Figure 35. Maximum Duty Cycle vs. Frequency Figure 38. Minimum Off-Time vs. VDD (Low Input Voltage) 7788868024 VVDDDD == 53..56VV ++–421025°5°CC°C 870200 VVVDDDDDD === 253...756VVV ++–421025°5°CC°C %) 74 640 MUM DUTY CYCLE ( 556666677680246802 TIFIER DROP (mV) 544680000 AXI 5524 REC 320 M 50 240 48 46 44 160 42 40 3.6 4.8 6.0 7.2 8.4 9V.6IN (V10).8 12.0 13.2 14.4 15.6 08297-036 80300 400 500 FRE6Q00UENCY7 0(0kHz) 800 900 1000 08297-039 Figure 36. Maximum Duty Cycle vs. High Voltage Input (VIN) Figure 39. Internal Rectifier Drop vs. Frequency Rev. B | Page 12 of 40

Data Sheet ADP1872/ADP1873 1280 1200 VVIINN == 51.35VV 130M0HkzHz TA = 25°C OUTPUT VOLTAGE 1120 VIN = 16.5V 1040 1 960 V) m 880 P ( 800 O INDUCTOR CURRENT DR 720 2 R 640 E FI 560 TI C 480 SW NODE E R 400 3 320 240 LOW SIDE 160 4 802.7 3.1 3.5 3.9VDD (V4).3 4.7 5.1 5.5 08297-040 CCHH31 1500mVV BWBW CCHH42 55VA Ω MT 4 0305n.8s% A CH2 3.90A 08297-043 Figure 40. Internal Boost Rectifier Drop vs. VDD (Low Input Voltage) Figure 43. Power Saving Mode (PSM) Operational Waveform, 100 mA over VIN Variation 720 300kHz +125°C OUTPUT VOLTAGE 1MHz +25°C 640 –40°C 1 560 V) INDUCTOR CURRENT m P ( 480 O R R D 400 2 E FI CTI 320 SW NODE E R 240 3 160 LOW SIDE 4 802.7 3.1 3.5 3.9VDD (V4).3 4.7 5.1 5.5 08297-041 CCHH31 1500mVV BWBW CCHH42 55VA Ω MT 4 .305µ.8s% A CH2 3.90A 08297-044 Figure 41. Internal Boost Rectifier Drop vs. VDD Figure 44. PSM Waveform at Light Load, 500 mA 80 300kHz +125°C OUTPUT VOLTAGE s) 72 1MHz +–4205°°CC 4 n E ( 64 M TI N 56 O TI INDUCTOR CURRENT C 48 U D N O 40 C E D 32 O DI 1 Y 24 OD SW NODE B 16 3 82.7 3.1 3.5 3.9VDD (V4).3 4.7 5.1 5.5 08297-042 CCHH31 150AV Ω CH4 100mV BW MT 4 0300n.6s% A CH3 2.20V 08297-045 Figure 42. Lower Side MOSFET Body Conduction Time vs. VDD (Low Input Voltage) Figure 45. CCM Operation at Heavy Load, 18 A (See Figure 91 for Application Circuit) Rev. B | Page 13 of 40

ADP1872/ADP1873 Data Sheet OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE 20A STEP 20A STEP 1 1 LOW SIDE SW NODE 3 2 SW NODE LOW SIDE 4 3 CCHH13 1200AV Ω CCHH24 250V0mV BW MT 2 m75s.6% A CH1 3.40A 08297-046 CCHH13 1200AV Ω CCHH24 52V00mV BW MT 2 m15s.6% A CH1 6.20A 08297-049 Figure 46. Load Transient Step—PSM Enabled, 20 A Figure 49. Load Transient Step—Forced PWM at Light Load, 20 A (See Figure 91 Application Circuit) (See Figure 91 Application Circuit) OUTPUT VOLTAGE OUTPUT VOLTAGE 2 4 20A POSITIVE STEP 20A POSITIVE STEP SW NODE 1 LOW SIDE 1 3 2 SW NODE LOW SIDE 4 3 CCHH13 1200AV Ω CCHH24 250V0mV BW MT 2 03µ0.s6% A CH1 3.40A 08297-047 CCHH13 1200AV Ω CCHH24 52V00mV BW MT 2 04µ3.s8% A CH1 6.20A 08297-050 Figure 47. Positive Step During Heavy Load Transient Behavior—PSM Enabled, Figure 50. Positive Step During Heavy Load Transient Behavior—Forced PWM 20 A, VOUT = 1.8 V (See Figure 91 Application Circuit) at Light Load, 20 A, VOUT = 1.8 V (See Figure 91 Application Circuit) OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 2 20A NEGATIVE STEP 20A NEGATIVE STEP 1 1 SW NODE SW NODE 3 3 LOW SIDE LOW SIDE 4 4 CCHH13 1200AV Ω CCHH24 250V0mV BW MT 2 04µ8.s2% A CH1 3.40A 08297-048 CCHH13 1200VA Ω CCHH24 250V0mV BW MT 1 02µ3.s8% A CH1 5.60A 08297-051 Figure 48. Negative Step During Heavy Load Transient Behavior—PSM Enabled, Figure 51. Negative Step During Heavy Load Transient Behavior—Forced PWM 20 A (See Figure 91 Application Circuit) at Light Load, 20 A (See Figure 91 Application Circuit) Rev. B | Page 14 of 40

Data Sheet ADP1872/ADP1873 OUTPUT VOLTAGE OUTPUT VOLTAGE 1 1 INDUCTOR CURRENT 2 LOW SIDE INDUCTOR CURRENT 2 4 LOW SIDE 4 SW NODE SW NODE 3 3 CCHH31 120VVBW CCHH24 55AV Ω MT 4 m49s.4% A CH1 920mV 08297-052 CCHH31 120VVBW CCHH24 55AV Ω MT 4 m41s.6% A CH1 720mV 08297-055 Figure 52. Output Short-Circuit Behavior Leading to Hiccup Mode Figure 55. Power-Down Waveform During Heavy Load 1 OUTPUT VOLTAGE OUTPUT VOLTAGE 1 INDUCTOR CURRENT INDUCTOR CURRENT 2 2 SW NODE SW NODE 3 3 LOW SIDE LOW SIDE 4 4 CCHH31 150VVBW CCHH24 150VA Ω MT 1 03µ6.s2% A CH2 8.20A 08297-053 CCHH31 1500VmVBWBW CCHH24 55AV Ω MT 2 µ35s.8% A CH2 3.90A 08297-056 Figure 53. Magnified Waveform During Hiccup Mode Figure 56. Output Voltage Ripple Waveform During PSM Operation at Light Load, 2 A OUTPUT VOLTAGE 1 OUTPUT VOLTAGE 1 INDUCTOR CURRENT LOW SIDE 2 4 LOW SIDE 4 SW NODE 3 SW NODE INDUCTOR CURRENT 3 2 CCHH31 120VVBW CCHH24 55AV Ω MT 2 m32s.8% A CH1 720mV 08297-054 CCHH31 110VVBBWW CCHH24 52AV Ω MT 1 m63s.2% A CH1 1.56V 08297-057 Figure 54. Start-Up Behavior at Heavy Load, 18 A, 300 kHz Figure 57. Soft Start and RES Detect Waveform (See Figure 91 Application Circuit) Rev. B | Page 15 of 40

ADP1872/ADP1873 Data Sheet LOW SIDE TA = 25°C 570 VVDDDD == 53..56VV VDD = 2.7V 550 S) µ 4 CE ( 530 N A HIGH SIDE CT 510 U D SW NODE CON 490 S N A R 470 T 23 M 450 HS MINUS SW CMHA3T H 5 V 2V 40ns CCHH24 52VV MT 4 02n9.s0% A CH2 4.20V 08297-058 430–40 –20 0 T2E0MPER4A0TURE6 0(°C) 80 100 120 08297-061 Figure 58. Output Drivers and SW Node Waveforms Figure 61. Transconductance (GM) vs. Temperature LOW SIDE 16ns (tf, DRVL) TA = 25°C 680 ++12255°C°C 630 –40°C S) 4 22ns (tpdh, DRVH) CE (µ 580 N HIGH SIDE TA 530 C U D ON 480 C 25ns (tr, DRVH) NS SW NODE A 430 R T 23 380 HS MINUS M SW 330 CMHA3T H 5 V 2V 40ns CCHH24 52VV MT 4 02n9.s0% A CH2 4.20V 08297-059 2.7 3.0 3.3 3.6 3.9VDD 4(V.2) 4.5 4.8 5.1 5.4 08297-062 Figure 59. Upper Side Driver Rising and Lower Side Falling Edge Waveforms Figure 62. Transconductance (GM) vs. VDD (CGATE = 4.3 nF (Upper/Lower Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)) 1.30 18ns (tr, DRVL) LOW SIDE 1.25 1.20 A)1.15 m 4 T (1.10 +125°C N HIGH SIDE 24ns (tpdh, DRVL) RE1.05 R +25°C CU1.00 T N0.95 HS MINUS CE –40°C SW S0.90 23 11ns (tf, DRVH) SW NODE QUIE0.85 0.80 M TA = 25°C 0.75 CMHA3T H 5 V 2V 20ns CCHH24 52VV MT 2 03n9.s2% A CH2 4.20V 08297-060 0.702.7 3.1 3.5 3.9VDD (V)4.3 4.7 5.1 5.5 08297-163 Figure 60. Upper Side Driver Falling and Lower Side Rising Edge Waveforms Figure 63. Quiescent Current vs. VDD (VIN = 13 V) (CGATE = 4.3 nF (Upper/Lower Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)) Rev. B | Page 16 of 40

Data Sheet ADP1872/ADP1873 ADP1872/ADP1873 BLOCK DIGRAM ADP1872/ COMP/EN PRECISION ENABLE TO ENABLE ADP1873 BLOCK ALL BLOCKS VDD BIAS tON VIN BLOCK FILTER VDD VDD BST REF_ZERO ISS SS PFM DRVH COMP CSS MSATCAHTINEE DRIVERS kΩ SW SS_REF ERROR 300 AMP DRVL FB Ω k 8 0.6V PGND PWM IREV COMP VREG CS 800kΩ LOWER AMP COMP CLAMP CS GAIN REF_ZERO CS GAIN SET ADC PROGRAMMING GND 08297-063 Figure 64. ADP1872/ADP1873 Block Diagram Rev. B | Page 17 of 40

ADP1872/ADP1873 Data Sheet THEORY OF OPERATION ADP1872/ADP1873 The ADP1872/ADP1873 are versatile current-mode, synchronous step-down controllers that provide superior transient response, FB optimal stability, and current limit protection by using a constant VDD on-time, pseudo-fixed frequency with a programmable current- sense gain, current-control scheme. In addition, these devices offer SS optimum performance at low duty cycles by using valley current- ERROR mode control architecture. This allows the ADP1872/ COMP/EN AMPLIFIER 0.6V ADP1873 to drive all N-channel power stages to regulate output CC PRECISION voltages as low as 0.6 V. CC2 ENABLE RC STARTUP TO ENABLE ALL BLOCKS The ADP1872/ADP1873 have an input low voltage pin (VDD) for 285mV bbiyapsainssg caanpda csiutoprp lsyhionugl pdo bwe elro cfoarte tdh ed iirnetcetglrya atecdro Mss OthSeF VETD Ddr i(vPeirns .5 A) 08297-064 Figure 65. Release COMP/EN Pin to Enable the ADP1872/ADP1873 and PGND (Pin 7) pins. Included in the power-up sequence is the biasing of the current-sense amplifier, the current-sense gain COMP/EN circuit (see the Programming Resistor (RES) Detect Circuit section), the soft start circuit, and the error amplifier. >2.4V HICCUP MODE INITIALIZED 2.4V MAXIMUM CURRENT (UPPER CLAMP) The current-sense blocks provide valley current information (see the Programming Resistor (RES) Detect Circuit section) and are a variable of the compensation equation for loop stability (see the Compensation Network section). The valley current 1.0V ZERO CURRENT information is extracted by forcing 0.4 V across the DRVL output USABLE RANGE ONLY AFTER SOFT START PERIOD IF CONTUNUOUS CONDUCTION and the PGND pin, which generates a current depending on the MODE OF OPERATION IS SELECTED. resistor across DRVL and PGND in a process performed by the 500mV LOWER CLAMP RES detect circuit. The current through the resistor is used to set t8h0e0 c µusr,r aenftte-rs ewnhseic ahm tphleif dierri vgea isni.g Tnhails p purlosceess asp tpakeeasr aapt ptrhoex DimRaVteLly 285m0VV P3R5EmCVIS HIOYNS TEENRAEBSLIES THRESHOLD 08297-065 and DRVH pins synchronously and the output voltage begins to Figure 66. COMP/EN Voltage Range rise in a controlled manner through the soft start sequence. UNDERVOLTAGE LOCKOUT The rise time of the output voltage is determined by the soft start The undervoltage lockout (UVLO) feature prevents the part and error amplifier blocks (see the Soft Start section). At the from operating both the upper side and lower side MOSFETs beginning of a soft start, the error amplifier charges the external at extremely low or undefined input voltage (VDD) ranges. compensation capacitor, causing the COMP/EN pin to rise above the Operation at an undefined bias voltage may result in the incorrect enable threshold of 285 mV, thus enabling the ADP1872/ADP1873. propagation of signals to the high-side power switches. This, in SOFT START turn, results in invalid output behavior that can cause damage The ADP1872/ADP1873 have digital soft start circuitry, which to the output devices, ultimately destroying the device tied at involves a counter that initiates an incremental increase in current, the output. The UVLO level has been set at 2.65 V (nominal). by 1 µA, via a current source on every cycle through a fixed internal THERMAL SHUTDOWN capacitor. The output tracks the ramping voltage by producing The thermal shutdown is a self-protection feature to prevent the IC PWM output pulses to the upper side MOSFET. The purpose is to from damage due to a very high operating junction temperature. limit the in-rush current from the high voltage input supply (VIN) If the junction temperature of the device exceeds 155°C, the to the output (V ). OUT part enters the thermal shutdown state. In this state, the device PRECISION ENABLE CIRCUITRY shuts off both the upper side and lower side MOSFETs and The ADP1872/ADP1873 employ precision enable circuitry. The disables the entire controller immediately, thus reducing the enable threshold is 285 mV typical with 35 mV of hysteresis. power consumption of the IC. The part resumes operation after The devices are enabled when the COMP/EN pin is released, the junction temperature of the part cools to less than 140°C. allowing the error amplifier output to rise above the enable threshold (see Figure 65). Grounding this pin disables the ADP1872/ADP1873, reducing the supply current of the devices to approximately 140 µA. For more information, see Figure 66. Rev. B | Page 18 of 40

Data Sheet ADP1872/ADP1873 PROGRAMMING RESISTOR (RES) DETECT CIRCUIT VALLEY CURRENT-LIMIT SETTING Upon startup, one of the first blocks to become active is the RES The architecture of the ADP1872/ADP1873 is based on valley detect circuit. This block powers up before soft start begins. It current-mode control. The current limit is determined by three forces a 0.4 V reference value at the DRVL output (see Figure 67) components: the R of the lower side MOSFET, the error amplifier ON and is programmed to identify four possible resistor values: 47 kΩ, output voltage swing (COMP), and the current-sense gain. The 22 kΩ, open, and 100 kΩ. COMP range is internally fixed at 1.4 V. The current-sense gain is programmable via an external resistor at the DRVL pin (see The RES detect circuit digitizes the value of the resistor at the the Programming Resistor (RES) Detect Circuit section). The DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code R of the lower side MOSFET can vary over temperature and that is used to program four separate gain configurations in the ON usually has a positive T (meaning that it increases with current-sense amplifier (see Figure 68). Each configuration C temperature); therefore, it is recommended to program the corresponds to a current-sense gain (A ) of 3 V/V, 6 V/V, 12 V/V, CS current-sense gain resistor based on the rated R of the 24 V/V, respectively (see Table 5 and Table 6). This variable is used ON MOSFET at 125°C. for the valley current-limit setting, which sets up the appropriate current-sense gain for a given application and sets the compensation Because the ADP1872/ADP1873 are based on valley current necessary to achieve loop stability (see the Valley Current-Limit control, the relationship between I and I is CLIM LOAD Setting and Compensation Network sections).  K  I I 1 I  ADP1872 CLIM LOAD  2  Q1 DRVH where: I is the desired valley current limit. SW CLIM I is the current load. LOAD Q2 DRVL KI is the ratio between the inductor ripple current and the PROGRCASM MGIANIGN RRES 08297-066 hdeelspirse tdo adveetreargme ilnoea dth ceu irnrdenutc t(oser ev Faliugeu r(es e1e0 t)h. eE sItnadbulicsthoirn g KI Figure 67. Programming Resistor Location Selection section), but in most cases, K = 0.33. I SW CS AMP PGND RIPPLE CURRENT =ILO3AD ADC LOAD CURRENT CS GAIN SET 0.4V DRVL VALLEY CURRENT LIMIT 08297-068 Figure 69. Valley Current Limit to Average Current Relation RES 08297-067 Wtheh ecnu rtrheen dt-esseirnesde vgaallieny c caunr rbeen tc alilmcuitl a(tIeCLdIM b)y h as been determined, Figure 68. RES Detect Circuit for Current-Sense Gain Programming 1.4V Table 5. Current-Sense Gain Programming I  CLIM A R Resistor A (V/V) CS ON CS 47 kΩ 3 where: 22 kΩ 6 ACS is the current-sense gain multiplier (see Table 5 and Table 6). Open 12 RON is the channel impedance of the lower side MOSFET. 100 kΩ 24 Although the ADP1872/ADP1873 have only four discrete current- sense gain settings for a given RON variable, Table 6 and Figure 70 outline several available options for the valley current setpoint based on various R values. ON Rev. B | Page 19 of 40

ADP1872/ADP1873 Data Sheet Table 6. Valley Current Limit Program1 The valley current limit is programmed as outlined in Table 6 Valley Current Level and Figure 70. The inductor chosen must be rated to handle the R 47 kΩ 22 kΩ Open 100 kΩ peak current, which is equal to the valley current from Table 6 ON (mΩ) A = 3 V/V A = 6 V/V A = 12 V/V A = 24 V/V plus the peak-to-peak inductor ripple current (see the Inductor CS CS CS CS 1.5 38.9 Selection section). In addition, the peak current value must be 2 29.2 used to compute the worst-case power dissipation in the MOSFETs 2.5 23.3 (see Figure 71). 3 39.0 19.5 49A 3.5 33.4 16.7 MAXIMUM DC LOAD CURRENT 4.5 26.0 13 5 23.4 11.7 39.5A 5.5 21.25 10.6 ICNUDRURCETNOTR ∆OI F= 3675A% 37A OCUOTMPUPT 35A 10 23.3 11.7 5.83 15 31.0 15.5 7.75 3.87 ∆OI F= 3303A% 30A O∆FI =32 4.255%A 32.25A 18 26.0 13.0 6.5 3.25 2.4V 1 Refer to Figure 70 for more information and a graphical representation. VALLEY CURRENT LIMIT THRESHOLD (SET FOR 25A) 39 COMP 37 OUTPUT 35 SWING 33 RES = 47kΩ A) 31 ACS = 3V/V T ( 29 MI 27 RENT LI 222531 0A 1V 08297-070 UR 19 RES = 22kΩ Figure 71. Valley Current-Limit Threshold in Relation to Inductor Ripple Current LEY C 1175 RAECSS = = N 1O2 VR/EVS ACS = 6V/V HICCUP MODE DURING SHORT CIRCUIT AL 13 V 11 A current-limit violation occurs when the current across the 9 RES = 100kΩ source and drain of the lower side MOSFET exceeds the current- 7 ACS = 24V/V 5 limit setpoint. When 32 current-limit violations are detected, 3 1 2 3 4 5 6 7 8 9RO1N0 (1m1Ω1)21314151617181920 08297-069 t6h me cs,o anltlroowllienrg e tnhtee rcso indvlee rmteor dtoe acnodol t duornwsn o. fTf htheen ,M thOeS cFoEnTtrso flolerr Figure 70. Valley Current-Limit Value vs. RON of the Lower Side MOSFET re-establishes soft start and begins to cause the output to ramp for Each Programming Resistor (RES) up again (see Figure 72). While the output ramps up, COMP is monitored to determine if the violation is still present. If it is still present, the idle event occurs again, followed by the full-chip power-down sequence. This cycle continues until the violation no longer exists. If the violation disappears, the converter is allowed to switch normally, maintaining regulation. REPEATED CURRENT LIMIT VIOLATION DETECTED HS A PREDETERMINED NUMBER SOFT START IS CLIM OF PULSES IS COUNTED TOREINITIALIZED TO ALLOW THE CONVERTER MONITOR IF THE TO COOL DOWN VIOLATION STILL EXISTS CURZREERNOT 08297-071 Figure 72. Idle Mode Entry Sequence Due to Current-Limit Violations Rev. B | Page 20 of 40

Data Sheet ADP1872/ADP1873 SYNCHRONOUS RECTIFIER As soon as the forward current through the lower side MOSFET decreases to a level where The ADP1872/ADP1873 employ an internal lower side MOSFET driver to drive the external upper side and lower side MOSFETs. 10 mV = IQ2 × RON(Q2) The synchronous rectifier not only improves overall conduction the zero-cross comparator (or I comparator) emits a signal to REV efficiency but also ensures proper charging to the bootstrap turn off the lower side MOSFET. From this point, the slope of the capacitor located at the upper side driver input. This is beneficial inductor current ramping down becomes steeper (see Figure 75) during startup to provide sufficient drive signal to the external as the body diode of the lower side MOSFET begins to conduct upper side MOSFET and attain fast turn-on response, which is current and continues conducting current until the remaining essential for minimizing switching losses. The integrated upper energy stored in the inductor has been depleted. and lower side MOSFET drivers operate in complementary fashion with built-in anticross conduction circuitry to prevent ANOTHERtON EDGE IS TRIGGERED WHEN VOUT unwanted shoot-through current that may potentially damage the FALLS BELOW REGULATION MOSFETs or reduce efficiency as a result of excessive power loss. SW tON POWER SAVING MODE (PSM) VERSION (ADP1873) The power saving mode version of the ADP1872 is the ADP1873. The ADP1873 operates in the discontinuous conduction mode HS AND LS (DCM) and pulse skips at light load to midload currents. It LS IN IDLE MODE outputs pulses as necessary to maintain output regulation. Unlike the continuous conduction mode (CCM), DCM operation prevents negative current, thus allowing improved system ZERO-CROSS COMPARATOR efficiency at light loads. Current in the reverse direction through ILOAD DETECTS 10mV OFFSET AND TURNS OFF LS this pathway, however, results in power dissipation and therefore a dHeScrease in efficiency. 0A 10mV = RON × ILOAD 08297-074 tON Figure 75. 10 mV Offset to Ensure Prevention of Negative Inductor Current The system remains in idle mode until the output voltage drops below regulation. A PWM pulse is then produced, turning on the upper side MOSFET to maintain system regulation. The ADP1873 does not have an internal clock; therefore, it switches purely as a HS AND LS ARE OFF LS OR IN IDLE MODE hysteretic controller, as described in this section. tOFF TIMER OPERATION The ADP1872/ADP1873 employ a constant on-time architecture, AS THE INDUCTOR which provides a variety of benefits, including improved load CURRENT APPROACHES ILOAD ZMEARCOH ICNUER TRUERNNTS, TOHFEF STTHAETE and line transient response when compared with a constant LOWER SIDE MOSFET. (fixed) frequency current-mode control loop of comparable 0A 08297-072 tlohoe ph digehs iignnp.u Tt hvoe lctaognes (tVanItN o)n a-ntdim thee t iomutepru, ot rv otOltNa gteim (Ver, se)n usseins g Figure 73. Discontinuous Mode of Operation (DCM) OUT SW waveform information to produce an adjustable one-shot To minimize the chance of negative inductor current buildup, PWM pulse that varies the on-time of the upper side MOSFET in an on-board, zero-cross comparator turns off all upper side response to dynamic changes in input voltage, output voltage, and and lower side switching activities when the inductor current load current conditions to maintain regulation. It then generates approaches the zero current line, causing the system to enter an on-time (t ) pulse that is inversely proportional to V . ON IN idle mode, where the upper side and lower side MOSFETs are V turned off. To ensure idle mode entry, a 10 mV offset, connected t K OUT ON VIN in series at the SW node, is implemented (see Figure 74). where K is a constant that is trimmed using an RC timer product ZERO-CROSS COMPARATOR SW for the 300 kHz, 600 kHz, and 1.0 MHz frequency options. IQ2 10mV Q2 LS 08297-073 Figure 74. Zero-Cross Comparator with 10 mV of Offset Rev. B | Page 21 of 40

ADP1872/ADP1873 Data Sheet VDD VIN To illustrate this feature more clearly, this section describes tON one such load transient event—a positive load step—in detail. During load transient events, the high-side driver output pulse C width stays relatively consistent from cycle to cycle; however, I the off-time (DRVL on-time) dynamically adjusts according to SW the instantaneous changes in the external conditions mentioned. INFORMATION R(TRIMMED) 08297-075 Wphhaesen oaf pthoesi toiuvtep luota, dV sOtUeTp) opcrcoudrusc, etsh en eewrr ovro latmagpel iifniefor r(mouatt ioofn Figure 76. Constant On-Time Timer at its output (COMP). In addition, the current-sense amplifier senses new inductor current information during this positive The constant on-time (t ) is not strictly constant because it varies ON load transient event. The error amplifier’s output voltage with VIN and V . However, this variation occurs in such a OUT reaction is compared to the new inductor current information way as to keep the switching frequency virtually independent that sets the start of the next switching cycle. Because current of VIN and V . OUT information is produced from valley current sensing, it is sensed The t timer uses a feedforward technique, applied to the constant ON at the down ramp of the inductor current, whereas the voltage on-time control loop, making it pseudo-fixed frequency to a first loop information is sensed through the counter action upswing order. Second-order effects, such as dc losses in the external power of the error amplifier’s output (COMP). MOSFETs (see the Efficiency Consideration section), cause some The result is a convergence of these two signals (see Figure 77), variation in frequency vs. load current and line voltage. These which allows an instantaneous increase in switching frequency effects are shown in Figure 22 to Figure 33. The variations in during the positive load transient event. In summary, a positive frequency are much reduced compared with the variations generated when the feedforward technique is not used. load step causes VOUT to transient down, which causes COMP to transient up and therefore shortens the off time. This resulting The feedforward technique establishes the following relationship: increase in frequency during a positive load transient helps to fSW = 1/K quickly bring VOUT back up in value and within the regulation window. where f is the controller switching frequency (300 kHz, SW 600 kHz, and 1.0 MHz). Similarly, a negative load step causes the off time to lengthen in The tON timer senses VIN and VOUT to minimize frequency variation response to VOUT rising. This effectively increases the inductor with VIN and VOUT as previously explained. This provides a demagnetizing phase, helping to bring VOUT to within regulation. pseudo-fixed frequency, see the Pseudo-Fixed Frequency section In this case, the switching frequency decreases, or experiences a for additional information. To allow headroom for VIN/V foldback, to help facilitate output voltage recovery. OUT sensing, the following two equations must be adhered to. For Because the ADP1872/ADP1873 has the ability to respond typical applications where VDD is 5 V, these equations are not rapidly to sudden changes in load demand, the recovery period relevant; however, for lower VDD, care may be required. in which the output voltage settles back to its original steady V ≥ VIN/8 + 1.5 state operating point is much quicker than it would be for a DD fixed-frequency equivalent. Therefore, using a pseudo-fixed V ≥ V /4 DD OUT frequency, results in significantly better load transient PSEUDO-FIXED FREQUENCY performance than using a fixed frequency. The ADP1872/ADP1873 employ a constant on-time control scheme. During steady state operation, the switching frequency stays relatively constant, or pseudo-fixed. This is due to the one- shot t timer that produces a high-side PWM pulse with a fixed LOAD CURRENT ON DEMAND duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state. During CS AMP OUTPUT load transients, the frequency momentarily changes for the duration of the transient event so that the output comes back ERROR AMP within regulation quicker than if the frequency were fixed or if OUTPUT VALLEY TRIP POINTS it were to remain unchanged. After the transient event is complete, the frequency returns to a pseudo-fixed value to a first-order. PWM OUTPUT fSW >fSW 08297-076 Figure 77. Load Transient Response Operation Rev. B | Page 22 of 40

Data Sheet ADP1872/ADP1873 APPLICATIONS INFORMATION FEEDBACK RESISTOR DIVIDER Table 7. Recommended Inductors The required resistor divider network can be determine for a L DCR ISAT Dimensions (µH) (mΩ) (A) (mm) Manufacturer Model No. given V value because the internal band gap reference (V ) OUT REF 0.12 0.33 55 10.2 × 7 Würth Elektronic 744303012 is fixed at 0.6 V. Selecting values for R and R determines the T B 0.22 0.33 30 10.2 × 7 Würth Elektronic 744303022 minimum output load current of the converter. Therefore, for a 0.47 0.8 50 14.2 × 12.8 Würth Elektronic 744355147 given value of RB, the RT value can be determined by 0.72 1.65 35 10.5 × 10.2 Würth Elektronic 744325072 (V −0.6V) 0.9 1.6 28 13 × 12.8 Würth Elektronic 744355090 R =R × OUT 1.2 1.8 25 10.5 × 10.2 Würth Elektronic 744325120 T B 0.6V 1.0 3.3 20 10.5 × 10.2 Würth Elektronic 7443552100 1.4 3.2 24 14 × 12.8 Würth Elektronic 744318180 INDUCTOR SELECTION 2.0 2.6 22 13.2 × 12.8 Würth Elektronic 7443551200 The inductor value is inversely proportional to the inductor 0.8 27.5 Sumida CEP125U-0R8 ripple current. The peak-to-peak ripple current is given by I OUTPUT RIPPLE VOLTAGE (ΔV ) ∆I =K ×I ≈ LOAD RR L I LOAD 3 The output ripple voltage is the ac component of the dc output where K is typically 0.33. voltage during steady state. For a ripple error of 1.0%, the output I capacitor value needed to achieve this tolerance can be determined The equation for the inductor value is given by using the following equation. (Note that an accuracy of 1.0% is L=(VIN−VOUT)×VOUT only possible during steady state conditions, not during load ∆I ×f VIN transients.) L SW where: ΔVRR = (0.01) × VOUT VIN is the high voltage input. OUTPUT CAPACITOR SELECTION V is the desired output voltage. OUT The primary objective of the output capacitor is to facilitate f is the controller switching frequency (300 kHz, 600 kHz, SW the reduction of the output voltage ripple; however, the output and 1.0 MHz). capacitor also assists in the output voltage recovery during load When selecting the inductor, choose an inductor saturation rating transient events. For a given load current step, the output voltage that is above the peak current level and then calculate the ripple generated during this step event is inversely proportional inductor current ripple (see the Valley Current-Limit Setting to the value chosen for the output capacitor. The speed at which section and Figure 78). the output voltage settles during this recovery period depends 52 on where the crossover frequency (loop bandwidth) is set. This 50 48 ΔI = 50% crossover frequency is determined by the output capacitor, the 46 T (A) 444024 ΔI = 40% ecoqmuivpaelnesnatt isoenri ense rtwesoisrtka.n ce (ESR) of the capacitor, and the N E 38 RR 36 To calculate the small signal voltage ripple (output ripple U 34 OR C 3302 ΔI = 33% voltage) at the steady state operating point, use the following T 28 equation: UC 26 D 24 PEAK IN 11226802 COUT =∆IL×8×fSW×[∆VRIPP1LE−(∆IL×ESR)] 14 12 where ESR is the equivalent series resistance of the output 10 86 8 10 12VA1L4LEY1 C6UR1R8ENT2 0LIMI2T2 (A)24 26 28 30 08297-077 cTaop caaclictourlast. e the output load step, use the following equation: Figure 78. Peak Current vs. Valley Current Threshold for ∆I 33%, 40%, and 50% of Inductor Ripple Current C =2× LOAD OUT f ×(∆V −(∆I ×ESR)) SW DROOP LOAD where ΔV is the amount that V is allowed to deviate for DROOP OUT a given positive load current step (ΔI ). LOAD Rev. B | Page 23 of 40

ADP1872/ADP1873 Data Sheet Ceramic capacitors are known to have low ESR. However, the Error Amplifier Output Impedance (Z ) COMP trade-off of using X5R technology is that up to 80% of its capaci- Assuming C is significantly smaller than C , C can be C2 COMP C2 tance may be lost due to derating because the voltage applied omitted from the output impedance equation of the error amplifier. across the capacitor is increased (see Figure 79). Although X7R The transfer function simplifies to series capacitors can also be used, the available selection is R (f + f ) limited to only up to 22 µF. Z = COMP CROSS ZERO COMP f 20 CROSS 10 and X7R (50V) 0 1 E (%)–10 fCROSS =12×fSW G–20 HAR–30 where fZERO, the zero frequency, is set to be 1/4th of the crossover E C–40 frequency for the ADP1872. C N A–50 Error Amplifier Gain (G ) PACIT–60 X5R (25V) The error amplifier gain (trMansconductance) is CA–70 X5R (16V) –80 GM = 500 µA/V 10µF TDK 25V, X7R, 1210 C3225X7R1E106M –90 22µF MURATA 25V, X7R, 1210 GRM32ER71E226KE15L Current-Sense Loop Gain (G ) 47µF MURATA 16V, X5R, 1210 GRM32ER61C476KE15L CS –100 0 5 10DC VOLT1A5GE (VDC)20 25 30 08297-078 The current-sens1e loop gain is Figure 79. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors G = (A/V) CS A ×R CS ON Electrolytic capacitors satisfy the bulk capacitance requirements for most high current applications. Because the ESR of electrolytic where: capacitors is much higher than that of ceramic capacitors, when ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V using electrolytic capacitors, several MLCCs should be mounted (see the Programming Resistor (RES) Detect Circuit and Valley in parallel to reduce the overall series resistance. Current-Limit Setting sections). R is the channel impedance of the lower side MOSFET. COMPENSATION NETWORK ON Crossover Frequency Due to its current-mode architecture, the ADP1872/ADP1873 require Type II compensation. To determine the component The crossover frequency is the frequency at which the overall values needed for compensation (resistance and capacitance loop (system) gain is 0 dB (H = 1 V/V). It is recommended for values), it is necessary to examine the converter’s overall loop current-mode converters, such as the ADP1872, that the user gain (H) at the unity gain frequency (f /10) when H = 1 V/V. set the crossover frequency between 1/10th and 1/15th of the SW switching frequency. V H=1V/V=G ×G × OUT ×Z ×Z M CS VREF COMP FILT fCROSS =112 fSW Examining each variable at high frequency enables the unity The relationship between C and f (zero frequency) is gain transfer function to be simplified to provide expressions COMP ZERO for the R and C component values. 1 COMP COMP f = Output Filter Impedance (ZFILT) ZERO 2π×RCOMP×CCOMP Examining the filter’s transfer function at high frequencies The zero frequency is set to 1/4th of the crossover frequency. simplifies to Combining all of the above parameters results in ZFILTER = sC1OUT RCOMP = fCROSfSCR+OSfSZERO ×2πfGCRMOGSSCCSOUT ×VVORUEFT at the crossover frequency (s = 2πfCROSS). 1 C = COMP 2×π×R ×f COMP ZERO Rev. B | Page 24 of 40

Data Sheet ADP1872/ADP1873 EFFICIENCY CONSIDERATION 800 VDD = 2.7V One of the important criteria to consider in constructing a dc-to-dc 720 VDD = 3.6V VDD = 5.5V converter is efficiency. By definition, efficiency is the ratio of the 640 output power to the input power. For high power applications at V) m 560 load currents up to 20 A, the following are important MOSFET P ( O parameters that aid in the selection process: R 480 D R  VGS (TH): the MOSFET support voltage applied between the TIFIE 400 gate and the source. EC 320 R  RDS (ON): the MOSFET on resistance during channel 240 conduction. +125°C 160  QG: the total gate charge +–4205°°CC  CCNN12:: tthhee iinnppuutt ccaappaacciittaannccee ooff tthhee luopwpeerr ssiiddee sswwiittcchh 80300 400 500 FRE6Q00UENCY7 0(k0Hz) 800 900 1000 08297-079 Figure 80. Internal Rectifier Voltage Drop vs. Switching Frequency The following are the losses experienced through the external MOSFET Switching Loss component during normal switching operation: The SW node transitions due to the switching activities of the  Channel conduction loss (both the MOSFETs) upper side and lower side MOSFETs. This causes removal and  MOSFET driver loss replenishing of charge to and from the gate oxide layer of the  MOSFET switching loss MOSFET, as well as to and from the parasitic capacitance  Body diode conduction loss (lower side MOSFET) associated with the gate oxide edge overlap and the drain and  Inductor loss (copper and core loss) source terminals. The current that enters and exits these charge Channel Conduction Loss paths presents additional loss during these transition times. This can be approximately quantified by using the following During normal operation, the bulk of the loss in efficiency is due equation, which represents the time in which charge enters and to the power dissipated through MOSFET channel conduction. exits these capacitive regions. Power loss through the upper side MOSFET is directly proportional to the duty cycle (D) for each switching period, and the power tSW-TRANS = RGATE × CTOTAL loss through the lower side MOSFET is directly proportional to where: 1 − D for each switching period. The selection of MOSFETs is R is the gate input resistance of the MOSFET. GATE governed by the amount of maximum dc load current that the C is the C + C of the external MOSFET used. TOTAL GD GS converter is expected to deliver. In particular, the selection of The ratio of this time constant to the period of one switching cycle the lower side MOSFET is dictated by the maximum load is the multiplying factor to be used in the following expression: current because a typical high current application employs duty cycles of less than 50%. Therefore, the lower side MOSFET is in t P  SW-TRANS I VIN2 the on state for most of the switching period. SW(LOSS) t LOAD SW P = [D × R + (1 − D) × R ] × I2 or N1, N2 (CL) N1 (ON) N2 (ON) LOAD MOSFET Driver Loss PSW (LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2 Other dissipative elements are the MOSFET drivers. The contributing factors are the dc current flowing through the driver during operation and the Q parameter of the external GATE MOSFETs.    P  V  f C V I  DR(LOSS) DR SW upperFETDR BIAS V  f C V I DD SW lowerFET DD BIAS where: C is the input gate capacitance of the upper-side MOSFET. upperFET C is the input gate capacitance of the lower-side MOSFET. lowerFET V is the driver bias voltage (that is, the low input voltage (V ) DR DD minus the rectifier drop (see Figure 80)). I is the dc current flowing into the upper- and lower-side drivers. BIAS V is the bias voltage. DD Rev. B | Page 25 of 40

ADP1872/ADP1873 Data Sheet Body Diode Conduction Loss INPUT CAPACITOR SELECTION The ADP1872/ADP1873 employ anticross conduction circuitry The goal in selecting an input capacitor is to reduce or to minimize that prevents the upper side and lower side MOSFETs from input voltage ripple and to reduce the high frequency source conducting current simultaneously. This overlap control is impedance, which is essential for achieving predictable loop beneficial, avoiding large current flow that may lead to stability and transient performance. irreparable damage to the external components of the power The problem with using bulk capacitors, other than their physical stage. However, this blanking period comes with the trade-off of geometries, is their large equivalent series resistance (ESR) and a diode conduction loss occurring immediately after the large equivalent series inductance (ESL). Aluminum electrolytic MOSFETs change states and continuing well into idle mode. capacitors have such high ESR that they cause undesired input The amount of loss through the body diode of the lower side voltage ripple magnitudes and are generally not effective at high MOSFET during the antioverlap state is given by switching frequencies. t P  BODY(LOSS)I V 2 If bulk capacitors are to be used, it is recommended to use multi- BODY(LOSS) tSW LOAD F layered ceramic capacitors (MLCC) in parallel due to their low ESR values. This dramatically reduces the input voltage ripple where: amplitude as long as the MLCCs are mounted directly across t is the body conduction time (refer to Figure 81 for BODY (LOSS) the drain of the upper side MOSFET and the source terminal of dead time periods). the lower side MOSFET (see the Layout Considerations section). t is the period per switching cycle. SW Improper placement and mounting of these MLCCs may cancel V is the forward drop of the body diode during conduction. F their effectiveness due to stray inductance and an increase in (Refer to the selected external MOSFET data sheet for more trace impedance. information about the V parameter.) F   80 V  VINV 1MHz +125°C I I  OUT OUT s) 72 300kHz +–4205°°CC CIN,RMS LOAD,MAX VOUT n ME ( 64 The maximum input voltage ripple and maximum input capacitor N TI 56 rms current occur at the end of the duration of 1 − D while the O TI upper side MOSFET is in the off state. The input capacitor rms DUC 48 current reaches its maximum at time D. When calculating the N CO 40 maximum input voltage ripple, account for the ESR of the input E OD 32 capacitor as follows: DI DY 24 VMAX, RIPPLE = VRIPP + (ILOAD, MAX × ESR) O B 16 where: V is usually 1% of the minimum voltage input. 8 RIPP 2.7 3.4 VD4D. 1(V) 4.8 5.5 08297-080 IELSORAD ,i Ms AtXh ies etqhue imvaalxenimt suemri elso areds cisutarrnecnet .r ating of the input Figure 81. Body Diode Conduction Time vs. Low Voltage Input (VDD) capacitor used. Inductor Loss Inserting V into the charge balance equation to calculate MAX, RIPPLE During normal conduction mode, further power loss is caused the minimum input capacitor requirement gives by the conduction of current through the inductor windings, I D(1D) which have dc resistance (DCR). Typically, larger sized inductors C  LOAD,MAX  IN,min V f have smaller DCR values. MAX,RIPPLE SW The inductor core loss is a result of the eddy currents generated or within the core material. These eddy currents are induced by the I changing flux, which is produced by the current flowing through C  LOAD,MAX IN,min 4f V the windings. The amount of inductor core loss depends on the SW MAX,RIPPLE core material, the flux swing, the frequency, and the core volume. where D = 50%. Ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. It is recommended to use shielded ferrite core material type inductors with the ADP1872/ADP1873 for a high current, dc-to-dc switching application to achieve minimal loss and negligible electromagnetic interference (EMI). PDCR (LOSS) = DCR × IL2OAD+ Core Loss Rev. B | Page 26 of 40

Data Sheet ADP1872/ADP1873 THERMAL CONSIDERATIONS For example, if the external MOSFET characteristics are θ JA (10-lead MSOP) = 171.2°C/W, f = 300 kHz, I = 2 mA, The ADP1872/ADP1873 are used for dc-to-dc, step down, high SW BIAS C = 3.3 nF, C = 3.3 nF, V = 5.12 V, and V = 5.5 V, current applications that have an on-board controller and on-board upperFET lowerFET DR DD then the power loss is MOSFET drivers. Because applications may require up to 20 A of load current delivery and be subjected to high ambient temperature PDR (LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VDD × surroundings, the selection of external upper side and lower side (fSWClowerFETVDD + IBIAS)] MOSFETs must be associated with careful thermal consideration = [5.12 × (300 × 103 × 3.3 × 10−9 × 5.12 + 0.002)] + to not exceed the maximum allowable junction temperature [5.5 × (300 × 103 ×3.3 × 10−9 × 5.5 + 0.002)] of 125°C. To avoid permanent or irreparable damage if the = 77.13 mW junction temperature reaches or exceeds 155°C, the part enters The rise in package temperature is thermal shutdown, turning off both external MOSFETs, and T = θ × P does not re-enable until the junction temperature cools to 140°C R JA DR (LOSS) = 171.2°C × 77.13 mW (see the Thermal Shutdown section). = 13.2°C The maximum junction temperature allowed for the ADP1872/ Assuming a maximum ambient temperature environment of 85°C, ADP1873 ICs is 125°C. This means that the sum of the ambient the junction temperature is temperature (T ) and the rise in package temperature (T ), which A R is caused by the thermal impedance of the package and the internal TJ = TR × TA = 13.2°C + 85°C = 98.2°C power dissipation, should not exceed 125°C, as dictated by which is below the maximum junction temperature of 125°C. TJ = TR × TA DESIGN EXAMPLE where: The ADP1872/ADP1873 are easy to use, requiring only a few T is the maximum junction temperature. J design criteria. For example, the example outlined in this section T is the rise in package temperature due to the power R uses only four design criteria: V = 1.8 V, I = 15 A (pulsing), OUT LOAD dissipated from within. VIN = 12 V (typical), and f = 300 kHz. SW T is the ambient temperature. A Input Capacitor The rise in package temperature is directly proportional to its The maximum input voltage ripple is usually 1% of the thermal impedance characteristics. The following equation minimum input voltage (11.8 V × 0.01 = 120 mV). represents this proportionality relationship: V = 120 mV T = θ × P RIPP R JA DR (LOSS) V = V − (I × ESR) where: MAX, RIPPLE RIPP LOAD, MAX = 120 mV − (15 A × 0.001) = 45 mV θ is the thermal resistance of the package from the junction to JA the outside surface of the die, where it meets the surrounding air. I 15A C = LOAD,MAX = PDR (LOSS) is the overall power dissipated by the IC. IN,min 4fSWVMAX,RIPPLE 4×300×103×105mV The bulk of the power dissipated is due to the gate capacitance = 120 µF of the external MOSFETs. The power loss equation of the Choose five 22 µF ceramic capacitors. The overall ESR of five MOSFET drivers (see the MOSFET Driver Loss section in the 22 µF ceramic capacitors is less than 1 mΩ. Efficiency Consideration section) is I = I /2 = 7.5 A RMS LOAD P = [V × (f C V + I )] + [V × DR (LOSS) DR SW upperFET DR BIAS DD P = (I )2 × ESR = (7.5A)2 × 1 mΩ = 56.25 mW (f C V + I )] CIN RMS SW lowerFET DD BIAS Inductor where: C is the input gate capacitance of the upper side MOSFET. Determining inductor ripple current amplitude: upperFET C is the input gate capacitance of the lower side MOSFET. lowerFET I IBIAS is the dc current (2 mA) flowing into the upper side and ∆IL ≈ LO3AD = 5 A lower side drivers. so calculating for the inductor value V is the driver bias voltage (that is, the low input voltage (V ) DR DD minus the rectifier drop (see Figure 80)). L=(VIN,MAX −VOUT)× VOUT VDD is the bias voltage ∆I × f V L SW IN,MAX (13.2V−1.8V) 1.8V = × 5V×300×103 13.2V = 1.03 µH Rev. B | Page 27 of 40

ADP1872/ADP1873 Data Sheet The inductor peak current is approximately Choose five 270 µF polymer capacitors. 15 A + (5 A × 0.5) = 17.5 A The rms current through the output capacitor is Therefore, an appropriate inductor selection is 1.0 µH with 1 1 (V −V ) V I = × IN,MAX OUT × OUT DCR = 3.3 mΩ (7443552100) from Table 7 with peak current RMS 2 3 L×f V SW IN,MAX handling of 20 A. 1 1 (13.2V−1.8V) 1.8V = × × =1.49A P =DCR×I2 2 3 1μF×300×103 13.2V DCR(LOSS) LOAD = 0.003 × (15 A)2 = 675 mW The power loss dissipated through the ESR of the output Current Limit Programming capacitor is The valley current is approximately PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW 15 A − (5 A × 0.5) = 12.5 A Feedback Resistor Network Setup Assuming a lower side MOSFET RON of 4.5 mΩ, choosing 13 A It is recommended to use RB = 15 kΩ. Calculate RT as as the valley current limit from Table 6 and Figure 70 indicates (1.8V−0.6V) that a programming resistor (RES) of 100 kΩ corresponds to an R =15kΩ× =30kΩ T 0.6V A of 24 V/V. CS Compensation Network Choose a programmable resistor of R = 100 kΩ for a current- RES sense gain of 24 V/V. To calculate RCOMP, CCOMP, and CPAR, the transconductance parameter and the current-sense gain variable are required. The Output Capacitor transconductance parameter (G ) is 500 µA/V, and the current- M Assume a load step of 15 A occurs at the output and no more sense loop gain is than 5% is allowed for the output to deviate from the steady 1 1 state operating point. The ADP1872’s advantage is, because the G = = =8.33A/V frequency is pseudo-fixed, the converter is able to respond CS ACSRON 24×0.005 quickly because of the immediate, though temporary, increase where A and R are taken from setting up the current limit CS ON in switching frequency. (see the Programming Resistor (RES) Detect Circuit and Valley ΔV = 0.05 × 1.8 V = 90 mV Current-Limit Setting sections). DROOP Assuming the overall ESR of the output capacitor ranges from The crossover frequency is 1/12th of the switching frequency: 5 mΩ to 10 mΩ, 300 kHz/12 = 25 kHz C =2× ∆ILOAD The zero frequency is 1/4th of the crossover frequency: OUT f ×(∆V ) SW DROOP 25 kHz/4 = 6.25 kHz 15A =2×300×103×(90mV) R = fCROSS ×2πfCROSSCOUT ×VOUT COMP f + f G G V = 1.11 mF CROSS ZERO M CS REF 25×103 2×3.141×25×103×1.11×10−3 1.8 Therefore, an appropriate inductor selection is five 270 µF = × × 25×103+6.25×103 500×10−6×8.3 0.6 polymer capacitors with a combined ESR of 3.5 mΩ. = 100 kΩ Assuming an overshoot of 45 mV, determine if the output 1 capacitor that was calculated previously is adequate: C = COMP 2πR f COUT = ((V −∆(LV×I2LOA)2D−)(V )2) = COM1P ZERO OUT OVSHT OUT 2×3.14×100×103×6.25×103 1×10−6×(15A)2 = = 250 pF (1.8−45mV)2−(1.8)2 = 1.4 mF Rev. B | Page 28 of 40

Data Sheet ADP1872/ADP1873 Loss Calculations P = f × R × C × I × VIN × 2 SW (LOSS) SW GATE TOTAL LOAD = 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2 Duty cycle = 1.8/12 V = 0.15 = 534.6 mW RON (N2) = 5.4 mΩ [ ( )] P = V × f C V +I + tBODY(LOSS) = 20 ns (body conduction time) [DR(LOS(S) DR SW upperFET)]DR BIAS V × f C V +I V = 0.84 V (MOSFET forward voltage) DD SW lowerFET DD BIAS F = (5.12 × (300 × 103 × 3.3 × 10−9 × 5.12 + 0.002)) + CIN = 3.3 nF (MOSFET gate input capacitance) (5.5 × (300 × 103 ×3.3 ×10−9 ×5.5 + 0.002)) Q = 17 nC (total MOSFET gate charge) = 77.13 mW N1, N2 RGATE = 1.5 Ω (MOSFET gate input resistance) PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW [ ] P = D×R +(1−D)×R ×I2 P =DCR×I2 = 0.003 × (15 A)2 = 675 mW N1,N2(CL) N1(ON) N2(ON) LOAD DCR(LOSS) LOAD = (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)2 P = (I )2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW CIN RMS = 1.215 W P = P + P + P + P + P + P + P LOSS N1, N2 BODY (LOSS) SW DCR DR COUT CIN P =tBODY(LOSS)×I ×V ×2 = 1.215 W + 151.2 mW + 534.6 mW + 77.13 mW + BODY(LOSS) t LOAD F 3.15 mW + 675 mW + 56.25 mW SW = 20 ns × 300 × 103 × 15 A × 0.84 × 2 = 2.62 W = 151.2 mW Rev. B | Page 29 of 40

ADP1872/ADP1873 Data Sheet EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 8 are with f = 1/12 × f , f = ¼ × f , R = 100 kΩ, R = 15 kΩ, R = 5.4 mΩ (BSC042N03MS G), CROSS SW ZERO CROSS RES BOT ON V = 5 V, and a maximum load current of 14 A. DD The ADP1873 models listed in Table 8 are the PSM versions of the device. Table 8. External Component Values Marking Code V VIN L1 R C C R OUT C COMP PAR TOP SAP Model ADP1872 ADP1873 (V) (V) C (µF) C (µF) (µH) (kΩ) (pF) (pF) (kΩ) IN OUT ADP1872ARMZ-0.3-R7/ LDT LDF 0.8 13 5 × 222 5 × 5603 0.72 47 740 74 5.0 ADP1873ARMZ-0.3-R7 LDT LDF 1.2 13 5 × 222 4 × 5603 1.0 47 740 74 15.0 LDT LDF 1.8 13 4 × 222 4 × 2704 1.0 47 571 57 30.0 LDT LDF 2.5 13 4 × 222 3 × 2704 1.53 47 571 57 47.5 LDT LDF 3.3 13 5 × 222 2 × 3305 2.0 47 571 57 67.5 LDT LDF 5 13 4 × 222 3305 3.27 34 800 80 110.0 LDT LDF 7 13 4 × 222 222 + (4 × 476) 3.44 34 800 80 160.0 LDT LDF 1.2 16.5 4 × 222 4 × 5603 1.0 47 740 74 15.0 LDT LDF 1.8 16.5 3 × 222 4 × 2704 1.0 47 592 59 30.0 LDT LDF 2.5 16.5 3 × 222 4 × 2704 1.67 47 592 59 47.5 LDT LDF 3.3 16.5 3 × 222 2 × 3305 2.00 47 592 59 67.5 LDT LDF 5 16.5 3 × 222 2 × 1507 3.84 34 829 83 110.0 LDT LDF 7 16.5 3 × 222 222 + 4 × 476 4.44 34 829 83 160.0 ADP1872ARMZ-0.6-R7/ LDU LDK 0.8 5.5 5 × 222 4 × 5603 0.22 47 339 34 5.0 ADP1873ARMZ-0.6-R7 LDU LDK 1.2 5.5 5 × 222 4 × 2704 0.47 47 326 33 15.0 LDU LDK 1.8 5.5 5 × 222 3 × 2704 0.47 47 271 27 30.0 LDU LDK 2.5 5.5 5 × 222 3 × 1808 0.47 47 271 27 47.5 LDU LDK 1.2 13 3 × 222 5 × 2704 0.47 47 407 41 15.0 LDU LDK 1.8 13 5 × 109 3 × 3305 0.47 47 307 31 30.0 LDU LDK 2.5 13 5 × 109 3 × 2704 0.90 47 307 31 47.5 LDU LDK 3.3 13 5 × 109 2 × 2704 1.00 47 307 31 67.5 LDU LDK 5 13 5 × 109 1507 1.76 34 430 43 110.0 LDU LDK 1.2 16.5 3 × 109 4 × 2704 0.47 47 362 36 15.0 LDU LDK 1.8 16.5 4 × 109 2 × 3305 0.72 47 326 33 30.0 LDU LDK 2.5 16.5 4 × 109 3 × 2704 0.90 47 326 33 47.5 LDU LDK 3.3 16.5 4 × 109 3305 1.0 47 296 30 67.5 LDU LDK 5 16.5 4 × 109 4 × 476 2.0 34 415 41 110.0 LDU LDK 7 16.5 4 × 109 3 × 476 2.0 34 380 38 160.0 ADP1872ARMZ-1.0-R7/ LDV LDL 0.8 5.5 5 × 222 4 × 2704 0.22 47 223 22 5.0 ADP1873ARMZ-1.0-R7 LDV LDL 1.2 5.5 5 × 222 2 × 3305 0.22 47 223 22 15.0 LDV LDL 1.8 5.5 3 × 222 3 × 1808 0.22 47 163 16 30.0 LDV LDL 2.5 5.5 3 × 222 2704 0.22 47 163 16 47.5 LDV LDL 1.2 13 3 × 109 3 × 3305 0.22 47 233 23 15.0 LDV LDL 1.8 13 4 × 109 3 × 2704 0.47 47 210 21 30.0 LDV LDL 2.5 13 4 × 109 2704 0.47 47 210 21 47.5 LDV LDL 3.3 13 5 × 109 2704 0.72 47 210 21 67.5 LDV LDL 5 13 4 × 109 3 × 476 1.0 34 268 27 110.0 LDV LDL 1.2 16.5 3 × 109 4 × 2704 0.47 47 326 33 15.0 LDV LDL 1.8 16.5 3 × 109 3 × 2704 0.47 47 261 26 30.0 LDV LDL 2.5 16.5 4 × 109 3 × 1808 0.72 47 233 23 47.5 LDV LDL 3.3 16.5 4 × 109 2704 0.72 47 217 22 67.5 Rev. B | Page 30 of 40

Data Sheet ADP1872/ADP1873 Marking Code V VIN L1 R C C R OUT C COMP PAR TOP SAP Model ADP1872 ADP1873 (V) (V) C (µF) C (µF) (µH) (kΩ) (pF) (pF) (kΩ) IN OUT LDV LDL 5 16.5 3 × 109 3 × 476 1.0 34 268 27 110.0 LDV LDL 7 16.5 3 × 109 222 + 476 1.0 34 228 23 160.0 1 See the Inductor Selection section (See Table 9). 2 22 µF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm). 3 560 µF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm). 4 270 µF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm). 5 330 µF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm). 6 47 µF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm). 7 150 µF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm). 8 180 µF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm). 9 10 µF TDK 25 V, X7R, 1210 C3225X7R1E106M. Table 9. Recommended Inductors L (µH) DCR (mΩ) ISAT (A) Dimension (mm) Manufacturer Model Number 0.12 0.33 55 10.2 × 7 Würth Elektronik 744303012 0.22 0.33 30 10.2 × 7 Würth Elektronik 744303022 0.47 0.8 50 14.2 × 12.8 Würth Elektronik 744355147 0.72 1.65 35 10.5 × 10.2 Würth Elektronik 744325072 0.9 1.6 28 13 × 12.8 Würth Elektronic 744355090 1.2 1.8 25 10.5 × 10.2 Würth Elektronic 744325120 1.0 3.3 20 10.5 × 10.2 Würth Elektronic 7443552100 1.4 3.2 24 14 × 12.8 Würth Elektronic 744318180 2.0 2.6 22 13.2 × 12.8 Würth Elektronic 7443551200 0.8 27.5 Sumida CEP125U-0R8 Table 10. Recommended MOSFETs R I V C Q ON D DS IN TOTAL VGS = 4.5 V (mΩ) (A) (V) (nF) (nC) Package Manufacturer Model Number Upper-Side MOSFET 5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G (Q1/Q2) 10.2 53 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G 6.0 19 30 35 SO-8 Vishay Si4842DY 9 14 30 2.4 25 SO-8 International Rectifier IRF7811 Lower-Side MOSFET 5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G (Q3/Q4) 10.2 82 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G 6.0 19 30 35 SO-8 Vishay Si4842DY Rev. B | Page 31 of 40

ADP1872/ADP1873 Data Sheet LAYOUT CONSIDERATIONS Figure 82 shows the schematic of a typical ADP1872/ADP1873 The performance of a dc-to-dc converter depends highly on used for a high power application. Blue traces denote high current how the voltage and current paths are configured on the printed pathways. VIN, PGND, and V traces should be wide and circuit board (PCB). Optimizing the placement of sensitive OUT possibly replicated, descending down into the multiple layers. analog and power components are essential to minimize output Vias should populate, mainly around the positive and negative ripple, maintain tight regulation specifications, and reduce terminals of the input and output capacitors, alongside the source PWM jitter and electromagnetic interference. of Q1/Q2, the drain of Q3/Q4, and the inductor. LOW VOLTAGE INPUT HIGH VOLTAGE INPUT VDD = 5.0V VIN = 12V JP1 C3 C4 C5 C6 C7 CC ADP1872/ 22µF 22µF 22µF 22µF 22µF 571pF ADP1873 C12 CF RC 1 VIN BST 10 100nF Q1 Q2 57pF 47kΩ R1 30kΩ 2 COMP/EN SW 9 1.0µH VOUT = 1.8V, 15A VOUT R2 3 FB DRVH 8 R6 C20 + C21 + C22 + C23 + 15kΩ 4 GND PGND 7 Q3 Q4 2CΩ13 270µF 270µF 270µF 270µF 1.5nF 5 VDD DRVL 6 C2 C1 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 0.1µF 1µF R5 22µF, 25V, X7R, 1210 GRM32ER71E226KE15L 100kΩ PANASONIC: (OUTPUT CAPACITORS) 270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) WB1UµSRHCT,H0 38 .I03NNmD0ΩU3,CM 2TS0O AGR 7S(4U:4P3P5E52R1-0S0IDE) 08297-081 Figure 82. ADP1872/ADP1873 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths) Rev. B | Page 32 of 40

Data Sheet ADP1872/ADP1873 SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER SECTION. SW SEPARATE ANALOG GROUND PLANE FOR THE ANALOG COMPONENTS (THAT IS, COMPENSATION AND FEEDBACK RESISTORS). OUTPUT CAPACITORS ARE MOUNTED ON THE RIGHTMOST AREA OF BYPASS POWER CAPACITOR (C1) THE EVB, WRAPPING FOR VREG BIAS DECOUPLING BACK AROUND TO THE AND HIGH FREQUENCY MAIN POWER GROUND CAPACITOR (C2) AS CLOSE AS PLANE, WHERE IT MEETS POSSIBLE TO THE IC. WITH THE NEGATIVE TERMINALS OF THE INPUT CAPACITORS INPUT CAPACITORS ARE MOUNTED CLOSE TO DRAIN OF Q1/Q2 AND SOURCE OF Q3/Q4. 08297-082 Figure 83. Overall Layout of the ADP1872 High Current Evaluation Board Rev. B | Page 33 of 40

ADP1872/ADP1873 Data Sheet 08297-083 Figure 84. Layer 2 of Evaluation Board Rev. B | Page 34 of 40

Data Sheet ADP1872/ADP1873 TOP RESISTOR FEEDBACK TAP VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK (SEE FIGURE 82). THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING BACK TO THE ANALOG PLANE (SEE FIGURE 86, LAYER 4 FOR PGND TAP). 08297-084 Figure 85. Layer 3 of Evaluation Board Rev. B | Page 35 of 40

ADP1872/ADP1873 Data Sheet BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE PGND SENSE TAP FROM NEGATIVE TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE FROM FIGURE 84. 08297-085 Figure 86. Layer 4 (Bottom Layer) of Evaluation Board Rev. B | Page 36 of 40

Data Sheet ADP1872/ADP1873 IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND). With SW the shortest path possible, connect the analog ground plane to the GND pin (Pin 4). This plane should only be on the top layer VOUT of the evaluation board. To avoid crosstalk interference, there should not be any other voltage or current pathway directly below this plane on Layer 2, Layer 3, or Layer 4. Connect the negative terminals of all sensitive analog components to the analog ground plane. Examples of such sensitive analog com- ponents include the resistor divider’s bottom resistor, the high frequency bypass capacitor for biasing (0.1 µF), and the compensation network. M(Poinu n5t) aa n1d µ tFh eb yPpGaNssD ca ppianc i(tPoirn d 7ir)e. cIntl ya dacdriotisosn t,h ae 0V.1D µDF pshino uld VIN PGND 08297-086 Figure 87. Primary Current Pathways During the On State of the Upper-Side be tied across the VDD pin (Pin 5) and the GND pin (Pin 4). MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow) POWER SECTION DIFFERENTIAL SENSING As shown in Figure 83, an appropriate configuration to localize Because the ADP1872/ADP1873 operate in valley current- large current transfer from the high voltage input (VIN) to the mode control, a differential voltage reading is taken across the output (VOUT) and then back to the power ground is to put the drain and source of the lower-side MOSFET. The drain of the VIN plane on the left, the output plane on the right, and the main lower-side MOSFET should be connected as close as possible to power ground plane in between the two. Current transfers from the SW pin (Pin 9) of the IC. Likewise, the source should be the input capacitors to the output capacitors, through Q1/Q2, connected as close as possible to the PGND pin (Pin 7) of the during the on state (see Figure 87). The direction of this current IC. When possible, both of these track lines should be narrow (yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 and away from any other active device or voltage/current paths. turns on. When Q3/Q4 turns on, the current direction continues to be maintained (red arrow) as it circles from the bulk capacitor’s power ground terminal to the output capacitors, through the SW Q3/Q4. Arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through Q1/Q2 stops abruptly. Sudden changes in flux, usually at source PGND terminals of Q1/Q2 and drain terminals of Q3/Q4, cause large dV/dts at the SW node. The SW node is near the top of the evaluation board. The SW node should use the least amount of area possible and be away from any sensitive analog circuitry and components because tphoisss iisb lwe,h reerpel imcaotset tshuids dpeand cohnatnog Leas yienr f2lu axn dde Lnasyiteyr o3c fcourr .t hWerhmena l L(DARYAEIRN 1O:F S LEONWSEE RLI NMEO FSOFERT S)W L(SAOYUERRC 1E: SOEFN LSOEW LEINRE M FOOSRF PEGT)ND 08297-087 relief and eliminate any other voltage and current pathways directly Figure 88. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS Amp Differential Sensing (Yellow Sense Line on Layer 2) beneath the SW node plane. Populate the SW node plane with vias, mainly around the exposed pad of the inductor terminal Differential sensing should also be applied between the and around the perimeter of the source of Q1/Q2 and the drain outermost output capacitor to the feedback resistor divider (see of Q3/Q4. The output voltage power plane (VOUT) is at the right- Figure 85 and Figure 86). Connect the positive terminal of the most end of the evaluation board. This plane should be replicated, output capacitor to the top resistor (RT). Connect the negative descending down to multiple layers with vias surrounding the terminal of the output capacitor to the negative terminal of the inductor terminal and the positive terminals of the output bulk bottom resistor, which connects to the analog ground plane as capacitors. Ensure that the negative terminals of the output well. Both of these track lines, as previously mentioned, should capacitors are placed close to the main power ground (PGND), be narrow and away from any other active device or voltage/ as previously mentioned. All of these points form a tight circle current paths. (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 − D. Rev. B | Page 37 of 40

ADP1872/ADP1873 Data Sheet TYPICAL APPLICATION CIRCUITS DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT LOW VOLTAGE INPUT HIGH VOLTAGE INPUT VDD = 5.0V VIN = 12V JP1 C3 C4 C5 C6 C7 CC ADP1872/ 22µF 22µF 22µF 22µF 22µF 571pF ADP1873 C12 CF RC 1 VIN BST 10 100nF Q1 Q2 57pF 47kΩ R1 30kΩ 2 COMP/EN SW 9 1.0µH VOUT = 1.8V, 15A VOUT R2 3 FB DRVH 8 R6 C20 + C21 + C22 + C23 + 15kΩ 4 GND PGND 7 Q3 Q4 2CΩ13 270µF 270µF 270µF 270µF 1.5nF 5 VDD DRVL 6 C2 C1 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 0.1µF 1µF R5 22µF, 25V, X7R, 1210 GRM32ER71E226KE15L 100kΩ PANASONIC: (OUTPUT CAPACITORS) 270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) WB1UµSRHCT,H0 38 .I03NNmD0ΩU3,CM 2TS0O AGR 7S(4U:4P3P5E52R1-0S0IDE) 08297-088 Figure 89. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect). SINGLE-INPUT, 600 kHz APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 5.5V JP1 C3 C4 C5 C6 C7 CC ADP1872/ 22µF 22µF 22µF 22µF 22µF 271pF ADP1873 C12 CF RC 1 VIN BST 10 100nF Q1 Q2 27pF 47kΩ R1 47.5kΩ 2 COMP/EN SW 9 0.47µH VOUT = 2.5V, 15A VOUT R2 3 FB DRVH 8 R6 C20 + C21 + C22 + 15kΩ 4 GND PGND 7 Q3 Q4 2CΩ13 180µF 180µF 180µF 1.5nF 5 VDD DRVL 6 C2 C1 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 0.1µF 1µF R5 22µF, 25V, X7R, 1210 GRM32ER71E226KE15L 100kΩ PANASONIC: (OUTPUT CAPACITORS) 180µF (SP-SERIES) 4V, 10mΩ EEFUE0G181XR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) WB0U.SR4C7TµH0H8 I0,N N0D.08U3mCMΩTSO, G5R0 S(AU: P74P4E3R5-5S1I4D7E) 08297-089 Figure 90. Application Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect) Rev. B | Page 38 of 40

Data Sheet ADP1872/ADP1873 DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT LOW VOLTAGE INPUT HIGH VOLTAGE INPUT VDD = 5V VIN = 13V JP1 C3 C4 C5 C6 C7 CC ADP1872/ 22µF 22µF 22µF 22µF 22µF CF 8R0C0pF 1 VINADP1873BST 10 C10102nF Q1 Q2 80pF 33.5kΩ R1 30kΩ 2 COMP/EN SW 9 0.8µH VOUT = 1.8V, 20A VOUT R2 3 FB DRVH 8 R6 C20 + C21 + C22 + C23 + 15kΩ 4 GND PGND 7 Q3 Q4 2CΩ13 270µF 270µF 270µF 270µF 1.5nF 5 VDD DRVL 6 C2 C1 MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 0.1µF 1µF 22µF, 25V, X7R, 1210 GRM32ER71E226KE15L PANASONIC: (OUTPUT CAPACITORS) 270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) WB0U.SR7C2TµH0H8 I0,N N1D.06U35CMmTSΩO G,R 3 S(5U:AP 7P4E4R3-2S5I0D7E2) 08297-090 Figure 91. Application Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect) Rev. B | Page 39 of 40

ADP1872/ADP1873 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 92. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding ADP1872ARMZ-0.3-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDT ADP1872ARMZ-0.6-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDU ADP1872ARMZ-1.0-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDV ADP1872-0.3-EVALZ Forced PWM, 300 kHz Evaluation Board ADP1872-0.6-EVALZ Forced PWM, 600 kHz Evaluation Board ADP1872-1.0-EVALZ Forced PWM, 1 MHz Evaluation Board ADP1873ARMZ-0.3-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDF ADP1873ARMZ-0.6-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDK ADP1873ARMZ-1.0-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDL ADP1873-0.3-EVALZ Power Saving Mode, 300 kHz Evaluation Board ADP1873-0.6-EVALZ Power Saving Mode, 600 kHz Evaluation Board ADP1873-1.0-EVALZ Power Saving Mode, 1 MHz Evaluation Board 1 Z = RoHS Compliant Part. ©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08297-0-7/12(B) Rev. B | Page 40 of 40