2 A, Low V , Low Dropout IN Linear Regulator Data Sheet ADP1740/ADP1741 FEATURES TYPICAL APPLICATION CIRCUITS Maximum output current: 2 A VIN = 1.8V VOUT = 1.5V Input voltage range: 1.6 V to 3.6 V Low shutdown current: 2 µA 4.7µF 4.7µF 16 15 14 13 Low dropout voltage: 160 mV at 2 A load VIN VIN VOUTVOUT Initial accuracy: ±1% 1VIN VOUT12 Accuracy over line, load, and temperature: ±2% ADP1740 100kΩ 2VIN VOUT11 7 fixed output voltage options with soft start: TOP VIEW (Not to Scale) 0.75 V to 2.5 V (ADP1740) 3VIN VOUT10 Adjustable output voltage options with soft start: PG 4EN SENSE 9 0.75 V to 3.3 V (ADP1741) PG GND SS NC High PSRR 5 6 7 8 65 dB at 1 kHz 6554 ddBB aatt 1100 0k HkHz z 10nF 07081-001 Figure 1. ADP1740 with Fixed Output Voltage, 1.5 V 23 μV rms at 0.75 V output Stable with small 4.7 µF ceramic output capacitor VIN = 1.8V VOUT = 0.5V(1 + R1/R2) Excellent load and line transient response Current-limit and thermal overload protection 4.7µF 4.7µF 16 15 14 13 Power-good indicator VIN VIN VOUTVOUT Logic-controlled enable 1VIN VOUT12 Reverse current protection 100kΩ 2VIN ADP1741 VOUT11 TOP VIEW APPLICATIONS (Not to Scale) 3VIN VOUT10 R1 Server computers PG 4EN ADJ 9 Memory components PG GND SS NC R2 Telecommunications equipment 5 6 7 8 NDSetPw/FoPrGk Aeq/muiipcrmopenrot cessor supplies 10nF 07081-002 Instrumentation equipment/data acquisition systems Figure 2. ADP1741 with Adjustable Output Voltage, 0.75 V to 3.3 V GENERAL DESCRIPTION The ADP1740/ADP1741 are low dropout (LDO) CMOS linear voltages ranging from 0.75 V to 3.3 V via an external divider. regulators that operate from 1.6 V to 3.6 V and provide up to 2 A The ADP1740/ADP1741 allow an external soft start capacitor of output current. These low V /V LDOs are ideal for regu- to be connected to program the startup. A digital power-good IN OUT lation of nanometer FPGA geometries operating from 2.5 V down output allows power system monitors to check the health of the to 1.8 V I/O rails, and for powering core voltages down to 0.75 V. output voltage. Using an advanced, proprietary architecture, the ADP1740/ The ADP1740/ADP1741 are available in a 16-lead, 4 mm × ADP1741 provide high power supply rejection ratio (PSRR) and 4 mm LFCSP, making them not only very compact solutions, low noise, and achieve excellent line and load transient response but also providing excellent thermal performance for applica- with only a small 4.7 µF ceramic output capacitor. tions that require up to 2 A of output current in a small, low The ADP1740 is available in seven fixed output voltage options. profile footprint. The ADP1741 is an adjustable version that allows output Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADP1740/ADP1741 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Soft Start Function ..................................................................... 11 Adjustable Output Voltage (ADP1741) ................................... 12 Applications ....................................................................................... 1 Typical Application Circuits ............................................................ 1 Enable Feature ............................................................................ 12 Power-Good Feature .................................................................. 12 General Description ......................................................................... 1 Revision History ............................................................................... 2 Reverse Current Protection Feature ........................................ 13 Specifications ..................................................................................... 3 Applications Information .............................................................. 14 Capacitor Selection .................................................................... 14 Input and Output Capacitor, Recommended Specifications .. 4 Absolute Maximum Ratings ............................................................ 5 Undervoltage Lockout ............................................................... 15 Current-Limit and Thermal Overload Protection ................. 15 Thermal Data ................................................................................ 5 Thermal Resistance ...................................................................... 5 Thermal Considerations ............................................................ 15 PCB Layout Considerations ...................................................... 17 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 19 Theory of Operation ...................................................................... 11 REVISION HISTORY 1/15—Rev. G to Rev. H Changes to Ordering Guide .......................................................... 19 4/14—Rev. F to Rev. G Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Figure 3 and Figure 4 ................................................... 6 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 8/13—Rev. E to Rev. F Changes to Ordering Guide .......................................................... 19 6/13—Rev. D to Rev. E Changed Adjustable Output Voltage Option with Soft Start (ADP1755) from 0.75 V to 3.0 V to 0.75 V to 3.3 V (Throughout) .................................................................................... 1 Updated Outline Dimensions ....................................................... 19 12/12—Rev. C to Rev. D Added Junction Temperature of 150°C, Table 3 ........................... 5 Changes to Ordering Guide .......................................................... 19 9/12—Rev. B to Rev. C Changes to Table 3 ............................................................................ 5 Changes to Ordering Guide .......................................................... 19 2/10—Rev. A to Rev. B Changes to Table 4 ............................................................................ 5 Changes to Ordering Guide .......................................................... 19 4/09—Rev. 0 to Rev. A Changes to Table 3 ............................................................................ 5 10/08—Revision 0: Initial Version Rev. H | Page 2 of 20

Data Sheet ADP1740/ADP1741 SPECIFICATIONS V = (V + 0.4 V) or 1.6 V (whichever is greater), I = 100 mA, C = C = 4.7 µF, T = 25°C, unless otherwise noted. IN OUT OUT IN OUT A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V T = −40°C to +125°C 1.6 3.6 V IN J OPERATING SUPPLY CURRENT1 I I = 500 µA 90 µA GND OUT I = 100 mA 400 µA OUT I = 100 mA, T = −40°C to +125°C 800 µA OUT J I = 2 A 1.5 mA OUT I = 2 A, T = −40°C to +125°C 1.8 mA OUT J SHUTDOWN CURRENT I EN = GND, V = 3.6 V 2 6 µA GND-SD IN EN = GND, V = 1.6 V, T = −40°C to +85°C 30 µA IN J EN = GND, V = 3.6 V, T = −40°C to +85°C 100 µA IN J OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy V I = 100 mA −1 +1 % OUT OUT (ADP1740) I = 10 mA to 2 A −1.5 +1.5 % OUT 10 mA < I < 2 A, T = −40°C to +125°C −2 +2 % OUT J Adjustable Output Voltage V I = 100 mA 0.495 0.5 0.505 V ADJ OUT Accuracy (ADP1741)2 I = 10 mA to 2 A 0.492 0.508 V OUT 10 mA < I < 2 A, T = −40°C to +125°C 0.490 0.510 V OUT J LINE REGULATION ∆V /∆V V = (V + 0.4 V) to 3.6 V, T = −40°C to +125°C −0.3 +0.3 %/V OUT IN IN OUT J LOAD REGULATION3 ∆V /∆I I = 10 mA to 2 A, T = −40°C to +125°C 0.5 %/A OUT OUT OUT J DROPOUT VOLTAGE4 V I = 100 mA, V ≥ 1.8 V 10 mV DROPOUT OUT OUT I = 100 mA, V ≥ 1.8 V, T = −40°C to +125°C 18 mV OUT OUT J I = 2 A, V ≥ 1.8 V 160 mV OUT OUT I = 2 A, V ≥ 1.8 V, T = −40°C to +125°C 280 mV OUT OUT J START-UP TIME5 t C = 0 nF, I = 10 mA 200 µs START-UP SS OUT C = 10 nF, I = 10 mA 5.2 ms SS OUT CURRENT-LIMIT THRESHOLD6 I 2.4 3 5 A LIMIT THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C PG OUTPUT LOGIC LEVEL PG Output Logic High PG 1.6 V ≤ V ≤ 3.6 V, I < 1 µA 1.0 V HIGH IN OH PG Output Logic Low PG 1.6 V ≤ V ≤ 3.6 V, I < 2 mA 0.4 V LOW IN OL PG Output Delay from EN 1.6 V ≤ V ≤ 3.6 V, C = 10 nF 5.5 ms IN SS Transition, Low to High PG OUTPUT THRESHOLD Output Voltage Falling PG 1.6 V ≤ V ≤ 3.6 V −10 % FALL IN Output Voltage Rising PG 1.6 V ≤ V ≤ 3.6 V −6.5 % RISE IN EN INPUT EN Input Logic High V 1.6 V ≤ V ≤ 3.6 V 1.2 V IH IN EN Input Logic Low V 1.6 V ≤ V ≤ 3.6 V 0.4 V IL IN EN Input Leakage Current V EN = VIN or GND 0.1 1 µA I-LEAKAGE UNDERVOLTAGE LOCKOUT UVLO Input Voltage Rising UVLO 1.58 V RISE Input Voltage Falling UVLO 1.25 V FALL Hysteresis UVLO 100 mV HYS SOFT START CURRENT I 1.6 V ≤ V ≤ 3.6 V 0.6 0.9 1.2 µA SS IN ADJ INPUT BIAS CURRENT ADJ 1.6 V ≤ V ≤ 3.6 V, T = −40°C to +125°C 10 150 nA I-BIAS IN J (ADP1741) Rev. H | Page 3 of 20

ADP1740/ADP1741 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit SENSE INPUT BIAS CURRENT SNS 1.6 V ≤ V ≤ 3.6 V 10 µA I-BIAS IN (ADP1740) OUTPUT NOISE OUT 10 Hz to 100 kHz, V = 0.75 V 23 µV rms NOISE OUT 10 Hz to 100 kHz, V = 2.5 V 65 µV rms OUT POWER SUPPLY REJECTION RATIO PSRR V = V + 1 V, I = 10 mA IN OUT OUT 1 kHz, V = 0.75 V 65 dB OUT 1 kHz, V = 2.5 V 56 dB OUT 10 kHz, V = 0.75 V 65 dB OUT 10 kHz, V = 2.5 V 56 dB OUT 100 kHz, V = 0.75 V 54 dB OUT 100 kHz, V = 2.5 V 51 dB OUT 1 Minimum output load current is 500 μA. 2 Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of the resistors used. 3 Based on an endpoint calculation using 10 mA and 2 A loads. See Figure 6 for typical load regulation performance. 4 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.6 V. 5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 95% of its nominal value. 6 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit MINIMUM INPUT AND OUTPUT CAPACITANCE1 C T = –40°C to +125°C 3.3 µF MIN A CAPACITOR ESR R T = –40°C to +125°C 0.001 0.1 Ω ESR A 1 The minimum input and output capacitance should be greater than 3.3 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during capacitor selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with this LDO. Rev. H | Page 4 of 20

Data Sheet ADP1740/ADP1741 ABSOLUTE MAXIMUM RATINGS board design is required. The value of θ may vary, depending Table 3. JA on PCB material, layout, and environmental conditions. The Parameter Rating specified values of θ are based on a 4-layer, 4 in × 3 in circuit VIN to GND −0.3 V to +4.0 V JA board. Refer to JEDEC JESD51-7 for detailed information about VOUT to GND −0.3 V to V IN board construction. For more information, see the AN-772 EN to GND −0.3 V to V IN Application Note, A Design and Manufacturing Guide for the SS to GND −0.3 V to V IN Lead Frame Chip Scale Package (LFCSP), at www.analog.com. PG to GND −0.3 V to +4.0 V SENSE/ADJ to GND −0.3 V to VIN ΨJB is the junction-to-board thermal characterization parameter Storage Temperature Range −65°C to +150°C with units of °C/W. ΨJB of the package is based on modeling and Junction Temperature Range −40°C to +125°C calculation using a 4-layer board. The JEDEC JESD51-12 Junction Temperature 150°C document, Guidelines for Reporting and Using Electronic Package Soldering Conditions JEDEC J-STD-020 Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. Ψ measures Stresses at or above those listed under Absolute Maximum JB the component power flowing through multiple thermal paths Ratings may cause permanent damage to the product. This is a rather than through a single path, as in thermal resistance (θ ). JB stress rating only; functional operation of the product at these Therefore, Ψ thermal paths include convection from the top of JB or any other conditions above those indicated in the operational the package, as well as radiation from the package, factors that section of this specification is not implied. Operation beyond make Ψ more useful in real-world applications. Maximum JB the maximum operating conditions for extended periods may junction temperature (T) is calculated from the board temper- affect product reliability. J ature (T ) and the power dissipation (P ) using the following B D THERMAL DATA formula: Absolute maximum ratings apply only individually, not in T = T + (P × Ψ ) J B D JB combination. The ADP1740/ADP1741 may be damaged when Refer to the JEDEC JESD51-8 and JESD51-12 documents for junction temperature limits are exceeded. Monitoring ambient more detailed information about Ψ . JB temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with THERMAL RESISTANCE high power dissipation and poor PCB thermal resistance, the maximum ambient temperature may need to be derated. In θJA and ΨJB are specified for the worst-case conditions, that is, a applications with moderate power dissipation and low PCB device soldered in a circuit board for surface-mount packages. thermal resistance, the maximum ambient temperature can Table 4. Thermal Resistance exceed the maximum limit as long as the junction temperature Package Type θ Ψ Unit JA JB is within specification limits. 16-Lead LFCSP with Exposed Pad 42 25.5 °C/W The junction temperature (T) of the device is dependent on the J ambient temperature (T ), the power dissipation of the device A (P ), and the junction-to-ambient thermal resistance of the ESD CAUTION D package (θ ). T is calculated using the following formula: JA J T = T + (P × θ ) J A D JA The junction-to-ambient thermal resistance (θ ) of the package JA is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal Rev. H | Page 5 of 20

ADP1740/ADP1741 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS T T T T VIN VIN VOU VOU VIN VIN VOU VOU 61 51 41 31 61 51 41 31 VIN 1 12 VOUT VIN 1 12 VOUT VIN 2 ADP1740 11 VOUT VIN 2 ADP1741 11 VOUT VIN 3 TOP VIEW 10 VOUT VIN 3 TOP VIEW 10 VOUT EN 4 9 SENSE EN 4 9 ADJ 5 6 7 8 5 6 7 8 G D S C G D S C P N S N P N S N G G NOTES NOTES 1.NC = NO CONNECT. 1.NC = NO CONNECT. 2.THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES 2.THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES TIBNHESE CIDROEMN ATNLHE EPC EPTREAFDCO KTRAOMG TAEHN. EICT GE I SRA ORNUEDNC ISDO MEPLMLEAECNNTEDR EOIDCN A TTLHHLAEYT BC TOOHANERN EDEX.CPTOESDE TDO P GANDD 07081-003 TIBNHESE ICDROEMN ATNLHE EPC EPTREAFDCO KTRAOMG TAEHN. EICT GE I SRA ORNUEDNC ISDO MEPLLMEAECNNTEDR EOICDNA TTLHHLAEYT BC TOOHANERN EDEX.CPTOESDE TDO P GANDD 07081-004 Figure 3. ADP1740 Pin Configuration Figure 4. ADP1741 Pin Configuration Table 5. Pin Function Descriptions Pin No. ADP1740 ADP1741 Mnemonic Description 1, 2, 3, 15, 16 1, 2, 3, 15, 16 VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. Note that all five VIN pins must be connected to the source supply. 4 4 EN Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For automatic startup, connect EN to VIN. 5 5 PG Power-Good Output. This open-drain output requires an external pull-up resistor to VIN. If the part is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, the PG pin immediately transitions low. 6 6 GND Ground. 7 7 SS Soft Start Pin. A capacitor connected to this pin determines the soft start time. 8 8 NC Not Connected. No internal connection. 9 SENSE Sense Input. This pin measures the actual output voltage at the load and feeds it to the error amplifier. Connect the SENSE pin as close to the load as possible to minimize the effect of IR drop between the regulator output and the load. 9 ADJ Adjust Pin. A resistor divider from VOUT to ADJ sets the output voltage. 10, 11, 12, 10, 11, 12, VOUT Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor. Note that 13, 14 13, 14 all five VOUT pins must be connected to the load. EP EP Exposed The exposed pad on the bottom of the LFCSP enhances thermal performance and is pad electrically connected to GND inside the package. It is recommended that the exposed pad be connected to the ground plane on the board. Rev. H | Page 6 of 20

Data Sheet ADP1740/ADP1741 TYPICAL PERFORMANCE CHARACTERISTICS V = 1.9 V, V = 1.5 V, I = 100 mA, C = C = 4.7 µF, T = 25°C, unless otherwise noted. IN OUT OUT IN OUT A 1.520 1600 LOAD = 10mA LOAD = 2A 1.515 LOAD = 100mA 1400 LOAD = 400mA LOAD = 800mA GE (V) 11..551005 LLOOAADD == 12.A2A NT (µA) 11020000 LOAD = 1.2A A E LOAD = 800mA T R OL 1.500 UR 800 UTPUT V 1.495 OUND C 600 LOAD = 400mA O R LOAD = 100mA 1.490 G 400 LOAD = 10mA 1.485 200 1.480 0 –40 JU–N5CTION TEM25PERATURE8 (5°C) 125 07081-005 –40 JU–N5CTION TEM25PERATURE8 (5°C) 125 07081-008 Figure 5. Output Voltage vs. Junction Temperature Figure 8. Ground Current vs. Junction Temperature 1.520 1600 1.515 1400 GE (V) 11..550150 NT (µA) 11200000 A E T R OL 1.500 UR 800 V C UTPUT 1.495 OUND 600 O R 1.490 G 400 1.485 200 1.480 0 10 10L0OAD CURRENT (mA1)k 10k 07081-006 10 10L0OAD CURRENT (mA1)k 10k 07081-009 Figure 6. Output Voltage vs. Load Current Figure 9. Ground Current vs. Load Current 1.520 1600 LOAD = 10mA 1.515 LOAD = 100mA 1400 LOAD = 400mA LOAD = 2A LOAD = 800mA GE (V) 11..551005 LLOOAADD == 12.A2A NT (µA) 11200000 LOAD = 1.2A A E T R OL 1.500 UR 800 UTPUT V 1.495 OUND C 600 LLOOAADD == 480000mmAA O R 1.490 G 400 LOAD = 100mA 1.485 200 LOAD = 10mA 1.480 0 1.8 2.0 2.2 2.4INPUT2 .V6OLT2A.8GE (V3).0 3.2 3.4 3.6 07081-007 1.8 2.0 2.2 2.4INPUT2. 6VOLT2A.8GE (V3).0 3.2 3.4 3.6 07081-010 Figure 7. Output Voltage vs. Input Voltage Figure 10. Ground Current vs. Input Voltage Rev. H | Page 7 of 20

ADP1740/ADP1741 Data Sheet 100 4500 1.9V LOAD = 10mA 90 2.0V 4000 LOAD = 100mA 2.4V LOAD = 400mA NT (µA) 7800 233...606VVV T (µA) 33500000 LLLOOOAAADDD === 8120.A20AmA RE 60 EN R R 2500 U R C 50 U WN D C 2000 UTDO 4300 ROUN 1500 H G S 1000 20 10 500 0 0 –40 –15 TE1M0PERATURE3 5(°C) 60 85 07081-011 2.3 2.4 INP2U.5T VOLTAG2E.6 (V) 2.7 2.8 07081-014 Figure 11. Shutdown Current vs. Temperature at Various Input Voltages Figure 14. Ground Current vs. Input Voltage (in Dropout), VOUT = 2.5 V 0.25 T ILOAD 0.20 V) E ( G A 0.15 1 T 1mA TO 2A LOAD STEP, 2.5A/µs, 1A/DIV L VO 1.6V T OU 0.10 VOUT P 2 O R D 2.5V 0.05 50mV/DIV VIN = 3.6V VOUT = 1.5V 0 1 10 LOAD CU1R0R0ENT (mA) 1k 10k 07081-012 CH1 1.0 A ΩBW CH2 50mV BW MT 1 01µ0.s40%A CH1 380mA 07081-015 Figure 12. Dropout Voltage vs. Load Current, VOUT = 1.6 V, 2.5 V Figure 15. Load Transient Response, CIN = 4.7 µF, COUT = 4.7 µF 2.50 T 2.45 ILOAD 2.40 V) E ( G 2.35 1 A LT 1mA TO 2A LOAD STEP, 2.5A/µs, 1A/DIV O 2.30 V T TPU 2.25 2 VOUT U LOAD = 10mA O 2.20 LOAD = 100mA LOAD = 400mA 50mV/DIV LOAD = 800mA 2.15 LOAD = 1.2A VIN = 3.6V LOAD = 2A VOUT = 1.5V 2.10 2.3 2.4 INP2U.5T VOLTAG2E.6 (V) 2.7 2.8 07081-013 CH1 1.0 A ΩBW CH2 50mV BW MT 1 01µ0.s20%A CH1 880mA 07081-016 Figure 13. Output Voltage vs. Input Voltage (in Dropout), VOUT = 2.5 V Figure 16. Load Transient Response, CIN = 22 µF, COUT = 22 µF Rev. H | Page 8 of 20

Data Sheet ADP1740/ADP1741 0 T LOAD = 2A VIN –10 LOAD = 1.2A LOAD = 800mA –20 LOAD = 400mA LOAD = 100mA 3V TO 3.5V INPUT VOLTAGE STEP, 2V/µs –30 LOAD = 10mA B) –40 d R ( –50 R VOUT S P –60 2 5mV/DIV –70 –80 VOUT = 1.5V –90 CIN = COUT = 4.7µF 1 CH1 500mVBW CH2 5mV BW MT 1 09µ.4s0% A CH4 800mV 07081-017 –10010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 07081-020 Figure 17. Line Transient Response, Load Current = 2 A Figure 20. Power Supply Rejection Ratio vs. Frequency, VOUT = 0.75 V, VIN = 1.75 V 70 0 LOAD = 2A 2.5V –10 LOAD = 1.2A 60 LOAD = 800mA –20 LOAD = 400mA 50 –30 LLOOAADD == 11000mmAA s) E (µV rm 40 1.5V RR (dB) ––5400 S 30 S OI P –60 N 20 0.75V –70 –80 10 –90 0 –100 0.0001 0.001 LO0.A0D1 CURREN0T.1 (A) 1 10 07081-018 10 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 07081-021 Figure 18. Noise vs. Load Current and Output Voltage Figure 21. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.5 V, VIN = 2.5 V 10 0 LOAD=2A Hz) –10 LLOOAADD==810.20AmA V/ –20 LOAD=400mA TY (µ 1 –30 LLOOAADD==1100m0mAA NSI B) –40 AL DE 1.5V RR (d –50 R S T 2.5V P –60 C SPE 0.1 –70 E OIS 0.75V –80 N –90 0.01 –100 10 100 FREQUE1NkCY (Hz) 10k 100k 07081-019 10 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 07081-022 Figure 19. Noise Spectral Density vs. Output Voltage, ILOAD = 10 mA Figure 22. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.5 V, VIN = 3.5 V Rev. H | Page 9 of 20

ADP1740/ADP1741 Data Sheet 0 1.5V/2A –10 2.5V/10mA 0.75V/2A 2.5V/2A –20 0.75V/10mA 1.5V/10mA –30 B) d R ( –40 R S P –50 –60 –70 –80 10 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 07081-048 Figure 23. Power Supply Rejection Ratio vs. Frequency and Output Voltage Rev. H | Page 10 of 20

Data Sheet ADP1740/ADP1741 THEORY OF OPERATION The ADP1740 is available in seven fixed output voltage options The ADP1740/ADP1741 are low dropout linear regulators from 0.75 V to 2.5 V. The ADP1740 allows for connection of an that use an advanced, proprietary architecture to provide high external soft start capacitor, which controls the output voltage power supply rejection ratio (PSRR) and excellent line and load ramp during startup. The ADP1741 is an adjustable version with transient response with only a small 4.7 µF ceramic output capac- an output voltage that can be set to a value from 0.75 V to 3.3 V itor. Both devices operate from a 1.6 V to 3.6 V input rail and by an external voltage divider. Both devices are controlled by an provide up to 2 A of output current. Supply current in shutdown enable pin (EN). mode is typically 2 µA. SOFT START FUNCTION ADP1740 REVPERROSTEE PCOTLIOANRITY For applications that require a controlled startup, the ADP1740/ ADP1741 provide a programmable soft start function. The VIN VOUT programmable soft start is useful for reducing inrush current UVLO upon startup and for providing voltage sequencing. To implement soft start, connect a small ceramic capacitor from SS to GND. GND SHORT-CIRCUIT Upon startup, a 0.9 µA current source charges this capacitor. AND THERMAL PROTECTION SENSE The ADP1740/ADP1741 start-up output voltage is limited by R1 the voltage at SS, providing a smooth ramp-up to the nominal PG 0.5V output voltage. The soft start time is calculated as follows: REF R2 t = V × (C /I ) (1) PG SS REF SS SS DETECT 0.9µA where: SS t is the soft start period. EN SHUTDOWN 07081-023 VSSREF is the 0.5 V reference voltage. C is the soft start capacitance from SS to GND. Figure 24. ADP1740 Internal Block Diagram SS I is the current sourced from SS (0.9 µA). SS When the ADP1740/ADP1741 are disabled (using the EN pin), ADP1741 REVPERROSTEE PCOTLIOANRITY the soft start capacitor is discharged to GND through an internal 100 Ω resistor. VIN VOUT 2.50 UVLO 2.25 EN 2.00 GND SHORT-CIRCUIT AND THERMAL 1.75 PROTECTION E (V) 1.50 1nF G PG 0R.E5VF ADJ LTA 1.25 4.7nF O 1.00 V PG 10nF DETECT 0.75 0.9µA SS 0.50 EN SHUTDOWN 07081-024 0.25 Figure 25. ADP1741 Internal Block Diagram 0 Internally, the ADP1740/ADP1741 consist of a reference, 0 2 4TIME (ms)6 8 10 07081-025 an error amplifier, a feedback voltage divider, and a PMOS Figure 26. VOUT Ramp-Up with External Soft Start Capacitor pass transistor. Output current is delivered via the PMOS pass transistor, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feed- back voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. Rev. H | Page 11 of 20

ADP1740/ADP1741 Data Sheet The EN pin active/inactive thresholds are derived from the VIN T EN voltage. Therefore, these thresholds vary with changing input voltage. Figure 29 shows typical EN active/inactive thresholds 1 when the input voltage varies from 1.6 V to 3.6 V. 1.1 1.0 VOUT V) 0.9 LD ( EN ACTIVE O H 2 500mV/DIV VCOINU =T =C O1U.5TV = 4.7µF THRES 0.8 EN INACTIVE CH1 2.0V BW CH2 500mV BW MT 4 09µ.8s% A CH1 920mV 07081-026 EN 0.7 Figure 27. VOUT Ramp-Up with Internal Soft Start 0.6 ADJUSTABLE OUTPUT VOLTAGE (ADP1741) 0.5 T3.h3e V o uratpnugte .v Tolhtea goeu otpf utht ev oAltDagPe1 7is4 s1e ct abny bceo nsente octvienrg a a 0 r.e7s5i sVti vteo 1.6 1.8 2.0 2.2INP2U.4T VO2.L6TAG2E.8 (V)3.0 3.2 3.4 3.6 07081-028 Figure 29. Typical EN Pin Thresholds vs. Input Voltage voltage divider from VOUT to ADJ. The output voltage is calcu- lated using the following equation: POWER-GOOD FEATURE VOUT = 0.5 V × (1 + R1/R2) (2) The ADP1740/ADP1741 provide a power-good pin, PG, to indicate the status of the output. This open-drain output where: requires an external pull-up resistor to VIN. If the part is in R1 is the resistor from VOUT to ADJ. shutdown mode, current-limit mode, or thermal shutdown, or R2 is the resistor from ADJ to GND. if it falls below 90% of the nominal output voltage, the power- The maximum bias current into ADJ is 150 nA, so to achieve less good pin (PG) immediately transitions low. During soft start, than 0.5% error due to the bias current, use values less than the rising threshold of the power-good signal is 93.5% of the 60 kΩ for R2. nominal output voltage. ENABLE FEATURE The open-drain output is held low when the ADP1740/ADP1741 The ADP1740/ADP1741 use the EN pin to enable and disable have sufficient input voltage to turn on the internal PG transistor. the VOUT pins under normal operating conditions. As shown An optional soft start delay can be detected. The PG transistor in Figure 28, when a rising voltage on EN crosses the active is terminated via a pull-up resistor to VOUT or VIN. threshold, VOUT turns on. When a falling voltage on EN Power-good accuracy is 93.5% of the nominal regulator output crosses the inactive threshold, VOUT turns off. voltage when this voltage is rising, with a 90% trip point when this voltage is falling. Regulator input voltage brownouts or T glitches trigger power no-good if V falls below 90%. OUT EN A normal power-down triggers power no-good when V OUT drops below 90%. VOUT 21 VOUT = 1.5V 500mV/DIV CIN = COUT = 4.7µF CH1 500mV BW CH2 500mV BW MT 2 .209m.6s% A CH1 1.05V 07081-027 Figure 28. Typical EN Pin Operation As shown in Figure 28, the EN pin has hysteresis built in. This hysteresis prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. Rev. H | Page 12 of 20

Data Sheet ADP1740/ADP1741 REVERSE CURRENT PROTECTION FEATURE T VIN The ADP1740/ADP1741 have additional circuitry to protect 1V/DIV against reverse current flow from VOUT to VIN. For a typical LDO with a PMOS pass device, there is an intrinsic body diode 1 VOUT between VIN and VOUT. When VIN is greater than VOUT, this 500mV/DIV diode is reverse-biased. If VOUT is greater than VIN, the intrinsic diode becomes forward-biased and conducts current from VOUT to VIN, potentially causing destructive power dissipation. PG 1V/DIV The reverse current protection circuitry detects when VOUT is greater than V and reverses the direction of the intrinsic diode IN 22 VOUT = 1.5V connection, reverse-biasing the diode. The gate of the PMOS CIN = COUT = 4.7µF pass device is also connected to VOUT, keeping the device off. CCHH13 11..00VV BBWW CH2 500mV BW MT 4 05.00.µ40s%A CH3 900mV 07081-029 Fdiigffuerree n3t2ia slh. ows a plot of the reverse current vs. the VOUT to VIN Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V) 4000 3500 T VIN A) 3000 1V/DIV NT (µ 2500 E R R U 2000 1 VOUT SE C 500mV/DIV R 1500 E V E R 1000 500 PG 22 CVOINU =T =C O1U.5TV = 4.7µF 1V/DIV 00 0.3 0.6 0.9 1.2 V1.O5UT 1–. 8VIN 2(.V1) 2.4 2.7 3.0 3.3 3.6 07081-132 CCHH13 11..00VV BBWW CH2 500mV BW MT 4 05.00.µ40s%A CH3 900mV 07081-030 Figure 32. Reverse Current vs. VOUT − VIN Figure 31. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.5 V) Rev. H | Page 13 of 20

ADP1740/ADP1741 Data Sheet APPLICATIONS INFORMATION Input Bypass Capacitor CAPACITOR SELECTION Output Capacitor Connecting a 4.7 µF capacitor from the VIN pin to GND reduces the circuit sensitivity to printed circuit board (PCB) The ADP1740/ADP1741 are designed for operation with small, layout, especially when long input traces or high source space-saving ceramic capacitors, but they function with most impedance are encountered. If output capacitance greater than commonly used capacitors as long as care is taken with regard 4.7 µF is required, it is recommended that the input capacitor be to the effective series resistance (ESR) value. The ESR of the increased to match it. output capacitor affects the stability of the LDO control loop. A Input and Output Capacitor Properties minimum of 3.3 µF capacitance with an ESR of 100 mΩ or less is recommended to ensure the stability of the ADP1740/ADP1741. Any good quality ceramic capacitors can be used with the Transient response to changes in load current is also affected by ADP1740/ADP1741, as long as they meet the minimum output capacitance. Using a larger value of output capacitance capacitance and maximum ESR requirements. Ceramic improves the transient response of the ADP1740/ADP1741 to capacitors are manufactured with a variety of dielectrics, each large changes in load current. Figure 33 and Figure 34 show the with different behavior over temperature and applied voltage. transient responses for output capacitance values of 4.7 µF and Capacitors must have a dielectric adequate to ensure the 22 µF, respectively. minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage T ILOAD 1A/DIV rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature 1mA TO 2A LOAD STEP, 2.5A/µs and dc bias characteristics. 1 Figure 35 shows the capacitance vs. voltage bias characteristics of an 0805 case, 4.7 μF, 10 V, X5R capacitor. The voltage stability VOUT of a capacitor is strongly influenced by the capacitor size and 50mV/DIV 2 voltage rating. In general, a capacitor in a larger package or with a higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is approximately ±15% over the −40°C to +85°C temperature range and is not a function of VIN = 3.6V, VOUT = 1.5V CIN = COUT = 4.7µF package size or voltage rating. CH1 1.0A ΩBW CH2 50.0mV BWMT 1 .100µ.8s0%A CH1 380mA 07081-032 5 MURATA P/N GRM219R61A475KE34 Figure 33. Output Transient Response, COUT = 4.7 µF 4 F) µ T ILOAD CE ( 3 1A/DIV N A T 1mA TO 2A LOAD STEP, 2.5A/µs CI A 2 P A C 1 1 VOUT 50mV/DIV 2 0 0 2 VO4LTAGE BIAS6 (V) 8 10 07081-133 Figure 35. Capacitance vs. Voltage Bias Characteristics VIN = 3.6V, VOUT = 1.5V CIN = COUT = 22µF Use Equation 3 to determine the worst-case capacitance, CH1 1.0A ΩBW CH2 50.0mV BWMT 1 .101µ.8s0%A CH1 880mA 07081-033 apcocnoeunnt ttionlge rfaonr ccea,p aancdit ovro lvtaargiea.t ion over temperature, com- Figure 34. Output Transient Response, COUT = 22 µF C = C × (1 − TEMPCO) × (1 − TOL) (3) EFF OUT where: C is the effective capacitance at the operating voltage. EFF TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. Rev. H | Page 14 of 20

Data Sheet ADP1740/ADP1741 In this example, the worst-case temperature coefficient THERMAL CONSIDERATIONS (TEMPCO) over −40°C to +85°C is assumed to be 15% for an To guarantee reliable operation, the junction temperature of the X5R dielectric. The tolerance of the capacitor (TOL) is assumed ADP1740/ADP1741 must not exceed 125°C. To ensure that the to be 10%, and C = 4.46 μF at 1.8 V, as shown in Figure 35. OUT junction temperature stays below this maximum value, the user Substituting these values in Equation 3 yields needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient tem- C = 4.46 μF × (1 − 0.15) × (1 − 0.1) = 3.41 μF EFF perature, power dissipation in the power device, and thermal Therefore, the capacitor chosen in this example meets the resistance between the junction and ambient air (θ ). The θ JA JA minimum capacitance requirement of the LDO over temper- value is dependent on the package assembly compounds used ature and tolerance at the chosen output voltage. and the amount of copper to which the GND pin and the exposed To guarantee the performance of the ADP1740/ADP1741, pad (EP) of the package are soldered on the PCB. Table 6 shows it is imperative that the effects of dc bias, temperature, and typical θ values for the 16-lead LFCSP for various PCB copper JA tolerances on the behavior of the capacitors be evaluated for sizes. Table 7 shows typical Ψ values for the 16-lead LFCSP. JB each application. Table 6. Typical θ Values JA UNDERVOLTAGE LOCKOUT Copper Size (mm2) θ (°C/W), LFCSP JA The ADP1740/ADP1741 have an internal undervoltage lockout 01 130 circuit that disables all inputs and the output when the input 100 80 voltage is less than approximately 1.58 V. This ensures that the 500 69 ADP1740/ADP1741 inputs and the output behave in a predict- 1000 54 able manner during power-up. 6400 42 CURRENT-LIMIT AND THERMAL OVERLOAD 1 Device soldered to minimum size pin traces. PROTECTION Table 7. Typical Ψ Values JB The ADP1740/ADP1741 are protected against damage due to Copper Size (mm2) Ψ (°C/W) at 1 W JB excessive power dissipation by current-limit and thermal 100 32.7 overload protection circuits. The ADP1740/ADP1741 are 500 31.5 designed to reach current limit when the output load reaches 1000 25.5 3 A (typical). When the output load exceeds 3 A, the output voltage is reduced to maintain a constant current limit. The junction temperature of the ADP1740/ADP1741 can be Thermal overload protection is included, which limits the calculated from the following equation: junction temperature to a maximum of 150°C (typical). Under T = T + (P × θ ) (4) J A D JA extreme conditions (that is, high ambient temperature and power where: dissipation) when the junction temperature begins to rise above T is the ambient temperature. 150°C, the output is turned off, reducing the output current to A P is the power dissipation in the die, given by zero. When the junction temperature drops below 135°C D (typical), the output is turned on again and output current is P = [(V − V ) × I ] + (V × I ) (5) D IN OUT LOAD IN GND restored to its nominal value. where: Consider the case where a hard short from VOUT to ground V and V are the input and output voltages, respectively. IN OUT occurs. At first, the ADP1740/ADP1741 reach current limit so I is the load current. LOAD that only 3 A is conducted into the short. If self-heating of the I is the ground current. GND junction becomes great enough to cause its temperature to rise Power dissipation due to ground current is quite small and can above 150°C, thermal shutdown activates, turning off the output be ignored. Therefore, the junction temperature equation can and reducing the output current to zero. As the junction temper- be simplified as follows: ature cools and drops below 135°C, the output turns on and T = T + {[(V − V ) × I ] × θ } (6) conducts 3 A into the short, again causing the junction temper- J A IN OUT LOAD JA ature to rise above 150°C. This thermal oscillation between As shown in Equation 6, for a given ambient temperature, input- 135°C and 150°C causes a current oscillation between 3 A and to-output voltage differential, and continuous load current, a 0 A that continues as long as the short remains at the output. minimum copper size requirement exists for the PCB to ensure that the junction temperature does not rise above 125°C. Figure 36 Current-limit and thermal overload protections are intended to through Figure 41 show junction temperature calculations for protect the device against accidental overload conditions. For different ambient temperatures, load currents, V to V reliable operation, device power dissipation should be externally IN OUT differentials, and areas of PCB copper. limited so that junction temperatures do not exceed 125°C. Rev. H | Page 15 of 20

ADP1740/ADP1741 Data Sheet 140 140 MAX JUNCTION MAX JUNCTION TEMPERATURE TEMPERATURE C) 120 C) 120 E, T (°J 100 LOAD = 2A E, T (°J 100 LOAD = 2A LOAD = 500mA R LOAD = 1A R LOAD = 1A U U AT 80 AT 80 LOAD = 250mA ER LOAD = 500mA ER P P M M E 60 E 60 N T LOAD = 250mA N T TIO 40 LOAD = 100mA TIO 40 LOAD = 100mA LOAD = 10mA C C N N U U J 20 LOAD = 10mA J 20 0 0 0.5 1.0 1V.5IN – VOUT (2V.)0 2.5 3.0 07081-034 0.5 1.0 1V.5IN – VOUT (2V.)0 2.5 3.0 07081-037 Figure 36. 6400 mm2 of PCB Copper, TA = 25°C, LFCSP Figure 39. 6400 mm2 of PCB Copper, TA = 50°C, LFCSP 140 140 MAX JUNCTION LOAD = 2A MAX JUNCTION TEMPERATURE TEMPERATURE C) 120 C) 120 RE, T (°J 100 LOAD = 2ALOAD = 1A RE, T (°J 100 LOAD = 1A LOAD = 500mA ERATU 80 LOAD = 500mA LOAD = 250mA ERATU 80 LOAD = 250mA P P EM 60 EM 60 LOAD = 100mA T T N LOAD = 100mA N O O LOAD = 10mA TI 40 TI 40 C C N N U U J 20 LOAD = 10mA J 20 0 0 0.5 1.0 1V.5IN – VOUT (2V.)0 2.5 3.0 07081-035 0.5 1.0 1V.5IN – VOUT (2V.)0 2.5 3.0 07081-038 Figure 37. 500 mm2 of PCB Copper, TA = 25°C, LFCSP Figure 40. 500 mm2 of PCB Copper, TA = 50°C, LFCSP 140 140 MAX JUNCTION LOAD = 1A MAX JUNCTION TEMPERATURE TEMPERATURE C) 120 C) 120 E, T (°J 100 LOAD = 1A E, T (°J 100 LOAD = 500mA LOAD = 250mA UR LOAD = 500mA LOAD = 250mA UR AT 80 AT 80 R R LOAD = 100mA E E P P M M E 60 E 60 T T ON LOAD = 100mA ON LOAD = 10mA TI 40 TI 40 C C N N U U J 20 LOAD = 10mA J 20 0 0 0.5 1.0 1V.5IN – VOUT (2V.)0 2.5 3.0 07081-036 0.5 1.0 1V.5IN – VOUT (2V.)0 2.5 3.0 07081-039 Figure 38. 0 mm2 of PCB Copper, TA = 25°C, LFCSP Figure 41. 0 mm2 of PCB Copper, TA = 50°C, LFCSP Rev. H | Page 16 of 20

Data Sheet ADP1740/ADP1741 In cases where the board temperature is known, the thermal 140 MAX JUNCTION characterization parameter, Ψ , can be used to estimate the TEMPERATURE JB jidusi nscsaciltpciaoutnliao ttneem d( PfprDeo)r mauts utihnreeg rbtihoseea .rf Mdo ltlaoexmwimipneugrm afot ujrurmne uc(tTliaoB: )n a tnemd tpheer aptouwree r(T J) URE, T (°C)J 112000 LOAD = 2A LOAD = 1A TJ = TB + (PD × ΨJB) (7) ERAT 80 Figure 42 through Figure 45 show junction temperature EMP 60 LOAD = 500mA T calculations for different board temperatures, load currents, ON LOAD = 250mA VIN to VOUT differentials, and areas of PCB copper. CTI 40 N U 140 J 20 LOAD = 10mA MAX JUNCTION LOAD = 100mA TEMPERATURE RE, T (°C)J 112000 LOAD = 2A LOAD = 1A 00.2F5igure 440. .170500 mm21 o.V2fI 5NP C–B V COUoTp 1(pV.e7)5r, TB = 252°C.2,5 LFCSP 2.75 07081-042 U ERAT 80 LOAD = 500mA 140 MAX JUNCTION P TEMPERATURE M JUNCTION TE 642000 LLOOAADD == 21500mmAA ATURE, T (°C)J 11208000 LOAD = 2A LOADL =O 1AAD = 500mA LOAD = 100mA ER LOAD = 250mA P 00.25 0.75 1.V2I5N – VOUT 1(V.7)5 2.25 2.75 07081-040 TION TEM 6400 LOAD = 100mA LOAD = 10mA Figure 42. 500 mm2 of PCB Copper, TB = 25°C, LFCSP NC U 140 J 20 MAX JUNCTION TEMPERATURE RE, T (°C)J 112000 LOAD = 2ALOAD = 1A 00.2F5igure 450. .170500 mm21 o.V2fI 5NP C– BV OCUoTp 1(pV.e7)5r, TB = 502°C.2,5 LFCSP 2.75 07081-043 U LOAD = 500mA RAT 80 LOAD = 250mA PCB LAYOUT CONSIDERATIONS E P EM 60 Heat dissipation from the package can be improved by increasing T N the amount of copper attached to the pins of the ADP1740/ O LOAD = 10mA CTI 40 LOAD = 100mA ADP1741. However, as shown in Table 6, a point of diminishing N U returns is eventually reached, beyond which an increase in the J 20 copper size does not yield significant heat dissipation benefits. 00.25 0.75 1.V2I5N – VOUT 1(V.7)5 2.25 2.75 07081-041 H ereP alraec ea tfheew i ngepnuet rcaalp taipcsit worh aesn c dloesseig ansi npgo sPsCibBles :t o the VIN Figure 43. 500 mm2 of PCB Copper, TB = 50°C, LFCSP and GND pins.  Place the output capacitor as close as possible to the VOUT and GND pins.  Place the soft start capacitor close to the SS pin.  Connect the load as close as possible to the VOUT and SENSE pins (ADP1740) or to the VOUT and ADJ pins (ADP1741). Use of 0603 or 0805 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. Rev. H | Page 17 of 20

ADP1740/ADP1741 Data Sheet 07081-044 07081-046 Figure 46. Evaluation Board Figure 48. Typical Board Layout, Bottom Side 07081-045 Figure 47. Typical Board Layout, Top Side Rev. H | Page 18 of 20

Data Sheet ADP1740/ADP1741 OUTLINE DIMENSIONS 4.10 0.35 4.00 SQ 0.30 PIN 1 3.90 0.25 INDICATOR PIN 1 0.65 13 16 INDICATOR BSC 12 1 EXPOSED 2.25 PAD 2.10 SQ 1.95 9 4 0.70 8 5 0.25 MIN TOP VIEW 0.60 BOTTOM VIEW 0.50 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WGGC. 111908-A Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-23) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Output Voltage (V) Package Description Package Option ADP1740ACPZ-0.75R7 −40°C to +125°C 0.75 16-Lead LFCSP_WQ CP-16-23 ADP1740ACPZ-1.0-R7 −40°C to +125°C 1.0 16-Lead LFCSP_WQ CP-16-23 ADP1740ACPZ-1.1-R7 −40°C to +125°C 1.1 16-Lead LFCSP_WQ CP-16-23 ADP1740ACPZ-1.2-R7 −40°C to +125°C 1.2 16-Lead LFCSP_WQ CP-16-23 ADP1740ACPZ-1.3-R7 −40°C to +125°C 1.3 16-Lead LFCSP_WQ CP-16-23 ADP1740ACPZ-1.5-R7 −40°C to +125°C 1.5 16-Lead LFCSP_WQ CP-16-23 ADP1740ACPZ-1.8-R7 −40°C to +125°C 1.8 16-Lead LFCSP_WQ CP-16-23 ADP1740ACPZ-2.5-R7 −40°C to +125°C 2.5 16-Lead LFCSP_WQ CP-16-23 ADP1741ACPZ-R7 −40°C to +125°C Adjustable, 0.75 to 3.3 16-Lead LFCSP_WQ CP-16-23 ADP1740-1.5-EVALZ 1.5 Evaluation Board ADP1741-EVALZ Adjustable Evaluation Board 1 Z = RoHS Compliant Part. Rev. H | Page 19 of 20

ADP1740/ADP1741 Data Sheet NOTES ©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07081-0-1/15(H) Rev. H | Page 20 of 20