Thermoelectric Cooler Controller ADN8830 FEATURES GENERAL DESCRIPTION High Efficiency The ADN8830 is a monolithic controller that drives a thermo- Small Size: 5 mm (cid:2) 5 mm LFCSP electric cooler (TEC) to stabilize the temperature of a laser diode Low Noise: <0.5% TEC Current Ripple or a passive component used in telecommunications equipment. Long-Term Temperature Stability: (cid:3)0.01(cid:4)C This device relies on a negative temperature coefficient (NTC) Temperature Lock Indication thermistor to sense the temperature of the object attached to the Temperature Monitoring Output TEC. The target temperature is set with an analog input voltage Oscillator Synchronization with an External Signal either from a DAC or an external resistor divider. Clock Phase Adjustment for Multiple Controllers The loop is stabilized by a PID compensation amplifier with Programmable Switching Frequency up to 1 MHz high stability and low noise. The compensation network can be Thermistor Failure Alarm adjusted by the user to optimize temperature settling time. The Maximum TEC Voltage Programmability component values for this network can be calculated based on APPLICATIONS the thermal transfer function of the laser diode or obtained Thermoelectric Cooler (TEC) Temperature Control from the lookup table given in the Application Notes section. Resistive Heating Element Control Voltage outputs are provided to monitor both the temperature of Temperature Stabilization Substrate (TSS) Control the object and the voltage across the TEC. A voltage reference of 2.5V is also provided. FUNCTIONAL BLOCK DIAGRAM PID COMPENSATION NETWORK P-CHANNEL FROM (UPPER MOSFET) THERMISTOR TEMPERATURE PWM MEASUREMENT CONTROLLER N-CHANNEL TEMPERATURE AMPLIFIER MOSFET SET DRIVERS INPUT P-CHANNEL VREF REVFOELRTAEGNECE OSCILLATOR (LOWER MOSFET) N-CHANNEL FREQUENCY/PHASE CONTROL REV.D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781/461-3113 © 2012 Analog Devices, Inc. All rights reserved.

ADN8830–SPECIFICATIONS (@ V = 3.3 V to 5.0 V, V = 0 V, T = 25(cid:4)C, T = 25(cid:4)C, using typical application DD GND A SET configuration as shown in Figure 1, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit TEMPERATURE STABILITY Long-Term Stability Using 10 kΩ thermistor with (cid:2) = –4.4% at 25°C 0.01 °C PWM OUTPUT DRIVERS Output Transition Time t , t C = 3,300 pF 20 ns R F L Nonoverlapping Clock Delay 50 65 ns Output Resistance R (N1, P1) I = 50 mA 6 Ω O L Output Voltage Swing OUT A V = 0 V 0 V V LIM DD Output Voltage Ripple (cid:3)OUT A f = 1 MHz 0.2 % CLK Output Current Ripple (cid:3)I f = 1 MHz 0.2 % TEC CLK LINEAR OUTPUT AMPLIFIER Output Resistance R I = 2 mA 85 Ω O, P2 OUT R I = 2 mA 178 Ω O, N2 OUT Output Voltage Swing OUT B 0 V V DD POWER SUPPLY Power Supply Voltage V 3.0 5.5 V DD Power Supply Rejection Ratio PSRR V = 3.3 V to 5 V, V = 0 V 80 92 dB DD TEC –40°C ≤ T ≤ +85°C 60 dB A Supply Current I PWM not switching 8 12 mA SY –40°C ≤ T ≤ +85°C 15 mA A Shutdown Current I Pin 10 = 0 V 5 μA SD Soft-Start Charging Current I 15 μA SS Undervoltage Lockout V Low-to-high threshold 2.0 2.7 V OLOCK ERROR AMPLIFIER Input Offset Voltage V V = 1.5 V 50 250 μV OS CM Gain A 20 V/V V, IN Input Voltage Range V 0.2 2.0 V CM Common-Mode Rejection Ratio CMRR 0.2 V < V < 2.0 V 58 68 dB CM –40°C ≤ T ≤ +85°C 55 dB A Open-Loop Input Impedance R 1 GΩ IN Gain-Bandwidth Product GBW 2 MHz REFERENCE VOLTAGE Reference Voltage V I < 2 mA 2.37 2.47 2.57 V REF REF OSCILLATOR Synchronization Range f Pin 25 connected to external clock 200 1,000 kHz CLK Oscillator Frequency f Pin 24 = V ; (R = 150 kΩ; 800 1,000 1,250 kHz CLK DD Pin 25 = GND) LOGIC CONTROL* Logic Low Input Threshold 0.2 V Logic High Input Threshold 3 V Logic Low Output Level 0.2 V Logic High Output Threshold V – 0.2 V DD *Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 μA). Specifications subject to change without notice. –2– REV. D

ADN8830 ABSOLUTE MAXIMUM RATINGS* Package Type (cid:5) * (cid:5) Unit JA JC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . .GND to V + 0.3 V 32-Lead LFCSP (ACP) 35 10 °C/W S Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C *(cid:4) is specified for worst-case conditions, i.e., (cid:4) is specified for a device Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C soJAldered in a 4-layer circuit board for surface-mJoAunt packages. Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C ESD RATINGS 883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 1.0 kV *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION T MPOUTNDASENCOUTFTSTAREQNCIN CEGHYORY NTAPSSFS 2 1 0 9 8 7 6 5 33322222 THERMFAULT 1 PIN 1 24 COMPOSC THERMIN 2 INDICATOR 23 PGND SD 3 22 N1 TEMPSET 4 21 P1 ADN8830 TEMPLOCK 5 20 PVDD NC 6 TOP VIEW 19 OUT A VREF 7 18 COMPSWIN AVDD 8 17 COMPSWOUT 90123456 B 2 12 1L 1B 1T 1 M1C 1 OUT NPMPCTOMPFMPOUVLIVTE TECCO NC = NO CONNECT THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO VCC OR THE GND PLANE. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN8830 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. D –3–

ADN8830 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description 1 THERMFAULT Digital Output Indicates an Open or Short-Circuit Condition from Thermistor. 2 THERMIN Analog Input Thermistor Feedback Input. 3 SD Digital Input Puts Device into Low Current Shutdown Mode. Active low. 4 TEMPSET Analog Input Target Temperature Input. 5 TEMPLOCK Digital Output Indicates when Thermistor Temperature is within ±0.1°C of Target Tem- perature as Set by TEMPSET Voltage. 6 NC No Connection, except as Noted in the Application Notes Section. 7 VREF Analog Output 2.5 V Reference Voltage. 8 AVDD Power Power for Nondriver Sections. 3.0 V min; 5.5 V max. 9 OUT B Analog Input Linear Output Feedback. Will typically connect to TEC+ pin of TEC. 10 N2 Analog Output Drives Linear Output External NMOS Gate. 11 P2 Analog Output Drives Linear Output External PMOS Gate. 12 TEMPCTL Analog Output Output of Error Amplifier. Connects to COMPFB through feedforward section of compensation network. 13 COMPFB Analog Input Feedback Summing Node of Compensation Amplifier. Connects to TEMPCTL and COMPOUT through compensation network. 14 COMPOUT Analog Output Output of Compensation Amplifier. Connects to COMPFB through feed- back section of compensation network. 15 VLIM Analog Input Sets Maximum Voltage across TEC. 16 VTEC Analog Output Indicates Relative Voltage across the TEC. The 1.5 V corresponds to 0 V across TEC. The 3.0 V indicates maximum output voltage, maximum heat transfer through TEC. 17 COMPSWOUT Analog Output Compensation for Switching Amplifier. 18 COMPSWIN Analog Input Compensation for Switching Amplifier. Capacitor connected between COMPSWIN and COMPSWOUT. 19 OUT A Analog Input PWM Output Feedback. Will typically connect to TEC– pin of TEC. 20 PVDD Power Power for Output Driver Sections. 3.0 V min; 5.5 V max. 21 P1 Digital Output Drives PWM Output External PMOS Gate. 22 N1 Digital Output Drives PWM Output External NMOS Gate. 23 PGND Ground Power Ground. External NMOS devices connect to PGND. Can be connected to digital ground as noise sensitivity at this node is not critical. 24 COMPOSC Analog Input Connect as Indicated in the Application Notes Section. 25 SYNCIN Digital Input Optional Clock Input. If not connected, clock frequency set by FREQ pin. 26 FREQ Analog Input Sets Switching Frequency. 27 SOFTSTART Analog Input Controls Initialization Time for ADN8830 with Capacitor to Ground. 28 SYNCOUT Digital Output Phase Adjusted Clock Output. Phase set from PHASE pin. Can be used to drive SYNCIN of other ADN8830 devices. 29 PHASE Analog Input Sets Switching and SYNCOUT Clock Phase Relative to SYNCIN Clock. 30 AGND Ground Analog Ground. Should be low noise for highest accuracy. 31 TEMPOUT Analog Output Indication of Thermistor Temperature. 32 NC No Connection. EP Exposed Pad The exposed pad on the bottom of the package must be connected to V or the CC GND plane. –4– REV. D

Typical Performance Characteristics–ADN8830 360 VDD = 5V SYNC IN = 200kHz TA = 25(cid:4)C 320 TA = 25(cid:4)C P1 280 s) E (1V/DIV) FT (Degree224000 LTAG E SHI160 O S V A120 H P N1 80 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.4 0.8 1.2 1.6 2.0 2.4 TIME (20ns/DIV) VPHASE (V) TPC 1.N1 and P1 Rise Time TPC 4.Clock Phase Shift vs. Phase Voltage 2.480 VDD = 5V TA = 25(cid:4)C P1 2.475 V) DI 2.470 V/ V) E (1 ( EF G R A V LT 2.465 O V N1 2.460 0 2.455 0 0 0 0 0 0 0 0 0 0 0 –40 –15 10 35 60 85 TIME (20ns/DIV) TEMPERATURE ((cid:4)C) TPC 2.N1 and P1 Fall Time TPC 5.VREF vs. Temperature 360 1,000 SYNC IN = 1MHz VDD = 5V 320 TA = 25(cid:4)C TA = 25(cid:4)C 280 Hz) 800 ees)240 CY (k egr EN 600 E SHIFT (D126000 NG FREQU 400 PHAS120 WITCHI 80 S 200 40 0 0 0 0.4 0.8 1.2 1.6 2.0 2.4 0 250 500 750 1,000 1,250 1,500 VPHASE (V) RFREQ (k(cid:6)) TPC 3.Clock Phase Shift vs. Phase Voltage TPC 6.Switching Frequency vs. R FREQ REV. D –5–

ADN8830 1,000 45 VDD = 5V VDD = 5V 990 RFREQ = 150k(cid:6) 40 TA = 25(cid:4)C USING CIRCUIT SHOWN IN FIGURE 1 QUENCY (kHz) 998700 RENT (mA) 323055 E 960 R R U NG F 950 LY C 20 WITCHI 940 SUPP 15 S 10 930 5 920 0 –40 –15 10 35 60 85 200 300 400 500 600 700 800 900 1,000 TEMPERATURE ((cid:4)C) SWITCHING FREQUENCY (kHz) TPC 7.Switching Frequency vs. Temperature TPC 10.Supply Current vs. Switching Frequency 70 2.06 65 V) D ( L 60 O 2.05 (cid:7)OLTAGE (V) 5550 PER THRESH 2.04 T V UP SE 45 LT F U F A O F 40 M 2.03 R E H 35 T 30 2.02 –40 –15 10 35 60 85 –40 –15 10 35 60 85 TEMPERATURE ((cid:4)C) TEMPERATURE ((cid:4)C) TPC 8.Offset Voltage vs. Temperature TPC 11.Open Thermistor Fault Threshold vs. Temperature 200 0.26 V) 100 D ( L O V) SH (cid:7) 0 E 0.25 E ( HR OLTAG –100 WER T OFFSET V –200 FAULT LO 0.24 M R –300 HE T –400 0.23 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 –40 –15 10 35 60 85 COMMON-MODE VOLTAGE (V) TEMPERATURE ((cid:4)C) TPC 9.Offset Voltage vs. Common-Mode Voltage TPC 12.Short Thermistor Fault Threshold vs. Temperature –6– REV. D

ADN8830 APPLICATION NOTES In addition, an effective controller should operate down to 3.3 V Principle of Operation and have an indication of when the target temperature has been The ADN8830 is a controller for a TEC and is used to set and reached. The ADN8830 accomplishes all of these requirements stabilize the temperature of the TEC. A voltage applied to the with a minimum of external components. Figure 1 shows a input of the ADN8830 corresponds to a target temperature reference design for a typical application. setpoint. The appropriate current is then applied to the TEC Temperature is monitored by connecting the measurement to pump heat either to or away from the object whose tem- thermistor to a precision amplifier, called the error amplifier, perature is being regulated. The temperature of the object is with a simple resistor divider. This voltage is compared against measured by a thermistor and is fed back to the ADN8830 to the temperature set input voltage, creating an error voltage that correct the loop and settle the TEC to the appropriate final is proportional to their difference. To maintain accurate wave- temperature. For best stability, the thermistor should be mounted length and power from the laser diode, this difference voltage in close proximity to the object. In most laser diode modules, must be as accurate as possible. For this reason, self-correction the TEC and thermistor are already mounted in the unit and auto-zero amplifiers are used in the input stage of the ADN8830, are used to regulate the temperature of the laser diode. providing a maximum offset voltage of 250 μV over time and A complete TEC controller solution requires: temperature. This results in final temperature accuracy within • A precision input amplifier stage to accurately measure the ±0.01°C in typical applications, eliminating the ADN8830 as an error source in the temperature control loop. A logic output is difference between the target and object temperatures. • A compensation amplifier to optimize the stability and provided at TEMPLOCK to indicate when the target temperature has been reached. temperature settling time. • A high output current stage. Because of the high output The output of the error amplifier is then fed into a compensa- currents involved, a TEC controller should operate with tion amplifier. An external network consisting of a few resistors high efficiency to minimize the heat generated from and capacitors is connected around the compensation amplifier. power dissipation. This network can be adjusted by the user to optimize the step SYNCOUT TEMPOUT C1 R1 0.1(cid:7)F 150k(cid:6) 32 31 30 29 28 27 26 25 3.3V 4.L7(cid:7)1H COILCRAFT DO3316-472 THERMFAULT 1 24 TEC– THERMIN C2 1R0kT(cid:6)H R7.268k(cid:6) 2 23 2C2D(cid:7)EF ESRD @25(cid:4)C 0.1% Q1 VREF FDW2520C-B 3 22 3.3V Q2 TEMPSET 4 21 FDW2520C-A R3 10k(cid:6) ADN8830 0.1% TEMPLOCK 5 20 3.3V R4 C3 C4 7.68k(cid:6) 10(cid:7)F 0.1% 22(cid:7)F 6 19 CDE ESRD 3.3V VREF 7 18 C5 10nF 3.3V 8 17 3.3V 10C(cid:7)7F C8 10(cid:7)F 9 10 11 12 13 14 15 16 Q3 R5 C9 FDW2520C-A 205k(cid:6) 10(cid:7)F C6 2.2nF R6 C10 1C(cid:7)1F1 R7 100k(cid:6) 330pF Q4 TEC+ 1M(cid:6) VTEC FDW2520C-B C12 3.3nF Figure 1.Typical Application Schematic REV. D –7–

ADN8830 response of the TEC’s temperature either in terms of settling time simple integrator or PID loop, the dc forward gain of the or maximum current change. Details of how to adjust the compen- compensation section is equal to the open-loop gain of the sation network are given in the Compensation Loop section. compensation amplifier, which is over 80 dB or 10,000. The output from the compensation loop at COMPOUT is then fed The ADN8830 can be easily integrated with a wavelength locker to the linear amplifier. The output of the linear amplifier at for fine-tune temperature adjustment of the laser diode for a OUT B is fed with COMPOUT into the PWM amplifier whose specific wavelength. This is a useful topology for tunable wave- output is OUT A. These two outputs provide the voltage drive length lasers. Details are highlighted in the Using the TEC directly to the TEC. Including the external transistors, the gain of Controller ADN8830 with a Wave Locker section. the differential output section is fixed at 4. Details on the output The TEC is driven differentially using an H-bridge configura- amplifiers can be found in the Output Driver Amplifiers section. tion to maximize the output voltage swing. The ADN8830 drives external transistors that are used to provide current to the TEC. These transistors can be selected by the user based on the 1.5V maximum output current required for the TEC. The maximum COMPENSATION PWM/LINEAR INPUT AMPLIFIER AMPLIFIERS voltage across the TEC can be set through use of the VLIM pin 4 AMPLIFIER TEMPSET 19 on the ADN8830. 1.5V OUT A THERMIN To further improve the power efficiency of the system, one side 2 AV = 20 OUT B 9 of the H-bridge uses a switched output. Only one inductor and AV = Z2/Z1 AV = 4 one capacitor are required to filter out the switching frequency. 12 13 14 The output voltage ripple is a function of the output inductor Z1 Z2 TEMPCTL COMPOUT and capacitor and the switching frequency. For most applica- COMPFB tions, a 4.7 μH inductor, 22 μF capacitor, and switching frequency Figure 2.Signal Flow Block Diagram of the ADN8830 of 1 MHz maintains less than ±0.5% worst-case output voltage Thermistor Setup ripple across the TEC. The other side of the H-bridge does not The temperature of the thermal object, such as a laser diode, is require any additional circuitry. detected with a negative temperature coefficient (NTC) thermistor. The oscillator section of the ADN8830 controls the switched The thermistor’s resistance exhibits an exponential relationship to output section. A single resistor sets the switching frequency the inverse of temperature, meaning the resistance decreases at from 100 kHz to 1 MHz. The clock output is available at the higher temperatures. Thus, by measuring the thermistor resistance, SYNCOUT pin and can be used to drive another ADN8830 temperature can be ascertained. Betatherm is a leading supplier device by connecting to its SYNCIN pin. The phase of the of NTC thermistors. Thermistor information and details can be clock is adjusted by a voltage applied to the PHASE pin, which found at www.betatherm.com. can be set by a simple resistor divider. Phase adjustment allows For this application, the resistance is measured using a voltage two or more ADN8830 devices to operate from the same clock divider. The thermistor is connected between THERMIN (Pin 2) frequency and not have all outputs switch simultaneously, which and AGND (Pin 30). Another resistor (R ) is connected between could create an excessive power supply ripple. Details of how to X VREF (Pin 7) and THERMIN (Pin 2), creating a voltage divider adjust the clock frequency and phase are given in the Setting the for the VREF voltage. Figure 3 shows the schematic for this Switching Frequency section. configuration. For effective indication of a catastrophic system failure, the ADN8830 alerts to open-circuit or short-circuit conditions from the VDD thermistor, preventing an erroneous and potentially damaging 8 temperature correction from occurring. With some additional 7 external circuitry, output overcurrent detection can be imple- mented to provide warning in the event of a TEC short-circuit RX failure. This circuit is highlighted in the Setting Maximum 2 ADN8830 Output Current and Short-Circuit Protection section. Signal Flow Diagram RTHERM Figure 2 shows the signal flow diagram through the ADN8830. The input amplifier is fixed with a gain of 20. The voltage at 30 TEMPCTL can be expressed as ( ) TEMPCTL=20× TEMPSET –THERMIN +1.5 (1) Figure 3.Connecting a Thermistor to the ADN8830 With the thermistor connected from THERMIN to AGND, the When the temperature is settled, the thermistor voltage will be voltage at THERMIN will decrease as temperature increases. equal to the TEMPSET voltage, and the output of the input To maintain the proper input-to-output polarity in this configu- amplifier will be 1.5 V. ration, OUT A (Pin 19) should connect to the TEC– pin on the The voltage at TEMPCTL is then fed into the compensation TEC, and OUT B (Pin 9) should connect to the VTEC+ pin. amplifier whose frequency response is dictated by the compen- The thermistor can also be connected from VREF to THERMIN sation network. Details on the compensation amplifier can be with R connecting to ground. In this case, OUT A must connect to found in the Compensation Loop section. When configured as a X TEC+ with OUT B connected to TEC– for proper operation. –8– REV. D

ADN8830 Although the thermistor has a nonlinear relationship to tem- The setpoint voltage can be driven from a DAC or another perature, near optimal linearity over a specified temperature voltage source, as shown in Figure 4. The reference voltage range can be achieved with the proper value of R . First, the for the DAC should be connected to VREF (Pin 7) on the X resistance of the thermistor must be known, where ADN8830 to ensure best accuracy from device to device. R =R @T =T For a fixed target temperature, a voltage divider network can be THERM T1 LOW used as shown in Figure 5. R1 is set equal to R , and R2 is =R @T =T X T2 MID (2) equal to the value of R at the target temperature. THERM =R @T =T T3 HIGH T and T are the endpoints of the temperature range and 3.3V 3.3V LOW HIGH TMID is the average. These resistances can be found in most 7 8 thermistor data sheets. In some cases, only the coefficients 1–4 6 4 AD7390 corresponding to the Steinhart-Hart equation are given. The Steinhart-Hart equation is 5 8 ADN8830 1 =a+b1n(R)+c[1n(R)]3 (3) T (cid:7)C 7 where T is the absolute temperature of the thermistor in Kelvin (K = °C + 273.15), and R is the resistance of the thermistor at 30 that temperature. Based on the coefficients a, b, and c, R THERM can be calculated for a given T, albeit somewhat tediously, by Figure 4.Using a DAC to Control the Temperature solving the cubic roots of this equation Setpoint ⎡ 1 1⎤ ⎢⎛ 1⎞3 ⎛ 1⎞3⎥ 3.3V RTHERM =exp⎢⎢⎢⎜⎜⎜–2χ+⎛⎝⎜χ42 + ψ273⎞⎠⎟2⎟⎟⎟ +⎜⎜⎜–χ2–⎛⎝⎜χ42 + ψ273⎞⎠⎟2⎟⎟⎟ ⎥⎥⎥ (4) 7 8 ⎝ ⎠ ⎝ ⎠ ⎢ ⎥ ⎣ ⎦ R1 where 4 ADN8830 1 X =a–T andψ= b R2 c c 30 R is then found as X Figure 5.Using a Voltage Divider to Set a Fixed RX = RT1RTR2 ++RTR2RT–32–R2RT1RT3 (5) Temperature Setpoint T1 T3 T2 Design Example 1 A laser module requires a constant temperature of 25°C. From For the best accuracy as well as the widest selection range for the manufacturer’s data sheet, we find the thermistor in the laser resistances, R should be 0.1% tolerance. Naturally, the smaller X module has a value of 10 kΩ at 25°C. Because the laser is not the temperature range required for control, the more linear required to operate at a range of temperatures, the value of R the voltage divider will be with respect to temperature. The X can be set to 10 kΩ. TEMPSET can be set by a simple resistor voltage at THERMIN is divider as shown in Figure 5, with R1 and R2 both equal to 10kΩ. R V =VREF THERM (6) Design Example 2 X R +R THERM X A laser module requires a continuous temperature control from where VREF has a typical value of 2.47 V. 5°C to 45°C. The manufacturer’s data sheet shows the thermistor has a value of 10 kΩ at 25°C, 25.4 kΩ at 5°C, and 4.37kΩ at The ADN8830 control loop will adjust the temperature of the 45°C. Using Equation 5, R is calculated to be 7.68 kΩ to yield TEC until V equals the voltage at TEMPSET (Pin 4), which X X the most linear temperature-to-voltage conversion. A DAC we define as V . Target temperature can be set by SET will be used to set the TEMPSET voltage. ( ) V =mT –T +V (7) DAC Resolution for TEMPSET SET MID XMID The temperature setpoint voltage to THERMIN can be set from where T equals the target temperature, and a DAC. The DAC must have a sufficient number of bits to achieve V –V adequate temperature resolution from the system. The voltage m= X,HIGH X,LOW (8) range for THERMIN is found by multiplying the variable m T –T HIGH LOW from Equation 8 by the temperature range. VX for high, mid, and low are found by using Equation 6 and THERMINVoltageRange=m×(T –T ) (9) substituting R , R , and R , respectively, for R . The MAX MIN T3 T2 T1 THERM variable m is the change in V with respect to temperature and From Design Example 2, 40°C of the control temperature range X is expressed in V/°C. is achieved with a voltage range of only 1 V. REV. D –9–

ADN8830 To eliminate the resolution of the DAC as the principal source Table I. Switching Frequencies vs. R FREQ of system error, the step size of each bit, V , should be lower STEP f R than the desired system resolution. A practical value for absolute SWITCH FREQ DAC resolution is the equivalent of 0.05°C. The value of VSTEP 100 kHz 1.5 MΩ should be less than the value of m from Equation 8 multiplied 250 kHz 600 kΩ by the desired temperature resolution, or 500 kHz 300 kΩ V <0.05°C×m (10) 750 kHz 200 kΩ STEP 1 MHz 150 kΩ where m is the slope of the voltage-to-temperature conversion line, as found from Equation 8. From Design Example 2, where For other frequencies, the value for this resistor, R , should FREQ m = 25 mV/°C, we see the DAC should have resolution better be set to than 1.25 mV per step. 150×109 The minimum number of bits required is then given as RFREQ = f (12) ( ) ( ) SWITCH logV –logV Numberof Bits= FS ( ) STEP (11) where fSWITCH is the switching frequency in Hz. log 2 Higher switching frequencies reduce the voltage ripple across where V is the full-scale output voltage from the DAC, which the TEC. However, high switch frequencies will create more FS should be equal to the reference voltage from the ADN8830, power dissipation in the external transistors. This is due to the VREF = 2.47 V as given in the Specifications table for the more frequent charging and discharging of the transistors’ gate Reference Voltage. In this example, the minimum resolution is capacitances. If large transistors are needed for a high output 11bits. A12-bit DAC, such as the AD7390, can be readily current application, faster switching frequencies could reduce found. the overall power efficiency of the circuit. This is covered in detail in the Calculating Power Dissipation and Efficiency section. It is important that the full-scale voltage input to the DAC is tied to the ADN8830 reference voltage, as shown in Figure 4. This The switching frequency of the ADN8830 can be synchronized eliminates errors from slight variances of VREF. with an external clock by connecting the clock signal to SYNCIN (Pin 25). Pin 24 should also be connected to an R-C network, as Thermistor Fault and Temperature Lock Indications shown in Figure 6. This network is simply used to compensate a Both the THERMFAULT (Pin 1) and TEMPLOCK (Pin 5) PLL to lock on to the external clock. To ensure the quickest outputs are CMOS compatible outputs that are active high. synchronization lock-in time, R should be set to 1.5 MΩ. THERMFAULT will be a logic low while the thermistor is FREQ operating normally and will go to a logic high if a short or open is detected at THERMIN (Pin 2). The trip voltage for 1nF ADN8830 THERMFAULT is when THERMIN falls below 0.2 V or COMPOSC exceeds 2.0 V. THERMFAULT provides only an indication of 24 1k(cid:6) 0.1(cid:7)F a fault condition and does not activate any shutdown or protec- tion circuitry on the ADN8830. To shut down the ADN8830, a logic low voltage must be asserted on Pin 3, as described in the FREQ Shutdown Mode section. 26 1.5M(cid:6) TEMPLOCK will output a logic high when the voltage at THERMIN is within 2.5 mV of TEMPSET. This voltage can Figure 6.Using an R-C Network on Pin 24 with be related to temperature by solving for m from Equation 8. For anExternal Clock most laser diode applications, 2.5 mV is equivalent to ±0.1°C. The relative phase of the ADN8830 internal oscillator compared If the voltage difference between THERMIN and TEMPSET is to the external clock signal can be adjusted. This is accomplished greater than 2.5 mV, then TEMPLOCK will output a logic low. by adjusting the voltage to PHASE (Pin 29) according to TPCs3 The input offset voltage of the ADN8830 is guaranteed to within and 4. The phase shift versus voltage can be approximated as 250 μV, which for most applications is within ±0.01°C. V Setting the Switching Frequency PhaseShift°=360°× PHASE (13) The ADN8830 has an internal oscillator to generate the switch- VREF ing frequency for the output stage. This oscillator can be either where V is the voltage at Pin 29, and VREF has a typical PHASE set in free-run mode or synchronized to an external clock value of 2.47 V. signal. For free-run operation, SYNCIN (Pin 25) should be To ensure the oscillator operates correctly, V should remain PHASE connected to ground and COMPOSC (Pin 24) should be higher than 100 mV and lower than 2.3 V. This is required for connected to AVDD. The switching frequency is then set by a either internal clock or external synchronization operation. A single resistor connected from FREQ (Pin 26) to ground. resistor divider from VREF to ground can establish this voltage Table I shows R for some common switching frequencies. FREQ easily, although any voltage source, such as a DAC, could be used as well. If phase is not a consideration, for example with a single ADN8830 being used, Pin 29 can be tied to Pin 6, which pro- vides a 1.5V reference voltage. –10– REV. D

ADN8830 The phase adjusted output from the ADN8830 is available at Soft Start on Power-Up SYNCOUT (Pin 28). This pin can be used as a master clock The ADN8830 can be programmed to ramp up for a specified signal for driving other ADN8830 devices. Multiple ADN8830 time after the power supply is applied or after shutdown is devices can be either driven from a single master ADN8830 de-asserted. This feature, known as soft start, is useful for device by connecting its SYNCOUT pin to each slave’s SYNCIN gradually increasing the duty cycle of the PWM amplifier. The pin or daisy-chained by connecting each device’s SYNCOUT to soft start time is set with a single capacitor connected from Pin 27 the next device’s SYNCIN pin. to ground according to Equation 14. Phase shifting is useful in systems that use more than one τ =150×C (14) SS SS ADN8830 TEC controller. It ensures the ADN8830 devices where C is the value of the capacitor in microfarads, and (cid:5) is will not switch at the same time, which could create excessive SS SS the soft start time in milliseconds. To set a soft start time of 15 ms, ripple on the power supply voltage. By adjusting the phase of C should equal 0.1 μF. A minimum soft start time of 10 ms is each device, the switching transients can be spaced equally over SS recommended to ensure proper initialization of the ADN8830 the clock period, reducing potential supply ripple and easing the on power-up. instantaneous current demand from the supply. Using a single master clock, each slave ADN8830 should have a Shutdown Mode The ADN8830 has a shutdown mode that deactivates the output different value phase shift. For example, with four TEC con- trollers, one slave device should be set for 90° of phase shift, stage and puts the device into a low current standby state. The another for 180°, and the last for 270°. In a daisy-chain configu- current draw for the ADN8830 in shutdown is less than 100 μA. The shutdown input, Pin 3, is active low. To shut down the ration, each slave device would be set with equal phase. Using the previous example, each slave would be set to 90° with its device, Pin 3 should be driven to logic low. Once a logic high is applied, the ADN8830 will reactivate after the delay set by the SYNCOUT pin connected to the next device’s SYNCIN pin. soft start circuitry. Refer to the Soft Start on Power-Up section Examples are shown in Figures 7 and 8. for more details on this feature. Pin 3 should not be left floating as there are no internal pull-up 25 ADN8830 28 or pull-down resistors. If the shutdown function is not required, NC 7 SLAVE Pin 3 should be tied to V to ensure the device is always active. DD 50k(cid:6) 29 26 241k(cid:6) 1nF Compensation Loop 150k(cid:6) 0.1(cid:7)F The ADN8830 TEC controller has a built-in amplifier dedicated VDD for loop compensation. The exact compensation network is set by the user and can vary from a simple integrator to PI, PID, or 24 any other type of network. The type of compensation and com- 25 ADN8830 28 25 ADN8830 28 ponent values should be determined by the user since it will NC MASTER 7 SLAVE depend on the thermal response of the object and the TEC. One 6 29 26 100k(cid:6) 29 26 241k(cid:6) 1nF method for determining these values empirically is to input a step 0.1(cid:7)F function to TEMPSET, thus changing the target temperature, RFREQ 100k(cid:6) 1.5M(cid:6) and adjusting the compensation network to minimize the set- tling time of the object’s temperature. A typical compensation network used for temperature control 25 ADN8830 28 of a laser module is a PID loop, which consists of a very low NC 7 SLAVE frequency pole and two separate zeros at higher frequencies. 150k(cid:6) 29 26 241k(cid:6) 1nF Fpeignusraet i9o ns.h oAwns aad sdiimtipolnea nl eptowloer iks faodr dimedp laetm ae hnitginhge rP fIrDeq cuoemn-cy 0.1(cid:7)F 50k(cid:6) 1.5M(cid:6) than the zeros to reduce the noise sensitivity of the control loop. The bode plot of the magnitude is shown in Figure 10. Figure 7.Multiple ADN8830 Devices Driven from a Master Clock 1nF 1nF 1nF VDD 24 0.1(cid:7)F 1k(cid:6) 24 0.1(cid:7)F 1k(cid:6) 24 0.1(cid:7)F 1k(cid:6) 24 25 ADN8830 28 25 ADN8830 28 25 ADN8830 28 25 ADN8830 28 NC NC MASTER 7 SLAVE 7 SLAVE 7 SLAVE 6 150k(cid:6) 150k(cid:6) 150k(cid:6) 29 26 29 26 29 26 29 26 RFREQ 50k(cid:6) 1.5M(cid:6) 50k(cid:6) 1.5M(cid:6) 50k(cid:6) 1.5M(cid:6) Figure 8.Multiple ADN8830 Devices Using a Daisy Chain REV. D –11–

ADN8830 The unity-gain crossover frequency of the feedforward amplifier is given as f = 1 ×80×TECGAIN (15) ALE) 0dB Tloow eer n st0hudBaren stth2aebπ itRlhite3yrC,m t1hael tuimniety c-ognaisnta cnrto ossfo tvheer TfrEeqCu eanncdy t hsheormulids tboer. DE (LOG SC R2R||1R3 U However, this thermal time constant may not be specified and T NI can be difficult to characterize. AG R1 M R3 There are many texts written on loop stabilization, and it is beyond the scope of this data sheet to discuss all methods and trade-offs in optimizing compensation networks. A simple method that 1 1 1 1 can be used to empirically determine a PID compensation loop 2(cid:8)R3C1 2(cid:8)R1C1 2(cid:8)C2(R2+R3) 2(cid:8)R2C2 as shown in Figure 9 involves the following procedure: FREQUENCY (Hz LOG SCALE) 1. Connect thermistor and TEC to the ADN8830 application Figure 10.Bode Plot for PID Compensation circuit. Power does not need to be applied to the laser diode Using the TEC Controller ADN8830 with a Wave Locker for this procedure. Monitor output voltage across the TEC Many optical applications require precision control of laser with an oscilloscope. wavelength. The wavelength of the laser diode can be adjusted 2. Short C1 and open C2, leaving just R1 and R3 as a simple by changing its temperature, which is done through temperature proportional-only compensation loop. control of the TEC. Wavelength control can be done by feeding 3. While maintaining a constant TEMPSET voltage, increase a wave locker or etalon output back to the microprocessor and the ratio of R1/R3, thus increasing the gain until loop oscilla- using the microprocessor to calculate and reinstruct the TEC tion starts to occur. Decrease this ratio by a factor of 2 from controller with a new target temperature. However, this method the point of oscillation. The R1/R3 ratio will likely be less is computationally expensive and has time delays before the than unity for most laser modules. adjustment is done. A faster responding and simpler method is 4. Add C1 capacitor and decrease value until oscillation starts, to feed the wave locker signal back to the TEC controller for then increase by a factor of 2. A good initial starting value for direct temperature control. C1 is to create a unity-gain crossover of 0.1 Hz based on The ADN8830 is designed to be compatible with a wave locker Equation 15. controller. Figure 11 shows the basic schematic. The TEMPCTL 5. Short R2 and increase C2 until oscillation starts. At this point, output from ADN8830 is proportional to the object’s actual either C2 can be decreased or R2 can be added to regain temperature. This voltage is fed to the wave locker controller. stability. Generally speaking, R2 will be greater than R3 and Also fed to the wave locker controller are the photodiode out- C2 will be one or more orders of magnitude less than C1. puts from the wave locker, as well as the laser diode power and 6. TEMPSET should be adjusted with a step change while a digital signal indicating a functional laser diode, both of which observing the output voltage settling time. A step change of come from the CW controller. The output of the wave locker 100mV should suffice. From here, C2, R2, and even C1 can controller is then connected to the input of the compensation be decreased to minimize settling time at the expense of network. This allows the wave locker controller to adjust the additional output voltage overshoot. TEC temperature based on the current temperature of the 7. An additional feedback capacitor, CF, in parallel with R1 object, the current wavelength of the laser diode, and the target and C1, can be added to add another high frequency pole. In wavelength. Once the target wavelength is reached, the wave many cases, this improves the stability of the system without locker controller sends a signal to the microcontroller indicating increasing the settling time as out-of-band noise is filtered that the laser signal is good. out of the control signal. A 330 pF to 1 nF capacitor should suffice, if required. (cid:9) LOCKER The typical values shown in the typical application circuit in FROM (cid:9) PD1 Figure 1 have R1 = 100 kΩ, R2 = 1 MΩ, R3 = 205 kΩ, C1 = 10 μF, LOCKER (cid:9) LOCKER PD2 C2 = 1 μF, and an additional feedback capacitor of 330 pF. For most pump laser modules, this results in a 10°C TEMPSET step WAVE LOCKER GOOD settling time to within 0.1°C in less than 5 seconds. ADN8830 TO LASER DIODE MICRO- FROM CW POWER PROCESSOR CONTROLLER LASER DIODE ADN8830 GOOD TEC REFERENCE CONTROL VOLTAGE TEMPCTL TEMP IN 12 COMPFB COMPOUT COMPOUT TEMPCTL COMPFB 13 14 12 13 C1 14 COMPENSATION R3 R1 NETWORK R2 C2 CF Figure 9.Implementing a PID Compensation Loop Figure 11.Using the ADN8830 with a Wave Locker –12– REV. D

ADN8830 Using TEMPOUT to Measure Temperature where V and V are the voltages at Pins 19 and 9, respec- OUT A OUT B The TEMPOUT pin is a voltage that is proportional to the tively. The ripple voltage at Pin 19 is filtered out internally and difference between the target temperature and the measured does not appear at VTEC, leaving it as an accurate dc output of thermistor temperature. The full equation for the voltage at the TEC voltage. TEMPOUT is The TEC is driven with a differential voltage, allowing current ( ) TEMPOUT =1.5+3× THERMIN –TEMPSET (16) to flow in either direction through the TEC. This can provide heat transfer either to or from the object being regulated without The voltage range of TEMPOUT is 0 V to 3.0 V and is inde- the use of a negative voltage rail. The maximum output voltage pendent of power supply voltage. across the TEC is set by the voltage at VLIM (Pin 15). Refer to the Setting the Maximum TEC Voltage and Current section for Setting the Maximum TEC Voltage and Current details on this operation. With VLIM set to ground, the maximum The ADN8830 can be programmed for a maximum output volt- output voltage is the power supply voltage, V . age to protect the TEC. A voltage from 0 V to 1.5 V applied to DD the VLIM (Pin 15) input to the ADN8830 sets the maximum To achieve a differential output, the ADN8830 has two separate TEC voltage, V . This voltage can be set with either a output stages. OUT A is a switched output or pulse-width TEC, MAX resistor divider or from a DAC. Because the output of the modulated (PWM) amplifier, and OUT B is a high gain linear ADN8830 is bidirectional, this voltage sets both the upper amplifier. Although they achieve the same result, to provide and lower limits of the TEC voltage. The equation governing constant voltage and high current, their operation is different. V is given in Equation 17 and the graph of this equation The exact equations for the two outputs are TEC, MAX is shown in Figure 12. ( ) OUT A=4× COMPOUT –1.5 +OUT B (19) ( ) V = 1.5V –VLIM ×4 (17) TEC,MAX OUT B=–14×(COMPOUT –1.5)+1.5 (20) 5 where COMPOUT is the voltage at Pin 13. The voltage at COMPOUT is determined by the compensation network that is fed by the input amplifier, which receives its input voltage from 4 TEMPSET and THERMIN. Equation 20 is valid only in the linear region of the linear amplifier. OUT B has a lower limit of V) 3 0 V and an upper limit of the power supply. (X A M Because the COMPOUT voltage is not readily known, Equa- C, VTE 2 tion 20 can be rewritten in terms of the TEC voltage, VTEC, which is defined as OUT B – OUT A. OUT B=4×VTEC+1.5 (21) 1 In Figure 1, Pins 10 and 11 provide the gate drive for Q3 and Q4, which complete the linear output amplifier. This output voltage 0 0 0.5 1.0 1.5 2.0 is fed back to Pin 9 (OUT B) to close its loop. The gate-to-drain VLIM (V) capacitance of Q3 and Q4 provide the compensation for the Figure 12.VLIM Voltage vs. Maximum TEC Voltage linear amplifier. If using the recommended FDW2520C transistors, If the supply voltage is lower than V , the maximum TEC it will be necessary to add an additional 2.2 nF of capacitance TEC, MAX voltage will obviously be equal to the supply voltage. The voltage from the gate to the drain of the PMOS transistor to maintain to VLIM should not exceed 1.5 V since this causes improper stability. A 3.3 nF capacitor should also be connected from the operation of the output voltage limiting circuitry. Setting VLIM to drain to ground to prevent small oscillations when there is very 1.5 V can be used to deactivate the TEC current without little or no current through the TEC. shutting down the ADN8830 in the event of a system failure. If a These extra capacitors are specified only when using FDW2520C maximum TEC voltage is not required, VLIM should be con- transistors in the linear amplifier. If other transistors are used, nected to ground. It is not advisable to leave VLIM floating as these values may need to be adjusted. To ensure the linear this would cause unpredictable output behavior. amplifier is stable, the total gate-to-source capacitance for both This feature should be used to limit the maximum output current Q3 and Q4 should be at least 2.5 nF. Refer to the transistor’s to the TEC as specified in the TEC data sheet. For example, if data sheet for its typical gate-to-drain capacitance values. the maximum TEC voltage is specified at 2 V, VLIM should be The output of the linear amplifier is proportional to the voltage set to 1 V. The maximum output voltage is then set to ±2V. at Pin 13 (COMPOUT). Because the linear amplifier operates with a gain of 14, its output will typically be at either ground or Output Driver Amplifiers The output voltage across the TEC as measured from Pin 19 to VDD if there is more than about 100 mA of current flowing Pin 9 can be monitored at Pin 16. This is labeled as VTEC in through the TEC. This ensures Q3 and Q4 will not be a domi- the typical application schematic in Figure 1. The voltage at nant source of power dissipation at high output currents. VTEC can vary from 0 V to 3 V independent of the power supply voltage. Its equation is given as ( ) VTEC =0.25× V –V +1.5 (18) OUTA OUTB REV. D –13–

ADN8830 Inductor Selection I =I +0.5×ΔI (24) L,MAX TEC,MAX L In addition to the external transistors, the PWM amplifier requires an inductor and a capacitor at its output to filter the switched where (cid:3)IL can be found from Equation 23 with the appropriate output waveform. Proper inductor selection is important to duty cycle calculated from Equation 22 with OUT A = VTEC, MAX. achieve the best efficiency. The duty cycle of the PWM sets the Design Example 3 OUT A output voltage and is A TEC is specified with a maximum current of 1.5 A and maxi- mum voltage of 2.5 V. The ADN8830 will be operating from a OUT A D= (22) 3.3 V supply voltage with a 200 kHz clock and a 4.7 μH inductor. V DD The duty cycle of the PWM amplifier at 2.5 V is calculated to be The average current through the inductor is equal to the TEC 75.8%. Using Equation 23, the inductor ripple current is found current. The ripple current through the inductor, (cid:3)I , varies to be 664 mA. From Equation 24, the maximum inductor current L with the duty cycle and is equal to will be 1.82 A and should be considered when selecting the ( ) inductor. Notice that increasing the clock frequency to 1 MHz would V ×D× 1–D ΔI = DD (23) reduce IL, MAX to 1.56 A. L L× f CLK Design Example 4 where f is the clock frequency as set by the resistor R at Using the same TEC as above, the ADN8830 will be powered CLK FREQ Pin 26 or an external clock frequency. Refer to the Setting the from 5.0 V instead. Here, the duty cycle is 50%, which happens Switching Frequency section for more information. Selecting a to be the worst-case duty cycle for inductor current ripple. Now faster switching frequency or a larger value inductor will reduce DIL equals 1.33 A with a 200 kHz clock, and I is 2.83 A. L, MAX the ripple current through the inductor. The waveform of the Reducing the inductor ripple current is another compelling inductor current is shown in Figure 13. reason to operate the ADN8830 from a 3.3 V supply instead. Table II lists some inductor manufacturers and part numbers along with some key specifications. The column I refers to the MAX maximum current at which the inductor is rated to remain linear. Although higher currents can be pushed through the inductor, A) ITEC ΔIL efficiency and ripple voltage will be dramatically degraded. T ( N E This is by no means a complete list of manufacturers or inductors R UR that can be used in the application. More information on these C R inductors is available at their websites. Note the trade-offs O T between inductor height, maximum current, and series resistance. C U D Smaller inductors cannot handle as muèH current and therefore N I require higher clock speeds to reduce their ripple current. They also have higher series resistance, which can lower the overall efficiency of the ADN8830. 1 T =fCLK TIME PWM Output Filter Requirements The switching of Q1 and Q2 creates a pulse width modulated Figure 13.Current Waveform Through Inductor (PWM) square wave from 0 V to V . This square wave must DD It is important to select an inductor that can tolerate the maxi- be filtered sufficiently to create a steady voltage that will drive mum possible current that could pass through it. Most TECs the TEC. The ripple voltage across the TEC is a function of the are specified with a maximum voltage and current for proper inductor ripple current, the L-C filter cutoff frequency, and the and reliable operation. The maximum instantaneous inductor equivalent series resistance (ESR) of the filter capacitor. The current can be found as equivalent circuit for the PWM side is given in Figure 14. Table II. Partial List of Inductors and Key Specifications Inductance ((cid:7)H) I (A) R (m(cid:6)) Height (mm) Part Number Manufacturer Website MAX S, TYP 4.7 1.1 200 1 LPO1704-472M Coilcraft www.coilcraft.com 4.7 1.59 55 2 A918CY-4R7M Toko www.toko.com 4.7 3.9 48 2.8 UP2.8B-4R7 Cooper www.cooperet.com 4.7 1.5 90 3 DO1608C-472 Coilcraft www.coilcraft.com 4.7 1.32 56 3 CDRH4D28 4R7 Sumida www.sumida.com 4.7 7.5 12 4.5 892NAS-4R7M Toko www.toko.com 4.7* 5.4 18 5.2 DO3316P-472 Coilcraft www.coilcraft.com 10 2.7 80 2.8 UP2.8B-100 Cooper www.cooperet.com 15 8 32 8 DO5022P-153HC Coilcraft www.coilcraft.com 47 4.5 86 7.1 DO5022P-473 Coilcraft www.coilcraft.com *Recommend inductor in typical application circuit Figure 1. –14– REV. D

ADN8830 PVDD Calculating PWM Output Ripple Voltage OUT A Although it may seem that f can be arbitrarily lowered to reduce C P1 Q1 output ripple, the ripple voltage is also dependent on the ESR of R2 L1 RL C1, shown as R1 in Figure 14. This resistance creates a zero VX OUT B that turns the second-order filter into a first-order filter at high N1 Q2 R1 frequencies. The location of this zero is C1 DENOTES 1 PGND Z1= (28) 2πR1C1 Figure 14.Equivalent Circuit for PWM Amplifier and Filter With a clock frequency greater than Z1, and presumably greater In this circuit, RL is the TEC resistance, R2 is the parasitic than fC, the output voltage ripple is resistance of the inductor combined with the equivalent r DS, ON ΔOUT A=ΔI ×R1 (29) of Q1 and Q2, and R1 is the ESR of C1. The voltage, VX, is the L pulse-width modulated waveform that switches between PVDD ( ) V D 1–D R1 ( ) and ground. This is a second-order low-pass filter with an exact ΔOUT A= DD for f > Z1 (30) cutoff frequency of L1fCLK CLK 1 R2+R The worst-case voltage ripple occurs when the duty cycle of the fC = 2π (R1+R )CL1L1 (25) PWM output is exactly 50%, or when OUT A = 0.5 (cid:7) VDD. As L shown in Equation 31 Practically speaking, R1 and R2 are several tens of milliohms and V R1 ( ) aorhem ms.u Tchh es mcuatlloefrf tfhreaqnu tehnec yT EcaCn rbees irsotaungchely, waphpicrho xciamna bteed a a fsew (cid:3) OUT AMAX ≈ 4fDCDLKL1 for fCLK >Z1 (31) Here it can be directly seen that increasing the inductor value or 1 1 clock frequency will reduce the ripple. Choosing a low ESR f = (26) C 2π C1L1 capacitor will ensure R1 remains low. Operating from a lower supply voltage will also help reduce the output ripple voltage This cutoff frequency should be much lower than the clock from the L-C filter. With a clock frequency equal to Z1 but frequency to achieve adequate filtering of the switched output presumably greater than f , the worst-case output voltage ripple is waveform. Also of importance is the damping factor, (cid:6), of the C ( ) L-C filter. Too low a damping factor will result in a longer 16R12C12f 2 +1 settling time and could potentially cause stability problems for ΔOUT A =V CLK for(f =Z1) (32) the temperature control loop. Neglecting R1 and R2 again, the MAX DD 32L1C1fCLK CLK damping factor is simply Which, if f < Z1, can be further simplified to CLK 1 L1 V ( ) ζ= (27) ΔOUT A = DD for f <Z1 (33) 2RL C1 MAX 32L1C1fCLK2 CLK Using the recommended values of L1 = 4.7 μH and C1 = 22 μF A typical 100 μF surface-mount electrolytic capacitor can have results in a cutoff frequency of 15.7 kHz. With a TEC resistance an ESR of over 100 mΩ, pulling this zero to below 16 kHz, and of 2 Ω, the damping factor is 0.12. The cutoff frequency can be resulting in an excess of ripple voltage across the TEC. Low ESR decreased to lower the output voltage ripple with slower clock capacitors, such as ceramic or polymer aluminum capacitors, frequencies by increasing L1 or C1. Increasing C1 may appear are recommended instead. Polymer aluminum capacitors can to be a simpler approach as it would not increase the physical provide more bulk capacitance per unit area over ceramic ones, size of the inductor, but there is a potential stability danger in saving board space. Table IV shows a limited list of capacitors lowering the damping factor too far. It is recommended that ζ with their equivalent series resistances. remain greater than 0.05 to provide a reasonable settling time for the TEC. Increasing ζ also makes finding the proper PID This is by no means a complete list of all capacitor manufacturers or capacitor types that can be used in the application. The 22μF compensation easier as there is less ringing in the L-C output capacitor recommended has a maximum ESR of 35 mΩ, which filter. To allow adequate phase and gain margin for the PWM puts Z1 at 207 kHz. Using a 3.3 V supply with the recommended amplifier, Table III should be used to find the lower limit of inductor and capacitor listed with a 1 MHz clock frequency will cutoff frequency for a given damping factor. yield a worst-case ripple voltage at OUT A of about 6 mV. Table III. Minimum L-C Filter Cutoff External FET Requirements Frequency vs. Damping Factor External FETs are required for both the PWM and linear amplifiers that drive OUT A and OUT B from the ADN8830. Although it (cid:10) f (kHz) C, MIN is important to select FETs that can supply the maximum current 0.05 8 required to the TEC, they should also have a low enough resis- 0.1 4 tance (rDS, ON) to prevent excessive power dissipation and improve 0.2 2 efficiency. Other key requirements from these FET pairs are 0.3 1.9 slightly different for the PWM and linear outputs. 0.5 1.6 > 0.707 1.5 REV. D –15–

ADN8830 The gate drive outputs for the PWM amplifier at P1 (Pin 21) Bear in mind that the addition of these capacitors is only and N1 (Pin 22) have a typical nonoverlap delay of 65ns. for local stabilization. The stability of the entire TEC appli- This is done to ensure that one FET is completely off before cation may need adjustment, which should be done around the the other FET is turned on, preventing current from shooting compensation amplifier. This is covered in the Compensation through both simultaneously. Loop section. The input capacitance (C ) of the FET should not exceed 5 nF. There is one additional consideration for selecting both the ISS The P1 and N1 outputs from the ADN8830 have a typical output linear output FETs; they must have a minimum threshold impedance of 6 Ω. This creates a time constant in combination voltage (V ) of 0.6 V. Lower threshold voltages could cause T with C of the external FETs equal to 6 Ω (cid:7) C . To ensure shoot-through current in the linear output transistors. ISS ISS shoot-through does not occur through these FETs, this time Table V shows the recommended FETs that can be used for the constant should remain less than 30 ns. linear output in the ADN8830 application. Table V includes the The linear output from the ADN8830 uses N2 (Pin 10) and appropriate external gate-to-drain capacitance (external C ) GD P2 (Pin 11) to drive the gates of the linear side FETs, shown as and snubber capacitor value (C ) connected from OUT B to SNUB Q3 and Q4 in Figure 1. Local compensation for the linear ampli- ground that should be added to ensure local stability. Table VI fier is achieved through the gate-to-drain capacitances (C ) of shows the recommended PWM output FETs. Although other GD Q3 and Q4. The value of C , which can be determined from transistors can be used, these combinations have been tested GD the data sheet, is usually referred to as C , the reverse transfer and are proved stable and reliable for typical applications. RSS capacitance. The exact C value should be determined from a RSS Data sheets for these devices can be found at their respective graph that shows capacitance versus drain-to-source voltage, websites: using the power supply voltage as the appropriate V . DS Fairchild – www.fairchildsemi.com To ensure stability of the linear amplifier, the total C of the GD Vishay Siliconix – www.vishay.com PMOS device, Q3, should be greater than 2.5 nF and the total International Rectifier – www.irf.com C of the NMOS should be greater than 150 pF. External GD capacitance can be added around the FET to increase the effective Calculating Power Dissipation and Efficiency C of the transistor. This is the function of C6 in the typical The total efficiency of the ADN8830 application circuit is simply GD application schematic shown in Figure 1. If external capacitance the ratio of the output power to the TEC divided by the total must be added, it will generally only be required around the power delivered from the supply. The idea in minimizing power PMOS transistor. dissipation is to avoid both drawing additional power and reduc- ing heat generated from the circuit. The dominant sources In the event of zero output current through the TEC, there will of power dissipation will include resistive losses, gate charge be no current flowing through Q3 and Q4. In this condition, loss, core loss from the inductor, and the current used by the these FETs will not provide any small signal gain and thus no ADN8830 itself. negative feedback for the linear amplifier. This leaves only a feedforward signal path through C , which could cause a The on-channel resistance of both the linear and PWM output GD settling problem at OUT B. This is often seen as a small signal FETs will affect efficiency primarily at high output currents. oscillation at OUT B, but only when the TEC is at or very near Because the linear amplifier operates in a high gain configuration, zero current. it will be at either ground or VDD when significant current is flowing through the TEC. In this condition, the power dissipation The remedy for this potential minor instability is to add through the linear output FET will be capacitance from OUT B to ground. This may need to be deter- mined empirically, but a good starting point is 1.5 times the P =r ×I 2 (34) FET,LIN DS,ON TEC total C . This is the function of C12 in Figure 1. Note that GD while adding more CGD around Q3 and Q4 will help to ensure using either the rDS, ON for the NMOS or the PMOS depending stability, it could potentially increase instability in the zero current on the direction of the current flow. In the typical application dead band region, requiring additional capacitance from setup in Figure 2, if the TEC is cooling the target object, the OUT B to ground. PMOS is sourcing the current. If the TEC is heating the object, the NMOS will be sinking current. Table IV. Partial List of Capacitors and Key Specifications Value ((cid:7)F) ESR (m(cid:6)) Voltage Rating (V) Part Number Manufacturer Website 10 60 6.3 NSP100M6.3D2TR NIC Components www.niccomp.com 22* 35 8 ESRD220M08B Cornell Dubilier www.cornell-dubilier.com 22 35 8 NSP220M8D5TR NIC Components www.niccomp.com 22 35 8 EEFFD0K220R Panasonic www.maco.panasonic.co.jp 47 25 6.3 NSP470M6.3D2TR NIC Components www.niccomp.com 68 18 8 ESRD680M08B Cornell Dubilier www.cornell-dubilier.com 100 95 10 594D107X_010C2T Vishay www.vishay.com *Recommend capacitor in typical application circuit Figure 1. –16– REV. D

ADN8830 Although the FETs that drive OUT A alternate between Q1 and total current used by the ADN8830. The power dissipated from Q2 being on, they have an equivalent series resistance that is the device itself is equal to a weighted average of their r values. DS, ON P =V ×10mA (40) ( ) ADN8830 DD R =D×r + 1–D ×r (35) EQIV DS,P1 DS,N1 There are certainly other minor mechanisms for power dissipa- The resistive power loss from the PWM transistors is then tion in the circuit. However, a rough estimate of the total power dissipated can be found by summing the preceding power dissi- P =R ×I 2 (36) pation equations. Efficiency is then found by comparing the FET,PWM EQIV TEC power dissipated with the required output power to the load. There is also a power loss from the continuing charging and discharging of the gate capacitances on Q1 and Q2. The power P dissipated due to gate charge loss (P ) is Efficiency= P +LOPAD (41) GCL LOAD DISS,TOT P = 1C V 2f (37) where GCL 2 ISS DD CLK P =I ×V LOAD LOAD LOAD using the appropriate input capacitance (C ) for the NMOS ISS The measured efficiency of the system will likely be less than the and PMOS. Both transistors are switching, so P should be GCL calculated efficiency. Measuring the efficiency of the application calculated for each one and will be added to find the total power circuit is fairly simple but must be done in an exact manner to dissipated from the circuit. ensure the correct numbers are being measured. Using two high The series resistance of the inductor, R2 from Figure 14, will current, low impedance ammeters and two voltmeters, the cir- also exhibit a power dissipation equal to cuit should be set up as shown in Figure 15. P =R2×I 2 (38) R2 TEC POWER SUPPLY Core loss from the inductor arises as a result of nonidealities of the inductor. Although this is difficult to calculate explicitly, it VDD GND can be estimated as 80% of P at 1 MHz switching frequen- RLS cies and 50% of P at 100 kHz. Judging conservatively A RL P =0.8×P (39) V LOSS RL A Fcuinrraellnyt, tuhsee dp obwye trh dei sdseipvaicteed m buyl ttihpel iAedD bNy8 t8h3e0 s ius pepqluya vl otolt athgee. ADN8830 V LTOEACD Again, this exact equation is difficult to determine as we have already taken into account some of the current while finding the Figure 15.Measuring Efficiency of the ADN8830 Circuit gate charge loss. A reasonable estimate is to use 40 mA as the Table V. Recommended FETs for Linear Output Amplifier Part Number Type C (nF) Ext. C (nF) C (nF) r (m(cid:6)) I (A) Manufacturer GD GD SNUB DS, ON MAX FDW2520C* NMOS 0.17 18 6.0 Fairchild PMOS 0.15 2.2 3.3 35 4.5 Fairchild IRF7401 NMOS 0.5 22 8.7 International Rectifier IRF7233 PMOS 2.2 1.0 3.3 20 9.5 International Rectifier FDR6674A NMOS 0.23 9.5 11.5 Fairchild FDR840P PMOS 0.6 1.0 3.3 12 10 Fairchild *Recommend transistors in typical application circuit Figure 1. Table VI. Recommended FETs for PWM Output Amplifier Part Number Type C (nF) r (m(cid:6)) Continuous I (A) Manufacturer ISS DS,ON MAX FDW2520C* NMOS 1.33 18 6.0 Fairchild PMOS 1.33 35 4.5 Fairchild Si7904DN NMOS 1.0 30 5.3 Vishay Siliconix Si7401DN PMOS 3.5 17 7.3 Vishay Siliconix IRF7401 NMOS 1.6 22 8.7 International Rectifier IRF7404 PMOS 1.5 40 6.7 International Rectifier *Recommend transistors in typical application circuit Figure 1. REV. D –17–

ADN8830 The voltmeter to the TEC or output load should include the series POWER SUPPLY ammeter since the power delivered to the ammeter is considered part of the total output power. However, the voltmeter measuring the VDD GND voltage delivered to the ADN8830 circuit should not include the series ammeter from the power supply. This prevents a false supply voltage power measurement since we are interested only in the AVDD AGND PGND PVDD supply voltage power delivered to the ADN8830 circuit. Figures 16 and 17 show some efficiency measurements using the typical appli- SSENENCOSTIISTIOEIVNE SOEUCTTPIUOTN LTOOEARCD cation circuit shown in Figure1. 100 Figure 18.Using Star Connections to Minimize VSY = 3V Noise Pickup from Switched Output The low noise power and ground are referred to as AVDD and 80 AGND, with the output supply and ground paths labeled PVDD and PGND. These pins are labeled on the ADN8830 and should %) VSY = 5V Y ( 60 be connected appropriately. Both sets of external FETs should be NC connected to PVDD and PGND. All output filtering and PVDD E CI supply bypass capacitors should be connected to PGND. FI 40 F E All remaining connections to ground and power supply should be done through AVDD and AGND. A 4-layer board layout is rec- 20 ommended for best performance with split power and ground planes between the top and bottom layers. This provides the lowest impedance for both supply and ground points. Setting the 0 0 500 1,000 1,500 2,000 ADN8830 above the AGND plane will reduce the potential noise ITEC (mA) injection into the device. Figure 19 shows the top layer of the Figure 16.Efficiency with f = 1 MHz layout used for the ADN8830 evaluation boards, highlighting the CLK power and ground split planes. 100 VSY = 3V 80 VSY = 5V %) Y ( 60 C N E CI FI 40 F E 20 0 0 500 1,000 1,500 2,000 ITEC (mA) Figure 17.Efficiency with f = 200 kHz CLK Note that higher efficiency can be achieved using a lower supply voltage or a slower clock frequency. This is due to the fact that the dominant source of power dissipation at high clock frequencies is the gate charge loss on the PWM transistors. Figure 19.Top Layer Reference Layout for ADN8830 Layout Considerations Proper supply voltage bypassing should also be taken into consid- The two key considerations for laying out the board for the eration to minimize the ripple voltage on the power supply. A ADN8830 are to minimize both the series resistance in the output minimum bypass capacitance of 10 μF should be placed in close and the potential noise pickup in the precision input section. The proximity to each component connected to the power supply. This best way to accomplish both of these objectives is to divide the includes Pins 8 and 20 on the ADN8830 and both external PMOS layout into two sections, one for the output components and the transistors. An additional 0.1 μF capacitor should be placed in other for the remainder of the circuit. These sections should have parallel to each 10 μF capacitor to provide bypass for high fre- independent power supply and ground current paths that are each quency noise. Using a large bulk capacitor, 100 μF or greater, in connected together at a single point near the power supply. This is parallel with a low ESR capacitor where AVDD and PVDD con- used to minimize power supply and ground voltage bounce on the nect will further improve voltage supply ripple. This is covered in more sensitive input stages to the ADN8830 caused by the switch- more detail in the Power Supply Ripple section. ing of the PWM output. Such a layout technique is referred to as a “star” ground and supply connection. Figure 18 shows a block dia- gram of the concept. –18– REV. D

ADN8830 Power Supply Ripple A 10 mΩ resistor placed in series with the PVDD supply line creates a Minimizing ripple on the power supply voltage can be an impor- voltage drop proportional to the absolute value of the output current. tant consideration, particularly in signal source laser applications. The AD8601 is a CMOS amplifier that is configured as a com- If the laser diode is operated from the same supply rail as the TEC parator. As long as the voltage at its inverting input (V) exceeds S controller, ripple on the supply voltage could cause inadvertent the voltage set by the resistor divider at the noninverting input (V ), X modulation of the laser frequency. As most laser diodes are driven the gate of Q1 will remain at ground. This leaves Q1on, effectively from a 5 V supply, it is recommended the ADN8830 be operated connecting D1 to the positive rail and leaving the voltage on C1 at from a separate 3.3 V regulated supply unless higher TEC voltages V . Should enough current flow through R to drop V below V , DD S S X are required. Operation from 3.3 V also improves efficiency, thus Q1 will turn off and C1 will discharge through R2 down to a logic minimizing power dissipation. low to activate the ADN8830 shutdown. Once V returns to a S voltage greater than V , Q1 will turn back on and C1 will charge The power supply ripple is primarily a function of the supply by- X back to V through R1. The shutdown and reactivation time pass capacitance, also called bulk capacitance, and the inductor DD constants are approximately ripple current. Similar to the L-C filter at the PWM amplifier output, using more capacitance with low equivalent series resis- (cid:5) =C1×R1 SD (42) tance (ESR) will lower the supply ripple. A larger inductor value (cid:5) =C1×R1 will reduce the inductor ripple current, but this may not be ON The shutdown time constant should be a minimum of 10 clock practical in the application. A recommended approach is to use a cycles to ensure high current switching transients do not trigger a standard electrolytic capacitor in parallel with a low ESR capacitor. A surface-mount 220 μF electrolytic in parallel with a 22 μF poly- false activation. If powered from 5 V, the circuit shown will shut down the ADN8830 should PVDD deliver over 5 A for more than mer aluminum low ESR capacitor can occupy an approximate total 1 ms. After shutdown, the circuit will reactivate the ADN8830 in board area of only 0.94 square inches or 61 square millimeters. Using these capacitors along with a 4.7 μH inductor can yield a about 1 second. supply ripple of less than 5 mV. The voltage drop across R is found as S High frequency transient spikes may appear on the supply voltage I 2R R as well. This is due to the fast switching times on the PWM transis- V = OUT L S (43) tors and the sharp edges of their gate voltages. Although these RS ηVDD transient spikes can reach several tens of millivolts at their peak, where RL is the load resistance or resistance of the TEC and (cid:8) is they typically last for less than 20 ns and have a resonance greater the efficiency of the system. An estimate of efficiency can be calculated than 100 MHz. Additional bulk capacitance will not appreciably either from the Calculating Power Dissipation and Efficiency section affect the level of these spikes as such capacitance is not reactive at or from Figures 16 and 17. A reasonable approximation is (cid:8) = these frequencies. Adding 0.01 μF ceramic capacitors on the sup- 0.85. Although the exact resistance of a TEC varies with tempera- ply line near the PWM PMOS transistor can reduce this switching ture, an estimation can be made by dividing the maximum voltage noise. Inserting an RF inductor with a High-Q around 100 MHz in rating of the TEC by its maximum current rating. series with PVDD will also block this noise from traveling back to In addition to providing protection against a short at the output, the power supply. this circuit will also protect the FETs against shoot-through current. Setting Maximum Output Current and Short-Circuit Shoot-through will not occur when using the recommended Protection transistors and additional capacitance shown in Tables V and VI. Although the maximum output voltage can be programmed However, if different transistors are used where their shoot- through VLIM to protect the TEC from overvoltage damage, through potential is unknown, implementing the short-circuit the user may wish to protect the ADN8830 circuit from a possible protection circuit will unconditionally protect these transistors. short circuit at the output. Such a short could quickly damage the To set a maximum output current limit, use the circuit in Figure external FETs or even the power supply since they would attempt 21. This circuit can share the 10 mΩ power supply shunt resistor to drive excessive current. Figure 20 shows a simple modification as the short-circuit protection circuit to sense the output current. that will protect the system from an output short circuit. In normal operation Q1 is on, pulling the ADN8830 VLIM pin down to the voltage set by VLIMIT. This sets the maximum out- TO VS RS PVDD AVDD put voltage limit as described in the Setting the Maximum TEC FETS 10m(cid:6) Voltage and Current section. AND DECOUPLING PVDD CAPS R3 Q1 R1 TO VSY RS PVDD AVDD 1k(cid:6) FDV304P 1M(cid:6) FETS 10m(cid:6) OR EQUIVALENT AND R1 100kR(cid:6)4 VX AD86011kR(cid:6)2 MA11OD6R1CT-ND C1(cid:7)1F SD DECCOAUPPSLIN1G78R(cid:6)P3VDD 3.48k(cid:6) QFOD1RV301N C1n1F R1.247kT (cid:6)VOLIM EQUIVALENT AD8605 EQUIVALENT R4 100k(cid:6) VX DENOTES DENOTES AGND PGND VLIMIT (0V TO 1.5V) Figure 20.Implementing Output Short-Circuit Protection DENOTES DENOTES AGND PGND Figure 21.Setting a Maximum Output Current Limit REV. D –19–

ADN8830 5V IOUTA ADT70 IOUTB +INOA TO THERM_IN R3 = 1V @ 25(cid:4)C 82.5(cid:6) OUTOA 25mV/(cid:4)C +INIA RGA R3 4.99k(cid:6) IANMSPT 82.5(cid:6) RGB –INIA RTD R3 1k(cid:6) 1k(cid:6) GND AGND OUTIA –INOA SENSE 1k(cid:6) 5.11k(cid:6) NOTE: ADDITIONAL PINS OMITTED FOR CLARITY Figure 22.Using an RTD for Temperature Feedback to the ADN8830 If the voltage at VSY drops below VX, Q1 is turned off and the RS AVDD AVDD AVDD cVvaoLllctIauMglae pt eaindc r wforsiolslm bth eEe s qeoutu attotpi ou1nt.s5 4 tVo3, . 0e fVfe.c tTivheely v soeltttaingeg dthivei dmearx fiomru VmX is TETOC 10mIL(cid:6) TOOUATV DBD VHI 200k(cid:6) 3.48kR(cid:6)1 TVOLIM R2 Design Example 5 1nF 300k(cid:6) 1.47k(cid:6) Q1,Q2 A maximum output current limit needs to be set at 1.5 A for a 8 FDG6303N TEC with a maximum voltage rating of 2.5 V. The ADN8830 is AD626 VX AD8602 EQUIVOAR- powered from 5 V. The TEC resistance is estimated at 1.67 Ω and LENT efficiency at 85%. Using Equation 43, the voltage drop across 300k(cid:6) R will be 8.8 mV when 1.5 A is delivered to the TEC. The trip S voltage V is set to 4.991 V with R3 = 178 Ω and R4 = 100 kΩ X as shown in Figure 21. To set the output voltage limit to 2.5 V, the voltage at VLIMIT should be set to 0.875 V according to VRTOEF VLO 200k(cid:6) (0VV TLOIM 1I.T5V) Equation 17. The C1 capacitor is added to smooth the voltage transitions at Figure 23.High Accuracy Output Current Limit VLIM. Once an overcurrent condition is detected, the output The upper and lower trip point voltages can be set independently, voltage will turn down to 0 V within 30 ms. allowing different maximum output current limits depending on For a more exact measurement of the output current, place a the direction of the current. The resistor divider for VHI and sense resistor in series with the output load, as shown in Figure23. VLO is tapped to VREF to maintain window accuracy with any The AD626 instrumentation amplifier is set for a gain of 100 changes in VREF. Using the values from Figure 23 with a 5 V with a reference voltage of 2.47 V from VREF. The output of supply, the output current will not exceed 1.5 A in either direction. the AD626 is equal to 100 × RS × IL and is fed to the AD8602, Adding the current sensing resistor will slightly reduce efficiency. which is set up as a window comparator. With VX greater than The power dissipated by this resistor is D × ITEC2 × RS if the VLO but less than VHI, VLIM will be pulled down to the volt- TEC is heating, or (1–D) × ITEC2 × R if the TEC is cooling. S age at VLIMIT. Should VX fall outside the voltage window, Include this when calculating efficiency as described in the VLIM will be pulled to 1.5 V as in Figure 21. The trip points Calculating Power Dissipation and Efficiency section. should be set according to VHI =VREF+100×R I S LIMIT+ (44) VLO=VREF–100×R I S LIMIT– –20– REV. D

ADN8830 Using an RTD for Temperature Sensing PVDD OUT A The ADN8830 can be used with a resistive temperature device (RTD) as the temperature feedback sensor. The resistance of an P1 Q1 RTD is linear with respect to temperature, offering an advan- L1 RL OUT B tage over thermistors that have an exponential relationship to temperature. A constant current applied through an RTD will N1 Q2 C1 Q3 N2 yield a voltage proportional to temperature. However, this volt- age could be on the order of only 0.5 mV/°C, thus requiring the use of additional amplification to achieve a usable signal level. NO CONNECTION TO P2 REQUIRED The ADT70 from Analog Devices can be used to bias and amplify Figure 24.Using the ADN8830 to Drive a Heating Element the voltage across an RTD, which can then be fed directly to the Current is delivered from the PWM amplifier through Q3 when THERMIN pin on the ADN8830 to provide temperature the voltage at THERMIN is lower than TEMPSET. If the object feedback for the TEC controller. The ADT70 uses a 0.9 mA temperature is greater than the target temperature, Q3 will turn current source to drive the RTD and an instrumentation ampli- off and the current through the load goes to zero, allowing the fier with adjustable gain to boost the RTD voltage. Application object to cool back toward the ambient temperature. As the notes and typical schematics for this device can be found in the target temperature is approached, a steady output current should ADT70 Data Sheet. be reached. Naturally, a proper compensation network must be Most RTDs have a positive temperature coefficient, also called found to ensure stability and adequate temperature settling time. tempco, as opposed to thermistors, which have a negative tempco. The P2 output from the ADN8830 should be left unconnected. For the OUT A output to drive the TEC– input as shown in Suggested Pad Layout for CP-32 Package Figure 1, the signal from an RTD must be conditioned to create Figure 25 shows the dimensions for the PC board pad layout for a negative tempco. This can be easily done using an inverting the ADN8830, which is a 5 (cid:7) 5, 32-lead lead frame chipscale amplifier. Alternately, OUT A can be connected to drive TEC+ package. This package has a metallic heat slug that should be with OUT B driving TEC– with a positive tempco at THERMIN. soldered to a copper pad on the PC board. Although the pack- This is highlighted in the Output Driver Amplifiers section. age slug is electrically connected to the substrate of the IC, the For the ADN8830, proper operation care should be taken copper pad should be left electrically floating. This prevents to ensure the voltage at THERMIN remains within 0.4 V potential noise injection into the substrate while maintaining and 2.0 V. Using a 1 kΩ RTD with the ADT70 will yield a good thermal conduction to the PC board. THERMIN voltage of 0.9V at 25°C. Using the application circuit shown in Figure22 will provide a nominal output 0.69 voltage of 1.0 V at 25°C and a total gain of 66.7 mV/Ω. (0.0272) Using an RTD with a temperature coefficient of 0.375 Ω/°C will give a THERMIN voltage swing from 1.5V at 5°C to 0.5 V at 45°C, well within the input range of the ADN8830. 0.10 (0.0039) 0.28 (0.0110) Using a Resistive Load as a Heating Element The ADN8830 can be used in applications that do not neces- 5.36 3.78 (0.2110) (0.1488) sarily drive a TEC but require only a high current output into a load resistance. Such applications generally only require heating 0.50 above ambient temperature and simply use the power dissipated (0.0197) by the load element to accomplish this. Because the power PACKAGE dissipated by such an element is proportional to the square of 3.68 OUTLINE the output voltage, the ADN8830 application circuit must be (0.1449) modified. Figure 24 shows the preferred method for driving a CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS heating element load. (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN THERMAL PAD SHOULD BE SOLDERED TO AN ELECTRICALLY FLOATING PAD ON THE PC BOARD Figure 25.Suggested PC Board Layout for CP-32 Pad Landing REV. D –21–

ADN8830 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.25 PAD 3.10 SQ 2.95 17 8 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A Figure 26. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADN8830ACPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7 ADN8830ACPZ-REEL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7 ADN8830ACPZ-REEL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7 1 Z = RoHS Compliant Part. REVISION HISTORY 3/12—Rev. C to Rev. D 8/03—Rev. A to Rev. B Added EPAD Notation ..................................................................... 3 Updated Ordering Guide ................................................................. 3 Updated Outline Dimensions ........................................................ 22 Updated Thermal Setup Section ..................................................... 8 Changes to Ordering Guide ........................................................... 22 Updated Outline Dimensions ........................................................ 23 11/03—Rev. B to Rev. C 2/03—Rev. 0 to Rev. A Changes to Ordering Guide ............................................................. 3 Renumbered Figures .......................................................... Universal Deleted Figure 24 ............................................................................ 21 Changes to Thermistor Setup Section ............................................ 8 Deleted Boosting the Output Voltage section ............................. 22 Changes to Figure 14 ...................................................................... 15 Deleted Figure 26 ............................................................................ 22 Changes to Figure 23 ...................................................................... 20 Deleted Equations 45, 46 and 47 ................................................... 22 Changes to Figure 25 ...................................................................... 21 Updated Outline Dimensions ........................................................ 23 Updated Outline Dimensions ........................................................ 23 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02793-0-3/12(B) –22– REV. D