Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663 FEATURES FUNCTIONAL BLOCK DIAGRAM ±15 kV ESD protection on output pins VCC 600 Mbps (300 MHz) switching rates ADN4663 Flow-through pinout simplifies PCB layout DOUT1+ 300 ps typical differential skew DIN1 DOUT1– 700 ps maximum differential skew 1.5 ns maximum propagation delay DOUT2+ 3.3 V power supply DIN2 DOUT2– ±355 mV differential signaling LInotwer poopwerearb dleis wsipitaht eioxnis: t2in3g m 5W V tLyVpDicSa rle ceivers GND 07927-001 Figure 1. Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range (−40°C to +85°C) Available in surface-mount (SOIC) package APPLICATIONS Backplane data transmission Cable data transmission Clock distribution GENERAL DESCRIPTION The ADN4663 is a dual, CMOS, low voltage differential twisted-pair cable. The transmitted signal develops a differential signaling (LVDS) line driver offering data rates of over voltage of typically ±355 mV across a termination resistor at the 600 Mbps (300 MHz), and ultralow power consumption. receiving end, and this is converted back to a TTL/CMOS logic It features a flow-through pinout for easy PCB layout and level by a line receiver. separation of input and output signals. The ADN4663 and a companion receiver offer a new solution The device accepts low voltage TTL/CMOS logic signals and to high speed point-to-point data transmission, and a low converts them to a differential current output of typically power alternative to emitter-coupled logic (ECL) or positive ±3.1 mA for driving a transmission medium such as a emitter-coupled logic (PECL). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

ADN4663 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions ..............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 11 Revision History ............................................................................... 2 Applications Information .......................................................... 11 Specifications ..................................................................................... 3 Outline Dimensions ....................................................................... 12 AC Characteristics ........................................................................ 4 Ordering Guide .......................................................................... 12 Absolute Maximum Ratings ............................................................ 6 REVISION HISTORY 1/09—Revision 0: Initial Version Rev. 0 | Page 2 of 12

ADN4663 SPECIFICATIONS V = 3.0 V to 3.6 V; R = 100 Ω; C = 15 pF to GND; all specifications T to T , unless otherwise noted. CC L L MIN MAX Table 1. Parameter1, 2 Symbol Min Typ Max Unit Test Conditions LVDS OUTPUTS (D , D ) OUTx+ OUTx− Differential Output Voltage V 250 355 450 mV See Figure 2 and Figure 4 OD Change in Magnitude of V for ΔV 1 35 |mV| See Figure 2 and Figure 4 OD OD Complementary Output States Offset Voltage V 1.125 1.2 1.375 V See Figure 2 and Figure 4 OS Change in Magnitude of V for ΔV 3 25 |mV| See Figure 2 and Figure 4 OS OS Complementary Output States Output High Voltage V 1.4 1.6 V See Figure 2 and Figure 4 OH Output Low Voltage V 0.90 1.1 V See Figure 2 and Figure 4 OL INPUTS (D , D ) IN1 IN2 Input High Voltage V 2.0 V V IH CC Input Low Voltage V GND 0.8 V IL Input High Current I −10 ±2 +10 μA V = 3.3 V or 2.4 V IH IN Input Low Current I −10 ±1 +10 μA V = GND or 0.5 V IL IN Input Clamp Voltage V −1.5 −0.6 V I = −18 mA CL CL LVDS OUTPUT PROTECTION (D , D ) OUTx+ OUTx− Output Short-Circuit Current3 I −5.7 −8.0 mA D = V , D = 0 V or D = GND, D = 0 V OS INx CC OUTx+ INx OUTx− LVDS OUTPUT LEAKAGE (D , D ) OUTx+ OUTx− Power-Off Leakage I −10 ±1 +10 μA V = V or GND, V = 0 V OFF OUT CC CC POWER SUPPLY Supply Current, Unloaded I 8 14 mA No load, D = V or GND CC INx CC Supply Current, Loaded I 10 20 mA D = V or GND CCL INx CC ESD PROTECTION D , D Pins ±15 kV Human body model OUTx+ OUTx− All Pins Except D , D ±4 kV Human body model OUTx+ OUTx− 1 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS. 2 The ADN4663 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is 90 Ω to 110 Ω. 3 Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only. Rev. 0 | Page 3 of 12

ADN4663 AC CHARACTERISTICS V = 3.0 V to 3.6 V; R = 100 Ω; C 1 = 15 pF to GND; all specifications T to T , unless otherwise noted. CC L L MIN MAX Table 2. Parameter2 Symbol Min Typ Max Unit Conditions/Comments3, 4 Differential Propagation Delay High to Low t 0.3 0.8 1.5 ns See Figure 3 and Figure 4 PHLD Differential Propagation Delay Low to High t 0.3 1.1 1.5 ns See Figure 3 and Figure 4 PLHD Differential Pulse Skew |t − t |5 t 0 0.3 0.7 ns See Figure 3 and Figure 4 PHLD PLHD SKD1 Channel-to-Channel Skew6 t 0 0.4 0.8 ns See Figure 3 and Figure 4 SKD2 Differential Part-to-Part Skew7 t 0 1.0 ns See Figure 3 and Figure 4 SKD3 Differential Part-to-Part Skew8 t 0 1.2 ns See Figure 3 and Figure 4 SKD4 Rise Time t 0.2 0.5 1.0 ns See Figure 3 and Figure 4 TLH Fall Time t 0.2 0.5 1.0 ns See Figure 3 and Figure 4 THL Maximum Operating Frequency9 f 350 MHz See Figure 3 MAX 1 CL includes probe and jig capacitance. 2 AC parameters are guaranteed by design and characterization. 3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns. 4 All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND. 5 tSKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 6 tSKD2 is the differential channel-to-channel skew of any event on the same device. 7 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. 8 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay. 9 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching. Rev. 0 | Page 4 of 12

ADN4663 Test Circuits and Timing Diagrams DOUTx+ VCC VCC RL/2 DINx VOS VOD V V RL/2 DOUTx– 07927-002 Figure 2. Test Circuit for Driver VOD and VOS VCC DOUTx+ CL SIGNAL DINx RL GENERATOR 50Ω DOUTx– CL CL INCLUDES LOAD AND TEST JIG CAPACITANCE. 07927-003 Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency 3V DINx 1.5V 1.5V 0V tPLHD tPHLD DOUTx– VOH 0V (DIFFERENTIAL)VOD 0V DOUTx+ VOL 80% 80% VDIFF 0V VDIFF = DOUT+ – DOUT– 0V 20% 20% tTHL tTHL 07927-004 Figure 4. Driver Propagation Delay and Transition Time Waveforms Rev. 0 | Page 5 of 12

ADN4663 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. All voltages are relative to Stresses above those listed under Absolute Maximum Ratings A their respective ground. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 3. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute VCC to GND −0.3 V to +4 V maximum rating conditions for extended periods may affect Input Voltage (DINx) to GND −0.3 V to VCC + 0.3 V device reliability. Output Voltage (D , D ) to GND −0.3 V to V + 0.3 V OUTx+ OUTx− CC Short-Circuit Duration (D , D ) to GND Continuous OUTx+ OUTx− Operating Temperature Range ESD CAUTION Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J Power Dissipation (T max − T )/θ J A JA SOIC Package θ Thermal Impedance 149.5°C/W JA Reflow Soldering Peak Temperature Pb-Free 260°C ± 5°C Rev. 0 | Page 6 of 12

ADN4663 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCC 1 8 DOUT1– DIN1 2 ADN4663 7 DOUT1+ TOP VIEW GDNIND2 34 (Not to Scale) 65 DDOOUUTT22+– 07927-005 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 V Power Supply Input. The part can be operated from 3.0 V to 3.6 V, and the supply should be decoupled with a CC 10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND. 2 D Driver Channel 1 Logic Input. IN1 3 D Driver Channel 2 Logic Input. IN2 4 GND Ground reference point for all circuitry on the part. 5 D Channel 2 Inverting Output Current Driver. When D is high, current flows into D . When D is low, current OUT2− IN2 OUT2− IN2 flows out of D . OUT2− 6 D Channel 2 Noninverting Output Current Driver. When D is high, current flows out of D . When D is low, OUT2+ IN2 OUT2+ IN2 current flows into D . OUT2+ 7 D Channel 1 Noninverting Output Current Driver. When D is high, current flows out of D . When D is low, OUT1+ IN1 OUT1+ IN1 current flows into D . OUT1+ 8 D Channel 1 Inverting Output Current Driver. When D is high, current flows into D . When D is low, current OUT1− IN1 OUT1− IN1 flows out of D . OUT1− Rev. 0 | Page 7 of 12

ADN4663 TYPICAL PERFORMANCE CHARACTERISTICS 1.415 325.0 TRAL == 2150°0CΩ mV) TRAL == 2150°0CΩ (V)OH E, V (OD 324.8 V G AGE, 1.414 OLTA 324.6 T V H VOL TPUT G U 324.4 PUT HI 1.413 TIAL O T N OU RE 324.2 E F F DI 1.412 324.0 3.0 3.1 POWE3R. 2SUPPLY3 V.3OLTAGE3,. V4CC (V) 3.5 3.6 07927-006 3.0 3.1 POWE3R. 2SUPPLY3 V.3OLTAGE3, .V4CC (V) 3.5 3.6 07927-009 Figure 6. Output High Voltage vs. Power Supply Voltage Figure 9. Differential Output Voltage vs. Power Supply Voltage 1.090 500 TRAL == 2150°0CΩ mV) TVAC C= =2 53°.3CV V (V)OL GE, V (OD 450 AGE, 1.089 OLTA 400 T V W VOL TPUT UT LO 1.088 AL OU 350 P TI T N OU RE 300 E F F DI 1.087 250 3.0 3.1 POWE3R. 2SUPPLY3 V.3OLTAGE3,. 4VCC (V) 3.5 3.6 07927-007 90 100 L1O10AD RES1IS2T0OR, RL 1(Ω30) 140 150 07927-010 Figure 7. Output Low Voltage vs. Power Supply Voltage Figure 10. Differential Output Voltage vs. Load Resistor –3.9 1.252 VIN = GNDTA O =R 2 V5C°CC TRAL == 2150°0CΩ A) VOUT = 0V m (OS mV) NT, I –4.0 V (OS 1.251 RE E, R G U A C T UIT VOL CIRC –4.1 SET 1.250 ORT- OFF H S –4.2 1.249 3.0 3.1 POWE3R. 2SUPPLY3 V.3OLTAGE3, .V4CC (V) 3.5 3.6 07927-008 3.0 3.1 POWER3. 2SUPPLY 3V.3OLTAGE3, .V4CC (V) 3.5 3.6 07927-011 Figure 8. Output Short-Circuit Current vs. Power Supply Voltage Figure 11. Offset Voltage vs. Power Supply Voltage Rev. 0 | Page 8 of 12

ADN4663 1200 mA) 1179 TCVVACILN C === =2 10 553V°p.3C FTVO 3.3V AY (ns) RL = 100Ω PERCTf LAD = ==R 1 I12VM55EpH°RCFz (C RL = 100Ω PER DRIVER EL C D ENT, I 15 BOTH CHANNELS SWITCHING TION 1100 tPHLD R A CUR 13 PAG tPLHD Y O PL 11 ONE CHANNEL SWITCHING PR R SUP 9 NTIAL 1000 E E W R O E P 7 FF DI 5 900 0.01 0.1 SWITCHIN1G FREQUE1N0CY (MHz) 100 1k 07927-012 3.0 3.1 POWE3R. 2SUPPLY3 V.3OLTAGE3,. 4VCC (V) 3.5 3.6 07927-015 Figure 12. Power Supply Current vs. Switching Frequency Figure 15. Differential Propagation Delay vs. Power Supply Voltage 12.5 1200 TA = 25°C VCC = 3.3V f = 1MHz s) f = 1MHz mA) 12.0 CVILN == 105Vp FTO 3.3V AY (n CRLL == 1150p0ΩF PER DRIVER (CC RL = 100Ω PER DRIVER DEL tPLHD NT, I ON 1100 E 11.5 TI R A R G U A C P PLY 11.0 PRO tPHLD WER SUP 10.5 RENTIAL 1000 O E P FF DI 10.0 900 3.0 3.1 POWE3R. 2SUPPLY3 V.3OLTAGE3, .4VCC (V) 3.5 3.6 07927-013 –40 –20 AM0BIENT TE20MPERAT40URE, TA6 (0°C) 80 100 07927-016 Figure 13. Power Supply Current vs. Power Supply Voltage Figure 16. Differential Propagation Delay vs. Ambient Temperature 15 100 VCC = 3.3V TA = 25°C f = 1MHz f = 1MHz A) CL = 15pF CL = 15pF PLY CURRENT, I (mCC 111234 VRILN == 100V0 ΩTO P E3VR DRIVER TIAL SKEW, t (ps)SKD1 468000 RL = 100Ω PER DRIVER P N U E S R OWER 11 DIFFE 20 P 10 0 –40 –15 TE1M0PERATURE3 5(°C) 60 85 07927-014 3.0 3.1 POWE3R. 2SUPPLY3 V.3OLTAGE3,. 4VCC (V) 3.5 3.6 07927-017 Figure 14. Power Supply Current vs. Ambient Temperature Figure 17. Differential Skew vs. Power Supply Voltage Rev. 0 | Page 9 of 12

ADN4663 50 400 VCC = 3.3V VCC = 3.3V f = 1MHz f = 1MHz CL = 15pF CL = 15pF s) 40 RL = 100Ω PER DRIVER RL = 100Ω PER DRIVER p (D1 s) 380 K p W, tS 30 ME ( tTLH E TI NTIAL SK 20 NSITION 360 tTHL E A R R E T F 340 DIF 10 0 320 –40 –20 AM0BIENT TE20MPERAT40URE, TA6 (0°C) 80 100 07927-018 –40 –20 AM0BIENT TE20MPERAT40URE, TA6 (0°C) 80 100 07927-020 Figure 18. Differential Skew vs. Ambient Temperature Figure 20. Transition Time vs. Ambient Temperature 400 TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 380 ps) tTLH E ( M TI TION 360 tTHL SI N A R T 340 320 3.0 3.1 POWE3R. 2SUPPLY3 V.3OLTAGE3,. 4VCC (V) 3.5 3.6 07927-019 Figure 19. Transition Time vs. Power Supply Voltage Rev. 0 | Page 10 of 12

ADN4663 THEORY OF OPERATION The ADN4663 is a dual line driver for low voltage differential A current mode device simply reverses a constant current signaling. It takes a single-ended 3 V logic signal and converts between its two outputs, with no significant overlap currents. it to a differential current output. The data can then be transmitted This is similar to emitter-coupled logic (ECL) and positive for considerable distances, over media such as a twisted-pair cable emitter-coupled logic (PECL), but without the high quiescent or PCB backplane, to an LVDS receiver, where it develops a voltage current of ECL and PECL. across a terminating resistor, R. This resistor is chosen to match T the characteristic impedance of the medium, typically around APPLICATIONS INFORMATION 100 Ω. The differential voltage is detected by the receiver and Figure 21 shows a typical application for point-to-point data converted back into a single-ended logic signal. transmission using the ADN4663 as the driver and a LVDS When D is high (Logic 1), current flows out of the D pin INx OUTx+ receiver. (current source) through R and back into the D pin (current T OUTx− +3.3V +3.3V sink). At the receiver, this current develops a positive differential 0.1µF +10µF + TANTALUM voltage across R (with respect to the inverting input) and results T VCC VCC in a Logic 1 at the receiver output. When D is low, D INx OUTx+ sinks current and DOUTx− sources current; a negative differential ADN4663 DOUTx+ DIN+ LVDS RECEIVER voltage across RT results in a Logic 0 at the receiver output. RT The output drive current is between ±2.5 mA and ±4.5 mA DINx DO1U0T0xΩ– DIN– DOUT (atcyrpoiscsa al l1y0 ±03 Ω.5 5te mrmAi)n, adtieovne lroepsiinstgo br.e Ttwhee ernec ±e2iv5e0d m voVlt aagned i±s 4ce5n0t mereVd GND GND 07927-021 Figure 21. Typical Application Circuit around the receiver offset of 1.2 V. Therefore, the noninverting receiver input is typically (1.2 V + [355 mV/2]) = 1.377 V, and the inverting receiver input is (1.2 V − [355 mV/2]) = 1.023 V for Logic 1. For Logic 0, the inverting and noninverting output voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across R is T twice the differential voltage. Current mode drivers offer considerable advantages over voltage mode drivers such as RS-422 drivers. The operating current remains fairly constant with increased switching frequency, whereas that of voltage mode drivers increase exponentially in most cases. This is caused by the overlap as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. Rev. 0 | Page 11 of 12

ADN4663 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 0.25 (0.0098) 1.35 (0.0532) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 SEATING 0.31 (0.0122) 0.25 (0.0098) 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANTTO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS A (RINEFPEARREENNCTEH EOSNELSY)AANRDE ARROEU NNODETDA-POPFRFO MPIRLLIAIMTEE TFEORR EUQSUEI VINA LDEENSTIGS NF.OR 012407- Figure 22. 8-Lead Standard Small Outline Package [SOIC(N)] (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option ADN4663BRZ1 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC-N] R-8 ADN4663BRZ-REEL71 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC-N] R-8 1 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07927-0-1/09(0) Rev. 0 | Page 12 of 12

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADN4663BRZ ADN4663BRZ-REEL7