±15 kV ESD Protected, Slew Rate Limited, 5 V, RS-485 Transceiver ADM483E FEATURES FUNCTIONAL BLOCK DIAGRAM ±15 kV ESD protection ADM483E 250 kbps data rate Reduced slew rate for low EM interference RO R Single 5 V ± 10% supply RE B −7 V to +12 V bus common-mode range DE A Up to 32 nodes on the bus DI D RShecoeritv-ceirr coupiet np-rcoitrecuctitio, fna il-safe design 06012-001 Figure 1. 36 μA supply current 0.1 μA shutdown current APPLICATIONS Low power RS-485 systems Electrically harsh environments EMI sensitive applications DTE-DCE interface Packet switching Local area networks GENERAL DESCRIPTION The ADM483E is a 5 V, low power data transceiver with ±15 kV Drivers are short-circuit current-limited and are protected ESD protection suitable for half-duplex communication on against excessive power dissipation by thermal shutdown multipoint bus transmission lines. The ADM483E is designed circuitry that places their outputs into a high impedance state. for balanced data transmission and complies with TIA/EIA The receiver input has a fail-safe feature that guarantees a logic Standards RS-485 and RS-422, which allow up to 32 transceivers high output if the input is open circuit. on a bus. The ADM483E is fully specified over the industrial temperature The ADM483E has a low current shutdown mode in which it ranges and is available in 8-lead SOIC_N packages. consumes only 0.1 μA. Because only one driver is enabled at any time, the output of a disabled or power-down driver is three-stated to avoid overloading the bus. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1997–2007 Analog Devices, Inc. All rights reserved.

ADM483E TABLE OF CONTENTS Features..............................................................................................1 Test Circuits and Switching Characteristics...................................9 Applications.......................................................................................1 General Information......................................................................11 Functional Block Diagram..............................................................1 ESD Transient Protection Scheme...........................................11 General Description.........................................................................1 ESD Testing.................................................................................12 Revision History...............................................................................2 Applications Information..............................................................13 Specifications.....................................................................................3 Differential Data Transmission................................................13 Timing Specifications..................................................................4 Cable and Data Rate...................................................................13 Absolute Maximum Ratings............................................................5 Outline Dimensions.......................................................................14 ESD Caution..................................................................................5 Ordering Guide..........................................................................14 Pin Configuration and Function Descriptions.............................6 Typical Performance Characteristics.............................................7 REVISION HISTORY 12/07—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Features .........................................................................1 Changes to General Description....................................................1 Changes to Table 1............................................................................3 Changes to Table 2............................................................................4 Changes to Table 3............................................................................5 Changes to Table 5............................................................................6 Changes to Typical Performance Characteristics Section...........7 Changes to Test Circuits and Switching Characteristics Section...9 Changes to General Information Section....................................11 Updated Outline Dimensions.......................................................14 Changes to Ordering Guide..........................................................14 1/97—Revision 0: Initial Version Rev. A | Page 2 of 16

ADM483E SPECIFICATIONS V = 5 V ± 10%. All specifications T to T , unless otherwise noted. CC MIN MAX Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Differential Output Voltage, V 5.0 V V = 5.25 V; R = ∞, see Figure 15 OD CC 2.0 5.0 V R = 50 Ω (RS-422), see Figure 15 1.5 5.0 V R = 27 Ω (RS-485), see Figure 15 1.5 5.0 V V = –7 V to +12 V IN Δ|V | for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 15 OD Common-Mode Output Voltage, V 3 V R = 27 Ω or 50 Ω, see Figure 15 OC Δ|V | for Complementary Output States 0.2 V R = 27 Ω or 50 Ω OC Output Short-Circuit Current (V = High) 250 mA –7 V ≤ V ≤ +12 V OUT O Output Short-Circuit Current (V = Low) 250 mA –7 V ≤ V ≤ +12 V OUT O CMOS Input Logic Threshold Low, V 1.4 0.8 V INL CMOS Input Logic Threshold High, V 2.0 1.4 V INH Logic Input Current (DE, DI) ±1.0 μA RECEIVER Differential Input Threshold Voltage, V −0.2 +0.2 V −7 V ≤ V ≤ +12 V TH CM Input Voltage Hysteresis, ΔV 70 mV V = 0 V TH CM Input Resistance 12 kΩ −7 V ≤ V ≤ +12 V CM Input Current (A, B) 1 mA V = 12 V IN −0.8 mA V = –7 V IN Logic Enable Input Current (RE) ±1 μA CMOS Output Voltage Low, V 0.4 V I = 4.0 mA OL OUT CMOS Output Voltage High, V 4.0 V I = −4.0 mA OH OUT Short-Circuit Output Current 7 85 mA V = GND or V OUT CC Three-State Output Leakage Current ±2.0 μA 0.4 V ≤ V ≤ 2.4 V OUT POWER SUPPLY CURRENT Outputs unloaded, receivers enabled I 36 120 μA DE = 0 V (disabled), RE = 0 V CC 270 360 μA DE = 5 V (enabled), RE = 0 V Supply Current in Shutdown 0.1 10 μA DE = 0 V, RE = V CC ESD IMMUNITY ESD Protection ±15 kV HBM air discharge; Pin A, Pin B Rev. A | Page 3 of 16

ADM483E TIMING SPECIFICATIONS V = 5 V ± 10%. All specifications T to T , unless otherwise noted. CC MIN MAX Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DRIVER Propagation Delay Input to Output (t , t ) 250 2000 ns R Diff = 54 Ω, C = C = 100 pF, see Figure 16 and PLH PHL L L1 L2 Figure 17 Driver Output to Output (t ) 100 800 ns R Diff = 54 Ω, C = C = 100 pF, see Figure 16 and SKEW L L1 L2 Figure 17 Driver Rise/Fall Time (t, t) 250 2000 ns R Diff = 54 Ω, C = C = 100 pF, see Figure 16 and R F L L1 L2 Figure 17 Driver Enable to Output Valid 250 2000 ns R = 500 Ω, C = 100 pF, see Figure 18 and Figure 19 L L Driver Disable Timing 300 3000 ns R = 500 Ω, C = 15 pF, see Figure 18 and Figure 19 L L RECEIVER Propagation Delay Input to Output (t , t ) 250 2000 ns C = 15 pF, see Figure 20 PLH PHL L Skew (|t – t |) 200 ns PLH PHL Receiver Enable (t ) 10 50 ns R = 1 kΩ, C = 15 pF, see Figure 22 EN1 L L Receiver Disable (t ) 10 50 ns R = 1 kΩ, C = 15 pF, see Figure 22 EN2 L L SHUTDOWN Time to Shutdown 50 200 3000 ns Driver Enable from Shutdown 5000 ns R = 500 Ω, C = 100 pF, see Figure 18 and Figure 19 L L Receiver Enable from Shutdown 5000 ns R = 1 kΩ, C = 15 pF, see Figure 22 L L Rev. A | Page 4 of 16

ADM483E ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational VCC to GND −0.5 V to +6 V section of this specification is not implied. Exposure to absolute Digital I/O Voltage (DE, RE) −0.5 V to (VCC + 0.5 V) maximum rating conditions for extended periods may affect Driver Input Voltage (DI) −0.5 V to (VCC + 0.5 V) device reliability. Receiver Output Voltage (RO) −0.5 V to (V + 0.5 V) CC Driver Output/Receiver Input Voltage −9 V to +14 V (Pin A, Pin B) ESD CAUTION ESD Rating: Air (Human Body Model) ±15 kV (Pin A, Pin B) Power Dissipation 8-Lead SOIC_N 470 mW θ , Thermal Impedance 110°C/W JA Operating Temperature Range Industrial (A Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Rev. A | Page 5 of 16

ADM483E PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RO 1 8 VCC RE 2 ADM483E 7 B DDEI 34 (NToOt Pto V SIEcWale) 65 AGND 06012-002 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 RO Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low. 2 RE Receiver Output Enable. A low level enables the receiver output, RO. A high level places the receiver output in a high impedance state. 3 DE Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places the driver differential outputs in a high impedance state. 4 DI Driver Input. When the driver is enabled, a logic low on DI forces A low and B high. A logic high on DI forces A high and B low. 5 GND Ground Connection, 0 V. 6 A Noninverting Receiver Input A/Driver Output A. 7 B Inverting Receiver Input B/Driver Output B. 8 V Power Supply, 5 V ± 10%. CC Table 5. Selection Table Part No. Duplex Data Rate (kbps) Low Power Shutdown Tx/Rx Enable I (μA) No. of Tx/Rx on Bus ESD kV CC ADM483E Half 250 Yes Yes 36 32 ±15 Rev. A | Page 6 of 16

ADM483E TYPICAL PERFORMANCE CHARACTERISTICS 50 0.9 45 0.8 40 V) 0.7 mA) 35 GE ( 0.6 URRENT ( 2350 W VOLTA 0.5 C O 0.4 UT 20 T L UTP 15 TPU 0.3 O U O 0.2 10 5 0.1 0 0 0 0.5 OUTPU1T.0 LOW VOL1T.A5GE (V) 2.0 2.5 06012-003 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06012-006 Figure 3. Output Current vs. Receiver Output Low Voltage Figure 6. Receiver Output Low Voltage vs. Temperature –30 45 40 –25 35 A) )A m –20 m 30 T ( T ( N N E E 25 R R R –15 R U U C C 20 T T U U TP –10 TP 15 U U O O 10 –5 5 0 0 1.5 2.0 2O.5UTPUT3 H.0IGH VO3L.5TAGE (4V.)0 4.5 5.0 06012-004 0 0.5 D1I.F0FER1E.N5TIAL2 .O0UTP2U.5T VOL3.T0AGE3 (.V5) 4.0 4.5 06012-007 Figure 4. Output Current vs. Receiver Output High Voltage Figure 7. Driver Output Current vs. Differential Output Voltage 4.5 2.3 4.4 E (V) 2.2 LTAGE (V) 4.3 T VOLTAG 22..01 O U H V 4.2 UTP 1.9 G O HI L T A 1.8 PU 4.1 NTI UT RE 1.7 O E F 4.0 F DI 1.6 3.9 1.5 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06012-005 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06012-008 Figure 5. Receiver Output High Voltage vs. Temperature Figure 8. Driver Differential Output Voltage vs. Temperature Rev. A | Page 7 of 16

ADM483E 140 10 9 120 8 T CURRENT (mA) 1068000 WN CURRENT (µA) 4567 U O P D UT 40 UT 3 O H S 2 20 1 0 0 0 2 OU4TPUT LOW6 VOLTAGE8 (V) 10 12 06012-009 –60 –40 –20 TE0MPERA20TURE (4°0C) 60 80 100 06012-012 Figure 9. Output Current vs. Driver Output Low Voltage Figure 12. Shutdown Current vs. Temperature –140 –120 A)–100 m T ( EN –80 RR A B U 2 T C –60 U P T U –40 O RO –20 1 0 –8 –6 –O4UTPUT– H2IGH VO0LTAGE (V2) 4 6 06012-010 CCHH13 55.0000mVV CH2 500mV MT 2 0 0 n 5s7.60% A CH1 2.80V 06012-013 Figure 10. Output Current vs. Driver Output High Voltage Figure 13. ADM483E Receiver tPHL 600 500 A) µ 400 T ( N E R B A R 300 U 2 C Y L UPP 200 DE = VCC AND RE = x S DE = 0 AND RE = 0 DE = 0 AND RE = VCC 100 RO 1 0 –40 –20 0TEMPER2A0TURE (°C40) 60 80 06012-011 CCHH13 55.0000mVV CH2 500mV MT 2 0 0 n 6s0.80% A CH1 2.80V 06012-014 Figure 11. ADM483E Supply Current vs. Temperature Figure 14. ADM483E Receiver tPLH Driven by External RS-485 Device Rev. A | Page 8 of 16

ADM483E TEST CIRCUITS AND SWITCHING CHARACTERISTICS Y VCC RL = 500Ω S1 RL 0V OR 5V D OUT CL VOD Z RL VOC 06012-015 GENERATOR 50Ω Figure 15. Driver DC Test Load 5V 5V DE VCC/2 0V DE t CL tDZL(SHDDZNL), tDLZ A VCC DI B VOD RL CL OUT VOL 2.3V 0.5V 06012-019 06012-016 Figure 19. Driver Enable and Disable Times (tDZL, tDLZ, tDZL(SHDN)) Figure 16. Driver Timing Test Circuit B RECEIVER OUTPUT ATE VID R DI50VV 1.5V A 06012-020 tDPLH tDPHL 1/2 VO Figure 20. Receiver Propagation Delay Test Circuit B A +1V VO A B –1V 1/2VO tRPLH tRPHL VDIFF+–VV0VOO tDR10% 90t%SKVEDWIFF==t DVP (LAH) –– VtD (PBH)L90% 10%tDF 06012-017 RO VVOOHL THE RISFEig 1T.uI5MrVeE 2 A1N. DR eFcAeLiLv eTrI MPEro OpFa gINaPtUioTn A D AeNlDa yINs PUT B < 4ns 06012-021 Figure 17. Driver Propagation Delays S1 0 OR 5V D OUT CL RL = 500Ω GENERATOR 50Ω 5V DE 1.5V 0V t t DZH, DZH(SHDN) 0.5V VOH OUT 2.3V tDHZ 0V 06012-018 Figure 18. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN)) Rev. A | Page 9 of 16

ADM483E S1 +1.5V S3 VCC –1.5V 1kΩ VID 0V OR 5V CL 15pF S2 GENERATOR 50Ω S1 OPEN S1 CLOSED S2 CLOSED S2 OPEN S3 = +1.5V S3 = –1.5V +5V +5V RE RE +1.5V 0V 0V t t RZL, RZL(SHDN) t t RZH, RZH(SHDN) VOH VCC RO +1.5V RO +1.5V 0V VOL S1 OPEN S1 CLOSED S2 CLOSED S2 OPEN S3 = +1.5V S3 = +1.5V +5V +5V RE RE +1.5V +1.5V 0V 0V t t RLZ RHZ VOH VCC +0.5V RO 0V RO +0.5V VOL 06012-022 Figure 22. Receiver Enable and Disable Times Rev. A | Page 10 of 16

ADM483E GENERAL INFORMATION The ADM483E is a robust RS-485 transceiver that operates +5V +5V from a single 5 V supply. 0.1µF 0.1µF It is ideally suited for operation in electrically harsh environ- ments or where cables may be plugged and unplugged. It is also RE VCC VCC DE immune to high RF field strengths without special shielding RO DI precautions. The ADM483E is intended for balanced data B B transmission and complies with both EIA Standards RS-485 and ADM483E A A ADM483E RS-422. It contains a differential line driver and a differential DI RS-485/RS-422 LINK line receiver; it is suitable for half-duplex data transmission RO because the driver and receiver share the same differential pins. DE RE GND GND T32h etr iannpsucte iivmerpse odnan tchee odnif ftehree nAtDiaMl b4u8s3. E is 12 kΩ, allowing up to 06012-023 Figure 23. Typical Half-Duplex Link Application The ADM483E operates from a single 5 V ± 10% power supply. Table 6 and Table 7 show the truth tables for transmitting and Excessive power dissipation caused by bus contention or by receiving. output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high impedance state Table 6. Transmitting Truth Table if, during fault conditions, a significant temperature increase is Inputs Outputs detected in the internal driver circuitry. RE DE DI B A The receiver has a fail-safe feature that results in a logic high X1 1 1 0 1 output state if the inputs are unconnected (floating). X1 1 0 1 0 A high level of robustness is achieved using internal protection 0 0 X1 High-Z High-Z circuitry, eliminating the need for external protection components 1 0 X1 High-Z High-Z such as transorbs or surge suppressors. 1 X = don’t care. Low electromagnetic emissions are achieved using slew limited Table 7. Receiving Truth Table drivers, minimizing interference both conducted and radiated. Inputs Outputs The ADM483E can transmit at data rates up to 250 kbps. RE DE A − B RO 0 0 ≥ +0.2 V 1 A typical application for the ADM483E is illustrated in Figure 23. 0 0 ≤ −0.2 V 0 This figure shows a half-duplex link where data may be 0 0 Inputs O/C 1 transferred at rates up to 250 kbps. A terminating resistor is 1 0 X1 High-Z shown at both ends of the link. This termination is not critical because the slew rate is controlled by the ADM483E and 1 X = don’t care. reflections are minimized. The communications network can be extended to include ESD TRANSIENT PROTECTION SCHEME multipoint connections as shown in Figure 26. Up to 32 The ADM483E uses protective clamping structures on its inputs transceivers can be connected to the bus. and outputs that clamp the voltage to a safe level and dissipate the energy present in ESD (electrostatic discharge). The protection structure achieves ESD protection up to ±15 kV according to the Human Body Model. Rev. A | Page 11 of 16

ADM483E ESD TESTING It is, therefore, extremely important to have high levels of ESD protection on the I/O lines. Two coupling methods are used for ESD testing: contact It is possible that the ESD discharge could induce latch-up in discharge and air-gap discharge. Contact discharge calls for a the device under test. Therefore, it is important that ESD testing direct connection to the unit being tested. Air-gap discharge on the I/O pins be carried out while device power is applied. uses a higher test voltage but does not make direct contact with This type of testing is more representative of a real-world I/O the unit under test. With air-gap discharge, the discharge gun is discharge where the equipment is operating normally when the moved toward the unit under test, developing an arc across the discharge occurs. air gap. This method is influenced by humidity, temperature, barometric pressure, distance, and rate of closure of the discharge 100% gun. The contact discharge method, though less realistic, is 90% more repeatable and is gaining acceptance and preference over the air-gap method. Although very little energy is contained within an ESD pulse, K the extremely fast rise time, coupled with high voltages, can EA P I cause failures in unprotected semiconductors. Catastrophic destruction may occur immediately as a result of arcing or 36.8% heating. Even if catastrophic failure does not occur immediately, the device may suffer from parametric degradation, which can 10% result in degraded performance. The cumulative effects of continuous expoHsIuGHre may eventually lead to complete failure. tRL tDL TIME (t) 06012-025 VOLTAGE R2 Figure 25. Human Body Model ESD Current Waveform GENERATOR C1 DEVICE UNDER TEST Table 8. ADM483E ESD Test Results ESD Test Method I/O Pins EHSUDM ATNES BTO MDEYT MHOODDEL R1.25kΩ C1010pF 06012-024 Human Body Model: Air ±15 kV Figure 24. ESD Generator Human Body Model: Contact ±8 kV I/O lines are particularly vulnerable to ESD damage. Simply touching or plugging in an I/O cable can result in a static discharge that may damage or completely destroy the interface product connected to the I/O port. Rev. A | Page 12 of 16

ADM483E APPLICATIONS INFORMATION DIFFERENTIAL DATA TRANSMISSION CABLE AND DATA RATE Differential data transmission is used to reliably transmit data at The transmission line of choice for RS-485 communications is a high rates over long distances and through noisy environments. twisted pair. Twisted pair cable tends to cancel common-mode Differential transmission nullifies the effects of ground shifts noise and also cancels the magnetic fields generated by the and noise signals that appear as common-mode voltages on the current flowing through each wire, thereby reducing the line. There are two main standards approved by the Electronics effective inductance of the pair. Industries Association (EIA) that specify the electrical character- A typical application showing a multipoint transmission istics of transceivers used in differential data transmission. network is shown in Figure 26. An RS-485 transmission line can The RS-422 standard specifies data rates up to 10 MBaud and have as many as 32 transceivers on the bus. Only one driver can line lengths up to 4000 feet. A single driver can drive a transmission transmit at a particular time, but multiple receivers can be line with up to 10 receivers. enabled simultaneously. To accommodate true multipoint communications, the RS-485 RT RT standard was defined. This standard meets or exceeds all the requirements of RS-422 and also allows for up to 32 drivers and D D 32 receivers to be connected to a single bus. An extended common-mode range of −7 V to +12 V is defined. The most R R significant difference between RS-422 and RS-485 is the fact that the drivers can be disabled, thereby allowing more than one (32, in fact) to be connected to a single line. Only one driver R R sahdoduitlido nbael esnpaebcliefidc aatti oan tsim toe ,g buuatr athnete Re Sd-e4v8i5ce s tsaanfedtayr idn c tohnet eavinesn t D D 06012-026 of line contention. Figure 26. Typical RS-485 Network Rev. A | Page 13 of 16

ADM483E OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27 (0.0500) 0.50 (0.0196) BSC 1.75 (0.0688) 0.25 (0.0099) 45° 0.25 (0.0098) 1.35 (0.0532) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 0.10 SEATING 0.31 (0.0122) 0.25 (0.0098) 10..2470 ((00..00510507)) PLANE 0.17 (0.0067) COMPLIANTTO JEDEC STANDARDS MS-012-AA C(RINOEFNPETARRREOENNLCLTEIHN EOGSN DELSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 012407-A Figure 27. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity ADM483EAR –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 ADM483EAR-REEL –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 2500 ADM483EARZ1 –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 ADM483EARZ-REEL1 –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 2500 1Z = RoHS Compliant Part. Rev. A | Page 14 of 16

ADM483E NOTES Rev. A | Page 15 of 16

ADM483E NOTES © 1997–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06012-0-12/07(A) Rev. A | Page 16 of 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADM483EAR-REEL ADM483EARZ ADM483EARZ-REEL