EMI/EMC-Compliant, ±15 kV, ESD-Protected RS-232 Line Drivers/Receivers ADM202E/ADM1181A FEATURES FUNCTIONAL BLOCK DIAGRAMS Complies with 89/336/EEC EMC directive 5V INPUT E±S8D k Vp:r ocotencttaicotn d tios cIhECar1g0e0 0-4-2 (801.2) 0.110µVF CC11+– +5DVVOO TLUOTBA L+GE1ER0V VVC+C 0C.31µF C0.51µF 6.3V ±±1155 kkVV:: haiurm-gaanp bdoisdcyh amrgoed el 0.110µVF CC22+– +1IVN0OVVL ETTROATG–E1ER0V V– C0.41µF 10V EFT fast transient/burst immunity (IEC1000-4-4) Low EMI emissions (EN55022) CMOS T1IN T1 T1OUT EIA/TIA-232 INPUTS OUTPUTS 230 kbits/s data rate guaranteed T2IN T2 T2OUT TSSOP package option Upgrade for MAX202E, 232E, LT1181A R1OUT R1 R1IN CMOS EIA/TIA-232 OUTPUTS INPUTS* APPLICATIONS R2OUT R2 R2IN General-purpose RS-232 data link ADM202E GND Portable instruments P DAs *INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT 00066-001 Figure 1. 5V INPUT 0.1µF C1+ +5VVO TLOTA +G1E0V VCC C5 10V C1– DOUBLER V+ 0.1µF C3 10V 0 .110µVF CC22+– +1IVN0OVVL ETTROATG–E1ER0V V– C0.41µF100.1VµF 10V GENERAL DESCRIPTION CMOS T1IN T1 T1OUT EIA/TIA-232 INPUTS OUTPUTS The ADM202E and ADM1181A are robust, high speed, T2IN T2 T2OUT 2-channel RS-232/V.28 interface devices that operate from a R1OUT R1 R1IN single 5 V power supply. Both products are suitable for operation CMOS EIA/TIA-232 OUTPUTS INPUTS* in harsh electrical environments and are compliant with the EU R2OUT R2 R2IN directive on EMC (89/336/EEC). Both the level of electromagnetic ADM1181A GND emissions and immunity are in compliance. EM immunity ifnasctl utrdaenss EieSnDt/ bpurorstet cptrioonte cinti oexnc (e1s0s 0o0f- ±41-45) k, aVn odn r aadlli aIt/eOd lines, *INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT 00066-002 immunity (1000-4-3). EM emissions include radiated and Figure 2. conducted emissions as required by Information Technology The ADM202E provides a robust pin-compatible upgrade for Equipment EN55022, CISPR22. existing ADM202, ADM232L, or MAX202E/MAX232E sockets. The ADM202E and ADM1181A conform to the EIA-232E It is available in a 16-lead PDIP, a wide SOIC, a narrow SOIC, and CCITT V.28 specifications and operate at data rates up and a space-saving TSSOP package that is 44% smaller than the to 230 kbps. SOIC package. Four external 0.1 µF charge-pump capacitors are used for the The ADM1181A provides a robust pin-compatible upgrade for voltage doubler/inverter, permitting operation from a single the LTC1181A, and it is available in a 16-lead PDIP package 5 V supply. and a wide 16-lead SOIC package. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.

ADM202E/ADM1181A TABLE OF CONTENTS Specifications.....................................................................................3 Typical Performance Characteristics..............................................8 Absolute Maximum Ratings............................................................4 ESD Testing (IEC1000-4-2)......................................................10 ESD Caution..................................................................................4 Fast Transient/Burst Testing (IEC1000-4-4)...........................11 Pin Configuration and Function Descriptions.............................5 IEC1000-4-3 Radiated Immunity............................................12 General Description.........................................................................6 Emissions/Interference..............................................................12 Circuit Description.......................................................................6 Conducted Emissions................................................................12 Charge-Pump DC-to-DC Voltage Converter.......................6 Radiated Emissions....................................................................13 Transmitter (Driver) Section..................................................6 Outline Dimensions.......................................................................14 Receiver Section.......................................................................6 Ordering Guide..........................................................................15 High Baud Rate.............................................................................6 ESD/EFT Transient Protection Scheme....................................7 REVISION HISTORY 2/05—Rev. B to Rev. C. Updated Format..................................................................Universal Changed Hysteresis Level..................................................Universal Change to Specifications..................................................................3 Added ESD Caution.........................................................................4 Change to Receiver Section.............................................................6 Updated Outline Dimensions.......................................................14 Changes to Ordering Guide..........................................................15 2/01—Rev. A to Rev. B. Deletion of one ESD Rating in ABSOLUTE MAXIMUM RATINGS.............................................4 Removal of one column in Table II................................................8 Rev. C | Page 2 of 16

ADM202E/ADM1181A SPECIFICATIONS V = 5.0 V ± 10%, C1 to C4 = 0.1 µF. All specifications T to T , unless otherwise noted. CC MIN MAX Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DC CHARACTERISTICS Operating Voltage Range 4.5 5.0 5.5 V V Power Supply Current 2.5 6.0 mA No load CC 13 18 mA R = 3 kΩ to GND L LOGIC Input Logic Threshold Low, V 0.8 V T INL IN Input Logic Threshold High, V 2.4 V T INH IN CMOS Output Voltage Low, V 0.4 V I = 3.2 mA OL OUT CMOS Output Voltage High, V 3.5 V I = −1 mA OH OUT Logic Pull-Up Current +12 ±25 µA T = 0 V IN RS-232 RECEIVER EIA-232 Input Voltage Range −30 +30 V EIA-232 Input Threshold Low 0.4 1.2 V EIA-232 Input Threshold High 1.6 2.4 V EIA-232 Input Hysteresis 0.65 V EIA-232 Input Resistance 3 5 7 kΩ T = 0°C to 85°C A RS-232 TRANSMITTER Output Voltage Swing ±5.0 ±9.0 V All transmitter outputs loaded with 3 kΩ to ground Transmitter Output Resistance 300 Ω V = 0 V, V = ±2 V CC OUT RS-232 Output Short-Circuit Current ±10 ±60 mA TIMING CHARACTERISTICS Maximum Data Rate 230 kbps R = 3 kΩ to 7 kΩ, C = 50 pF to 1000 pF L L Receiver Propagation Delay T 0.1 1 µs PHL T 0.3 1 µs PLH Transmitter Propagation Delay 1.0 1.5 µs R = 3 kΩ, C = 1000 pF L L Transition Region Slew Rate 3 8 30 V/µs R = 3 kΩ, C = 1000 pF L L Measured from +3 V to −3 V, or −3 V to +3 V EM IMMUNITY ESD Protection (I/O Pins) ±15 kV Human body model ±15 kV IEC1000-4-2 air discharge ±8 kV kV IEC1000-4-2 contact discharge EFT Protection (I/O Pins) ±2 kV IEC1000-4-4 EMI Immunity 10 V/m IEC1000-4-3 Rev. C | Page 3 of 16

ADM202E/ADM1181A ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Values may cause permanent damage to the device. This is a stress V −0.3 V to +6 V CC rating only; functional operation of the device at these or any V+ (V − 0.3 V) to +14 V CC other conditions above those indicated in the operational V– +0.3 V to −14 V sections of this specification is not implied. Exposure to Input Voltages absolute maximum rating conditions for extended periods may T 0.3 V to (V+, +0.3 V) IN affect device reliability. R ±30 V IN Output Voltages T ±15 V OUT R –0.3 V to (V + 0.3 V) OUT CC Short-Circuit Duration T Continuous OUT Power Dissipation N-16 450 mW (Derate 6 mW/°C Above 50°C) θ , Thermal Impedance 117°C/W JA Power Dissipation R-16 450 mW (Derate 6 mW/°C Above 50°C) θJA, Thermal Impedance 158°C/W Power Dissipation RU-16 500 mW (Derate 6 mW/°C Above 50°C) θ , Thermal Impedance 158°C/W JA Operating Temperature Range Industrial (A Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C ESD Rating (MIL-STD-883B) (I/O Pins) ±15 kV ESD Rating (IEC1000-4-2 Air) (I/O Pins) ±15 kV ESD Rating (IEC1000-4-2 Contact) ±8 kV (I/O Pins) EFT Rating (IEC1000-4-4) (I/O Pins) ±2 kV ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 4 of 16

ADM202E/ADM1181A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C1+ 1 16 VCC V+ 2 15 GND C1– 3 ADM202E 14 T1OUT ADM1181A C2+ 4 13 R1IN C2– 5 (NToOt Pto V SIEcaWle)12 R1OUT V– 6 11 T1IN T2OUT 7 10 T2IN R2IN 8 9 R2OUT 00066-003 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 16 V Power Supply Input: 5 V ± 10%. CC 2 V+ Internally Generated Positive Supply (+9 V nominal). 6 V− Internally Generated Negative Supply (−9 V nominal). 15 GND Ground Pin. Must be connected to 0 V. 1, 3 C1+, C1− External Capacitor 1 is connected between these pins. A 0.1 µF capacitor is recommended, but larger capacitors of up to 47 µF can be used. 4, 5 C2+, C2− External Capacitor 2 is connected between these pins. A 0.1 µF capacitor is recommended, but larger capacitors of up to 47 µF can be used. 10, 11 T Transmitter (Driver) Inputs. These inputs accept TTL/CMOS levels. IN 7, 14 T Transmitter (Driver) Outputs. These are RS-232 signal levels (typically ±9 V). OUT 8, 13 R Receiver Inputs. These inputs accept RS-232 signal levels. An internal 5 kΩ pull-down resistor to GND is IN connected on each input. 9, 12 R Receiver Outputs. These are CMOS output logic levels. OUT 5V INPUT 5V INPUT 0.1µF 1 C1+ +5VVO TLOTA +G1E0V VCC16 C3 C5 0.1µF 1 C1+ +5VVO TLOTA +G1E0V VCC 16 C5 10V 3 C1– DOUBLER V+ 2 0.1µF 0.1µF 10V 3 C1– DOUBLER V+ 2 0.1µF 6.3V C3 10V 0.110µVF 45 CC22+– +1IVN0OVVL ETTROATG–E1ER0V V– 6 C0.41µF 0 .110µVF 45 CC22+– +1IVN0OVVL ETTROATG–E1ER0V V– 6 C0.41µF100.1VµF 10V 10V T1IN 11 T1 14 T1OUT T1IN 11 T1 14 T1OUT CMOS EIA/TIA-232 CMOS EIA/TIA-232 INPUTS OUTPUTS INPUTS OUTPUTS T2IN 10 T2 7 T2OUT T2IN 10 T2 7 T2OUT R1OUT 12 R1 13 R1IN R1OUT 12 R1 13 R1IN CMOS EIA/TIA-232 CMOS EIA/TIA-232 OUTPUTS INPUTS* OUTPUTS INPUTS* R2OUT 9 R2 8 R2IN R2OUT 9 R2 8 R2IN ADM202E ADM1181A GND GND 15 15 *INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT 00066-004 *INTERNAL 5kΩPULL-DOWN RESISTOR ON EACH RS-232 INPUT 00066-005 Figure 4. ADM202E Typical Operating Circuit Figure 5. ADM1181A Typical Operating Circuit Rev. C | Page 5 of 16

ADM202E/ADM1181A GENERAL DESCRIPTION desired, larger capacitors (up to 47 µF) can be used for The ADM202E/ADM1181E are rugged RS-232 line Capacitor C1 to Capacitor C4. This facilitates direct substitution drivers/receivers. Step-up voltage converters coupled with level- with older generation charge-pump RS-232 transceivers. shifting transmitters and receivers allow RS-232 levels to be developed while operating from a single 5 V supply. Features include low power consumption, high transmission S1 S3 rates, and compliance with the EU directive on electromagnetic VCC V+ = 2VCC compatibility. EM compatibility includes protection against C1 C3 S2 S4 radiated and conducted interference, including high levels of GND VCC electrostatic discharge. INTERNAL Adilslc ihnaprugtess a onfd u opu ttop u±t1s5 c koVnt aainnd p erloetcetcritcioanl f aagsta itnrasnt seileencttrso osft autpic OSCILNLOATTEO: RC3 CONNECTS BETWEEN V+ AND GND ON THE ADM1181A 00066-006 to ±2 kV. This ensures compliance to IEC1000-4-2 and IEC1000-4-4 requirements. Figure 6. Charge-Pump Voltage Doubler The devices are ideally suited for operation in electrically harsh environments or where RS-232 cables are frequently being S1 S3 V+ GND plugged/unplugged. They are also immune to high RF field FROM VOLTAGE C2 C4 strengths without special shielding precautions. DOUBLER S2 S4 GND V– =–(V+) CMOS technology is used to minimize the power dissipation, allowing maximum battery life in portable applications. OISNCTIELRLANTAOLR 00066-007 The ADM202E/ADM1181A serve as a modification, Figure 7. Charge-Pump Voltage Inverter enhancement, and improvement to the ADM230–ADM241 family and its derivatives. It is essentially plug-in compatible and do not have materially different applications. Transmitter (Driver) Section CIRCUIT DESCRIPTION The drivers convert 5 V logic input levels into RS-232 output levels. When driving an RS-232 load with V = 5 V, the output The internal circuitry consists of four main sections: CC voltage swing is typically ±9 V. • A charge-pump voltage converter Receiver Section • 5 V logic to EIA-232 transmitters The receivers are inverting level shifters that accept RS-232 input levels and translate them into 5 V logic output levels. The • EIA-232 to 5 V logic receivers. inputs have internal 5 kΩ pull-down resistors to ground and are also protected against overvoltages of up to ±30 V. Unconnected • Transient protection circuit on all I/O lines inputs are pulled to 0 V by the internal 5 kΩ pull-down resistor. Charge-Pump DC-to-DC Voltage Converter Therefore, unconnected inputs and those connected to GND have a Logic 1 output level. The charge-pump voltage converter consists of a 200 kHz oscillator and a switching matrix. The converter generates a The receivers have Schmitt-trigger inputs with a hysteresis level ±10 V supply from the input 5 V level. This is done in two stages, of 0.65 V. This ensures error-free reception for both noisy using a switched capacitor technique, as illustrated in Figure 6 inputs and inputs with slow transition times. and Figure 7. First, the 5 V input supply is doubled to 10 V, using Capacitor C1 as the charge storage element. The 10 V level is HIGH BAUD RATE then inverted to generate −10 V, using C2 as the storage element. The ADM202E/ADM1181A feature high slew rates, permitting data transmission at rates well in excess of the EIA/RS-232-E Capacitor C3 and Capacitor C4 are used to reduce the output specifications. RS-232 voltage levels are maintained at data rates ripple. Their values are not critical and can be increased if of up to 230 kbps, even under worst case loading conditions. desired. On the ADM202E, Capacitor C3 is shown connected This allows for high speed data links between two terminals and between V+ and V , whereas it is connected between V+ and CC is also suitable for the new generation ISDN modem standards, GND on the ADM1181A. It is acceptable to use either which require data rates of 230 kbps. The slew rate is internally configuration with both the ADM202E and ADM1181A. If controlled to less than 30 V/µs to minimize EMI interference. Rev. C | Page 6 of 16

ADM202E/ADM1181A ESD/EFT TRANSIENT PROTECTION SCHEME R1 The ADM202E/ADM1181A use protective clamping structures RECEINIVPEURT RX D1 on all inputs and outputs to clamp the voltage to a safe level and RIN dissipate the energy present in electrostatic (ESD) and electrical D2 fparsott tercatniosnie nsttrsu (cEtFuTre) ids isshchowarng eisn. FAi gsuimrep 8li fainedd sFcihguemrea 9ti. cE oafc hth e 00066-008 Figure 8. Receiver Input Protection Scheme input and output contains two back-to-back high speed clamping diodes. During normal operation with maximum RS-232 signal levels, the diodes have no effect because one or the other is reverse biased depending on the polarity of the signal. However, if the voltage exceeds about 50 V in either direction, RX TOUT TORUATNPSUMTITTER D1 reverse breakdown occurs and the voltage is clamped at this level. The diodes are large p-n junctions that are designed to handle D2 instantaneous current surges that exceed several amperes. 00066-009 The transmitter outputs and receiver inputs have a similar Figure 9. Transmitter Output Protection Scheme protection structure. The receiver inputs can dissipate some of the energy through the internal 5 kΩ resistor to GND, as well as through the protection diodes. The protection structure achieves ESD protection up to ±15 kV and EFT protection up to ±2 kV on all RS-232 I/O lines. The methods used to test the protection scheme are discussed in the ESD Testing (IEC1000-4-2) and Fast Transient/Burst Testing (IEC1000-4-4) sections. Rev. C | Page 7 of 16

ADM202E/ADM1181A TYPICAL PERFORMANCE CHARACTERISTICS 15 80 TX O/P HI 10 70 TX O/P HI LOADED 60 5 V50 O/P (V) 0 dBµ40 LIMIT T X –5 30 TX O/P LO LOADED 20 –10 10 TX O/P LO 0START 30.0MHz STOP 200.0MHz 00066-010 –154 4.5 VCC (V) 5 5.5 00066-013 Figure 10. EMC Radiated Emissions Figure 13. Transmitter Output Voltage High/Low vs. VCC 15 80 10 70 60 LIMIT 5 50 V) dBVµ 40 V+, V– ( 0 30 –5 20 –10 10 0 0.3 0.6LOG1 FREQUENC3Y (MHz6) 10 30 00066-011 –15 0 5 10 ILOAD1 5(mA) 20 25 30 00066-014 Figure 11. EMC Conducted Emissions Figure 14. Charge Pump V+ and V− vs. Current 15 9 115KBPS 7 10 230KBPS 5 TX O/P HI 5 3 460KBPS V) V) O/P ( 1 O/P ( 0 TX–1 T X –5 –3 460KBPS TX O/P LO –5 230KBPS –10 –7 115KBPS –90 500 L1O0A00D CAP1A5C0I0TANCE2 0(p0F0) 2500 3000 00066-012 –150 2 4 6ILOAD(mA8) 10 12 14 00066-015 Figure 12. Transmitter Output Voltage High/Low vs. Load Capacitance Figure 15. Transmitter Output Voltage Low/High vs. Load Current @ 115 kbps, 230 kbps, and 460 kbps Rev. C | Page 8 of 16

ADM202E/ADM1181A 300 250 1 T V– 200 )Ω E ( C N150 A 2 ED V+ P M I100 T 50 Ch1 5.00V Ch2 5.00V M2.00
µs Ch1 –400mV 00066-016 04.0 4.5 VC5C.0 (V) 5.5 6.0 00066-017 Figure 16. 230 kbps Data Transmission Figure 17. Charge-Pump Impedance vs. VCC Rev. C | Page 9 of 16

ADM202E/ADM1181A ESD TESTING (IEC1000-4-2) HIGH R1 R2 VOLTAGE IEC1000-4-2 (previously 801-2) specifies compliance testing GENERATOR DEVICE using two coupling methods, contact discharge and air-gap C1 UNDER TEST discharge. Contact discharge calls for a direct connection to the unit being tested. Air-gap discharge uses a higher test voltage, ESD TEST METHOD R2 C1 bWuitt hd oaeirs- ngaopt mdiaskche adrigree,c tth ceo dnitsaccht awrgiteh gtuhne uisn mit obveeindg t otewsaterdd. the HIE.CB1O00D0Y-4M-2IL-STD883B 13.350kΩΩ 110500ppFF 00066-018 unit being tested, developing an arc across the air gap. This Figure 18. ESD Test Standards method is influenced by humidity, temperature, barometric pressure, distance, and rate of closure of the discharge gun. Although less realistic, the contact-discharge method is more 100 repeatable and is gaining preference to the air-gap method. 90 Although very little energy is contained within an ESD pulse, the extremely fast rise time coupled with high voltages can %) cause failures in unprotected semiconductors. Catastrophic (K A destruction can occur immediately as a result of arcing or PE I heating. Even if catastrophic failure does not occur immediately, 36.8 the device might suffer from parametric degradation, which can result in degraded performance. The cumulative effects of continuous exposure can eventually lead to complete failure. 10 tRL tDL TIME t 00066-019 I/O lines are particularly vulnerable to ESD damage. Simply Figure 19. Human Body Model ESD Current Waveform touching or plugging in an I/O cable can result in a static discharge, which can damage or completely destroy the interface product connected to the I/O port. Traditional ESD test methods, such as the MIL-STD-883B method 3015.7, do 100 not fully test a product’s susceptibility to this type of discharge. 90 This test was intended to test a product’s susceptibility to ESD damage during handling. Each pin is tested with respect to all %) other pins. There are some important differences between the (K A traditional test and the IEC test: PE I • The IEC test is much more stringent in terms of discharge energy. The injected peak current is over four times greater. 10 • The current rise time is significantly faster in the IEC test. 0.1TO1ns TIME t • The IEC test is carried out while power is applied to 30ns 60ns 00066-020 the device. Figure 20. IEC1000-4-2 ESD Current Waveform It is possible that the ESD discharge could induce latch-up in the The ADM202E/ADM1181E products are tested using both of device being tested. Therefore, this test is more representative of a the previously mentioned test methods. Pins are tested with real-world I/O discharge where the equipment is operating respect to all other pins as per the MIL-STD-883B specification. normally with power applied. For peace of mind, however, both In addition, I/O pins are tested as per the IEC test specification. tests should be performed to ensure maximum protection The products were tested under the following conditions: during both handling and field service. • Power-On • Power-Off There are four levels of compliance defined by IEC1000-4-2. The ADM202E/ADM1181A products meet the most stringent level of compliance both for contact and for air-gap discharge. This means that the products are able to withstand contact discharges in excess of 8 kV and air-gap discharges in excess of 15 kV. Rev. C | Page 10 of 16

ADM202E/ADM1181A Table 4. IEC1000-4-2 Compliance Levels A simplified circuit diagram of the actual EFT generator is Level Contact Discharge Air Discharge illustrated in Figure 22. 1 2 kV 2 kV The transients are coupled onto the signal lines using an EFT 2 4 kV 4 kV coupling clamp. The clamp, which is 1 m long, completely 3 6 kV 8 kV surrounds the cable, providing maximum coupling capacitance 4 8 kV 15 kV (50 pF to 200 pF typ) between the clamp and the cable. High energy transients are capacitively coupled to the signal lines. Table 5. ADM202E/ADM1181A ESD Test Results Fast rise times (5 ns), as specified by the standard, result in very ESD Test Method I/O Pins effective coupling. This test is very strenuous because high voltages are coupled onto the signal lines. The repetitive transients often MIL-STD-883B ±15 kV cause problems where single pulses do not. Destructive latch-up IEC1000-4-2 can be induced due to the high energy content of the transients. Contact ±8 kV Note that this stress is applied while the interface products are Air ±15 kV powered up and transmitting data. The EFT test applies hundreds of pulses with higher energy than ESD. Worst-case FAST TRANSIENT/BURST TESTING (IEC1000-4-4) transient current on an I/O line can be as high as 40 A. IEC1000-4-4 (previously 801-4) covers electrical fast transient (EFT)/burst immunity. Electrical fast transients occur as a result VOHLITGAHGE RC L RM CD 50Ω of arcing contacts in switches and relays. The tests simulate the SOURCE OUTPUT CC ZS idnistecrofnerneencctse agnen inerdautecdti vweh loenad, f. oAr espxaamrkp ilse g, ean peorwateerd r deluaey to the 00066-022 well-known back EMF effect. In fact, the spark consists of a Figure 22. IEC1000-4-4 Fast Transient Generator burst of sparks as the relay contacts separate. The voltage Test results are classified according to the following: appearing on the line, therefore, consists of a burst of extremely fast transient impulses. A similar effect occurs when switching • Classification 1: Normal performance within specifi- on fluorescent lights. cation limits The fast transient/burst test defined in IEC1000-4-4 simulates • Classification 2: Temporary degradation or loss of this arcing, and its waveform is illustrated in Figure 17. It performance that is self-recoverable consists of a burst of 2.5 kHz to 5 kHz transients repeating at 300 ms intervals. It is specified for both power and data lines. • Classification 3: Temporary degradation or loss of function or performance that requires operator intervention or V system reset • Classification 4: Degradation or loss of function that is not t recoverable due to damage 300ms 15ms The ADM202E/ADM1181A meet Classification 2 and have 5ns been tested under worst-case conditions using unshielded V cables. Data transmission during the transient condition is corrupted, but can resume immediately following the EFT event 50ns without user intervention. t 0.2/0.4ms 00066-021 Figure 21. IEC1000-4-4 Fast Transient Waveform Rev. C | Page 11 of 16

ADM202E/ADM1181A IEC1000-4-3 RADIATED IMMUNITY CONDUCTED EMISSIONS IEC1000-4-3 (previously IEC801-3) describes the measure- Conducted emissions is a measure of noise conducted onto the ment method and defines the levels of immunity to radiated mains power supply. Switching transients from the charge pump electromagnetic fields. It was originally intended to simulate the that are 20 V in magnitude and that contain significant energy electromagnetic fields generated by portable radio transceivers can lead to conducted emissions. Another source of conducted and other devices that generate continuous wave-radiated emissions is the overlap in switch-on times in the charge-pump electromagnetic energy. Its scope has since been broadened to voltage converter. In the voltage doubler shown in Figure 23, if include spurious EM energy, which can be radiated from S2 is not fully turned off before S4 turns on, a transient current fluorescent lights, thyristor drives, inductive loads, and glitch occurs between VCC and GND that results in conducted other sources. emissions. Therefore, it is important that the switches in the charge pump guarantee break-before-make switching under all Testing for immunity involves irradiating the device with an conditions to prevent instantaneous short-circuit conditions. EM field. There are various methods of achieving this, including The ADM202E is designed to minimize the switching transients use of anechoic chamber, stripline cell, TEM cell, and GTEM cell. A stripline cell consists of two parallel plates with an electric and ensure break-before-make switching, thereby minimizing field developed between them. The device being tested is placed conducted emissions. This results in emission levels well below the specified limits. No additional filtering or decoupling, other within the cell and exposed to the electric field. There are three than the recommended 0.1 µF capacitor, is required. severity levels that have field strengths ranging from 1 V to 10 V/m. Results are classified in a similar fashion to those for Conducted emissions are measured by monitoring the mains IEC1000-4-2. line. The equipment used consists of a spectrum analyzer and a LISN (line impedance stabilizing network) that essentially • Classification 1: Normal operation presents a fixed impedance at RF. The spectrum analyzer scans • Classification 2: Temporary degradation or loss of for emissions of up to 30 MHz; a plot for the ADM202E is function that is self-recoverable when the interfering shown in Figure 25. signal is removed • Classification 3: Temporary degradation or loss of function S1 S3 that requires operator intervention or system reset when VCC V+ = 2VCC the interfering signal is removed C1 C3 S2 S4 GND VCC • Classification 4: Degradation or loss of function that is not recoverable due to damage The ADM202E/ADM1181A products easily meet Classification 1 OISNCTIELRLANTAOLR 00066-023 at the most stringent (Level 3) requirement. In fact, field strengths Figure 23. Charge-Pump Voltage Doubler of up to 30 V/m showed no performance degradation, and error- free data transmission continued even during irradiation. ∅1 Table 6. Test Severity Levels (IEC1000-4-3) Level Field Strength V/m 1 1 ∅2 2 3 SWITCHING GLITCHES 3 10 EMISSIONS/INTERFERENCE 00066-024 Figure 24. Switching Glitches EN55 022 and CISPR22 define the permitted limits of radiated and conducted interference from information technology (IT) equipment. The objective of the standard is to minimize the level of emissions, both conducted and radiated. For ease of measurement and analysis, conducted emissions are assumed to predominate below 30 MHz, and radiated emissions are assumed to predominate above 30 MHz. Rev. C | Page 12 of 16

ADM202E/ADM1181A 80 was operated at maximum baud rates and configured like a typical RS-232 interface. Testing for radiated emissions was 70 carried out in a shielded anechoic chamber. 60 LIMIT 50 V RADIATED NOISE Bµ40 d 30 DUT 20 TO TURNTABLE ADJUSTABLE RECEIVER 10 ANTENNA 0 0.3 0.6 LO1G FREQUEN3CY (MH6z) 10 30 00066-025 00066-026 Figure 26. Radiated Emissions Test Setup Figure 25. ADM202E Conducted Emissions 80 RADIATED EMISSIONS 70 Radiated emissions are measured at frequencies in excess of 30 MHz. RS-232 outputs are designed for operation at high 60 baud rates, while driving cables can radiate high frequency EM 50 energy. The previously described causes of conducted emissions V can also cause radiated emissions. Fast RS-232 output transitions Bµ 40 LIMIT d can radiate interference, especially when lightly loaded and 30 driving unshielded cables. Charge-pump devices are also prone to radiating noise due to the high frequency oscillator and the 20 high voltages being switched by the charge pump. The move 10 tinow haigrdh esrm fraellqeur ecnacpya coistocirlsla ttoo rcso inns ethrvee c bhoaargrde- sppuamcep h daess rigensu, lted 0START 30.0MHz STOP 200.0MHz 00066-027 causing higher levels of conducted and radiated emissions. Figure 27. ADM202E Radiated Emissions vs. Frequency The RS-232 outputs on the ADM202E feature a controlled slew rate to minimize the level of radiated emissions, yet they are fast enough to support data rates of up to 230 kBaud. Figure 27 shows radiated emissions vs. frequency. The levels of emissions are well within specifications without the need for additional shielding or filtering components. The ADM202E Rev. C | Page 13 of 16

ADM202E/ADM1181A OUTLINE DIMENSIONS 10.50 (0.4134) 5.10 10.10 (0.3976) 5.00 4.90 16 9 7.60 (0.2992) 16 9 7.40 (0.2913) 10.65 (0.4193) 4.50 1 8 10.00 (0.3937) 4.40 B6.S4C0 4.30 1 8 1.27 (0.0500) BSC 2.65 (0.1043) 0.75 (0.0295)× 45° PIN 1 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 1.20 0.10 (0.0039) MAX 0.15 0.20 COPL0A.1N0ARITY CO00M..53P11L ((I00A..N0021T02 T12O)) JEDSPELEAACNT SIENTAGND00A..R3230D S((00 ..M0010S37-0091))380A°°A 10..2470 ((00..00510507)) 0.05 B0S.6C5 COPLANAR00I..T31Y09 SPELAANTIENG0.09 80°° 000...764505 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.10 (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 28. 16-Lead Standard Small Outline Package [SOIC] Wide Body Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RW-16) (RU-16) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters 0.785 (19.94) 0.765 (19.43) 0.295 (7.49) 0.745 (18.92) 0.285 (7.24) 0.275 (6.99) 10.00 (0.3937) 16 9 9.80 (0.3858) 1 8 0.325 (8.26) 4.00 (0.1575) 16 9 6.20 (0.2441) 0.10B0S (C2.54) 0.310 (7.87) 3.80 (0.1496) 1 8 5.80 (0.2283) 0.015 (0.38) 0.300 (7.62) 0.150 (3.81) MIN 0.135 (3.43) 0.180 (4.57) 0.120 (3.05) 1.27 (0.0500) 1.75 (0.0689) 0.50 (0.0197) MAX BSC 1.35 (0.0531) 0.25 (0.0098)× 45° 0.150 (3.81) 0.25 (0.0098) 0.10 (0.0039) 00..113100 ((32..3709)) 0.022 (0.56) 0.060 (1.52) SPELAANTIENG 00..001150 ((00..3285)) COPL0A.1N0ARITY 00..5311 ((00..00210212))SPELAANTIENG 00..2157 ((00..00009687)) 80°° 10..2470 ((00..00510507)) 00..001184 ((00..4366)) 00..005405 ((11..2174)) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MO-095AC COMPLIANT TO JEDEC STANDARDS MS-012AC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 29. 16-Lead Standard Small Outline Package [SOIC] Narrow Body Figure 31. 16-Lead Plastic Dual In-Line Package [PDIP] (R-16) (N-16) Dimensions shown in millimeters and (inches) Dimensions shown in inches and (millimeters) Rev. C | Page 14 of 16

ADM202E/ADM1181A ORDERING GUIDE Model Temperature Range Package Description Package Option ADM202EAN −40°C to +85°C Plastic DIP N-16 ADM202EANZ1 −40°C to +85°C Plastic DIP N-16 ADM202EARW −40°C to +85°C Wide SOIC R-16W ADM202EARW-REEL −40°C to +85°C Wide SOIC R-16W ADM202EARWZ1 −40°C to +85°C Wide SOIC R-16W ADM202EARWZ-REEL1 −40°C to +85°C Wide SOIC R-16W ADM202EARN −40°C to +85°C Narrow SOIC R-16N ADM202EARN-REEL −40°C to +85°C Narrow SOIC R-16N ADM202EARN-REEL7 −40°C to +85°C Narrow SOIC R-16N ADM202EARNZ1 −40°C to +85°C Narrow SOIC R-16N ADM202EARNZ-REEL1 −40°C to +85°C Narrow SOIC R-16N ADM202EARNZ-REEL71 −40°C to +85°C Narrow SOIC R-16N ADM202EARU −40°C to +85°C TSSOP RU-16 ADM202EARU-REEL −40°C to +85°C TSSOP RU-16 ADM202EARU-REEL7 −40°C to +85°C TSSOP RU-16 ADM202EARUZ1 −40°C to +85°C TSSOP RU-16 ADM202EARUZ-REEL1 −40°C to +85°C TSSOP RU-16 ADM202EARUZ-REEL71 −40°C to +85°C TSSOP RU-16 ADM1181AAN −40°C to +85°C Plastic DIP N-16 ADM1181AARW −40°C to +85°C Wide SOIC R-16W ADM1181AARW-REEL −40°C to +85°C Wide SOIC R-16W ADM1181AARWZ1 −40°C to +85°C Wide SOIC R-16W ADM1181AARWZ-REEL1 −40°C to +85°C Wide SOIC R-16W 1 Z = Pb-free part. Rev. C | Page 15 of 16

ADM202E/ADM1181A NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00066-0-2/05(C) Rev. C | Page 16 of 16