10 MHz to 10 GHz 67 dB TruPwr Detector Data Sheet ADL5906 FEATURES FUNCTIONAL BLOCK DIAGRAM Accurate rms-to-dc conversion from 10 MHz to 10 GHz VPOS1 VPOS2 3 10 Single-ended ±1.0 dB dynamic range: 67 dB at 2.14 GHz No balun or external input matching required ADL5906 TEMSPEENRSAOTRURE 8 VTEMP Response independent of waveform types, such as GSM-EDGE/CDMA/W-CDMA/TD-SCDMA/WiMAX/LTE RFIN+ 14 ISQR X2 Logarithmic slope: 55 mV/dB RFIN– 15 7 VSET Temperature stability: <±1 dB from −40°C to +125°C LINEAR-IN-dB VGA (NEGATIVE SLOPE) Operating temperature: −55°C to +125°C X2 ITGT Supply voltage: 4.75 V to 5.25 V NIC 2 G = 5 6 VRMS Sleep current: 250 µA NIC 16 Pin compatible with ADL5902 and AD8363 NIC 13 BDIOASWANN CDO PNOTWROELR V2R.3EVF 5 CRMS APPLICATIONS EPAD 26pF PTroawnesrm aimtteprl isfiigern lainl setarreinzagttiho nin/dcoicnattriooln l o(ToSpSsI ) PTAW1DDJN/ VR11EF VT12GT GND2 9 4 GND1 11287-001 RF instrumentation Figure 1. GENERAL DESCRIPTION The ADL5906 is a true rms responding power detector that has a Used as a power measurement device, VRMS is connected to 67 dB measurement range when driven with a single-ended 50 Ω VSET. The output is then proportional to the logarithm of the source. The easy to use input makes the ADL5906 frequency rms value of the input. In other words, the reading is presented versatile by eliminating the need for a balun or any other form directly in decibels and is scaled 1.1 V per decade, or 55 mV/dB; of external input tuning for operation up to 10 GHz. other slopes are easily arranged. In controller mode, the voltage applied to VSET determines the power level required at the The ADL5906 provides a solution in a variety of high frequency input to null the deviation from the setpoint. The output buffer systems requiring an accurate rms measurement of signal power. can provide high load currents. The ADL5906 can operate from 10 MHz to 10 GHz and can accept inputs from −65 dBm to +8 dBm with varying crest factors Requiring only a single supply of 5 V and a few capacitors, it is and bandwidths, such as GSM-EDGE, CDMA, W-CDMA, easy to use and capable of being driven single-ended or with a TD-SCDMA, WiMAX, and OFDM-based LTE carriers. In balun for differential input drive. The ADL5906 has a low 250 µA addition, its temperature stability over the broad temperature sleep current when powered down by a logic high applied to the range of −55°C to +125°C makes it ideally suited for a wide array PWDN pin. It powers up within approximately 1.4 µs to its of communications, military, industrial, and instrumentation nominal operating current of 68 mA at 25°C. applications. The ADL5906 is supplied in a 4 mm × 4 mm, 16-lead LFCSP, and it is pin compatible with the ADL5902 and the AD8363 TruPwr™ rms detectors. This feature allows the designer to create one circuit layout for projects requiring different dynamic ranges. A fully populated RoHS-compliant evaluation board is available. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADL5906 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 VSET Interface ............................................................................ 19 Applications ....................................................................................... 1 Output Interface ......................................................................... 19 Functional Block Diagram .............................................................. 1 VTGT Interface .......................................................................... 19 General Description ......................................................................... 1 Basis for Error Calculations ...................................................... 20 Revision History ............................................................................... 2 Measurement Mode Basic Connections.................................. 20 Specifications ..................................................................................... 3 Setting V ................................................................................ 20 TADJ Absolute Maximum Ratings ............................................................ 7 Setting V ................................................................................. 21 TGT ESD Caution .................................................................................. 7 Choosing a Value for C ......................................................... 21 RMS Pin Configuration and Function Descriptions ............................. 8 Output Voltage Scaling .............................................................. 22 Typical Performance Characteristics ............................................. 9 System Calibration and Error Calculation .............................. 24 Theory of Operation ...................................................................... 16 Using V to Improve Intercept Temperature Drift ........... 25 TEMP Square Law Detector and Amplitude Target .............................. 16 Description of Characterization ............................................... 27 RF Input Interface ...................................................................... 17 Evaluation Board ............................................................................ 28 Temperature Sensor Interface ................................................... 17 Evaluation Board Assembly Drawings .................................... 29 VREF Interface ........................................................................... 17 Outline Dimensions ....................................................................... 30 Temperature Compensation Interface ..................................... 18 Ordering Guide .......................................................................... 30 Power-Down Interface ............................................................... 19 REVISION HISTORY 10/13—Rev. 0 to Rev. A Changes to Table 2 ............................................................................ 7 Changes to Ordering Guide .......................................................... 30 3/13—Revision 0: Initial Version Rev. A | Page 2 of 32

Data Sheet ADL5906 SPECIFICATIONS VPOS1 = VPOS2 = 5 V, T = 25°C, single-ended input drive, R = 60.4 Ω, VRMS connected to VSET, V = 0.8 V, C = 0.1 µF. Negative A T TGT RMS current values imply that the ADL5906 is sourcing current out of the indicated pin. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OVERALL FUNCTION Frequency Range 10 to 10,000 MHz RF INPUT INTERFACE RFIN+, Pin RFIN− (Pin 14, Pin 15), ac-coupled Input Impedance Single-ended drive, 50 MHz 2500 Ω Common-Mode Voltage 2.5 V 100 MHz ±1.0 dB Dynamic Range Continuous wave (CW) input, T = 25°C 62 dB A Maximum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm 2 dBm Minimum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm −60 dBm Deviation vs. Temperature Deviation from output at 25°C, V = 0.35 V TADJ −40°C < T < +85°C; P = 0 dBm −0.8/+0.2 dB A IN −40°C < T < +85°C; P = −45 dBm −0.8/+0.4 dB A IN −55°C < T < +125°C; P = 0 dBm −1.3/+0.2 dB A IN −55°C < T < +125°C; P = −45 dBm −1.2/+0.6 dB A IN Logarithmic Slope −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm 59 mV/dB IN Logarithmic Intercept −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm −64 dBm IN 700 MHz ±1.0 dB Dynamic Range CW input, T = 25°C 62 dB A Maximum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm 2 dBm Minimum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm −60 dBm Deviation vs. Temperature Deviation from output at 25°C, V = 0.35 V TADJ −40°C < T < +85°C; P = 0 dBm −0.9/+0.3 dB A IN −40°C < T < +85°C; P = −45 dBm −0.9/+0.4 dB A IN −55°C < T < +125°C; P = 0 dBm −1.5/+0.3 dB A IN −55°C < T < +125°C; P = −45 dBm −1.3/+0.7 dB A IN Logarithmic Slope −65 dBm < P < +10 dBm; calibration at −40 dBm, and 0 dBm 59 mV/dB IN Logarithmic Intercept −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm −65 dBm IN 900 MHz ±1.0 dB Dynamic Range CW input, T = 25°C 63 dB A Maximum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm 3 dBm Minimum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm −60 dBm Deviation vs. Temperature Deviation from output at 25°C, V = 0.35 V TADJ −40°C < T < +85°C; P = 0 dBm −0.8/+0.3 dB A IN −40°C < T < +85°C; P = −45 dBm −0.9/+0.4 dB A IN −55°C < T < +125°C; P = 0 dBm −1.4/+0.3 dB A IN −55°C < T < +125°C; P = −45 dBm −1.4/+0.8 dB A IN Logarithmic Slope −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm 59 mV/dB IN Logarithmic Intercept −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm −65 dBm IN Deviation from CW Response 12.16 dB peak-to-rms ratio (four-carrier W-CDMA) −0.1 dB (−45 dBm to −5 dBm) 11.58 dB peak-to-rms ratio (LTE TM1, one-carrier, 20 MHz −0.2 dB bandwidth) 10.56 dB peak-to-rms ratio (W-CDMA) 0.05 dB 7.4 dB peak-to-rms ratio (64 QAM) −0.1 dB Rev. A | Page 3 of 32

ADL5906 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit 1900 MHz ±1.0 dB Dynamic Range CW input, T = 25°C 66 dB A Maximum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm 6 dBm Minimum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm −60 dBm Deviation vs. Temperature Deviation from output at 25°C, V = 0.35 V TADJ −40°C < T < +85°C; P = 0 dBm −0.8/+0.2 dB A IN −40°C < T < +85°C; P = −45 dBm −0.8/+0.5 dB A IN −55°C < T < +125°C; P = 0 dBm −1.4/+0.2 dB A IN −55°C < T < +125°C; P = −45 dBm −1.2/+0.9 dB A IN Logarithmic Slope −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm 57 mV/dB IN Logarithmic Intercept −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm −65 dBm IN 2140 MHz ±1.0 dB Dynamic Range CW input, T = 25°C 67 dB A Maximum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm 7 dBm Minimum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm −60 dBm Deviation vs. Temperature Deviation from output at 25°C, V = 0.35 V TADJ −40°C < T < +85°C; P = 0 dBm −0.8/+0.3 dB A IN −40°C < T < +85°C; P = −45 dBm −0.8/+0.6 dB A IN −55°C < T < +125°C; P = 0 dBm −1.3/+0.3 dB A IN −55°C < T < +125°C; P = −45 dBm −1.2/+0.9 dB A IN Logarithmic Slope −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm 56 mV/dB IN Logarithmic Intercept −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm −65 dBm IN Deviation from CW Response 12.16 dB peak-to-rms ratio (four-carrier W-CDMA) −0.1 dB (−45 dBm to −5 dBm) 11.58 dB peak-to-rms ratio (LTE TM1, one-carrier, 20 MHz 0.1 dB bandwidth) 10.56 dB peak-to-rms ratio (one-carrier W-CDMA) 0.1 dB 7.4 dB peak-to-rms ratio (64 QAM) −0.1 dB 2600 MHz ±1.0 dB Dynamic Range CW input, T = 25°C 68 dB A Maximum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm 8 dBm Minimum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm −60 dBm Deviation vs. Temperature Deviation from output at 25°C, V = 0.4 V TADJ −40°C < T < +85°C; P = 0 dBm −0.9/+0.3 dB A IN −40°C < T < +85°C; P = −45 dBm −1/+0.5 dB A IN −55°C < T < +125°C; P = 0 dBm −1.4/+0.3 dB A IN −55°C < T < +125°C; P = −45 dBm −1.4/+0.8 dB A IN Logarithmic Slope −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm 55 mV/dB IN Logarithmic Intercept −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm −65 dBm IN 3500 MHz ±1.0 dB Dynamic Range CW input, T = 25°C 65 dB A Maximum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm 5 dBm Minimum Input Level, ±1.0 dB Calibration at −55 dBm, −40 dBm, and 0 dBm −60 dBm Deviation vs. Temperature Deviation from output at 25°C, V = 0.45 V TADJ −40°C < T < +85°C; P = 0 dBm −1.5/0 dB A IN −40°C < T < +85°C; P = −45 dBm −1/+0.3 dB A IN −55°C < T < +125°C; P = 0 dBm −1.5/0 dB A IN −55°C < T < +125°C; P = −45 dBm −1.4/+0.4 dB A IN Logarithmic Slope −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm 52 mV/dB IN Logarithmic Intercept −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm −64 dBm IN Rev. A | Page 4 of 32

Data Sheet ADL5906 Parameter Test Conditions/Comments Min Typ Max Unit 5800 MHz ±1.0 dB Dynamic Range CW input, T = 25°C 57 dB A Maximum Input Level, ±1.0 dB Calibration at −50 dBm, −40 dBm, and 0 dBm 3 dBm Minimum Input Level, ±1.0 dB Calibration at −50 dBm, −40 dBm, and 0 dBm −54 dBm Deviation vs. Temperature Deviation from output at 25°C, V = 1 V TADJ −40°C < T < +85°C; P = 0 dBm −2.4/+0 dB A IN −40°C < T < +85°C; P = −45 dBm −1.4/-0.2 dB A IN −55°C < T < +125°C; P = 0 dBm −3.6/+0 dB A IN −55°C < T < +125°C; P = −45 dBm −2.1/-0.2 dB A IN Logarithmic Slope −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm 42 mV/dB IN Logarithmic Intercept −65 dBm < P < +10 dBm; calibration at −40 dBm and 0 dBm −60 dBm IN OUTPUT INTERFACE VRMS (Pin 6) Output Swing, Controller Mode Swing range minimum, R ≥ 500 Ω to ground 0.05 V L Swing range maximum, R ≥ 500 Ω to ground 3.92 V L Current Source/Sink Capability 10/10 mA Rise Time P = off to −10 dBm, 10% to 90%, C = 1 nF 0.1 µs IN RMS Fall Time P = −10 dBm to off, 90% to 10%, C = 1 nF 14.6 µs IN RMS SETPOINT INPUT VSET (Pin 7) Voltage Range Log conformance error ≤ 1 dB, minimum 2.14 GHz 3.92 V Log conformance error ≤ 1 dB, maximum 2.14 GHz 0.4 V Input Resistance 72 kΩ Logarithmic Scale Factor f = 2.14 GHz 56 mV/dB Logarithmic Intercept f = 2.14 GHz −65 dBm TEMPERATURE COMPENSATION TADJ/PWDN (Pin 1) Input Voltage Range 0 V V POS Input Bias Current V = 0.35 V 5 µA TADJ Input Resistance V = 0.35 V 70 kΩ TADJ VOLTAGE REFERENCE VREF (Pin 11) Output Voltage P = −55 dBm 2.3 V IN Temperature Sensitivity 25°C ≤ T ≤ 125°C −0.12 mV/°C A −55°C ≤ T ≤ +25°C 0.07 mV/°C A Short-Circuit Current Source/ 25°C ≤ T ≤ 125°C 4/0.05 mA A Sink Capability −55°C ≤ T ≤ +25°C 3/0.05 mA A Voltage Regulation T = 25°C, I = 2 mA −0.4 % A LOAD TEMPERATURE REFERENCE VTEMP (Pin 8) Output Voltage T = 25°C, R ≥ 10 kΩ 1.4 V A L Temperature Coefficient −40°C ≤ T ≤ +125°C, R ≥ 10 kΩ 4.8 mV/°C A L Short-Circuit Current Source/ 25°C ≤ T ≤ 125°C 4/0.05 mA A Sink Capability −55°C ≤ T ≤ +25°C 3/0.05 mA A Voltage Regulation T = 25°C, I = 1 mA −2.8 % A LOAD RMS TARGET INTERFACE VTGT (Pin 12) Input Voltage Range 0.2 2.5 V Input Bias Current V = 0.8 V 8 µA TGT Input Resistance 100 kΩ POWER-DOWN INTERFACE VTADJ/PWDN (Pin 1) Voltage Level to Enable V decreasing 1.3 V PWDN Voltage Level to Disable V increasing 1.4 V PWDN Input Bias Current V = 5 V 72 µA PWDN V = 0 V 0.1 µA PWDN Enable Time V low to V , 10% to 90%, C = 1 nF, P = 0 dBm 1.4 µs PWDN RMS RMS IN Disable Time V high to V , 90% to 10%, C = 1 nF, P = 0 dBm 1.0 µs PWDN RMS RMS IN Rev. A | Page 5 of 32

ADL5906 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY INTERFACE VPOS1, VPOS2 (Pin 3, Pin 10) Supply Voltage 4.75 5 5.25 V Quiescent Current T = 25°C, P < −60 dBm 68 mA A IN T = 125°C, P < −60 dBm 86 mA A IN Power-Down Current V > 1.4 V 250 µA PWDN Rev. A | Page 6 of 32

Data Sheet ADL5906 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage, VPOS1, VPOS2 5.25 V other conditions above those indicated in the operational Input Average RF Power1 21 dBm section of this specification is not implied. Exposure to absolute Equivalent Voltage, Sine Wave Input 2.51 V p-p maximum rating conditions for extended periods may affect Internal Power Dissipation 550 mW device reliability. θ 2 10.6°C/W JC θ 2 35.3°C/W JB θ 2 57.2°C/W JA ESD CAUTION Ψ 2 1.0°C/W JT Ψ 2 34°C/W JB Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +105°C (ADL5906ACPZN) Operating Temperature Range −55°C to +125°C (ADL5906SCPZN) Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C 1 This is for long durations. Excursions above this level, with durations much less than 1 second, are possible without damage. 2 No airflow with the exposed pad soldered to a 4-layer JEDEC board. Rev. A | Page 7 of 32

ADL5906 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS – + N N CIN IFR IFR CIN 6 5 4 3 1 1 1 1 PIN1 TADJ/PWDN 1 INDICATOR 12VTGT NIC 2 11VREF ADL5906 VPOS1 3 TOPVIEW 10VPOS2 GND1 4 (NottoScale) 9 GND2 5 6 7 8 S S T P M M E M RC RV SV ET V NOTES 1.NIC = NO INTERNAL CONNECTION. DO NOT CONNECTTO THIS PIN. 2 . OATFHN EDT HEEEXL PEPOCRTSINRETIDCEAPDAL CD CI RROCENUQNITUE ICBRTOEIOSA RNAD TG O(OP TCOHBDE) .T GHREORMUNADL 11287-002 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 TADJ/PWDN Temperature Compensation/Shutdown. This is a dual function pin used for controlling temperature slope compensation at voltages <1.0 V and/or for shutting down the device at voltages >1.4 V. The temperature compensation voltage is generally set by connecting this pin to VREF through a resistive voltage divider (see the Setting V section for additional information). See Figure 46 for an equivalent circuit. TADJ 2, 13, 16 NIC No Internal Connection. Do not connect to these pins. These pins are not internally connected. 3, 10 VPOS1, Power Supply. Because these pins are internally shorted, they must be connected to the same 5 V power VPOS2 supply. The power supply to each pin must also be decoupled using 100 pF and 100 nF capacitors located as close as possible to the pins. 4, 9 GND1, GND2 Ground. Connect both GND1 and GND2 to system ground using a low impedance path. 5 CRMS RMS Averaging Capacitor. Connect an rms averaging capacitor between CRMS and ground. See the Choosing a Value for C section for more information. See Figure 48 for an equivalent circuit. RMS 6 VRMS RMS Output. In measurement mode, this pin is connected to VSET either directly or through a resistor divider (when the slope is being increased). In controller mode, this pin is used to drive the gain control input of a voltage variable attenuator (VVA) or variable gain amplifier (VGA). See Figure 48 for an equivalent circuit. 7 VSET Setpoint Input. In measurement mode, this pin is connected to VRMS either directly or through a resistor divider. In controller mode, the voltage applied to this pin sets the decibel value of the required RF input level to balance the automatic power control loop. See Figure 47 for an equivalent circuit. 8 VTEMP Temperature Sensor Output of 1.4 V at 25°C with a Coefficient of 4.8 mV/°C. See Figure 43 for an equivalent circuit. 11 VREF Reference Voltage Output. This voltage reference has a nominal value of 2.3 V. This reference output voltage can be used to set the voltage to the TADJ/PWDN and VTGT pins. See Figure 44 for an equivalent circuit. 12 VTGT RMS Target Voltage. The voltage applied to this pin sets the target RF input at the output of the VGA that is also the rms squaring circuit. The recommended voltage for VTGT is 0.8 V. Increasing V above 0.8 V degrades the rms TGT accuracy of the ADL5906. Reducing V below 0.8 V can improve the rms accuracy for signals with very high crest TGT factors; however, it reduces the detection range of the ADL5906. See Figure 49 for an equivalent circuit. 14, 15 RFIN+, RFIN− RF Inputs. The RF inputs are normally applied single-ended with the RF input signal ac-coupled to RFIN+ and RFIN− ac-coupled to ground. See Figure 42 for an equivalent circuit. EPAD The exposed pad on the underside of the device (EPAD) is also internally connected to ground and requires a good thermal and electrical connection to the ground of the printed circuit board (PCB). Rev. A | Page 8 of 32

Data Sheet ADL5906 TYPICAL PERFORMANCE CHARACTERISTICS VPOS1 = VPOS2 = 5 V, single-ended input drive, VRMS connected to VSET, V = 0.8 V, C = 0.1 µF, T = +25°C (green), TGT RMS A −55°C (light blue), −40°C (blue), +85°C (red), +105°C (orange), and +125°C (black), where appropriate. Error referred to slope and intercept at indicated calibration points. Input RF signal is a sine wave (CW), unless otherwise indicated. 4.0 4.0 100MHzTO 1GHz 0dBm 3.5 3.5 –10dBm GE (V)23..50 234GGGHHHzzz GE (V)23..50 –20dBm A 5GHz A VOLT2.0 67GGHHzz VOLT2.0 –30dBm UTPUT 1.5 1089GGGHHHzzz UTPUT 1.5 –40dBm O O 1.0 1.0 –50dBm 0.5 20MHz 0.5 10MHz 0–65–60–55–50–45–40–35P–IN3 0(d–B2m5)–20–15–10 –5 0 5 10 11287-003 00.01 0.1FREQUENCY (GHz)1 10 11287-006 Figure 3. Typical VRMS vs. Input Power (dBm) vs. Frequency Figure 6. Typical VRMS vs. Frequency for Six RF Input Levels (10 MHz to 10 GHz) at 25°C 6.0 6 6.0 6 CW CW 5.5 QPSK PEP = 3.8dB 5 5.5 QPSK PEP = 3.8dB 5 16 QAM PEP = 6.3dB 16 QAM PEP = 6.3dB 5.0 64 QAM PEP = 7.4dB 4 5.0 64 QAM PEP = 7.4dB 4 4.5 3 4.5 3 V) V) E (4.0 2 E (4.0 2 VOLTAG33..05 01 OR (dB) VOLTAG33..05 01 OR (dB) PUT 2.5 –1 ERR PUT 2.5 –1 ERR UT2.0 –2 UT 2 –2 O O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0 –6 0 –6 –65 –55 –45 –3P5IN (dBm–2)5 –15 –5 5 11287-104 –65 –55 –45 –3P5IN (dBm–2)5 –15 –5 5 11287-007 Figure 4. Error from CW Linear Reference vs. Signal Modulation Figure 7. Error from CW Linear Reference vs. Signal Modulation (QPSK, 16 QAM, 64 QAM), Frequency = 900 MHz, CRMS = 0.1 µF, (QPSK, 16 QAM, 64 QAM), Frequency = 2.14 GHz, CRMS = 0.1 µF, Three Point Calibration at 0 dBm, −40 dBm, and −55 dBm Three Point Calibration at 0 dBm, −40 dBm, and −55 dBm 6.0 6 6.0 6 CW CW 5.5 CDMA 2000 PEP =11.02dB 5 5.5 LTE TM1 1CR 20MHz PEP =11.58dB 5 1CW-CDMA PEP = 10.56dB 5.0 4CW-CDMA PEP = 12.08dB 4 5.0 4 4.5 3 4.5 3 OUTPUT VOLTAGE (V)22334.....05050 ––01221 ERROR (dB) OUTPUT VOLTAGE (V)2334....25050 ––01221 ERROR (dB) 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0–65 –55 –45 –3P5IN (dBm–2)5 –15 –5 5–6 11287-005 0–65 –55 –45 –3P5IN (dBm–2)5 –15 –5 5–6 11287-008 Figure 5. Error from CW Linear Reference vs. Signal Modulation (CDMA 2000, Figure 8. Error from CW Linear Reference vs. Signal Modulation One-Carrier W-CDMA, Four-Carrier W-CDMA), Frequency = 2.14 GHz, (LTE TM1 One-Carrier, 20 MHz), Frequency = 2.14 GHz, CRMS = 0.1 µF, CRMS = 0.1 µF, Three Point Calibration at 0 dBm, −40 dBm, and −55 dBm Three Point Calibration at 0 dBm, −40 dBm, and −55 dBm Rev. A | Page 9 of 32

ADL5906 Data Sheet 6.0 6 6.0 6 5.5 VCTAALDIJB R= A0T.3I5OVNAT 0dBm, –40dBm,AND –55dBm 5 5.5 VTADJ = 0.35V 5 5.0 4 5.0 4 4.5 3 4.5 3 V)V) V) E (E (4.0 2 E (4.0 2 VOLTAGVOLTAG33..05 01 OR (dB) VOLTAG33..05 01 OR (dB) PUT PUT 2.5 –1 ERR PUT 2.5 –1 ERR UTUT2.0 –2 UT2.0 –2 OO O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0 –6 0 –6 –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 11287-009 –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 11287-012 Figure 9. VRMS and Log Conformance Error vs. Input Level and Temperature at Figure 12. Distribution of Log Conformance Error with Respect to VRMS at 100 MHz 25°C vs. Input Level and Temperature at 100 MHz 6.0 6 6.0 6 VTADJ = 0.35V VTADJ = 0.35V 5.5 CALIBRATIONAT 0dBm, –40dBm,AND –55dBm 5 5.5 5 5.0 4 5.0 4 4.5 3 4.5 3 V)V) V) E (E (4.0 2 E (4.0 2 VOLTAGVOLTAG33..05 01 OR (dB) VOLTAG33..05 10 OR (dB) PUT PUT 2.5 –1 ERR PUT 2.5 –1 ERR UTUT2.0 –2 UT2.0 –2 OO O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0 –6 0 –6 –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 11287-010 –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 1287-0131 Figure 10. VRMS and Log Conformance Error vs. Input Level and Temperature Figure 13. Distribution of Log Conformance Error with Respect to VRMS at at 700 MHz 25°C vs. Input Level and Temperature at 700 MHz 6.0 6 6.0 6 VTADJ = 0.35V VTADJ = 0.35V 5.5 CALIBRATIONAT 0dBm, –40dBm,AND –55dBm 5 5.5 5 5.0 4 5.0 4 4.5 3 4.5 3 V)V) V) E (E (4.0 2 E (4.0 2 PUT VOLTAGPUT VOLTAG233...505 01–1 ERROR (dB) PUT VOLTAG233...505 –011 ERROR (dB) UTUT2.0 –2 UT2.0 –2 OO O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0 –6 0 –6 –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 11287-011 –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 11287-014 Figure 11. VRMS and Log Conformance Error vs. Input Level and Temperature Figure 14. Distribution of Log Conformance Error with Respect to VRMS at at 900 MHz 25°C vs. Input Level and Temperature at 900 MHz Rev. A | Page 10 of 32

Data Sheet ADL5906 6.0 6 6.0 6 VTADJ = 0.35V VTADJ = 0.35V 5.5 CALIBRATIONAT 0dBm, –40dBm,AND –55dBm 5 5.5 5 5.0 4 5.0 4 4.5 3 4.5 3 V)V) V) E (E (4.0 2 E (4.0 2 VOLTAGVOLTAG33..05 01 OR (dB) VOLTAG33..05 01 OR (dB) PUT PUT 2.5 –1 ERR PUT 2.5 –1 ERR UTUT2.0 –2 UT2.0 –2 OO O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-015 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-018 Figure 15. VRMS and Log Conformance Error vs. Input Level and Temperature Figure 18. Distribution of Log Conformance Error with Respect to VRMS at at 1.9 GHz 25°C vs. Input Level and Temperature at 1.9 GHz 6.0 6 6.0 6 VTADJ = 0.35V VTADJ = 0.35V 5.5 CALIBRATIONAT 0dBm, –40dBm,AND –55dBm 5 5.5 5 5.0 4 5.0 4 4.5 3 4.5 3 V)V) V) E (E (4.0 2 E (4.0 2 PUT VOLTAGPUT VOLTAG233...505 01–1 ERROR (dB) PUT VOLTAG233...505 –011 ERROR (dB) UTUT2.0 –2 UT2.0 –2 OO O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-016 0–65 –55 –45 –3P5IN (dBm–2)5 –15 –5 5–6 11287-019 Figure 16. VRMS and Log Conformance Error vs. Input Level and Temperature Figure 19. Distribution of Log Conformance Error with Respect to VRMS at at 2.14 GHz 25°C vs. Input Level and Temperature at 2.14 GHz 6.0 6 6.0 6 VTADJ = 0.4V VTADJ = 0.4V 5.5 CALIBRATIONAT 0dBm, –40dBm,AND –55dBm 5 5.5 5 5.0 4 5.0 4 4.5 3 4.5 3 V)V) V) E (E (4.0 2 E (4.0 2 PUT VOLTAGPUT VOLTAG233...505 01–1 ERROR (dB) PUT VOLTAG233...505 –011 ERROR (dB) UTUT2.0 –2 UT2.0 –2 OO O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-017 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-020 Figure 17. VRMS and Log Conformance Error vs. Input Level and Temperature Figure 20. Distribution of Log Conformance Error with Respect to VRMS at at 2.6 GHz 25°C vs. Input Level and Temperature at 2.6 GHz Rev. A | Page 11 of 32

ADL5906 Data Sheet 6.0 6 6.0 6 VTADJ = 0.45V VTADJ = 0.45V 5.5 CALIBRATIONAT 0dBm, –40dBm,AND –55dBm 5 5.5 5 5.0 4 5.0 4 4.5 3 4.5 3 V)V) V) E (E (4.0 2 E (4.0 2 VOLTAGVOLTAG33..05 01 OR (dB) VOLTAG33..05 01 OR (dB) PUT PUT 2.5 –1 ERR PUT 2.5 –1 ERR UTUT2.0 –2 UT2.0 –2 OO O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-021 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-024 Figure 21. VRMS and Log Conformance Error vs. Input Level and Temperature Figure 24. Distribution of Log Conformance Error with Respect to VRMS at at 3.5 GHz 25°C vs. Input Level and Temperature at 3.5 GHz 3.00 6 6.0 6 VTADJ = 1V VTADJ = 1V 2.75 CALIBRATIONAT 0dBm, –40dBm,AND –50dBm 5 5.5 5 2.50 4 5.0 4 2.25 3 4.5 3 UTPUT VOLTAGE (V)11112.....0257005050 012––21 ERROR (dB) UTPUT VOLTAGE (V)22334.....05050 012––21 ERROR (dB) O O 0.75 –3 1.5 –3 0.50 –4 1.0 –4 0.25 –5 0.5 –5 0 –6 0 –6 –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 11287-022 –60 –50 –40 –3P0IN (dBm–2)0 –10 0 10 11287-025 Figure 22. VRMS and Log Conformance Error vs. Input Level and Temperature Figure 25. Distribution of Log Conformance Error with Respect to VRMS at at 5.8 GHz 25°C vs. Input Level and Temperature at 5.8 GHz 3.00 6 3.00 6 2.75 VCTAALDIJB R= A1TVIONAT 0dBm, –20dBm,AND –35dBm 5 2.75 VCTAALDIJB R= A1TVIONAT 0dBm, –10dBm,AND –20dBm 5 2.50 4 2.50 4 OUTPUT VOLTAGE (V)111122......025702050505 0123––21 ERROR (dB) OUTPUT VOLTAGE (V)111122......025702050505 0123––21 ERROR (dB) 0.75 –3 0.75 –3 0.50 –4 0.50 –4 0.25 –5 0.25 –5 0–45 –35 –25 PIN (d–B1m5) –5 5 –6 11287-023 0–35 –25 PIN– (1d5Bm) –5 5–6 11287-026 Figure 23. VRMS and Log Conformance Error vs. Input Level and Temperature Figure 26. VRMS and Log Conformance Error vs. Input Level and Temperature at 8 GHz at 10 GHz Rev. A | Page 12 of 32

Data Sheet ADL5906 1000 6.0 REPRESENTS 4500PARTS 5.5 RF BURST PULSE 5.0 800 4.5 4.0 0dBm NT600 T (V)3.5 –10dBm COU400 OUTPU23..50 –20dBm –30dBm 2.0 –40dBm 1.5 200 1.0 0.5 02.8 2.9 3.0 3.V1RMS (V3).2 3.3 3.4 3.5 11287-027 00 0.5 1.0 1.5 2.0TIM2E. 5(ms)3.0 3.5 4.0 4.5 5.0 11287-030 Figure 27. Distribution of VRMS, PIN = −10 dBm, 900 MHz Figure 30. Output Response to RF Burst Input, Carrier Frequency = 2.14 GHz, CRMS = 0.1 µF 1000 6.0 REPRESENTS 4500PARTS 5.5 TADJ/PWDN PULSE 5.0 800 4.5 V) E (4.0 0dBm S600 AG3.5 COUNT T VOLT3.0 ––1200ddBBmm 400 TPU2.5 –30dBm U2.0 O –40dBm 1.5 200 1.0 0.5 00.8 0.9 1.0 1.1VRMS (V1).2 1.3 1.4 1.5 11287-028 00 2 4 6 8 T1I0ME (1µ2s) 14 16 18 20 22 11287-031 Figure 28. Distribution of VRMS, PIN = −45 dBm, 900 MHz Figure 31. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency = 2.14 GHz, CRMS = 1 nF 6.0 6.0 5.5 RF BURST PULSE 5.5 TADJ/PWDN PULSE 5.0 5.0 OUTPUT VOLTAGE (V)223344......050505 ––––21403000d0ddddBBBBBmmmmm OUTPUT VOLTAGE (V)223344......050505 –––210300d0dddBBBBmmmm 1.5 1.5 –40dBm 1.0 1.0 0.5 0.5 00 5 10 15 20TIM2E5 (µs)30 35 40 45 50 11287-029 00 0.5 1.0TIME (ms)1.5 2.0 2.5 11287-032 Figure 29. Output Response to RF Burst Input, Carrier Frequency = 2.14 GHz, Figure 32. Output Response Using Power-Down Mode for Various RF Input CRMS = 1 nF Levels, Carrier Frequency = 2.14 GHz, CRMS = 0.1 µF Rev. A | Page 13 of 32

ADL5906 Data Sheet 240 40 220 Hz) 200 30 √ PECTRAL DENSITY (nV/ 11111024688000000 HANGE IN V (mV)REF–1120000 S C E 60 –20 S NOI 40 –30 20 0100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 11287-033 –40–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 11287-036 Figure 33. Noise Spectral Density of VRMS, PIN = −10 dBm, −35 dBm, and Figure 36. Change in VREF vs. Temperature with Respect to 25°C, −60 dBm (No Change in NSD vs. PIN), CRMS = 0.1 µF PIN = −40 dBm 2.5 5 1000 REPRESENTS 4500PARTS 2.3 4 2.1 3 800 1.9 2 V (V)TEMP11..57 01 RROR (°C) COUNT600 1.3 –1 E 400 1.1 –2 0.9 –3 200 0.7 –4 0.5–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125–5 11287-034 02.25 2.26 2.27VREF 2B.I2A8S VOL2T.2A9GE (V2).30 2.31 2.32 1287-0371 Figure 34. VTEMP and Linearity Error with Respect to Straight Line vs. Figure 37. Distribution of VREF at 25°C, No RF Input Temperature for Typical Device 1000 100 REPRESENTS 4500PARTS 800 A) VPWDN VPWDN m DECREASING INCREASING T ( 10 600 N T E N R U R O U C C 400 LY P P 1 U S 200 01.32 1.34 1.3V6TEMP V1O.3L8TAGE (V1).40 1.42 1.44 11287-035 0.11.20 1.25 1.30VPWDN (V1).35 1.40 1.45 11287-038 Figure 35. Distribution of VTEMP at 25°C, No RF Input Figure 38. Supply Current vs. VPWDN Rev. A | Page 14 of 32

Data Sheet ADL5906 90 10 85 0 mA) 80 dB) T ( 75 S( N S E O R L –10 UR 70 RN C U PLY 65 RET P U –20 S 60 5505–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 11287-004 –30START10MHz 1GHz/DIV STOP10GHz 11287-040 Figure 39. Supply Current vs. Temperature Figure 40. Return Loss at RF Input Port, 10 MHz to 10 GHz Rev. A | Page 15 of 32

ADL5906 Data Sheet THEORY OF OPERATION The ADL5906 is functionally nearly identical to the ADL5902 The VGA output is but has a broader frequency range (10 MHz to 10 GHz). It is a VSIG = GSET × RFIN = GO × RFIN e−(VSET/VGNS) (2) true rms responding detector with a 67 dB measurement range where RF is the ac voltage applied to the input terminals of the at 2.14 GHz and a greater than 57 dB measurement range at IN ADL5906. frequencies up to 5.8 GHz. It is pin compatible with the ADL5902 and AD8363. Transfer function peak-to-peak ripple is <±0.3 dB The output of the VGA, VSIG, is applied to a wideband square law over the entire dynamic range. Temperature stability of the rms detector. The detector provides the true rms response of the RF output measurements provides <±1 dB error typical over the input signal, independent of waveform. The detector output, ISQR, is temperature range of −40°C to +125°C up to 3.5 GHz. The device a fluctuating current with a positive mean value. The difference accurately measures waveforms that have a high peak-to-rms between ISQR and an internally generated current, ITGT, is integrated ratio (crest factor). by the parallel combination of CF and the external capacitor attached to the CRMS pin at the summing node. C is an on-chip The ADL5906 consists of a high performance automatic gain F 26 pF filter capacitor, and C , the external capacitance connected control (AGC) loop. As shown in Figure 41, the AGC loop RMS to the CRMS pin, can be used to arbitrarily increase the averaging comprises a wide bandwidth variable gain amplifier (VGA), square time while trading off with the response time. When the AGC law detectors, an amplitude target circuit, and an output driver. loop is at equilibrium The nomenclature used in this data sheet to distinguish between Mean(I ) = I (3) a pin name and the signal on that pin is as follows: SQR TGT This equilibrium occurs only when • The pin name is all uppercase, for example, CRMS, VSET, and VRMS. Mean(VSIG2) = VTGT2 (4) • The signal name or a value associated with that pin is the where V is the voltage presented at the VTGT pin. This pin TGT pin mnemonic with a partial subscript, for example, CRMS, can conveniently be connected to the VREF pin through a voltage VSET, and VRMS. divider to establish a target rms voltage, VATG, of ~40 mV rms when V = 0.8 V. SQUARE LAW DETECTOR AND AMPLITUDE TARGET TGT The VGA gain has the form Because the square law detectors are electrically identical and well matched, process and temperature dependent variations GSET = GO e−(VSET/VGNS) (1) are effectively cancelled. where: G is the basic fixed gain. O V is a scaling voltage that defines the gain slope (the decibel GNS change per voltage). The gain decreases with increasing VSET. VPOS1/VPOS2 CH (INTERNAL) SUMMING VTGT NODE VATG= 20 RFIN+ VSIG ISQR ITGT VGA X2 X2 VTGT RFIN– GSET CRMS VSET CRMS CF VRMS (EXTERNAL) (INTERNAL) GND1/GND2 TEMPERATURECOMPENSATION ANDBIAS TADJ/PWDN TEMPERATURE SENSOR VTEMP(1.4V) RBEAFNEDR EGNACPE VREF(2.3V) 11287-041 Figure 41. Simplified Architecture Details Rev. A | Page 16 of 32

Data Sheet ADL5906 When forcing the previous identity by varying the VGA setpoint, it VBIAS is apparent that VPOS RMS(V ) = √(Mean(V 2)) = √(V 2) = V (5) ESD ESD SIG SIG ATG ATG Substituting the value of V from Equation 2 results in 2.5kΩ 2.5kΩ SIG RMS(G0 × RFIN e−(VSET/VGNS)) = VATG (6) RFIN+ LOAD RFIN– When connected as a measurement device, V = V . Solving SET RMS for V as a function of RF , RMS IN V = V × log (RMS(RF )/V ) (7) RMS SLOPE 10 IN Z ESD ESD ESD ESD ESD where: VVSZL OisP Et h=e 1 i.n1t2e rVce/dpet cvaodltea (goer. 56 mV/dB) at 2.14 GHz. GND ESD ESD ESD ESD ESD ESD 11287-141 Figure 42. RF Inputs When RMS(RF ) = V , this implies that V = 0 V because IN Z RMS log (1) = 0. This makes the intercept the input that forces V = Extensive ESD protection is employed on the RF inputs, and this 10 RMS 0 V if the ADL5906 had no sensitivity limit. protection limits the maximum possible input to the ADL5906. In most applications, the AGC loop is closed through the setpoint TEMPERATURE SENSOR INTERFACE interface and the VSET pin. In measurement mode, VRMS is The ADL5906 provides a temperature sensor output with a scaling directly connected to VSET (see the Measurement Mode Basic factor of the output voltage of approximately 4.8 mV/°C. The Connections section for more information). In controller mode, output is capable of sourcing 4 mA and sinking 50 µA maximum a control voltage is applied to VSET, and the VRMS pin typically at 25°C. An external resistor can be connected from VTEMP to drives the control input of an amplification or attenuation system. GND to provide additional current sink capability. The typical In this case, the voltage at the VSET pin forces a signal amplitude output voltage at 25°C is approximately 1.4 V. at the RF inputs of the ADL5906 that balances the system through VPOS feedback. INTERNAL RF INPUT INTERFACE VPAT VTEMP Figure 42 shows the RF input connections within the ADL5906. 12kΩ Two internal 2.5 kΩ resistors connected between RFIN+ and RFIN− primarily set the input impedance. A dc level of approximately 4kΩ hthaelf c tehnet esru pppoliyn tv ooflt tahgee boina se arecshi sptoinr si.s E eistthaebrl itshhee dR FinINter+n oarll yth aet GND 11287-042 Figure 43. TEMP Interface Simplified Schematic RFIN− pin can be used as the single-ended RF input pin. Connect signal coupling capacitors from the input signal to the RFIN+ VREF INTERFACE and RFIN− pins. A single external 60.4 Ω resistor to ground The VREF pin provides an internally generated voltage reference from the desired input creates an equivalent 50 Ω impedance for the user. The VREF voltage is a temperature stable 2.3 V over a broad section of the operating frequency range. RF ac-couple reference that is capable of sourcing 4 mA and sinking 50 µA the other input pin to common (ground). The input signal high- maximum. An external resistor can be connected from VREF pass corner formed by the internal and external resistances of to GND to provide additional current sink capability. The the input coupling capacitor is voltage on this pin can be used to drive the TADJ/PWDN and f = 1/(2 × π × 50 × C) (8) VTGT pins. HIGHPASS where C is the capacitance in farads, and f is in hertz. VPOS HIGHPASS The input coupling capacitors must be large enough in value to INTERNAL VOLTAGE pass the input signal frequency of interest and determine the low VREF end of the frequency response. RFIN+ and RFIN− can also be driven differentially using a balun. 16kΩ GND 11287-143 Figure 44. VREF Interface Simplified Schematic Rev. A | Page 17 of 32

ADL5906 Data Sheet TEMPERATURE COMPENSATION INTERFACE 3.70 The ADL5906 has a TADJ pin that provides the ability to optimize 3.65 temperature performance using proprietary techniques as in 3.60 the ADL5902. Just like the ADL5902, the ADL5906 has dual V) 3.55 functionality on Pin 1, TADJ/PWDN; however, the PWDN AGE ( 3.50 function was redesigned to be driven by CMOS logic as low LT as 1.8 V. For more detail on the power-down interface, see the T VO 3.45 Power-Down Interface section. PU 3.40 T U O 3.35 For optimal performance, the output temperature drift must be compensated using the TADJ pin. The absolute value of 3.30 compensation varies with frequency and VTGT. For recommended 3.25 OVTnAeD Jd viaffleureesn acte p ionp tuhlea rte fmrepqeureantucirees c, oseme pthene sSaettitoinn go Vf tThAe DADJ sLe5c9ti0o6n . 3.200 0.1 0.2 0.3 VT0A.D4J VO0.L5TAG0E.6 (V) 0.7 0.8 0.9 1.0 11287-043 compared to the ADL5902 is that VTADJ adjusts the slope of the Figure 45. Effect of VTADJ at Various Temperatures, 2.14 GHz, 0 dBm detector, and with the ADL5902, the intercept was adjusted. Varying V has only a very slight effect on VRMS at device TADJ Adjusting the slope was found beneficial to locking in temperature temperatures near 25°C; however, the compensation circuit has drift and thereby producing parallel error curves over most increasing effect as the temperature departs farther from 25°C. frequencies. Any remaining intercept temperature drift can then be reduced in the digital domain after sampling V It is important to note that the slope is adjusted vs. temperature. RMS The pivot point of this is at low input power levels and thereby because the intercept drift is quite repeatable at frequencies moves the V output more at larger input signal levels; that up to approximately 5.8 GHz (see the Using VTEMP to RMS is, near maximum input power, the temperature drift can be Improve Intercept Temperature Drift section). minimized the most. This is advantageous in most power There is a trade-off in setting values, and optimizing for one measurement cases because errors at larger powers tend to have area of the dynamic range may mean less than optimal drift more of a negative effect. performance at other input amplitudes. In addition, different voltages applied to the VTGT pin impact drift; all TADJ voltages The TADJ/PWDN pin has a nominal input resistance of 70 kΩ and shown in the performance curves were determined with a can be conveniently driven from an external source or from an attenuated value of VREF using a resistor divider. The resistors are VTGT of 0.8 V. For VTGT values that do not deviate too far shown in the evaluation board schematic (see Figure 63). The from the nominal 0.8 V, and for frequencies up to approximately 5 GHz, it is expected that the TADJ voltages are a good starting voltage range for VTADJ is from 0 V to approximately 1.0 V because point for the best temperature drift compensation. approximately 1.3 V is the logic threshold for power down of the device. Compensating the device for temperature drift using V allows TADJ for great flexibility. If the user requires minimum temperature drift at a given input power, a subset of the dynamic range, or even over a different temperature range than shown in this data sheet, the V can be swept while monitoring V over the TADJ RMS temperature at the frequency and amplitude of interest. The optimal VTADJ to achieve minimum temperature drift at a given power and frequency is the value of V where the output has TADJ minimum movement. Rev. A | Page 18 of 32

Data Sheet ADL5906 POWER-DOWN INTERFACE OUTPUT INTERFACE Figure 46 shows a simplified schematic representation of the The ADL5906 incorporates rail-to-rail output drivers with pull-up TADJ/PWDN interface. and pull-down capabilities. The level shift circuitry and the output amplifier are very fast compared to the typical rms response The quiescent and power-down currents for the ADL5906 at required by a complex waveform. In essence, the output stage from 25°C are approximately 68 mA and 250 µA, respectively. The the CRMS pin to the VRMS output is only a dc signal because dual function TADJ/PWDN pin is connected to the temperature by definition V is supposed to be a single rms value. The compensation circuit as well as the power-down circuit. The RMS VRMS pin can source and sink up to 10 mA. temperature compensation circuit responds only to voltages between 0 V and 1 V. When the voltage on this pin is greater than VPOS ~1.4 V, the device is fully powered down. Figure 38 shows this ESD ISQR characteristic as a function of V . The TADJ/PWDN pin with PWDN CRMS ~2.1V DC BIAS an internal 70 kΩ resistor to ground sinks approximately 26 µA at 1.8 V, 47 µA at 3.3 V, and 72 µA at 5 V. The source used to disable ESD LSEHVIFETL the ADL5906 must have a sufficiently high current capability for CIRCUITRY VRMS 2kΩ this reason. Figure 31 shows the typical response times for various ITGT ESD CRMS RvaFlu ien pinu at plepvreolxsi.m Tahtee loyu 1t2p uµts rfeoarc CheRMs Sw =it 1h innF 1; hdoBw oefv ietsr, sttheea dreyf estraetnec e EXTERNAL 26pF 500Ω GND 11287-046 voltage is available to full accuracy in a much shorter time. This Figure 48. VRMS Interface Simplified Schematic wake-up response varies depending on the input coupling and VTGT INTERFACE the value of C . RMS VPOS The target voltage can be set with an external source or by MAXIMUM connecting the VREF pin (nominally 2.3 V) to the VTGT pin OPERATING TEMPERATURE VOLTAGE = 1V COMPENSATION through a resistive voltage divider. With 0.8 V on the VTGT pin, CIRCUIT ESD the rms voltage that must be provided by the VGA to balance TADJ/ TADJ 1kΩ the AGC feedback loop is 0.8 V × 0.05 = 40 mV rms. Most of PWDN ESD 70kΩ 20kΩ the characterization information in this data sheet was collected 5 LOGIC ESD PWD = PWDN ×7 1kΩ at VTGT = 0.8 V. Voltages higher and lower than this can be used; THRESHOLD ~1.3V ± 0.1V however, doing so increases or decreases the gain at the internal 50kΩ LOGIC SHUTDOWN GND T~H1RVE ±S H0.O1VLD CIRCUIT 11287-044 sinq uinarteinrcge cpetl.l ,T whhiisc, hin r etsuurlnts, ianf fae cctosr rthesep soenndsiintigv iintyc raenadse t hore duescarbelaes e measurement range, in addition to the sensitivity to different Figure 46. TADJ/PWDN Interface Simplified Schematic carrier modulation schemes. As V decreases, the squaring TGT VSET INTERFACE circuits produce more noise; this becomes noticeable in the output The VSET interface has a high input impedance of 72 kΩ. The response at low input signal amplitudes. As V increases, TGT voltage at VSET is converted to an internal current used to set the measurement error due to modulation increases, and temperature internal VGA gain. The VGA attenuation control is approximately drift tends to decrease. The chosen VTGT value of 0.8 V represents a 18 dB/V. compromise between these characteristics. GAINADJUST VPOS 63kΩ VSET ESD g×X2 9kΩ VTGT 50kΩ ITGT 1kΩ ESD GND 11287-045 ESD 50kΩ 20kΩ Figure 47. VSET Interface Simplified Schematic GND 1287-0471 Figure 49. VTGT Interface Rev. A | Page 19 of 32

ADL5906 Data Sheet BASIS FOR ERROR CALCULATIONS MEASUREMENT MODE BASIC CONNECTIONS The slope and intercept used in the error plots are calculated using The basic connections circuit for ADL5906 is shown in Figure 51. the coefficients of a linear regression performed on data collected The ADL5906 requires a single supply of nominally 5 V. The in its central operating range. The error plots in the Typical supply is connected to the VPOS1 and VPOS2 supply pins. Performance Characteristics section are shown in two formats: Decouple each of these pins using two capacitors with values equal error from the ideal line and error with respect to the 25°C output or similar to those shown in Figure 51. Place these capacitors as voltage. The error from the ideal line is the decibel difference in close as possible to the VPOS pins. The three no connect pins V from the ideal straight-line fit of V calculated by the linear (NIC) are not internally connected. Leave these pins unconnected. RMS RMS regression fit over the linear range of the detector, typically at An external 60.4 Ω resistor combines with the relatively high RF 25°C. The error in decibels is calculated by input impedance of the ADL5906 to provide a broadband 50 Ω Error (dB) = (V − Slope × (P − P ))/Slope (9) match. Place an ac coupling capacitor between this resistor and RMS IN Z RFIN+. AC-couple the RFIN− input to ground using the same where P is the x-axis intercept expressed in decibels relative to Z value capacitor. To operate down to 10 MHz, the coupling 1 mW (the input amplitude that produces a 0 V output if such an capacitors must be at least 100 pF. output were possible). The ADL5906 is placed in measurement mode by connecting The error from the ideal line is not a measure of absolute accuracy the VRMS pin to the VSET pin. In measurement mode, the output because it is calculated using the slope and intercept of each device. voltage is proportional to the log of the rms input signal level. However, it verifies the linearity and the effect of temperature and modulation on the response of the device. An example of SETTING V TADJ this type of plot is Figure 9. The slope and intercept that form As described in the Theory of Operation section, the output the ideal line are those at 25°C with CW modulation. Figure 4, temperature drift can be compensated by applying a voltage to Figure 5, Figure 7, and Figure 8 show the error with various the TADJ pin. The compensating voltage varies with frequency. popular forms of modulation with respect to the ideal CW The voltage for the TADJ pin can be easily derived from a resistor line. This method for calculating error is accurate, assuming divider connected to the VREF pin. Table 4 shows the recommended that each device is calibrated at room temperature. V voltages for operation from −55°C to +125°C, along with TADJ In the second plot format, the VRMS voltage at a given input resistor divider values. Resistor values are chosen so that they amplitude and temperature is subtracted from the corresponding neither pull too much current from the VREF pin (I = 4 mA) OUTMAX VRMS at 25°C and then divided by the 25°C slope to obtain an error nor are so large that the maximum bias current at a VTADJ = 1 V in decibels. This type of plot does not provide any information (14 µA) affects the resulting voltage. on the linear-in-dB performance of the device; it merely shows The V function provides temperature compensation of TADJ the decibel equivalent of the deviation of V over temperature, RMS theoutput slope of the ADL5906. The Using VTEMP to Improve given a calibration at 25°C. When calculating error from any Intercept Temperature Drift section describes how the temperature one particular calibration point, this error format is accurate. It stability of the ADL5906 can be further improved. is accurate over the full range shown on the plot assuming that enough calibration points are used. Figure 12 shows this plot type. Table 4. Recommended V Voltages TADJ Frequency V (V) R9 (Ω) R12 (Ω) The error calculations for Figure 34 are similar to those for the TADJ 10 MHz to 2.14 GHz 0.35 1500 270 V plots. The slope and intercept of the V function vs. RMS TEMP temperature are determined and applied as follows: 2.6 GHz 0.4 1500 316 3.5 GHz 0.45 1500 365 Error (°C) = (V − Slope × (Temp − T ))/Slope (10) TEMP Z 5.8 GHz 1.0 1540 1200 where: 8 GHz 1.0 1540 1200 V is the voltage at the TEMP pin at that temperature. TEMP 10 GHz 1.0 1540 1200 Slope is, typically, 4.8 mV/°C. Temp is the ambient temperature of the ADL5906 in degrees Celsius. T is the x-axis intercept expressed in degrees Celsius (the Z temperature that would result in a V of 0 V if this were TEMP possible). Rev. A | Page 20 of 32

Data Sheet ADL5906 SETTING V Figure 50 shows how output noise varies with C when the TGT RMS ADL5906 is driven by a single-carrier W-CDMA signal (Test As described in the Theory of Operation section, setting the Model TM1-64, peak envelope power = 10.56 dB, bandwidth = voltage on VTGT to 0.8 V represents a compromise between 3.84 MHz). achieving excellent rms accuracy and maximizing dynamic range. The voltage on VTGT can be derived from the VREF pin using 350 1000000 OUTPUT NOISE (V p-p) a resistor divider, as shown Figure 51. Like the resistors chosen RISE TIME (µs) 300 FALL TIME (µs) 100000 to set the V voltage, the resistors setting V must have TADJ TGT rothera acsta oVunsRaeb EblFiea msv aculuusrter sed ntehtl iaevrte rdro ortos n. gIonetn apedurdlalit tetioo tonh ,em n VoutTceAh Dt hJc aeun rcdroe mVnbtT GifnrTo evdmo cl tVuargRreeEsnF. t SE (mV p-p)220500 110000000 LL TIME (µs) TVhReE vFa cluurerse snht oowf 1n. 7in m FAig. uTrhei s5 c1u arnredn Tt aisb wlee 4ll rbeeslouwlt itnh ea m maaxximimuumm PUT NOI150 100 TIME/FA specified VREF current of 4 mA. OUT100 10 RISE CHOOSING A VALUE FOR C RMS 50 1 C provides the averaging function for the internal rms RMS qcoumickpeustta rteiospno. nUssei ntigm teh teo ma ipnuilmseudm w avvaelufoer mfo rb CutR lMeSa vaellso swigsn tihfiec ant 01 10 CRM10S0 (nF) 1000 100000.1 11287-049 output noise on the output voltage signal. By the same token, a Figure 50. Output Noise, Rise and Fall Times vs. CRMS Capacitance, large filter capacitor reduces output noise but at the expense of Single-Carrier W-CDMA (TM1-64) at 2.14 GHz with PIN = 0 dBm response time. Figure 50 also shows how the response time is affected by the In applications where response time is not critical, a relatively large value of C . To measure this, an RF burst at 2.14 GHz at 0 dBm RMS capacitor can be placed on the CRMS pin. In Figure 51, a value was applied to the ADL5906. The 10% to 90% rise time and of 0.1 µF is used. For most signal modulation schemes, this value 90% to 10% fall time were then measured. ensures excellent rms measurement compliance and low residual output noise. There is no maximum capacitance limit for C . RMS +5V +5V C3 C7 0.1µF 0.1µF C4 C5 100pF 100pF VPOS1 VPOS2 3 10 ADL5906 TEMSPEENRSAOTRURE 8 VTEMP C10 10nF RFIN+ RFIN 14 ISQR RFIN– X2 VSET R3 15 7 60.4Ω LINEAR-IN-dB VGA C12 (NEGATIVE SLOPE) 10nF X2 ITGT VRMS NIC 2 G = 5 6 VRMS NIC 16 NIC 13 BDIOASWANN CDO PNOTWROELR V2R.3EVF CRMS EPAD 5 C9 26pF 0.1µF 1 11 12 9 4 ((SAENED TTEAXBTL)E) TADJ/ VREF VTGT GND2 GND1 PWDN R9 R10 R12 ((ASNEDE TTAEBXLTE)) 3.74kΩ 2Rk1Ω1 11287-148 Figure 51. Basic Connections for Operation in Measurement Mode Rev. A | Page 21 of 32

ADL5906 Data Sheet Table 5. Recommended Minimum C Values for Various Modulation Schemes RMS Peak Envelope Carrier Output Noise Rise/Fall Modulation/Standard Power Ratio (dB) Bandwidth (MHz) C (nF) (mV p-p) Time (µs) RMSMIN QPSK, 5 MSPS (SQR COS Filter, α = 0.35) 3.8 5 1 84 0.2/10 QPSK ,15 MSPS (SQR COS Filter, α = 0.35) 3.8 15 1 42 0.2/10 64 QAM, 1 MSPS (SQR COS Filter, α = 0.35) 7.4 1 10 265 3/85 64 QAM, 5 MSPS (SQR COS Filter, α = 0.35) 7.4 5 1 380 0.2/10 64 QAM, 13 MSPS (SQR COS Filter, α = 0.35) 7.4 13 1 205 0.2/10 W-CDMA, One-Carrier, TM1-64 10.56 3.84 1 820 0.2/10 W-CDMA Four-Carrier, TM1-64, TM1-32, TM1-16, TM1-8 12.08 18.84 1 640 0.2/10 LTE, TM1, One-Carrier, 20 MHz (2048 QPSK Subcarriers) 11.58 20 1 140 0.2/10 Table 5 shows the recommended minimum values of C for If only a part of the RF input power range of the ADL5906 is RMS popular modulation schemes. Using lower capacitor values results being used (for example, −10 dBm to −60 dBm), increase the in rms measurement errors. Output response time is also shown. scaling so that this reduced input range fits into the available If the output noise shown in Table 5 is unacceptably high, it can output swing (0 V to 3.9 V) of the ADL5906. be reduced by The output swing is reduced by simply adding a voltage divider on • Increasing C the output pin, as shown in the A side of Figure 52. Reducing the RMS • Implementing an averaging algorithm after the output voltage output scaling can be used when interfacing the ADL5906 to an of the ADL5906 has been sampled by an analog-to-digital ADC with a 0 V to 2.5 V input range. converter (ADC) The values in Table 5 were experimentally determined to be the R2 minimum capacitance that ensures good rms accuracy for that particular signal type. This test was carried out by starting out 7 VSET 7 VSET with a large capacitance value on the CRMS pin (for example, R6 10 µF). The value of VRMS was noted for a fixed input power level VRMS R1 VRMS 6 6 (for example, −10 dBm). The value of C was then progressively RMS R15 reduced (this can be done with press-down capacitors) until the value of V started to deviate from its original value (this RMS iannddi ctahtaets C thRMatS tish eb eaccocmuriancgy toofo t hsme ramll)s. computation is degrading A B 11287-149 In general, the minimum required rms averaging capacitance Figure 52. Decreasing and Increasing Slope increases as the peak-to-average ratio of the carrier increases. The The output voltage swing can be increased using a technique that is minimum required C also tends to increase as the bandwidth RMS analogous to setting the gain of an op amp in noninverting mode of the carrier decreases. With narrow-band carriers, the noise (see the B side of Figure 52) with the VSET pin being the equivalent spectrum of the V output tends to have a correspondingly RMS of the inverting input of the op amp. narrow profile. The relatively narrow spectral profile demands With VRMS connected to VSET, the nominal transfer function a larger value of C that reduces the low-pass corner frequency RMS of the ADL5906 is given by of the averaging function and ensures a valid rms computation. V = Slope × (P − Intercept) OUTPUT VOLTAGE SCALING RMS IN For example at 3.5 GHz, with P equal to 0 dBm, the nominal The linear output voltage range of the ADL5906 is nominally IN output voltage is equal to 0.052 V/dB × (0 dBm − (−64 dBm) = 0.3 V to 3.7 V. V is clamped to a maximum voltage of ~3.9 V; RMS 3.328 V. this helps improve falling edge settling speeds because the V RMS output stays closer to the nominal linear-in-dB output range of To scale this voltage downward using a resistor divider, choose a 0.3 V to 3.7 V. Within the 0 V to 3.9 V maximum output range, value for R15 and calculate R1 using the following equation: the slope can be adjusted as needed via extra resistors, as shown V  in Figure 52. R1=R15×VR'MS −1 (11) RMS Rev. A | Page 22 of 32

Data Sheet ADL5906 To scale this voltage upward, choose a value for R2 and calculate It is also important to take into account part-to-part and frequency R6 using the following equation: variation in output swing along with the maximum output voltage (3.9 V) of the output stage of the ADL5906. The V part-to- V'  RMS R6=(R2||R ) RMS −1 (12) part distribution is well characterized at major frequency bands IN VRMS  in the Typical Performance Characteristics section (see Figure 12 through Figure 14, Figure 18 through Figure 20, Figure 24, and where: Figure 25). The resistor values in Table 6, which were calculated R is the input resistance of VSET (72 kΩ). IN based on 3.5 GHz operation, have been conservatively chosen so V' is the desired maximum output voltage. RMS that there is no chance that the desired output voltage swings V is the nominal maximum output voltage before scaling RMS exceed the output swing of the ADL5906 (when scaling upward) (see Figure 9 through Figure 26). or the input range of a 0 V to 2.5 V ADC (when scaling down- When choosing R1, R2, R6, and R15, notice the current drive ward). In each case, the nominal maximum voltage that results is capability of the VRMS pin and the input resistance of the VSET 100 mV below the desired maximum to account for part-to-part pin. The choice of resistors must not be too small because this variation and resistor tolerances. results in excessive current drawn out of the VRMS pin (the VRMS pin can source a maximum current of 10 mA). However, choosing an R2 that is too large is also problematic. If the value of R2 chosen is compatible with the input resistance of the VSET pin (72 kΩ), this input resistance, which varies slightly from part to part, contributes to the resulting slope and output voltage. In general, ensure that the value of R2 is at least 10 times smaller than the input resistance of VSET. Therefore, the values for R6 and R2 must be in the 1 kΩ to 5 kΩ range. Similar values must be used for R1 and R15. Table 6. Output Voltage Range Scaling Examples at 3.5 GHz Slope Increase Slope Decrease Desired Input Range (dBm) R6 (Ω) R2 (Ω) R1 (Ω) R15(Ω) New Slope (mV/dB) Nominal Maximum Output Voltage (V) 0 to −60 274 2000 59 3.8 −10 to −50 681 2000 70 3.8 0 to −60 787 2000 37 2.4 −10 to −50 348 2000 44 2.4 Rev. A | Page 23 of 32

ADL5906 Data Sheet SYSTEM CALIBRATION AND ERROR CALCULATION The log conformance error is the difference between this straight line and the actual performance of the detector. The measured transfer function of the ADL5906 at 2.14 GHz is shown in Figure 53, which contains plots of both output voltage Error (dB) = (VRMS(MEASURED) − VRMS(IDEAL))/Slope (17) vs. input level and linearity error vs. input level. As the input level Figure 53 includes a plot of this error at +25°C, −40°C, and +85°C varies from −65 dBm to +5 dBm, the output voltage varies from when using a two-point calibration (calibration points are 0 dBm ~0.25 V to ~3.9 V. and −40 dBm). The error at the calibration points at 25°C (in 6.0 6 this case, −40 dBm and 0 dBm) is equal to 0 dB by definition. OUTPUT VOLTAGE –40°C 5.5 OUTPUT VOLTAGE +25°C 5 OUTPUT VOLTAGE +85°C The residual nonlinearity of the transfer function that is apparent 5.0 ERROR –40°C 4 ERROR +25°C in the two-point calibration error plot can be reduced by V)4.5 ERROR +85°C 3 increasing the number of calibration points. Figure 54 shows E (4.0 2 VOLTAG33..05 01 OR (dB) tah me uplotsipt-ocianlti bcaralitbiroanti eornr,o trh pe ltortasn fsofre ra ftuhnreceti-opno iins ts ecgamlibernatteiodn, .w Withit h PUT 2.5 –1 ERR each segment having its own slope and intercept. Multiple known T power levels (three levels in this case) are applied, and multiple U2.0 –2 O voltages are measured. When the equipment is in operation, the 1.5 –3 measured voltage from the detector is first used to determine 1.0 –4 which of the stored slope and intercept calibration coefficients 0.5 –5 are to be used. Then, the unknown power level is calculated 0 –6 –65 –55 –45 –35PIN (d–B25m) –15 –5 5 11287-051 bEyq uinastieornti n1g6 .t he appropriate slope and intercept values into Figure 53. 2.14 GHz VRMS and Log Conformance Error at +25°C, −40°C, and +85°C Using Two-Point Calibration at 0 dBm and −40 dBm When choosing calibration points, there is no requirement for, or value in, equal spacing between the points. There is also no Because slope and intercept vary from device to device, board limit to the number of calibration points used. However, when level calibration must be performed to achieve high accuracy. more calibration points are used, calibration time increases. The equation for the idealized output voltage can be written as 6.0 6 VRMS(IDEAL) = Slope × (PIN − Intercept) (13) 5.5 VTADJ = 0.35V OOUUTTPPUUTT VVOOLLTTAAGGEE +–4205°°CC 5 OUTPUT VOLTAGE +85°C where: 5.0 ERROR –40°C 4 Slope is the change in output voltage divided by the change in V)4.5 EERRRROORR ++2855°°CC 3 input power (dB). E (4.0 2 Intercept is the calculated input power level at which the output TAG3.5 1 dB) voltage is equal to 0 V (note that Intercept is an extrapolated VOL3.0 0 OR ( theoretical value and not a measured value). PUT 2.5 –1 ERR T U2.0 –2 In general, calibration is performed during equipment manufacture O 1.5 –3 by applying two or more known signal levels to the input of the 1.0 –4 ADL5906 and measuring the corresponding output voltages. 0.5 –5 The calibration points must be within the linear operating range 0 –6 oWf itthhe a d tewvoic-pe.o int calibration, the slope and intercept are calculated –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 11287-152 Figure 54. 2.14 GHz VRMS and Log Conformance Error at +25°C, −40°C, and as follows: +85°C Using Three-Point Calibration at 0 dBm, −40 dBm, and −55 dBm Slope = (V − V )/(P − P ) (14) RMS1 RMS2 IN1 IN2 The −40°C and +85°C error plots in Figure 54 are generated using Intercept = P − (V /Slope) (15) the +25°C slope and intercept values. This is consistent with IN1 RMS1 equipment calibration in a mass production environment where After the slope and intercept are calculated and stored in nonvolatile calibration of multiple temperatures is not practical. memory during equipment calibration, an equation can be used to calculate an unknown input power based on the output voltage of the detector. P (Unknown) = (V /Slope) + Intercept (16) IN RMS(MEASURED) Rev. A | Page 24 of 32

Data Sheet ADL5906 USING VTEMP TO IMPROVE INTERCEPT Figure 55 to Figure 62 show typical plots of VRMS’ vs. input level TEMPERATURE DRIFT and temperature at frequencies from 100 MHz to 5.8 GHz when this temperature compensation algorithm is applied. In applications where V and V are both being digitized TEMP RMS by an ADC, the V voltage can be used to further improve From a system calibration and operation perspective, the only TEMP the temperature drift of the ADL5906. additional measurements that are required to implement this algorithm are measurement and storage of V during calibration As shown in Figure 54, whereas the slope is stable vs. the TEMP (that is, at ambient temperature) and measurement of V temperature at 2140 MHz, the intercept of the ADL5906 does TEMP during operation. All other information required to implement vary slightly vs. temperature (approximately +0.3 dB at +85°C this algorithm (that is, nominal temperature drift of V and and −0.8 dB at −40°C). This variation in intercept is constant vs. RMS temperature coefficient of V ) is based on typical data sheet input power level at most frequencies. Table 7 lists the average TEMP specifications. temperature coefficient of V in mV/°C at frequencies from RMS 6.0 6 100 MHz to 5.8 GHz. This temperature coefficient is given by VTADJ = 0.35V VRMS' –40°C the following equation: 5.5 VVRRMMSS'' ++2855°°CC 5 5.0 ERROR –40°C 4 TC = (DRIFT /Δ ) × Slope (18) ERROR +25°C VRMS VRMS TEMP 4.5 ERROR +85°C 3 where: 4.0 2 DamRbIFieTnVtR tMoS iesi tthheer s−p4e0ci°fCie odr d +r8if5t °oCf VatR aMnS (isncpaulet dp ionw deBr )le fvreolm o f ' (V)MS33..05 01 OR (dB) R R 0 dBm (see Table 1). V2.5 –1 ER ∆ is equal to either +65°C for cold drift (that is, +25°C − 2.0 –2 TEMP (−40°C)) or +60°C for hot drift (that is, +85°C − +25°C). 1.5 –3 Slope is the specified slope of V (see Table 1). 1.0 –4 RMS 0.5 –5 For example, at 2.14 GHz, TC for hot drift can be calculated as VRMS 0 –6 TCVRMS = (0.3 dB/60°C) × 56 mV/dB = 0.28 mV/°C –65 –55 –45 –35PIN (d–B2m5) –15 –5 5 11287-153 The value for slope that is used can also be the slope that is Figure 55. VRMS’ and Log Conformance Error vs. Input Level and Temperature calculated during device calibration. This gives results that are at 100 MHz Using VTEMP Intercept Compensation slightly more accurate because there is slight variation in slope 6.0 6 from device to device. 5.5 VTADJ = 0.35V VVRRMMSS'' –+4205°°CC 5 VRMS' +85°C Table 7 also lists the typical temperature coefficient of the V 5.0 ERROR –40°C 4 TEMP ERROR +25°C temperature sensor output. To calculate the appropriate amount of 4.5 ERROR +85°C 3 compensation required at a particular frequency, a V weighting 4.0 2 factor is calculated. This is simply the ratio of the tTeEmMPperature V)3.5 1 dB) coefficients of VTEMP and VRMS. These weighting factors are ' (MS3.0 0 OR ( R R also shown in Table 7. V2.5 –1ER 2.0 –2 Using the data shown in Table 7, an adjusted value for V (V ‘) RMS RMS 1.5 –3 can be calculated using the following equation: 1.0 –4  V −V  0.5 –5 VRMS'=VRMS−WeTiEgMhPtingTFEaMcPt2o5r (19) 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-054 where: Figure 56. VRMS’ and Log Conformance Error vs. Input Level and Temperature VTEMP25 is equal to the voltage measured on VTEMP during system at 700 MHz Using VTEMP Intercept Compensation calibration at ambient temperature. V is equal to the voltage on V during normal operation. TEMP TEMP Rev. A | Page 25 of 32

ADL5906 Data Sheet 6.0 6 6.0 6 55..05 VTADJ = 0.35V VVVERRRRMMMRSSSO'''R–++428–0554°°°0CCC°C 45 55..05 VTADJ = 0.4V VVEVRRRRMMMRSSSO''' R+–+ 428–0554°°°0CCC°C 45 ERROR+25°C ERROR +25°C 4.5 ERROR+85°C 3 4.5 ERROR +85°C 3 4.0 2 4.0 2 '(V)RMS33..05 01 ROR(dB) ' (V)RMS33..05 01 ROR (dB) V2.5 –1ER V2.5 –1 ER 2.0 –2 2.0 –2 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0–65 –55 –45 –35PIN(d–B2m5) –15 –5 5 –6 11287-155 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-058 Figure 57. VRMS’ and Log Conformance Error vs. Input Level and Temperature Figure 60. VRMS’ and Log Conformance Error vs. Input Level and Temperature at 900 MHz Using VTEMP Intercept Compensation at 2600 MHz Using VTEMP Intercept Compensation 6.0 6 6.0 6 55..05 VTADJ = 0.35V VVVERRRRMMMRSSSO''' R–++ 428–0554°°°0CCC°C 45 55..05 VTADJ = 0.45V VVVERRRRMMMRSSSO''' R+–+ 428–0554°°°0CCC°C 45 4.5 EERRRROORR ++2855°°CC 3 4.5 EERRRROORR ++2855°°CC 3 4.0 2 4.0 2 V' (V)RMS233...505 –011 ERROR (dB) V' (V)RMS233...505 –011 ERROR (dB) 2.0 –2 2.0 –2 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-156 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-059 Figure 58. VRMS’ and Log Conformance Error vs. Input Level and Temperature Figure 61. VRMS’ and Log Conformance Error vs. Input Level and Temperature at 1900 MHz Using VTEMP Intercept Compensation at 3500 MHz Using VTEMP Intercept Compensation 556...050 VTADJ = 0.35V VVVERRRRMMMRSSSO''' R–++ 428–0554°°°0CCC°C 456 556...050 VTADJ = 1V VVVERRRRMMMRSSSO''' R–++ 428–0554°°°0CCC°C 456 ERROR +25°C ERROR +25°C 4.5 ERROR +85°C 3 4.5 ERROR +85°C 3 4.0 2 4.0 2 V' (V)RMS233...505 –011 ERROR (dB) V' (V)RMS233...505 –011 ERROR (dB) 2.0 –2 2.0 –2 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-057 0–65 –55 –45 –35PIN (d–B2m5) –15 –5 5 –6 11287-060 Figure 59. VRMS’ and Log Conformance Error vs. Input Level and Temperature Figure 62. VRMS’ and Log Conformance Error vs. Input Level and Temperature at 2140 MHz using VTEMP Intercept Compensation at 5800 MHz Using VTEMP Intercept Compensation Rev. A | Page 26 of 32

Data Sheet ADL5906 Table 7. Scaling Factors for Intercept Temperature Drift Compensation Using V TEMP V Weighting Factor, V Weighting Factor, TEMP TEMP Frequency TC , −40°C to +25°C, TC , 25°C to 85°C, TC −40°C to +25°C +25°C to +85°C VRMS VRMS VTEMP (MHz) P = 0 dBm (mV/°C) P = 0 dBm (mV/°C) (mV/°C) (TC /TC ) (TC /TC ) IN IN VTEMP VRMS VTEMP VRMS 100 0.72615 0.19667 4.8 6.61017 24.40678 700 0.81692 0.295 4.8 5.87571 16.27119 900 0.72615 0.295 4.8 6.61017 16.27119 1900 0.70154 0.19 4.8 6.84211 25.26316 2140 0.68923 0.28 4.8 6.96429 17.14286 2600 0.76154 0.275 4.8 6.30303 17.45455 3500 1.2 0 4.8 4 ∞ 5800 1.23931 0.08041 4.8 5.99417 85.287 1TCVRMS based on temperature drift at PIN = −10 dBm. DESCRIPTION OF CHARACTERIZATION For a description on how characterization was completed, see the ADL5902 data sheet. Rev. A | Page 27 of 32

ADL5906 Data Sheet EVALUATION BOARD The ADL5906-EVALZ is a fully populated, 4-layer, FR4- signal is applied to the SMA connector (RFIN). The output based evaluation board. For normal operation, it requires a voltage is available on the SMA connector (VOUT1) or on the 5 V/100 mA power supply. The 5 V power supply must be test loop (VOUT). Configuration options for the evaluation connected to the VPOS and GND test loops. The RF input board are listed in Table 8. VPOS C3 C7 0.1µF 0.1µF C4 C5 100pF 100pF VPOS1 VPOS2 3 10 ADL5906 TEMSPEENRSAOTRURE 8 VTEMP C10 10nF RFIN+ R2 RFIN 14 IDET (OPEN) RFIN– X2 VSET R3 15 7 VSET 60.4Ω LINEAR-IN-dB VGA C101n2F (NEGATIVE SLOPE) X2 R0Ω6 VOUT ITGT R1 VRMS 0Ω NIC 2 G = 5 6 VOUT1 R15 NIC 16 (OPEN) NIC 13 BDIOASWANN CDO PNOTWROELR V2R.3EVF CRMS EPAD 5 C9 26pF 0.1µF 1 11 12 9 4 TADJ/ VREF VTGT GND2 GND1 PWDN GND R12 R9 R10 R11 270Ω 1.5kΩ 3.74kΩ 2kΩ TC2 VREF VTGT 11287-150 Figure 63. Evaluation Board Schematic Table 8. Evaluation Board Configuration Options Component Function/Notes Default Value RFIN, R3, C10, RF input. The evaluation board is configured for single-ended drive on the RFIN+ pin (Pin 14). RFIN = SMA connector, C12 Capacitors C10 and C12 have been set large enough so that the full frequency range of the C10 = C12 = 10 nF, device is covered. If operation down to 10 MHz is not required, the value of these capacitors R3 = 60.4 Ω can be reduced. VTGT, R10, VTGT interface. R10 and R11 are set up to provide 0.8 V to VTGT derived from VREF. If R10 and VTGT = black test loop, R11 R11 are removed, an external voltage can be applied on the VTGT test point. R10 = 3.74 kΩ, R11 = 2 kΩ, VTGT = 0.8 V VPOS, GND, Power supply interface and decoupling. Apply the power supply for the evaluation board to VPOS = red test loop, C3, C4, C5,C7 the VPOS and GND test loops. The nominal supply decoupling consists of a 100 pF capacitor and a GND = black test loop, 0.1 μF capacitor on each power supply pin, with the 100 pF capacitor placed closer to the pin. C3 = C7 = 0.1 μF, C4 = C5 = 100 pF Rev. A | Page 28 of 32

Data Sheet ADL5906 Component Function/Notes Default Value VOUT, VOUT1, Output interface. In measurement mode, a portion of the voltage at the VRMS pin is fed back VOUT = black test loop, VSET, R1, R2, to the VSET pin via R6 (R6 is normally set to 0 Ω). Using the voltage divider created by R2 and VOUT1 = SMA connector, R6, R15 R6, the magnitude of the slope of V is increased by reducing the portion of VRMS that is fed VSET = black test loop, RMS back to VSET. Resistors R1 and R15 can be used to reduce the output slope. R1 = R6 = 0 Ω, In controller mode, R6 must be open. In this mode, the ADL5906 can control the gain of a variable R15 = R2 = open gain amplifier (VGA) or voltage variable attenuator (VVA). A setpoint voltage is applied to the VSET test loop, and the VRMS test loop or SMA connector drives the gain control input of the VGA/VVA. C9 RMS averaging capacitor. The value of the rms averaging capacitor should be set based on the C9 = 0.1 µF peak-to-average ratio of the input signal and based on the desired output response time and residual output noise. TC2, R9, R12 TADJ/PWDN interface. The TADJ/PWDN pin controls the slope temperature compensation TC2 = black test loop, and/or shuts down the device. The evaluation board is configured with VTADJ connected to R9 = 1.5 kΩ, R12 = 270 Ω, VREF through a resistor divider (R9, R12). This voltage divider can be removed (or simply VTADJ = 0.35 V overdriven) allowing for the external application of a voltage to the VTADJ pin by applying a voltage to the TC2 test point. EVALUATION BOARD ASSEMBLY DRAWINGS 11287-055 11287-056 Figure 64. ADL5906 Evaluation Board Layout, Top Side Figure 65. ADL5906 Evaluation Board Layout, Bottom Side Rev. A | Page 29 of 32

ADL5906 Data Sheet OUTLINE DIMENSIONS 4.10 0.35 4.00 SQ 0.30 PIN 1 3.90 0.25 INDICATOR PIN 1 0.65 13 16 INDICATOR BSC 12 1 EXPOSED 2.25 PAD 2.10 SQ 1.95 9 4 0.70 8 5 0.25 MIN TOP VIEW 0.60 BOTTOM VIEW 0.50 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WGGC. 111908-A Figure 66. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-23) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Ordering Quantity ADL5906ACPZN-R2 −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-23 250 ADL5906ACPZN-R7 −40°C to +105°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-23 1,500 ADL5906SCPZN-R7 −55°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-23 1,500 ADL5906-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 30 of 32

Data Sheet ADL5906 NOTES Rev. A | Page 31 of 32

ADL5906 Data Sheet NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11287-0-10/13(A) Rev. A | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADL5906SCPZN-R7 ADL5906ACPZN-R7 ADL5906-EVALZ