4.5 GHz Ultrahigh Dynamic Range, Dual Differential Amplifier Data Sheet ADL5566 FEATURES FUNCTIONAL BLOCK DIAGRAM −3 dB bandwidth of 4.5 GHz (A = 16 dB) VCC1/VCC2 ENBL1 V Fixed 16 dB gain Channel-to-channel gain error: 0.1 dB at 100 MHz RF Channel-to-channel phase error: 0.06° at 100 MHz Differential or single-ended input to differential output VON1 I/O dc-coupled or ac-coupled Low noise input stage: 1.3 nV/√Hz RTI at A = 16 dB RG V VIP1 VCOM1 Low broadband distortion (AV = 16 dB), supply = 5 V VIN1 RG 10 MHz: −103 dBc (HD2), −107 dBc (HD3) 100 MHz: −95 dBc (HD2), −100 dBc (HD3) 200 MHz: −94.5 dBc (HD2), −87 dBc (HD3) VOP1 500 MHz: −83 dBc (HD2), −64 dBc (HD3) RF IMD3 of −95 dBc at 200 MHz center Maintains low single-ended distortion performance out to RF 500 MHz Slew rate: 16 V/ns VON2 Maintains low distortion down to 1.2 V VCOM Fixed 16 dB gain can be reduced by adding external resistors RG VIP2 VCOM2 Fast settling and overdrive recovery of 2.5 ns RG Single-supply operation: 2.8 V to 5.2 V VIN2 Power-down Low dc power consumption, 462 mW at 3.3 V supply VOP2 APPLICATIONS RF RDSiFinf/fgIeFlre ge-aneitnnida ble lAdoD-ctkCos -d driifvfeerres ntial conversion GND ENBL2 ADL5566 10916-001 Figure 1. SAW filter interfacing GENERAL DESCRIPTION The ADL5566 is a high performance, dual differential amplifier The quiescent current of the ADL5566, using a 3.3 V supply, is optimized for IF and dc applications. The amplifier offers low typically 70 mA per amplifier. When disabled, it consumes less noise of 1.3 nV/√Hz and excellent distortion performance over than 3.5 mA per amplifier and has −25 dB of input-to-output a wide frequency range, making it an ideal driver for high speed isolation at 100 MHz. 16-bit analog-to-digital converters (ADCs). The ADL5566 is The device is optimized for wideband, low distortion, and noise ideally suited for use in high performance, zero IF/complex performance, giving it unprecedented performance for overall IF receiver designs. In addition, this device has excellent low spurious-free dynamic range (SFDR). These attributes, together distortion for single-ended input drive applications. with its adjustable gain capability, make this device the amplifier The ADL5566 provides a gain of 16 dB. For the single-ended input of choice for driving a wide variety of ADCs, mixers, pin diode configuration, the gain is reduced to 14 dB. Using two external attenuators, SAW filters, and multi-element discrete devices. series resistors for each amplifier expands the gain flexibility of Fabricated on an Analog Devices, Inc., high speed SiGe process, the the amplifier and allows for any gain selection from 0 dB to 16 dB ADL5566 is supplied in a compact 4 mm × 4 mm, 24-lead LFCSP for a differential input and 0 dB to 14 dB for a single-ended input. package and operates over the −40°C to +85°C temperature range. In addition, this device maintains low distortion down to output (VOCM) levels of 1.2 V providing an added capability for driving CMOS ADCs at ac levels up to 2 V p-p. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADL5566 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 15 Applications ....................................................................................... 1 Basic Connections ...................................................................... 15 Functional Block Diagram .............................................................. 1 Input and Output Interfacing ................................................... 16 General Description ......................................................................... 1 Gain Adjustment and Interfacing ............................................ 16 Revision History ............................................................................... 2 ADC Interfacing ......................................................................... 18 Specifications ..................................................................................... 3 DC-Coupled Receiver Application .......................................... 19 Absolute Maximum Ratings ............................................................ 6 Layout Considerations ............................................................... 20 Thermal Resistance ...................................................................... 6 Soldering Information and Recommended Land Pattern .... 21 ESD Caution .................................................................................. 6 Evaluation Board ........................................................................ 21 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 24 Circuit Description ......................................................................... 14 REVISION HISTORY 12/13—Rev. 0 to Rev. A Changes to ENBL1/ENBL2 Threshold Parameter, Table 1 ......... 3 Change to Table 2 ............................................................................. 6 11/12—Revision 0: Initial Version Rev. A | Page 2 of 24

Data Sheet ADL5566 SPECIFICATIONS V = 3.3 V, V = 1.65 V, V = 5 V, V = 2.5 V, R = 200 Ω differential, A = 16 dB, C = 1 pF differential, f = 100 MHz, T = 25°C, S CM S CM L V L A parameters specified as ac-coupled differential input and differential output, unless otherwise noted. Table 1. Test Conditions/ 3.3 V 5 V Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth A = 16 dB, V ≤ 0.5 V p-p 4500 4500 MHz V OUT Bandwidth 0.1 dB Flatness V ≤ 1.0 V p-p 500 500 MHz OUT Gain Accuracy ±1 ±1 dB Gain Error ≤1000 MHz, Channel A to ≤0.02 ≤0.02 dB Channel B Phase Error ≤1000 MHz, Channel A to ≤0.5 ≤0.5 Degrees Channel B Gain Supply Sensitivity V ± 5% 3.4 5.6 mdB/V S Gain Temperature Sensitivity −40°C to +85°C 0.5 0.5 mdB/°C Slew Rate Rise, A = 16 dB, R = 200 Ω, 16 18 V/ns V L V = 2 V step OUT Fall, A = 16 dB, R = 200 Ω, 18 20 V/ns V L V = 2 V step OUT Settling Time 2 V step to 1% 890 750 ps Overdrive Recovery Time V = 4 V to 0 V step, 2.5 2.5 ns IN V ≤ ±10 mV OUT Reverse Isolation (S12) 75 75 dB Channel Isolation Channel A-to-Channel B 82.5 82.5 dB A = 16 dB V INPUT/OUTPUT CHARACTERISTICS Input Common-Mode Range 1.2 1.8 1.3 3.5 V Input Resistance (Differential) A = 16 dB 160 160 Ω V Input Resistance (Single-Ended) A = 14 dB 150 150 Ω V Input Capacitance (Single-Ended) 1.1 1.1 pF Input Bias Current ±5 ±5 µA CMRR 44 44 dB Output Common-Mode Range 1.25 1.8 1.25 3 V Output Common-Mode Offset Referenced to VCC/2 −100 +20 −100 +20 mV Output Common-Mode Drift −40°C to +85°C 2 3.5 mV/°C Output Differential Offset Voltage −20 +20 −20 +20 mV Output Differential Offset Drift −40°C to +85°C 1.1 1.7 mV/°C Output Resistance (Differential) 11 11 Ω Maximum Output Voltage Swing 1 dB compressed 3.4 5 V p-p POWER INTERFACE Supply Voltage 2.8 3.3 5.2 2.8 5 5.2 V ENBL1/ENBL2 Threshold Device disabled, ENBL low 0.5 0.6 V Device enabled, ENBL high 1.5 1.5 V ENBL1/ENBL2 Input Bias Current ENBL high 500 500 nA ENBL low −165 −165 µA Quiescent Current ENBL high 140 150 160 175 mA ENBL low 7 9 mA Rev. A | Page 3 of 24

ADL5566 Data Sheet Test Conditions/ 3.3 V 5 V Parameter Comments Min Typ Max Min Typ Max Unit NOISE/HARMONIC PERFORMANCE 10 MHz Second/Third Harmonic A = 16 dB, R = 200 Ω, −99.1/−111 −103.1/−107.3 dBc V L Distortion (HD2/HD3) V = 2 V p-p OUT Output IP3/Third-Order A = 16 dB, R = 200 Ω, +50.2/−103.3 +49.4/−101.8 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP3/IMD3) (2 MHz spacing) Output IP2 Second-Order AV = 16 dB, RL = 200 Ω, +90.8/−92.1 +91.2/−92.5 dBm/dBc Intermodulation V = 2 V p-p composite OUT Distortion (OIP2/IMD2) (2 MHz spacing) 1 dB Compression Point, RTO A = 16 dB 14 17.7 dBm V (OP1dB) Noise Spectral Density, A = 16 dB 1.28 1.32 nV/√Hz V RTI (NSD) Noise Figure (NF) A = 16 dB 6.47 6.66 dB V 100 MHz Second/Third Harmonic A = 16 dB, R = 200 Ω, −89/−92.1 −94.7/−100 dBc V L Distortion (HD2/HD3) V = 2 V p-p OUT Output IP3/Third-Order A = 16 dB, R = 200 Ω, +49.4/−101.9 +50.9/−104.7 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP3/IMD3) (2 MHz spacing) Output IP2 Second-Order A = 16 dB, R = 200 Ω, +96.9/−98.2 +98.9/−100.2 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP2/IMD2) (2 MHz spacing) 1 dB Compression Point, RTO A = 16 dB 14.2 17.8 dBm V (OP1dB) Noise Spectral Density, A = 16 dB 1.26 1.3 nV/√Hz V RTI (NSD) Noise Figure (NF) A = 16 dB 6.36 6.58 dB V 200 MHz Second/Third Harmonic A = 16 dB, R = 200 Ω, −92.7/−80.2 −94.5/−87.2 dBc V L Distortion (HD2/HD3) V = 2 V p-p OUT Output IP3/Third-Order A = 16 dB, R = 200 Ω, +45.9/−94.7 +46/−95 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP3/IMD3) (2 MHz spacing) Output IP2 Second-Order A = 16 dB, R = 200 Ω, +80.4/−81.7 +82.6/−83.9 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP2/IMD2) (2 MHz spacing) 1 dB Compression Point, RTO A = 16 dB 14.1 17.7 dBm V (OP1dB) Noise Spectral Density, A = 16 dB 1.25 1.28 nV/√Hz V RTI (NSD) Noise Figure (NF) A = 16 dB 6.31 6.48 dB V 500 MHz Second/Third Harmonic A = 16 dB, R = 200 Ω, −82.6/−60.5 −82.8/−64.2 dBc V L Distortion (HD2/HD3) V = 2 V p-p OUT Output IP3/Third-Order A = 16 dB, R = 200 Ω, +30.7/−64.7 +32.4/−67.8 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP3/IMD3) (2 MHz spacing) Output IP2 Second-Order A = 16 dB, R = 200 Ω, +74.2/−75.5 +75.8/−77.1 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP2/IMD2) (2 MHz spacing) Noise Spectral Density, A = 16 dB 1.32 1.35 nV/√Hz V RTI (NSD) Noise Figure (NF) A = 16 dB 6.64 6.83 dB V Rev. A | Page 4 of 24

Data Sheet ADL5566 Test Conditions/ 3.3 V 5 V Parameter Comments Min Typ Max Min Typ Max Unit 1000 MHz Second/Third Harmonic A = 16 dB, R = 200 Ω, −57.6/−43 −57.1/−45.9 dBc V L Distortion (HD2/HD3) V = 2 V p-p OUT Output IP3/Third-Order A = 16 dB, R = 200 Ω, +23.2/−49.4 +24.8/−52.6 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP3/IMD3) (2 MHz spacing) Output IP2 Second-Order A = 16 dB, R = 200 Ω, +56.1/−57.4 +55.9/−57.2 dBm/dBc V L Intermodulation V = 2 V p-p composite OUT Distortion (OIP2/IMD2) (2 MHz spacing) Noise Spectral Density, A = 16 dB 1.93 1.99 nV/√Hz V RTI (NSD) Noise Figure (NF) A = 16 dB 9.45 9.66 dB V Rev. A | Page 5 of 24

ADL5566 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Table 3 lists the junction-to-air thermal resistance (θ ) and the Parameter Rating JA junction-to-paddle thermal resistance (θ ) for the ADL5566. Output Voltage Swing × Bandwidth Product 2300 V p-p MHz JC Supply Voltage, V 5.25 V CC Table 3. Thermal Resistance VIPx, VINx V + 0.5 V CC Package Type θ 1 θ 2 Unit JA JC ±I Maximum ±30 mA OUT 24-Lead LFCSP 34.0 1.8 °C/W Internal Power Dissipation 900 mW Maximum Junction Temperature 135°C 1 Measured on Analog Devices evaluation board. For more information about board layout, see the Pattern section. Operating Temperature Range −40°C to +105°C 2 Based on simulation with JEDEC standard JESD51. Storage Temperature Range −65°C to +150°C ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 24

Data Sheet ADL5566 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BL1 OM1 C1 C C N C C C N N E V V N 42 32 22 12 02 91 VIN11 18VON1 VIP12 17VOP1 NC3 ADL5566 16NC NC4 TOP VIEW 15NC VIP25 14VOP2 VIN26 13VON2 7 8 9 01 11 21 C C 2 2 2 C N N ENBL VCOM VCC N 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2 . TGGHNREDO EUAXNNPDDO PMSLEUADSN TPE BA.ED DSLOEL IDSE IRNETDE RTNOA AL LLYO CWO INMNPEECDTAENDC ETO 10916-002 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VIN1 Balanced Differential Input for Amplifier 1. Biased to V /2, typically ac-coupled. Input for A = 16 dB. CC V 2 VIP1 Balanced Differential Input for Amplifier 1. Biased to V /2, typically ac-coupled. Input for A = 16 dB. CC V 3, 4, 7, 8, 12, 15, NC No Connect. Do not connect to this pin. Solder to ground. 16, 19, 23, 24 5 VIP2 Balanced Differential Input for Amplifier 2. Biased to V /2, typically ac-coupled. Input for A = 16 dB. CC V 6 VIN2 Balanced Differential Input for Amplifier 2. Biased to V /2, typically ac-coupled. Input for A = 16 dB. CC V 9 ENBL2 Enable for Amplifier 2. Apply positive voltage (1.3 V < ENBL2 < VCC2) to activate device. 10 VCOM2 Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the inputs and outputs of Amplifier 2. If left open, VCOM2 = V /2. Typically, it is decoupled to ground with a 0.1 µF CC capacitor. 11 VCC2 Positive Supply for Amplifier 2. 13 VON2 Balanced Differential Output for Amplifier 2. Biased to V /2, typically ac-coupled. CC 14 VOP2 Balanced Differential Output for Amplifier 2. Biased to V /2, typically ac-coupled. CC 17 VOP1 Balanced Differential Output for Amplifier 1. Biased to V /2, typically ac-coupled. CC 18 VON1 Balanced Differential Output for Amplifier 1. Biased to V /2, typically ac-coupled. CC 20 VCC1 Positive Supply for Amplifier 1. 21 VCOM1 Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the inputs and outputs of Amplifier 1. If left open, VCOM1 = V /2. Typically, it is decoupled to ground with a 0.1 µF CC capacitor. 22 ENBL1 Enable for Amplifier 1. Apply positive voltage (1.3 V < ENBL1 < VCC1) to activate device. EP The exposed paddle is internally connected to GND and must be soldered to a low impedance ground plane. Rev. A | Page 7 of 24

ADL5566 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = 3.3 V, V = 1.65 V, R = 200 Ω differential, A = 16 dB, C = 1 pF differential, f = 100 MHz, T = 25°C, parameters specified as S CM L V L A ac-coupled differential input and differential output, unless otherwise noted. 25 0.7 0.07 3.3V, 25°C SDD21 PHASE 5V, 25°C SDD21 MAG 20 0.6 0.06 15 es) 0.5 0.05 GAIN (dB) 105 ERROR (Degre 00..34 00..0034 N ERROR(dB) 0 E AI AS G H 0.2 0.02 –5 P –10 0.1 0.01 –1510M 100FMREQUENCY (Hz) 1G 10916-003 010 FREQUE1N0C0Y (MHz) 10000 10916-106 Figure 3. Gain vs. Frequency Response for 200 Ω Differential Load, Figure 6. Channel-to-Channel Gain Error and Phase Error vs. Frequency VPOS = 3.3 V and VPOS = 5 V, 25°C 25 25 3.3V, –40°C 3.3V, +25°C 20 3.3V, +85°C 3.3V, +105°C 20 15 AIN(dB) 105 dB (dBm) 15 G 0 OP1 10 5V, +25°C –5 55VV,, –+4805°°CC 5 5V, +105°C 3.3V, +25°C –10 3.3V, –40°C 3.3V, +85°C 3.3V, +105°C –1510M 100FMREQUENCY(Hz) 1G 10916-004 00 50 FR1E00QUENCY (1M5H0z) 200 250 10916-006 Figure 4. Gain vs. Frequency Response for 200 Ω Differential Load, Figure 7. OP1dB vs. Frequency for 200 Ω Differential Load, Four Four Temperatures, VPOS = 3.3 V Temperatures, VPOS = 3.3 V, VPOS = 5 V 25 10.0 5V, –40°C 3.3V SUPPLY 5V, +25°C 9.5 5V SUPPLY 20 5V, +85°C 5V, +105°C 9.0 8.5 15 8.0 B) N(dB) 105 GURE (d 767...505 AI FI G E 6.0 0 OIS 5.5 N 5.0 –5 4.5 –10 4.0 3.5 –1510M 100FMREQUENCY(Hz) 1G 10916-005 3.010M FREQU1E00NMCY (Hz) 1G 10916-007 Figure 5. Gain vs. Frequency Response for 200 Ω Differential Load, Figure 8. Noise Figure vs. Frequency at VPOS = 3.3 V, VPOS = 5 V, 25°C Four Temperatures, VPOS = 5 V Rev. A | Page 8 of 24

Data Sheet ADL5566 3.00 60 3.3V SUPPLY 2.75 5V SUPPLY √Hz) 2.50 50 OIP3, 3.3V, 25°C OIP3, 5V, 25°C V/ 2.25 n TY ( 2.00 40 NSI 1.75 m) E B TRAL D 11..2550 OIP3 (d 30 C PE 1.00 20 S E 0.75 S NOI 0.50 10 0.25 010M FREQU1E00NMCY (Hz) 1G 10916-008 0–6 –5 –4 –3 –2 –1 P0OUT1/TO2NE (3dBm4) 5 6 7 8 9 10 10916-011 Figure 9. Noise Spectral Density vs. Frequency at VPOS = 3.3 V and VPOS = 5 V Figure 12. Output Third-Order Intercept (OIP3) vs. Output Power (POUT) per Tone, Frequency 200 MHz, VPOS = 3.3 V and VPOS = 5 V 60 0 OIP3, 3.3V, 25°C, 2V p-p IMD3, 3.3V, +25°C, 2V p-p IMD3, 3.3V, +25°C, 1V p-p OIP3, 5V, 25°C, 2V p-p IMD3, 5V, +25°C, 2V p-p IMD3, 5V, +25°C, 1V p-p OIP3, 3.3V, 25°C, 1V p-p IMD3, 3.3V, +85°C, 2V p-p IMD3, 3.3V, +85°C, 1V p-p 50 OIP3, 5V, 25°C, 1V p-p –20 IIMMDD33,, 53V.3, V+,8 5–°4C0°, C2,V 2 pV- pp-p IIMMDD33,, 35.V3,V +, 8–54°0C°,C 1, V1 Vp -pp-p IMD3, 5V, –40°C, 2V p-p IMD3, 5V, –40°C, 1V p-p IMD3, 3.3V, +105°C, 2V p-p IMD3, 3.3V, +105°C, 1V p-p 40 –40 IMD3, 5V, +105°C, 2V p-p IMD3, 5V, +105°C, 1V p-p m) m) B B 3 (d 30 3 (d –60 P D OI M I 20 –80 10 –100 0 –120 0 100 200 300 FR4E00QUE5N0C0Y (6M0H0z) 700 800 900 1000 10916-009 0 100 200 300 FR4E00QUE5N0C0Y (6M0H0z) 700 800 900 1000 10916-012 Figure 10. Output Third-Order Intercept (OIP3) at Output Level at 2 V p-p Figure 13. IMD3 vs. Frequency, Over Temperature, Output Level at Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V 60 –20 –30 50 –40 –50 40 m) c) –60 5V B B SUPPLY OIP3 (d 30 IMD3 (d ––8700 3S.U3VPPLY 20 OIP3, 3.3V, +25°C, 2V p-p OIP3, 3.3V, +25°C, 1V p-p OIP3, 5V, +25°C, 2V p-p OIP3, 5V, +25°C, 1V p-p –90 OIP3, 3.3V, +85°C, 2V p-p OIP3, 3.3V, +85°C, 1V p-p OIP3, 5V, +85°C, 2V p-p OIP3, 5V, +85°C, 1V p-p –100 10 OIP3, 3.3V, –40°C, 2V p-p OIP3, 3.3V, –40°C, 1V p-p OIP3, 5V, –40°C, 2V p-p OIP3, 5V, –40°C, 1V p-p OIP3, 3.3V, +105°C, 2V p-p OIP3, 3.3V, +105°C, 1V p-p –110 OIP3, 5V, +105°C, 2V p-p OIP3, 5V, +105°C, 1V p-p 00 100 200 300 FR4E00QUE5N0C0Y(6M0H0z) 700 800 900 1000 10916-010 –1200 0.5 1.0 1.5 VCO2M.0 (V) 2.5 3.0 3.5 4.0 10916-017 Figure 11. Output Third-Order Intercept (OIP3) vs. Frequency, Figure 14. IMD3 vs. VCOM, Output Level at 2 V p-p Composite, RL = 200 Ω, Overtemperature, Output Level at 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V, Frequency = 100 MHz VPOS = 3.3 V and VPOS = 5 V Rev. A | Page 9 of 24

ADL5566 Data Sheet –50 0 –40 IMD3 100Ω LOAD HD3, 5V, 25°C, 1Vp-p –55 IMD3 150Ω LOAD HD3, 3.3V, 25°C, 2Vp-p IMD3 200Ω LOAD HD3, 5V, 25°C, 2Vp-p –60 –20 HD3, 3.3V, 25°C, 1Vp-p –60 –65 –70 –75 –40 –80 MD3 (dBc) –––988050 HD2 (dBc) –60 –100HD3 (dBc) I –95 –80 –120 –100 –105 –110 –100 HD2, 3.3V, 25°C, 2Vp-p –140 HD2, 5V, 25°C, 2Vp-p –115 HD2, 3.3V, 25°C, 1Vp-p HD2, 5V, 25°C, 1Vp-p –1200 50 100 150 FR2E00QUE2N5C0Y (3M0H0z) 350 400 450 500 10916-031 –1200 100 200 300 FR4E00QUE5N0C0Y (6M0H0z) 700 800 900 1000–160 10916-013 Figure 15. IMD3 vs. Frequency, RL = 100 Ω, RL = 150 Ω, and RL = 200 Ω, VPOS = 3.3 V, Figure 18. Harmonic Distortion (HD2/HD3) vs. Frequency, Input Common Mode = 1.65 V, Output Common Mode = 1.25 V, VOUT = 1.5 V p-p Output Level at 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V 60 0 –40 HD2, 3.3V, +25°C HD2, 5V, +25°C HD2, 3.3V, +85°C HD2, 5V, +85°C 55 HD2, 3.3V, –40°C HD2, 5V, –40°C –20 HD2, 3.3V, +105°C HD2, 5V, +105°C –60 50 –40 –80 45 m) c) c) B B B P3 (d 40 D2 (d –60 –100D3 (d OI H H 35 –80 –120 30 –100 HD3, 3.3V, +25°C HD3, 5V, +25°C –140 25 HD3, 3.3V, +85°C HD3, 5V, +85°C HD3, 3.3V, –40°C HD3, 5V, –40°C HD3, 3.3V, +105°C HD3, 5V, +105°C 200 50 100 150 FR2E00QUE2N5C0Y (3M0H0z) 350 400 450 500 10916-032 –1200 50 100 150 FR2E00QUE2N5C0Y (3M0H0z) 350 400 450 500–160 10916-014 Figure 16. Single-Ended OIP3 vs. Frequency, VPOS = 3.3 V, Figure 19. Harmonic Distortion (HD2/HD3) vs. Frequency, 2 V p-p Composite Output, RL = 200 Ω Output Level at 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V 120 0 –60 0 3.3V OIP2 3.3V, HD2, 25°C 5V OIP2 5V, HD2, 25°C 3.3V IMD2 100 5V IMD2 –20 –80 –20 80 –40 –100 –40 OIP2 (dBm) 60 –60MD2 (dBc) HD2 (dBc)–120 –60 HD3 (dBc) I 40 –80 –140 –80 20 –100 –160 –100 3.3V, HD3, 25°C 5V, HD3, 25°C 00 100 200 300 FR4E00QUE5N0C0Y (6M0H0z) 700 800 900 1000–120 10916-053 –180–2 0 2POUT/TO4NE (dBm)6 8 10–120 10916-015 Figure 17. OIP2/IMD2 vs. Frequency Figure 20. Harmonic Distortion (HD2/HD3) vs. Output Power (POUT) per Tone, Frequency = 200 MHz, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V Rev. A | Page 10 of 24

Data Sheet ADL5566 0 –60 HD2, 3.3V HD2 AT 3.3V –10 HHDD23,, 53.V3V –65 HHDD32 AATT 35..30VV –20 HD3, 5V c) –70 HD3 AT 5.0V B –30 d Bc) –40 ON ( –75 D3 (d –50 ORTI –80 AND H –60 C DIST ––9805 D2 –70 ONI H M –95 –80 R A H–100 –90 –100 –105 –1100.5 1.0 1.5VCOM (V)2.0 2.5 3.0 10916-016 –1100 100 FR2E00QUENCY (3M0H0z) 400 500 10916-033 Figure 21. Harmonic Distortion (HD2/HD3) vs. VCOM, Output Level at Figure 24. Single-Ended Harmonic Distortion (HD2/HD3) vs. Frequency, 2 V p-p, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V, Frequency = 100 MHz VPOS = 3.3 V and VPOS = 5 V, VOUT = 2 V p-p, RL = 200 Ω –50 –80 HD2 100Ω LOAD –55 HD2 200Ω LOAD –60 –85 –65 Bc) –90 –70 d c) ––8705 DUCT ( –95 HD2 B O HD2 (d ––9805 ON PR–100 IMD3 –95 TI–105 –100 TOR HD3 S–110 –105 DI –110 –115 –115 –1200 50 100 150 FR2E00QUE2N5C0Y (3M0H0z) 350 400 450 500 10916-029 –1200 1 2FREQUEN3CY(MHz)4 5 6 10916-019 Figure 22. HD2 vs. Frequency, RL = 100 Ω and RL = 200 Ω, VPOS = 3.3 V, Input Figure 25. Low Frequency Distortion (HD2/HD3/IMD3) vs. Frequency, Common Mode = 1.65 V, Output Common Mode = 1.25 V, VOUT = 1.5 V p-p Output Level at 2 V p-p, RL = 200 Ω, VPOS = 3.3 V –50 HD3 200Ω LOAD –55 HD3 100Ω LOAD –60 –65 –70 –75 c) –80 B 3 (d –85 3 HD –90 –95 –100 –105 2 –110 –115 –1200 50 100 150 FR2E00QUE2N5C0Y (3M0H0z) 350 400 450 500 10916-030 CCHH23 150000mmVV//DDIIVV 5500ΩΩBBWW 88GG A CH3 1.1V 10916-020 Figure 23. HD3 vs. Frequency, RL = 100 Ω and RL = 200 Ω, VPOS = 3.3 V, Input Figure 26. ENBLx Time Domain Response, VPOS = 3.3 V Common Mode = 1.65 V, Output Common Mode = 1.25 V, VOUT = 1.5 V p-p Rev. A | Page 11 of 24

ADL5566 Data Sheet 0 –10 –20 B) N (d –30 O TI –40 A 1 OL –50 S E I S –60 R E EV –70 R –80 –90 CH1 400mV 2ns A CH1 0V 10916-021 –10010 FREQUE1N0C0Y (MHz) 1000 10916-024 Figure 27. Large Signal Pulse Response Using a Slow Transient Signal Figure 30. Reverse Isolation (S12) vs. Frequency Generator, 4 V p-p, VPOS = 3.3 V 60 220 2.0 F) 455505 STANCE (Ω)220100 RCEASPIATCAINTCAENCE 11..68 PCITANCE (p 40 RESI190 1.4 CPA CMRR (dB) 233505 RIES INPUT 111678000 011...802 LLEL INPUT E A 20 S R NT 150 0.6 PA 15 E T 10 UIVAL140 0.4 ALEN 5 EQ130 0.2 UIV Q 010 FREQUE1N0C0Y (MHz) 1000 10916-022 12010 FREQUE1N0C0Y (MHz) 10000 E 10916-025 Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 31. S11 Equivalent RLC Parallel Network 1089000000 SISTANCE (Ω)121680 RCEASPIASCTIATNACNECE 8910 UCTANCE (nH) GROUP DELAY (ps) 12345670000000000000000 100 200 300 FR4E00QUE5N0C0Y (6M0H0z) 700 800 900 1000 10916-023 EQUIVALENT SERIES OUTPUT RE1110240246810 FREQUE1N0C0Y (MHz) 100456701230 EQUIVALENT SERIES OUTPUT IND 10916-026 Figure 29. Group Delay vs. Frequency Figure 32. S22 Equivalent RLC Parallel Network Rev. A | Page 12 of 24

Data Sheet ADL5566 0 85 –5 –10 –15 –20 80 –25 5V –30 B) –35 CROSSTALK (d ––––––665544505050 I (mA)SUPPLY 7705 3.3V –70 –75 –80 65 –85 –90 –95 –10010M 100MFREQUENCY (Hz)1G 10G 10916-028 60–40 –20 0 TEMP20ERATUR4E0 (°C) 60 80 100 09959-027 Figure 33. Output Referred Crosstalk, Channel A to Channel B, VPOS = 3.3 V, Figure 34. ISUPPLY vs. Temperature, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V VCOM = 1.65 V Rev. A | Page 13 of 24

ADL5566 Data Sheet CIRCUIT DESCRIPTION The ADL5566 is a high gain, fully differential dual amplifier/ADC industry for power consumed at frequencies beyond 100 MHz. driver that uses a 2.8 V to 5 V supply. It provides a 16 dB gain This amplifier achieves greater than −69 dBc IMD3 at 500 MHz that can be reduced by adding external series resistors. The 3 dB and −100 dBc at 200 MHz for 2 V p-p operation. In addition, bandwidth is 4.5 GHz, and it has a differential input impedance the ADL5566 can also deliver 5 V p-p operation under heavy of 160 Ω. It has a differential output impedance of 10 Ω and an loads. The internal gain is set at 16 dB, and the part has a noise output common-mode adjust voltage of 1.1 V to 1.8 V. figure of 6.5 dB and a RTI of 1.5 nV/√Hz. When comparing noise figure and distortion performance, this amplifier delivers the best in category spurious-free dynamic range (SFDR). 500Ω The ADL5566 is very flexible in terms of I/O coupling. It can be + 80Ω 5Ω 0.1µF + + ac- or dc-coupled. For dc coupling, the output common-mode ½ RS ½ 0.1µF voltage (VCOMx) can be adjusted (using the VCOMx pin) from ADL5566 RL 1.1 V to 1.8 V output for VCCx at 3.3 V and up to 3 V with VCCx AC at 5 V. For the best distortion, the common-mode output should 80Ω – 5Ω ½ RS + not go below 1.25 V at VCCx equal to 3.3 V and 1.35 V for 5 V 0.1µF 0.1µ+F 500Ω 10916-034 VtoC tChex VopCeOraMtioxn o. uNtoptuet t hvoatl ttahgee i nwphuetn c oacm-cmoounp-lmedo adte tvhoel tiangpeu stlsa.v es Figure 35. Basic Structure For dc-coupled inputs, the input common-mode voltage should also stay between 1.25 V and 1.8 V for a 3.3 V supply and 1.35 V to The ADL5566 is composed of a dual fully differential amplifier 3.5 V for a 5 V supply. Note again that, for ac-coupled applications with on-chip feedback and feed-forward resistors. The gain is fixed with series capacitors at the inputs, as in Figure 37, the output at 16 dB but can be reduced by adding two resistors in series with common-mode voltage, VCOMx, sets the common-mode input the two inputs (see the Gain Adjustment and Interfacing section). to the same level. Because of the wide input common-mode range, The amplifier is designed to provide a high differential open-loop this part can easily be dc-coupled to many types of mixers, gain and has an output common-mode circuit that enables the demodulators, and amplifiers. Forcing a higher input VCOMx user to change the output common-mode voltage by applying a does not affect the output VCOMx in dc-coupled mode. Note that, voltage to a VCOMx pin. The amplifier is designed to provide if the outputs are ac-coupled (see the ADC Interfacing section), superior low distortion at frequencies to and beyond 300 MHz no external VCOMx adjust is required because the amplifier with low noise and low power consumption. The low distortion common-mode outputs are set at VCCx/2. and noise are realized with a 3.3 V power supply at 140 mA. The dual amplifier has an extremely high gain bandwidth (GBW) product that results in distortion levels that are the best in the Rev. A | Page 14 of 24

Data Sheet ADL5566 APPLICATIONS INFORMATION BASIC CONNECTIONS and the output pins, Pin 13 (VON2) and Pin 14 (VOP2), are biased by applying a voltage to VCOM2. If VCOM2 is left open, Figure 36 shows the basic connections for operating the ADL5566. VCOM2 equals ½ of VCC2. The ADL5566 can be ac-coupled as Apply a voltage between 3 V and 5 V to the VCC1 and VCC2 shown in Figure 36 or can be dc-coupled if within the specified pins through a 5.1 nH inductor and decouple the supply side of the input and output common-mode voltage ranges (see the Circuit inductor with at least one low inductance, 0.1 µF surface-mount Description section). To enable the ADL5566, the ENBL1 and ceramic capacitor. In addition, decouple the VCOM1 and VCOM2 ENBL2 pins must be pulled high. Pulling the ENBL1/ENBL2 pins (Pin 21 and Pin 10) using a 0.1 µF capacitor. The ENBL1 pins low puts the ADL5566 in sleep mode, reducing the current and ENBL2 pins (Pin 22 and Pin 9) are tied to their amplifiers consumption to 7 mA at ambient. VCC_x pin to enable each amplifier. A differential signal is A series 5.1 nH inductor can be connected to the VCCx pins with applied to Amplifier 1 through Pin 1 (VIN1) and Pin 2 (VIP1) the V decoupling capacitor connected to the V bus side (see and to Amplifier 2 through Pin 5 (VIP2) and Pin 6 (VIN2). CC CC Figure 53.) This inductor with the internal capacitance of the Each amplifier has a gain of 16 dB. amplifier results in a two pole low-pass network and reduces the The input pins, Pin 1 (VIN1) and Pin 2 (VIP1), and the output amplifier V noise. CC pins, Pin 18 (VON1) and Pin 17 (VOP1), are biased by applying a voltage to Pin 21 (VCOM1). If VCOM1 is left open, VCOM1 equals ½ of VCC1. The input pins, Pin 5 (VIP2) and Pin 6 (VIN2), VCC + 0.01µF 0.01µF 10µF 5.1nH 5.1nH VCC2 VCC1 1181 1280 EXPOSED PAD RF 0.01µF VON1 1188 ½ RS 0.01µFVIP1 RG VCOM1 BASLOANUCRECDE VIN1 2121 2211 0.01µF BLOALAADNCED ½ RS 0.01µF RRGG VOP1 1177 ENBL1 RF 0.01µF VCC 222 ADL5566 ENBL2 VCC 19 RF 0.01µF VOP2 14 ½ RS 0.01µFVIP2 RG VCOM2 BASLOANUCRECDE VIN2 56 10 0.01µF BLOALAADNCED ½ RS 0.01µF RG VON2 13 RF 0.01µF NC NC 3 24 4 7 8 12 15 16 19 23 C C C C C C C C N N N N N N N N NOTES 1 . ETXOP AO LSOEDW PIMADPDEDLEA NISC EIN GTERRONUANLDL YP LCAONNEN.ECTED TO GND AND MUST BE SOLDERED 10916-035 Figure 36. Basic Connections Rev. A | Page 15 of 24

ADL5566 Data Sheet INPUT AND OUTPUT INTERFACING VCC The ADL5566 can be configured as a differential-input-to- differential-output driver, as shown in Figure 37. The 36 Ω RS 77RΩ2 0.1µ+F + ½ 0.1µ+F ½ RL resistors, R1 and R2, combined with the ETC1-1-13 balun ADL5566 transformer, provide a 50 Ω input match for the 160 Ω input AC ½ RL impedance. The input and output 0.1 μF capacitors isolate the – + + VCC/2 bias from the source and balanced load. The load should 0.1µF 0.1µF eSqpuecailf 2ic0a0t iΩon tso s pecrotivoind)e. the expected ac performance (see the 30RΩ1 10916-038 Figure 39. Single-Ended-Input-to-Differential-Output Configuration VCC The single-ended gain configuration of the ADL5566 is dependent ETC1-1-13 + + + on the source impedance and load, as shown in Figure 40. 50Ω R2 0.1µF 0.1µF ½ RL ½ ADL5566 AC 500Ω ½ RL – + + 80Ω 5Ω R1 0.1µF 0.1µF 10916-036 RS 77RΩ2 0.1µ+F +ADL½5566 0.1µ+F ½ RL Figure 37. Differential-Input-to-Differential-Output Configuration AC ½ RL The differential gain of the ADL5566 is dependent on the source 80Ω – 5Ω + + impedance and load, as shown in Figure 38. 0.1µF 0.1µF 500Ω 500Ω 30RΩ1 10916-039 Figure 40. Single-Ended Input Loading Circuit + 80Ω 5Ω 0.1µF + + The single-ended gain can be determined by the following two ½ RS ½ 0.1µF equations: ADL5566 RL AC R2131 R  80Ω – 5Ω MATCH R2131 ½ RS + 0.1µ+F 500Ω 0.1µF 10916-037 AV1805R0S0R2RSR2R2RMRAMTCAHTCHRS 10RLRL Figure 38. Differential Input Loading Circuit RSR2 The differential gain can be determined by GAIN ADJUSTMENT AND INTERFACING The effective gain of the ADL5566 can be reduced by adding two 500 RL AV  (1) resistors in series with the inputs to reduce the 16 dB gain. 80 10RL Single-Ended Input to Differential Output 500Ω The ADL5566 can also be configured in a single-ended-input-to- differential-output driver, as shown in Figure 39. In this RSERIES 80Ω 5Ω configuration, the gain of the part is reduced due to the application ½ RS 0.1µF + ½ 0.1µ+F of the signal to only one side of the amplifier. The input and output 0.1 μF capacitors isolate the V /2 bias from the source and the AC RSHUNT ADL5566 RL CC 0.1µF balanced load. R2 is used to match the single-ended input 80Ω – 5Ω impedance of the amplifier (131 Ω) with the 50 Ω source. R1 is ½ RS RSERIES 0.1µ+F 500Ω sAeNle-c0t9ed90 t ofo br amlaonrce ein tfhoer minaptuiot no fo tnh tee armmipnlaiftiienrg. Sseineg Alep-epnlidceatdi oinnp Nutost.e 10916-040 Figure 41. Gain Adjustment Using a Series Resistor Show The performance for this configuration is shown in Figure 16 and Figure 24. Rev. A | Page 16 of 24

Data Sheet ADL5566 To find RSERIES for a given AV gain and RL, use the following: The necessary shunt component, RSHUNT, to match to the source impedance, R, can be expressed as   S   1   R = (5) SHUNT 1 1   −   R 2R +160 S SERIES   500 R =  −80 (3) SERIES   The voltage gain for multiple shunt resistor values are summarized    AV  in Table 5. The source resistance and input impedance need  R  careful attention when using Equation 5. The reactance of the 10+LRL  input impedance of the ADL5566 and the ac coupling capacitors must be considered before assuming that they make a negligible To calculate the AV gain for a given RSERIES and RL, use the following: contribution. AGAIN= 500 × RL  (4) ––5550 HHDD23 33..33VV RSERIES+80 10+RL –60 IHMDD2 35.V3V 20 –65 HD3 5V 19 IMD 5V 18 –70 17 c) 111456 N (dB ––8705 1123 RTIO –85 11 O –90 dB) 109 DIST –95 GAIN ( 678 ––110050 5 4 –110 3 2 –115 1 –––3210 –1200 50 100 150 FR2E00QUE2N5C0Y (3M0H0z) 350 400 450 500 10916-042 –4 –51M 10M FREQU1E00NMCY (Hz) 1G 10G 10916-041 Figure 43. IMD, HD2, anVdP OHSD =3 3 v.3s. aFnredq VuPeOnS c=y ,5 A VV = 6 dB, 2 V p-p Output, Figure 42. SDD21, VPOS = 3.3 V, Three Gains, 25°C Table 5. Differential Gain Adjustment Using Series Resistor Target Gain (dB) Actual Gain (dB) R (Ω) R (Ω)1 R (Ω)1 S SERIES SHUNT 0 −0.1 50 396.2 52.8 1 +1.2 50 344.4 53.1 2 +2.1 50 298.3 53.5 3 +2.9 50 257.1 54 4 +4.1 50 220.5 54.5 5 +5.1 50 187.8 55.1 6 +6.1 50 158.7 55.8 7 +6.9 50 132.7 56.7 8 +8.1 50 109.6 57.6 9 +8.9 50 89 58.7 10 +10 50 70.6 60 11 +11.1 50 54.2 61.4 12 +12 50 39.6 63.2 13 +12.8 50 26.6 65.3 14 +14 50 15 67.9 15 +15.1 50 4.8 70.9 16 +15.8 50 0 72.7 1 The resistor values are rounded to the nearest real resistor value. Rev. A | Page 17 of 24

ADL5566 Data Sheet ADC INTERFACING FUNDAMENTAL1 = –7.03dBFS 0 FUNDAMENTAL2 = –7.05dBFS The ADL5566 is a dual high output linearity amplifier that is –15 IIMMDD ((22ff21 +– ff21)) == ––9906..5831ddBBcc optimized for ADC interfacing. One option of applying the –30 NOISE FLOOR = –114.703dB ADL5566 to drive an ADC is shown in Figure 47. The wideband FS) –45 1:1 transmission line balun provides a differential input to the dB amplifier, and the 36 Ω resistors provide a 50 Ω match to the DE ( –60 source. The ADL5566 is ac-coupled from the input and output LITU –75 to avoid common-mode loading. A reference voltage is required MP –90 A to bias the AD9268 inputs and is delivered through the 200 Ω –105 resistors. These, in parallel with the 400 Ω resistor, create the –120 low frequency amplifier load of 200 Ω. The 56 nH inductors –135 afinltde rt.h Teh 5e6 t wpFo c2a5p Ωac irteosri satroer su asered atod dcerdea ttoe raa 7is0e MthHe zA lDowL5-p56as6s –1500 6 12 18 F2R4EQUE30NCY 3(M6Hz)42 48 54 60 10916-044 output impedance, which reduces peaking when the filter drives a Figure 45. Measured Two-Tone Performance of the Circuit in Figure 47 for a light load. The two 25 Ω resistors provide isolation to the switching 32 MHz and 33 MHz Input Signals currents of the ADC sample-and-hold circuitry. The AD9268 2 dual ADC presents a 6 kΩ differential load impedance and requires 1 0 a 1 V p-p to 2 V p-p input signal to reach full scale. The system –1 –2 frequency response is shown in Figure 46. By applying a 2 V p-p, –3 –4 32 MHz single-tone signal from the ADL5566 in a gain of 16 dB, S) –5 BF –6 an SFDR of 94.6 dBc is achieved. By applying two half scale signals D (d ––87 of 32 MHz and 33 MHz from the ADL5566 in a gain of 16 dB, ZE –9 LI –10 an SFDR of 90.5 dBc is realized. MA –11 R –12 0 SNR = 74.28dB NO ––1143 FUND FREQ = 32.123MHz –15 FUND POWER = –1.014dBFS –15 SECOND HARM = –94.629dBc –16 –30 THIRD HARM = –95.19dBc –17 FOURTH HARM = –99.98dBc –18 E (dBFS) ––4650 FSIIFXTTHH HHAARRMM == ––110047..917015ddBBcc ––21090 20 40 F6R0EQUE8N0CY (M1H0z0) 120 140 160 10916-045 UD –75 Figure 46. Measured Relative Frequency Response of the Wideband ADC T LI –90 Interface Depicted in Figure 47 P AM–105 4 3 + 5 6 2 –120 –135 –150 0 6 12 18 FR24EQUE30NCY 3 (6MHz)42 48 54 60 10916-043 Figure 44. Measured Single-Tone Performance of the Circuit in Figure 47 for a 32 MHz Input Signal VCC 0.1µF ETC1-1 VIN_1 25Ω 25Ω + + + 50Ω 36Ω 0.1µF 200Ω ½ AC ADL5566 VREF 56pF 400Ω ASDID9E2 A68 16 200Ω VIP_1 – 25Ω 25Ω + + 36Ω 0.1µF 0.1µF 10916-046 Figure 47. Wideband ADC Interfacing Example Featuring the AD9268 Rev. A | Page 18 of 24

Data Sheet ADL5566 DC-COUPLED RECEIVER APPLICATION The ADL5566 is well suited for dc-coupled applications, such performance. When using the ADL5566 as shown in Figure 48, as zero-IF direct conversion receivers. An example receiver the OIP3s at the outputs are improved due to the high OIP3 of configuration is shown in Figure 48, consisting of the ADL5380 the amplifier pair (see Table 6). In a real-world receiver where quadrature demodulator and the ADL5566 dual differential blockers are present, it is advantageous to insert a low-pass filter amplifier. This is an ideal combination because of the wide RF between the ADL5380 and the ADL5566 to remove these input bandwidth from 400 MHz to 6 GHz, the high linearity of the undesired signals. ADL5566, and when operating on a 5 V supply, level shifting to If the ADL5566 is followed by an ADC, insert an antialiasing align the common-mode voltage is not required. filter between the ADL5566 and the ADC to prevent broadband The interface between the ADL5380 and the ADL5566 is noise from aliasing back in band. For more information on this straight forward because the impedance presented by the interface, see the ADC Interfacing section. ADL5566 is sufficiently high enough to permit directly The cascade of the performance of the circuit shown in Figure 48 is connecting the two devices without any degradation in presented in Table 6. VS VCC + 0.1µF 0.1µF 0.1µF 0.01µF 0.01µF 10µF 5.1nH 5.1nH 100pF 100pF 100pF 1.5kΩ CC1 CC2 CC3 DJ VCC2 1181 VCC1 2108 V V V A 6 13 24 19 RF NC 12 ILO VON1 0.01µF 4 1188 ENBL IHI VIP1 RG VCOM1 7 3 VIN1 2121 2211 0.01µF BLOALAADNCED 23GND3 RRGG VOP1 1177 TC1-1-13 100pF RFIP22 LOIP 100pF TC1-1-13 VCC ENBL1222 RF 0.01µF 9 90° ADL5566 0Ω 100pF RFIN 21 0° 10 LOIN 100pF R4 VCC ENBL2 19 RF GND31 20GND3 0Ω VIP2 RG 14 VVOCOP2M20.01µF GND1 16 QHI VIN2 56 10 0.01µF BLOALAADNCED 2 RG QLO VON2 15 13 GND1 RF 0.01µF 5 NC NC 18GND3 3 24 4 7 8 12 15 16 19 23 8 GND4 11 GND4 14 GND2 17 GND2 NC NC NC NC NC NC NC NC 10916-052 Figure 48. DC-Coupled Interface Example Featuring the ADL5380 Table 6. Cascade Performance of the ADL5380 and ADL5566 IF Frequency = 200 MHz, R = 200 Ω, V = 2 V p-p Composite L OUT Frequency (MHz) HD2 (dBc) HD3 (dBc) OIP3 (dBm) ADL5380 OIP3 (dBm)1 OIP2 (dBm) Voltage Gain (dB) Power Gain (dB) 900 −79.3 −84.2 44.9 26.2 91.8 18.1 12.0 1900 −82.2 −80.5 40.8 26.5 83.9 18.1 12.0 2700 −80.7 −73.9 39.6 25.7 75.6 18.1 12.0 1 Output referred IP3 of the ADL5380, PIN = −14 dBm, and RL = 200 Ω. Rev. A | Page 19 of 24

ADL5566 Data Sheet LAYOUT CONSIDERATIONS High-Q inductive drives and loads, as well as stray transmission many board designs, the signal trace widths should be minimal line capacitance in combination with package parasitics, can where the driver/receiver is no more than one-eighth of the wave- potentially form a resonant circuit at high frequencies, resulting length from the amplifier. This nontransmission line configuration in excessive gain peaking or possible oscillation. If RF transmission requires that underlying and adjacent ground and low impedance lines connecting the input or output are used, design them such planes be dropped from the signal lines. that stray capacitance at the input/output pins is minimized. In VCC + 0.1µF 5.1nH 0.1µF ETC1-1 VIN_1 84.5Ω ETC1-1 + + + 50Ω 36Ω 0.1µF ½ 34.8Ω 50Ω ADL5566 AC AMPLIFIER 1 ANALYZER VIP_1 – 84.5Ω + + 36Ω 0.1µF 0.1µF 34.8Ω 10916-047 Figure 49. General-Purpose Characterization Circuit VCC + 0.1µF 5.1nH 0.1µF 0.1µF PORT 1 VIN_1 50Ω PORT 3 + + + 50Ω ½ 50Ω 36Ω ADL5566 AC AC AMPLIFIER 1 PORT 2 VIP_1 – 50Ω PORT 4 + + 50Ω 0.1µF 0.1µF 50Ω AC AC 10916-048 Figure 50. Differential Characterization Circuit Using Agilent E8357A Four-Port PNA INPUT COMMON-MODE V ADJUST VCC + 0.1µF 2kΩ 2kΩ 5.1nH 0.1µF 0.1µF ETC1-1 VIN_1 84.5Ω ETC1-1 + + + 50Ω 36Ω 34.8Ω 50Ω ADL5566 AC AMPLIFIER 1 ANALYZER VIP_1 – 84.5Ω + + 36Ω 0.1µF 0.1µF 34.8Ω OVUCTOPMUT 10916-049 Figure 51. Distortion Measurement Circuit for Various Common-Mode Voltages Rev. A | Page 20 of 24

Data Sheet ADL5566 SOLDERING INFORMATION AND RECOMMENDED EVALUATION BOARD LAND PATTERN Figure 53 shows the schematic of the ADL5566 evaluation board. Figure 52 shows the recommended land pattern for the ADL5566. The board is powered by a single supply in the 3 V to 5 V range. The ADL5566 is contained in a 4 mm × 4 mm LFCSP package, The power supply is decoupled by 10 µF and 0.1 µF capacitors. The which has an exposed ground paddle (EPAD). This paddle is L1 and L2 inductors decouple the ADL5566 from the power supply. internally connected to the ground of the chip. To minimize Table 7 details the various configuration options of the evaluation thermal impedance and ensure electrical performance, solder board. Figure 54 and Figure 55 show the component and circuit the paddle to the low impedance ground plane on the printed side layouts of the evaluation board. circuit board (PCB). To further reduce thermal impedance, it The balanced input and output interfaces are converted to single is recommended that the ground planes on all layers under the ended with a pair of baluns (M/A-COM ETC1-1-13). The baluns paddle be stitched together with vias. at the input, T1 and T2, provide a 50 Ω single-ended-to-differential For more information on land pattern design and layout, refer transformation. The output baluns, T3 and T4, and the matching to the AN-772 Application Note, A Design and Manufacturing components are configured to provide a 200 Ω to 50 Ω impedance Guide for the Lead Frame Chip Scale Package (LFCSP). transformation with an insertion loss of about 11 dB. This land pattern, on the ADL5566 evaluation board, provides a measured thermal resistance (θ ) of 34.0°C/W. To measure θ , JA JA the temperature at the top of the LFCSP package is found with an IR temperature gun. Thermal simulation suggests a junction temperature 1.5°C higher than the top of package temperature. With additional ambient temperature and I/O power measure- ments, θ can be determined. JA 91 MILS 157.4 MILS 98.4 MILS 91 MILS 13 MILS 13.7 MILS 39 MILS 19.7 MILS 12 MILS 10916-050 Figure 52. Recommended Land Pattern Rev. A | Page 21 of 24

ADL5566 Data Sheet ENBL_1 VCOM-1 VCC 123 C6 GND VCC VPOS 0.1µF 0.C17µF VCC C21 + 10µF C3 0.1µF L2 5.1nH 2 2 C12 C10 DNI 24 23 22 21 20 19 DNI VOP1 VVIIPN11 DRN1I T1 R361Ω0 0.C0113µF 00RRΩΩ58 12 VVIIPIN1NC1 NC ENBL1 VCOM1 VCC1 VVNCOONP11 1187 0.C0118µ0F.C0117µF 8R4.154Ω R341.88Ω T3 RD2N7I VON1DNI DNI R9 C14 ADL5566 R13 R17 R25 R3 36Ω 0.01µF 84.5Ω 34.8Ω 0Ω 0Ω 3 NC NC 16 VON2 VIP2 T2 3R61Ω1 0.C0115µF R02Ω1 45 NVICP2 EXPOSEDPADDLE VONPC2 1154 0.C0210µF 8R4.156Ω R342.08Ω T4 R2 R24 DNI VOP2 VDINNI2 DNI 0RΩ4 R361Ω2 0.C0116µF 0Ω 6 VIN2NC NC ENBL2 VCOM2 VCC2 VNCON2 13 0.C0119µF 8R4.155Ω R341.98Ω R0Ω26 R28 DNI 2 7 8 9 10 11 12 2 C1 C11 DNI DNI L1 5.1nH VPOS C0.41µF C2 C5 0.1µF 0.1µF E1NB2L3_2 VCOM-2 VCC 10916-051 Figure 53. Evaluation Board Schematic Table 7. Evaluation Board Configuration Options Component Description Default Condition V , GND Ground and supply test loops. V , GND = installed POS POS C5, C7, C21, L1, Power supply decoupling. The supply decoupling consists of a 10 μF capacitor (C21) and C21 = 10 μF (Size D), L2 two 0.1μF capacitors, C5 and C7, connected between the supply lines and ground. C5, C7 = 0.1 μF (Size 0402), L1 and L2 decouple the ADL5566 from the power supply. L1, L2 = 5.1 nH (Size 0603) VIN1, VIP1, VIP2, Input interface. The SMA labeled VIN1 is the input to Amplifier 1. T1 is a 1:1 VIN1, VIP2 = installed, VIN2, R1, R2, R3, impedance ratio balun to transform a single-ended input into a balanced differential VIP1, VIN2 = not installed, R4, R5, R8, R9, signal. Removing R3, installing R1 (0 Ω), and installing an SMA connector (VIP1) allow R1, R2 = DNI, R10, R11, R12, driving from a differential source. C13 and C14 provide ac coupling. C12 is an R3, R4, R5, R8, R21, R24 = 0 Ω R21, R24, C13, optional bypass capacitor. R9 and R10 provide a differential 50 Ω input termination. The (Size 0402), C1, C12, C14, SMA labeled VIP2 is the input to Amplifier 2. T2 is a 1:1 impedance ratio balun to R9, R10, R11, R12 = 36 Ω (Size 0402), C15, C16, T1, T2 transform a single-ended input into a balanced differential signal. Removing R4, C13, C14, C15, C16 = 0.01 μF installing R2 (0 Ω), and installing an SMA connector (VIN2) allow driving from a (Size 0402), differential source. C15 and C16 provide ac coupling. C1 is an optional by pass capacitor. C1, C12 = DNI, R11 and R12 provide a differential 50 Ω input termination. T1, T2 = ETC1-1-13 (M/A-COM) VOP1, VON1, Output interface. The SMA labeled VOP1 is the output for Amplifier 1. T3 is a 1:1 VOP1, VON2 = installed, VON2, VOP2, impedance ratio balun used to transform a balanced differential signal to a single- VON1, VOP2 = not installed, C10, C11, C17, ended signal. Removing R25, installing R27 (0 Ω), and installing an SMA connector R13, R14, R15, R16 = 84.5 Ω C18, C19, C20, (VON1) allow differential loading. C10 is an optional bypass capacitor. C17 and C18 (Size 0402), R13, R14, R15, provide ac coupling. R13, R14, R17, and R16 are provided for generic placement of R17, R18, R19, R20 = 34.8 Ω R16, R17, R18, matching components. (Size 0402), R19, R20, R25, The SMA labeled VON2 is the output for Amplifier 2. T4 is a 1:1 impedance ratio balun R25, R26 = 0 Ω (Size 0402), R26, R27, R28, used to transform a balanced differential signal to a single-ended signal. Removing R26, R27, R28 = DNI (Size 0402), T3, T4 installing R28 (0 Ω), and installing an SMA connector (VOP2) allow differential loading. C10, C11 = DNI (Size 0402), C11 is an optional bypass capacitor. C19 and C20 provide ac coupling. R15, R16, R19, C17, C18 = 0.01 μF (Size 0402), and R20 are provided for generic placement of matching components. C19, C20 = 0.01 μF (Size 0402), The evaluation board is configured to provide a 200 Ω to 50 Ω impedance T3, T4 = ETC1-1-13 (M/A-COM) transformation with an insertion loss of 11 dB. Rev. A | Page 22 of 24

Data Sheet ADL5566 Component Description Default Condition ENBL_1, Device enable. ENBL_1 is the enable for Amplifier 1. Connecting a jumper between ENBL_1, ENBL_2 = installed, ENBL_2, C3, C4 Pin 2 and V enables Amplifier 1. C3 is a bypass capacitor. ENBL_2 is the enable for C3, C4 = 0.1 µF (Size 0402) POS Amplifier 2. Connecting a jumper between Pin 2 and V enables Amplifier 2. C4 is POS a bypass capacitor. VCOM-1, Common-mode voltage interface. VCOM1 is the common-mode interface for VCOM-1, VCOM-2 = installed VCOM-2, C2, C6 Amplifier 1. A voltage applied to this pin sets the common-mode voltage of the output C2, C6 = 0.1 µF (Size 0402) of Amplifier 1. VCOM2 is the common-mode interface for Amplifier 2. A voltage applied to this pin sets the common-mode voltage of the output of Amplifier 2. Typically decoupled to ground with a 0.1 µF capacitor (C2 and C6). With no reference applied, input and output common mode float to midsupply (V /2). CC 10916-054 10916-055 Figure 54. Layout of Evaluation Board, Component Side Figure 55. Layout of Evaluation Board, Circuit Side Rev. A | Page 23 of 24

ADL5566 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ PIN 1 3.90 INDICATOR PIN 1 0.50 19 24 INDICATOR BSC 18 1 2.40 EXPPAODSED 2.30 SQ 2.20 6 13 0.50 12 7 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.70 0.05 MAX FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.30 0.08 PLANE 0.25 0.203 REF 0.20COMPLIANTTOJEDEC STANDARDS MO-220-WGGD-8. 01-18-2012-A Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-14) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADL5566ACPZ-R7 −40°C to + 85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7” Tape and Reel CP-24-14 ADL5566-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10916-0-12/13(A) Rev. A | Page 24 of 24

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