DC to 6 GHz Envelope and TruPwr RMS Detector Data Sheet ADL5511 FEATURES FUNCTIONAL BLOCK DIAGRAM Envelope tracking RF detector with output proportional to VPOS 15 input voltage ADL5511 Separate TruPwr rms output 400Ω 20pF No balun or external tuning required ENBL 4 BDIAOSW ANN CDO PNOTWROERL- 14 FLT4 Excellent temperature stability 100Ω Input power dynamic range of 47 dB RMS G = 1.7 11 VRMS Input frequency range from dc to 6 GHz RFIN 2 10kΩ 250Ω 130 MHz envelope bandwidth ENVELOPE G = 1.5 10 VENV FLT1 3 Envelope delay: 2 ns 5pF 250Ω 9 EREF Single-supply operation: 4.75 V to 5.25 V 0.4pF 400Ω 0.8pF Supply current: 21.5 mA VPOS VPOS Power-down mode: 130 μW APPLICATIONS 13 6N7C 8 12 FL1T62 FL1T3 CO5MM 09602-001 Figure 1. RMS power and envelope detection of W-CDMA, CDMA2000, LTE, and other complex waveforms Drain modulation based power amplifier linearization VRMS CH1 HIGH 20mV Power amplifier linearization employing envelope-tracking methods VENV RF INPUT CCHH13 220000mmVV Ω CCHH24 3203.48mmVV ΩΩ MT 100n–s68nsA CH4 1.60V 09602-002 Figure 2. RMS and Envelope Response to a 20 MHz QPSK-Based LTE Carrier (Test Model E-TM1_1_20MHz) GENERAL DESCRIPTION The ADL5511 is an RF envelope and TruPwr™ rms detector. The ADL5511 can operate from dc to 6 GHz on signals with The envelope output voltage is presented as a voltage that is envelope bandwidths up to 130 MHz. proportional to the envelope of the input signal. The rms The extracted envelope can be used for RF power amplifier output voltage is independent of the peak-to-average ratio (PA) linearization and efficiency enhancements and the rms of the input signal. output can be used for rms power measurement. The high rms The rms output is a linear-in-V/V voltage with a conversion accuracy and fast envelope response are particularly useful for gain of 1.9 V/V rms at 900 MHz. The envelope output has a envelope detection and power measurement of broadband, high conversion gain of 1.46 V/V at 900 MHz and is referenced to peak-to-average signals that are used in CDMA2000, W-CDMA, an internal 1.1 V reference voltage, which is available on the and LTE systems. EREF pin. The ADL5511 operates from −40°C to +85°C and is available in a 16-lead, 3 mm × 3 mm LFCSP package. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADL5511 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Drive Capability and Buffering ................................... 18 Applications ....................................................................................... 1 Applications Information .............................................................. 19 Functional Block Diagram .............................................................. 1 Basic Connections ...................................................................... 19 General Description ......................................................................... 1 Operation Below 1 GHz/Envelope Filtering ........................... 19 Revision History ............................................................................... 2 Choosing a Value for the RMS Averaging Capacitor (C ) .. 20 FLT4 Specifications ..................................................................................... 3 Envelope Tracking Accuracy .................................................... 21 Absolute Maximum Ratings ............................................................ 7 Time Domain Envelope Tracking Accuracy .......................... 21 ESD Caution .................................................................................. 7 VRMS and VENV Output Offset ............................................. 22 Pin Configuration and Function Descriptions ............................. 8 Device Calibration and Error Calculation .............................. 23 Typical Performance Characteristics ............................................. 9 Error vs. Frequency .................................................................... 24 Circuit Description ......................................................................... 17 Evaluation Board ........................................................................ 24 Envelope Propagation Delay ..................................................... 17 Outline Dimensions ....................................................................... 27 RMS Circuit Description ........................................................... 17 Ordering Guide .......................................................................... 27 RMS Filtering .............................................................................. 17 REVISION HISTORY 7/2018—Rev. C to Rev. D Changes to Figure 55 and Figure 56 ............................................. 23 7/2017—Rev. B to Rev. C Changes to Table 1 ............................................................................ 3 Changes to Figure 3 .......................................................................... 8 Changes to Figure 4 Caption and Figure 5 Caption..................... 9 Updated Outline Dimensions ....................................................... 26 Change to Ordering Guide ............................................................ 26 5/2014—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 26 2/2012—Rev. 0 to Rev. A Changes to Equation 4 ................................................................... 19 Updated Outline Dimensions ....................................................... 26 7/2011—Revision 0: Initial Version Rev. D | Page 2 of 27

Data Sheet ADL5511 SPECIFICATIONS T = 25°C, V = 5 V, C = 100 nF, 75 Ω shunt termination resistor to ground on (ac-coupled) RFIN, three-point calibration on V A POS FLT4 ENV and V at +5 dBm, −15 dBm, and −26 dBm, unless otherwise noted. RMS Table 1. Parameter Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGE Input RFIN DC 6 GHz ENVELOPE CONVERSION (100 MHz) Input RFIN to output (V − V ) ENV EREF Input Range (±1 dB Error) CW input 46 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −29 dBm Conversion Gain V = (Gain × V ) + Intercept 1.42 V/V rms ENV IN Intercept −5 mV Output Voltage V − V ENV EREF High Power In P = +10 dBm, +707 mV rms 1.00 V IN Low Power In P = −20 dBm, +22.4 mV rms 26 mV IN RMS Conversion Input RFIN to output (V ) RMS Input Range (±1 dB Error) CW input 46 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −29 dBm Conversion Gain V = (Gain × V ) + Intercept 1.92 V/V rms RMS IN Intercept 11 mV Output Voltage High Power In P = +10 dBm, +707 mV rms 1.38 V IN Low Power In P = −20 dBm, +22.4 mV rms 53 mV IN ENVELOPE CONVERSION (900 MHz) Input RFIN to output (V − V ) ENV EREF Input Range (±1 dB Error) CW input 46 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −29 dBm Conversion Gain V = (Gain × V ) + Intercept 1.46 V/V rms ENV IN Intercept −5 mV Output Voltage V − V ENV EREF High Power In P = +10 dBm, +707 mV rms 1.02 V IN Low Power In P = −20 dBm, +22.4 mV rms 26 mV IN RMS Conversion Input RFIN to output (V ) RMS Input Range (±1 dB Error) CW input 46 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −29 dBm Conversion Gain V = (Gain × V ) + Intercept 1.9 V/V rms RMS IN Intercept 13 mV Output Voltage High Power In P = +10 dBm, +707 mV rms 1.35 V IN Low Power In P = −20 dBm, +22.4 mV rms 54 mV IN Rev. D | Page 3 of 27

ADL5511 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit ENVELOPE CONVERSION (1900 MHz) Input RFIN to output (V − V ) ENV EREF Input Range (±1 dB Error) CW input 47 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −30 dBm Conversion Gain V = (Gain × V ) + Intercept 1.5 V/V rms ENV IN Intercept −5 mV Output Voltage V − V ENV EREF High Power In P = +10 dBm, +707 mV rms 1.05 V IN Low Power In P = −20 dBm, +22.4 mV rms 28 mV IN RMS Conversion Input RFIN to output (V ) RMS Input Range (±1 dB Error) CW input 47 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −30 dBm Conversion Gain V = (Gain × V ) + Intercept 1.96 V/V rms RMS IN Intercept 14 mV Output Voltage High Power In P = +10 dBm, +707 mV rms 1.40 V IN Low Power In P = −20 dBm, +22.4 mV rms 56 mV IN ENVELOPE CONVERSION (2140 MHz) Input RFIN to output (V − V ) ENV EREF Input Range (±1 dB Error) CW Input 47 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −30 dBm Conversion Gain V = (Gain × V ) + Intercept 1.53 V/V rms ENV IN Intercept −5 mV Output Voltage V − V ENV EREF High Power In P = +10 dBm, +707 mV rms 1.07 V IN Low Power In P = −20 dBm, +22.4 mV rms 28 mV IN RMS Conversion Input RFIN to output (V ) RMS Input Range (±1 dB Error) CW input 47 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −30 dBm Conversion Gain V = (Gain × V ) + Intercept 1.99 V/V rms RMS IN Intercept 13 mV Output Voltage High Power In P = +10 dBm, +707 mV rms 1.42 V IN Low Power In P = −20 dBm, +22.4 mV rms 56 mV IN ENVELOPE CONVERSION (2600 MHz) Input RFIN to output (V − V ) ENV EREF Input Range (±1 dB Error) CW Input 47 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −30 dBm Conversion Gain V = (Gain × V ) + Intercept 1.56 V/V rms ENV IN Intercept −3 mV Output Voltage V − V ENV EREF High Power In P = +10 dBm, +707 mV rms 1.10 V IN Low Power In P = −20 dBm, +22.4 mV rms 30 mV IN RMS Conversion Input RFIN to output (V ) RMS Input Range (±1 dB Error) CW input 47 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −30 dBm Conversion Gain V = (Gain × V ) + Intercept 2.04 V/V rms RMS IN Intercept 15 mV Output Voltage Rev. D | Page 4 of 27

Data Sheet ADL5511 Parameter Test Conditions/Comments Min Typ Max Unit High Power In P = +10 dBm, +707 mV rms 1.46 V IN Low Power In P = −20 dBm, +22.4 mV rms 58 mV IN ENVELOPE CONVERSION (3500 MHz) Input RFIN to output (V − V ) ENV EREF Input Range (±1 dB Error) CW Input 47 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −30 dBm Conversion Gain V = (Gain × V ) + Intercept 1.56 V/V rms ENV IN Intercept −5 mV Output Voltage V − V ENV EREF High Power In P = +10 dBm, +707 mV rms 1.10 V IN Low Power In P = −20 dBm, +22.4 mV rms 28 mV IN RMS Conversion Input RFIN to output (V ) RMS Input Range (±1 dB Error) CW input 47 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −30 dBm Conversion Gain V = (Gain × V ) + Intercept 2.03 V/V rms RMS IN Intercept 12 mV Output Voltage High Power In P = +10 dBm, +707 mV rms 1.46 V IN Low Power In P = −20 dBm, +22.4 mV rms 57 mV IN ENVELOPE CONVERSION (6000 MHz) Input RFIN to output (V − V ) ENV EREF Input Range (±1 dB Error) CW Input 45 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −28 dBm Conversion Gain V = (Gain × V ) + Intercept 0.85 V/V rms ENV IN Intercept −10 mV Output Voltage V − V ENV EREF High Power In P = +10 dBm, +707 mV rms 0.60 V IN Low Power In P = −20 dBm, +22.4 mV rms 11 mV IN RMS Conversion Input RFIN to output (V ) RMS Input Range (±1 dB Error) CW input 45 dB Maximum Input Level 1 dB error 17 dBm Minimum Input Level 1 dB error −28 dBm Conversion Gain V = (Gain × V ) + Intercept 1.11 V/V rms RMS IN Intercept 7 mV Output Voltage High Power In P = +10 dBm, +707 mV rms 0.80 V IN Low Power In P = −20 dBm, +22.4 mV rms 35 mV IN ENVELOPE OUTPUT Pin VENV Maximum Output Voltage V = 5 V, R ≥ 500 Ω, C ≤ 10 pF 3.5 V POS LOAD LOAD Output Offset No signal at RFIN 2 mV Envelope Bandwidth 3 dB 130 MHz Pulse Response Time Input level = no signal to 5 dBm, 10% to 90% response time 4 ns Envelope Delay RFIN to VENV 2 ns Output Current Drive Load = 500 Ω||10 pF 15 mA RMS OUTPUT Pin VRMS Maximum Output Voltage V = 5 V, R ≥ 10 kΩ 3.8 V POS LOAD Output Offset No signal at RFIN 23 mV Output Current Drive Load = 1.3 kΩ 3 mA Rev. D | Page 5 of 27

ADL5511 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit ENABLE INTERFACE Pin ENBL Logic Level to Enable Power 4.75 V ≤ V ≤ 5.25 V 3.6 V POS Logic Level to Disable Power 4.75 V ≤ V ≤ 5.25 V 2.0 V POS POWER SUPPLIES Operating Range −40°C < T < +85°C 4.75 5.25 V A Quiescent Current RFIN < −10 dBm, ENBL high 21.5 mA RFIN < −10 dBm, ENBL low 26 μA RFIN = 15 dBm, ENBL high 43.8 mA Rev. D | Page 6 of 27

Data Sheet ADL5511 ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 2. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these Supply Voltage, VPOS 5.5 V or any other conditions above those indicated in the operational ENBL 0 V, VPOS section of this specification is not implied. Operation beyond RFIN (RFIN AC-Coupled) 5.6 V p-p the maximum operating conditions for extended periods may Equivalent RF Power (Peak Envelope Power or 19 dBm affect product reliability. CW), re: 50 Ω Internal Power Dissipation 580 mW θ 68.9°C/W JA ESD CAUTION θ 17.5°C/W JC Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C ESD (FICDM) 1250 V ESD (HBM) 2000 V Rev. D | Page 7 of 27

ADL5511 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LT2 POS LT4 C PIN 1 F V F N INDICATOR 16 15 14 13 FLT3 1 12 NC RFIN 2 ADL5511 11 VRMS FLT1 3 (NToOt Pto V SIEcaWle) 10 VENV ENBL 4 9 EREF 5 6 7 8 M C C C M N N N O C NOTES 12 .. TNTHOCE =B E ONXTOPH OC TSOHENEDNR EPMCAATDL. SDAHONO DNU OELLTDE CBCOETN RCNIOCENACNLT E GTCROTO ETUDHNISD SP.IN. 09602-103 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 16 FLT3, FLT2 External Envelope Filter. With the FLT3 and FLT2 pins not connected, two internal low-pass filters (operating in series) with corner frequencies of approximately 1000 MHz and 800 MHz remove the residual RF carrier (at two times the original input frequency) from the envelope signal. External, supply-referenced capacitors connected to FLT3 and FLT2 can be used to reduce this corner frequency. See the Basic Connections section for more information. 2 RFIN RF Input. RFIN should be externally ac-coupled. RFIN has a nominal input impedance of 250 Ω. To achieve a broadband 50 Ω input impedance, an external 75 Ω shunt resistor should be connected between the source side of the ac coupling capacitor and ground. 3 FLT1 External Envelope Filter. A capacitor to ground on this pin can be used to reduce the nominal minimum input frequency. The capacitance on this pin helps to reduce any residual RF carrier presence on the EREF output pin. See the Basic Connections section for more information. 4 ENBL Device Enable/Disable. A logic high on this pin enables the device. A logic low on this pin disables the device. 5 COMM Device Ground. Connect to a low impedance ground plane. 6, 7, 8, 12, 13 NC Do not connect to these pins. 9 EREF Reference Voltage for Envelope Output. The nominal value is 1.1 V. 10 VENV Envelope Output. The voltage on this pin represents the envelope of the input signal and is referred to EREF. VENV can source a current of up to 15 mA. Capacitive loading should not exceed 10 pF to achieve the specified envelope bandwidth. Lighter loads should be chosen when possible. The nominal output voltages on EREF and VENV with no signal present track with temperature. For dc-coupled envelope output, EREF should be used as a reference giving the true envelope voltage of V − V . For ac coupling of the ENV EREF envelope output, the VENV pin can drive a 50 Ω load, if maximum current drive capability of 15 mA is not exceeded. See the Output Drive Capability and Buffering section for more information. 11 VRMS RMS Output Pin. This voltage is ground referenced and has a nominal swing of 0 V to 3.8 V. V has a linear- RMS in-V/V transfer function with a nominal slope of 2 V/V. 14 FLT4 RMS Averaging Capacitor. Connect between FLT4 and VPOS. 15 VPOS Supply Voltage Pin. Operational range is 4.75 V to 5.25 V with a supply current of 21.5 mA. 0 EP Exposed Pad. The exposed pad should be connected to both thermal and electrical grounds. Rev. D | Page 8 of 27

Data Sheet ADL5511 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = 5 V, C = 100 nF, 75 Ω shunt termination resistor to ground on (ac-coupled) RFIN, T = +25°C (black), −40°C (blue), A POS FLT4 A +85°C (red), three-point calibration on V and V at +5 dBm, −15 dBm, and −26 dBm, unless otherwise noted. ENV RMS 10 10 100MHz 100MHz 900MHz 900MHz 1900MHz 1900MHz 2140MHz 2140MHz 2600MHz 2600MHz 1 3500MHz 3500MHz 6000MHz 6000MHz 1 V) V) T ( T ( PU 0.1 PU T T U U O O 0.1 0.01 0.001–30 –25 –20 –15 –1IN0PUT– 5(dBm)0 5 10 15 20 09602-003 0.01–30 –25 –20 –15 –1IN0PUT– 5(dBm)0 5 10 15 20 09602-006 Figure 4. VENV − VEREF Output vs. Input Level, at Various Frequencies Figure 7. VRMS Output vs. Input Level, at Various Frequencies at 25°C, at 25°C, Supply 5 V Supply 5 V 10 10 5V, –40°C 5V, –40°C 5V, +25°C 5V, +25°C 5V, +85°C 5V, +85°C 1 1 V) V) T ( T ( PU 0.1 PU T T U U O O 0.1 0.01 0.001–30 –25 –20 –15 –1IN0PUT– 5(dBm)0 5 10 15 20 09602-004 0.01–30 –25 –20 –15 –1IN0PUT– 5(dBm)0 5 10 15 20 09602-007 Figure 5. VENV − VEREF Output vs. Input Level and Temperature at Figure 8. VRMS Output vs. Input Level and Temperature at 1900 MHz, 1900 MHz, Supply 5 V Supply 5 V 75 450 3.0 –40°C 70 +25°C 2.8 65 +85°C 400 2.6 60 2.4 350 A) 55 Ω) 2.2 pF) T (m 50 CE ( 300 2.0 CE ( N 45 N 1.8 N SUPPLY CURRE 2233405050 SHUNT RESISTA 122505000 SHUNT RESISTANCE 01111.....80246 HUNT CAPACITA 15 100 0.6 S 10 0.4 50 5 SHUNT CAPACITANCE 0.2 0–30 –25 –20 –15 –1IN0PUT– 5(dBm0) 5 10 15 20 09602-005 00 1 2FREQUEN3CY (GHz)4 5 60 09602-008 Figure 6. Supply Current vs. Input Level and Temperature Figure 9. Input Impedance vs. Frequency Rev. D | Page 9 of 27

ADL5511 Data Sheet 3 3 2 2 1 1 B) B) d d R ( 0 R (0 O O R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-009 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-012 Figure 10. VENV Output Temperature Drift from +25°C, Three-Point Figure 13. VENV Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 100 MHz Multiple Devices at −40°C and +85°C at 100 MHz 3 3 2 2 1 1 B) B) d d R ( 0 R ( 0 O O R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-010 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-013 Figure 11. VRMS Output Temperature Drift from +25°C, Three-Point Figure 14. VRMS Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 100 MHz Multiple Devices at −40°C and +85°C at 100 MHz 3 3 2 2 1 1 B) B) d d R ( 0 R ( 0 O O R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (dB–5m) 0 5 10 15 09602-011 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-014 Figure 12. VENV Output Temperature Drift from +25°C, Three-Point Figure 15. VENV Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 900 MHz Multiple Devices at −40°C and +85°C at 900 MHz Rev. D | Page 10 of 27

Data Sheet ADL5511 3 3 2 2 1 1 ERROR (dB) 0 ERROR (dB) 0 –1 –1 –2 –2 –3 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-015 –30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-031 Figure 16. VRMS Output Temperature Drift from +25°C, Three-Point Figure 19. VRMS Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 900 MHz Multiple Devices at −40°C and +85°C at 900 MHz 3 3 2 2 1 1 B) B) d d OR ( 0 OR ( 0 R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-029 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-032 Figure 17. VENV Output Temperature Drift from +25°C, Three-Point Figure 20. VENV Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 1900 MHz Multiple Devices at −40°C and +85°C at 1900 MHz 3 3 2 2 1 1 B) B) OR (d 0 OR (d 0 R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-030 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-033 Figure 18. VRMS Output Temperature Drift from +25°C, Three-Point Figure 21. VRMS Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 1900 MHz Multiple Devices at −40°C and +85°C at 1900 MHz Rev. D | Page 11 of 27

ADL5511 Data Sheet 3 3 2 2 1 1 B) B) d d OR ( 0 OR ( 0 R R R R E E –1 –1 –2 –2 –3 –3 –30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-034 –30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-037 Figure 22. VENV Output Temperature Drift from +25°C, Three-Point Figure 25. VENV Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 2140 MHz Multiple Devices at −40°C and +85°C at 2140 MHz 3 3 2 2 1 1 B) B) OR (d 0 OR (d 0 R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-035 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-038 Figure 23. VRMS Output Temperature Drift from +25°C, Three-Point Figure 26. VRMS Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 2140 MHz Multiple Devices at −40°C and +85°C at 2140 MHz 3 3 2 2 1 1 B) B) OR (d 0 OR (d 0 ERR ERR –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-036 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-039 Figure 24. VENV Output Temperature Drift from +25°C, Three-Point Figure 27. VENV Output Delta from +25°C Output Voltage for Calibration for Multiple Devices at −40°C, +25°C, and +85°C at 2600 MHz Multiple Devices at −40°C and +85°C at 2600 MHz Rev. D | Page 12 of 27

Data Sheet ADL5511 3 3 2 2 1 1 B) B) d d OR ( 0 OR ( 0 R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-040 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-043 Figure 28. VRMS Output Temperature Drift from +25°C Linear Reference Figure 31. VRMS Output Delta from +25°C Output Voltage for for Multiple Devices at −40°C, +25°C, and +85°C, 2600 MHz Frequency Multiple Devices at −40°C and +85°C at 2600 MHz 3 3 2 2 1 1 B) B) OR (d 0 OR (d 0 R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-041 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-044 Figure 29. VENV Output Temperature Drift from +25°C Linear Reference Figure 32. VENV Output Delta from +25°C Output Voltage for for Multiple Devices at −40°C, +25°C, and +85°C, 3500 MHz Frequency Multiple Devices at −40°C and +85°C at 3500 MHz 3 3 2 2 1 1 B) B) d d OR ( 0 OR ( 0 R R R R E E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-042 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-045 Figure 30. VRMS Output Temperature Drift from +25°C Linear Reference Figure 33. VRMS Output Delta from +25°C Output Voltage for for Multiple Devices at −40°C, +25°C, and +85°C, 3500 MHz Frequency Multiple Devices at −40°C and +85°C at 3500 MHz Rev. D | Page 13 of 27

ADL5511 Data Sheet 3 3 2 2 1 1 RROR (dB) 0 ROR (dB) 0 E R E –1 –1 –2 –2 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-046 –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-016 Figure 34. VENV Output Temperature Drift from +25°C Linear Reference Figure 37. VENV Output Delta from +25°C Output Voltage for for Multiple Devices at −40°C, +25°C, and +85°C, 6000 MHz Frequency Multiple Devices at −40°C and +85°C at 6000 MHz 3 3 2 2 1 1 ERROR (dB) 0 ERROR (dB) 0 –1 –1 –2 –2 –3 –30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-047 –3–30 –25 –20 –15 –1P0IN (dB–5m) 0 5 10 15 09602-017 Figure 35. VRMS Output Temperature Drift from +25°C Linear Reference Figure 38. VRMS Output Delta from +25°C Output Voltage for for Multiple Devices at −40°C, +25°C, and +85°C, 6000 MHz Frequency Multiple Devices at −40°C and +85°C at 6000 MHz 20 B) 2 –40°C 10 E (d 0 ++2855°°CC S N 0 O P –2 S –10 Y RE –4 –20 NC E –6 U –30 Q E R –8 –40 FV EN –10 –50 V D –60 ZE –12 LI –70 TCHADR R(dIEBRc )SUPPRESSION (dBc) RMA –14 ENVELOPE GAIN (dB) O –80–35 –30 –25 –20 –15RF–I1N0 (dB–m5) 0 5 10 15 09602-020 N –161 ENV1E0LOPE FREQUENCY1 0(M0Hz) 1000 09602-065 Figure 36. THD on VENV vs. RF Input Level; 1900 MHz RF Input, AM Modulated Figure 39. Normalized5 V0E ΩNV SFpreeqctureunmcy A Rneaslpyzoenrs Leo, VaEdN V AC-Coupled into a by a 20 MHz Sine Wave (Modulation Index = 0.25), VENV Output AC-Coupled into a 50 Ω Spectrum Analyzer Load Rev. D | Page 14 of 27

Data Sheet ADL5511 PULSED RFIN 1 4 VENBL +5dBm VENV +1dBm VENV +5dBm –3dBm +1dBm –10dBm –3dBm –10dBm 2 R1 CCRHEHF13 412 2 0 5 01mm2V5VmΩΩV 10ns MT10ns111.6ns A CH2 1.88V 09602-023 REF1 250mV 1CµHs4 7V MT 1 µ s 3.996µs A CH4 3.78V 09602-026 Figure 40. VENV Output Response to Various RF Input Pulse Levels Figure 43. VENV Output Response to Enable Gating at Various RF Input Levels, 900 MHz Frequency 900 MHz Frequency 2 PULSED RFIN 4 VENBL +5dBm +1dBm +5dBm VRMS –3dBm VRMS +1dBm –3dBm –10dBm –10dBm R4 R1 CRHEF242 0 01m25VmΩV 1µs MT 1 µ s –824ns A CH4 2.2V 09602-024 REF1 220mV 1CµHs4 7V MT 1 µ s 4.012µs A CH4 3.78V 09602-027 Figure 41. VRMS Output Response to Various RF Input Pulse Levels Figure 44. VRMS Output Response to Enable Gating at Various RF Input Levels, 900 MHz Frequency, CFLT4 = Open 900 MHz Frequency, CFLT4 = Open 2 PULSED RFIN 4 VENBL +5dBm +1dBm +5dBm VRMS –3dBm VRMS c +1dBm B d –3dBm –10dBm –10dBm R4 R4 REF4 125mV 1C0H02µs200mVΩ MT 1 0 0 µ –s100.5µsA CH4 2.2V 09602-025 REF4 220mV 4C0Hµ4s7V MT 4 0 µ s 160.4µs A CH4 3.78V 09602-028 Figure 42. VRMS Output Response to Various RF Input Pulse Levels, Figure 45. VRMS Output Response to Enable Gating at Various RF Input Levels, 900 MHz Frequency, CFLT4 = 100 nF 900 MHz Frequency, CFLT4 = 100 nF Rev. D | Page 15 of 27

ADL5511 Data Sheet 3 3 CW CW QAM64 QAM64 QPSK QPSK 2 1CWCDMA 2 1CWCDMA 4CWCDMA 4CWCDMA LTE LTE 1 1 B) B) d d OR ( 0 OR ( 0 R R R R E E –1 –1 –2 –2 –3–25 –20 –15 –10 INP–U5T (dBm)0 5 10 15 09602-021 –3–25 –20 –15 –10 INP–U5T (dBm)0 5 10 15 09602-022 Figure 46. VRMS Error from CW Linear Reference vs. Signal Modulation, Figure 47. VRMS Error from CW Linear Reference vs. Signal Modulation, Frequency = 900 MHz, CLPF = 0.1 μF (CW, QPSK, QAM64, 1CW-CDMA, Frequency = 2140 MHz, CLPF = 0.1 μF (CW, QPSK, QAM64, 1CW-CDMA, 4CW-CDMA, LTE Test Model E-TM1_1_20MHz) 4CW-CDMA, LTE Test Model E-TM1_1_20MHz) Rev. D | Page 16 of 27

Data Sheet ADL5511 CIRCUIT DESCRIPTION The ADL5511 employs a proprietary rectification technique RMS CIRCUIT DESCRIPTION to strip off the carrier of an input signal to reveal the true The rms processing is done using a proprietary translinear envelope. In this first detection stage, the carrier frequency technique. This method is a mathematically accurate rms is doubled and an on-chip two-pole passive low-pass filter computing approach and achieves unprecedented rms accurately preserves the envelope and filters out the carrier. accuracies for complex modulation signals irrespective of The poles of this filter, as defined by the on-chip RC filters the crest factor of the input signal. An integrating filter (0.4 pF, 400 Ω, 0.8 pF, 250 Ω) values allow some carrier capacitor does the square-domain averaging. The VRMS leakthrough for common RF frequencies. This is to ensure output can be expressed as that maximum envelope bandwidth can be maintained. For more details, see the Basic Connections section. T2 V2 dt IN VPOS VRMSA T1 15 T2T1 ADL5511 (1) 400Ω 20pF ENBL 4 BDIAOSW ANN CDO PNOTWROERL- 14 FLT4 Note that A is a scaling parameter that is decided on by the on- chip resistor ratio, and there are no other scaling parameters RMS G = 1.7 100Ω 11 VRMS involved in this computation, which means that the rms output is inherently free from any sources of error due to temperature, RFIN 2 10kΩ 250Ω supply, and process variation. ENVELOPE G = 1.5 10 VENV FLT1 3 RMS FILTERING 5pF 250Ω 9 EREF 0.4pF 400Ω 0.8pF The on-chip rms filtering corner is internally set by a 400 Ω resistor and a 20 pF capacitor, yielding a corner frequency of VPOS VPOS 13 6N7C 8 12 FL1T62 FL1T3 CO5MM 09602-049 afrpepqruoexnimcieast,e lmy o2s0t MofH thze. Wmohderuelaasti tohni se fnivlteelrosp oeu its anlol ct afirlrtieerre d. For Figure 48. Block Diagram adequate rms filtering, connect an external filter capacitor between FLT4 (Pin 14) and VPOS (Pin 15). This capacitance The extracted envelope is further processed in two parallel acts on the internal 400 Ω resistor (see Figure 48) to yield a new channels, one computing the rms value of the envelope and corner frequency for the rms filter given by the other transferring the envelope with appropriate scaling to the envelope output. 1 C  20pF (2) ENVELOPE PROPAGATION DELAY FLT4 (2π f 400) RMS The delay specified in this data sheet is with no external For example, a supply-referenced 0.1 μF capacitor on FLT4 capacitor at the FLT2 and FLT3 pins. The delay through the reduces the corner frequency of the rms averaging circuit to ADL5511, although very small, depends upon a number of approximately 4 kHz. factors, notable of which are internal filter component values RMS filtering has a direct impact on rms accuracy. For most and op amp compensation capacitors. The delay will vary from accurate detection, the rms filter corner should be low enough part to part by approximately ±15% due to process variations. to filter out most of the modulation content. This will corre- In addition, the choice of external FLT2 and FLT3 values, as spond to a corner frequency that is significantly lower than the well as load on the VNEV pin will increase the delay. In this bandwidth of the signal being measured. See the Choosing a case, the delay variation will be dominated by the part-to-part Value for the RMS Averaging Capacitor (CFLT4) section for more tolerance of the external capacitors. details and filtering options. Rev. D | Page 17 of 27

ADL5511 Data Sheet OUTPUT DRIVE CAPABILITY AND BUFFERING A 50 Ω load should never be dc coupled to the VENV output, as it presents a current draw of >20 mA even for no-signal condition The envelope output of the ADL5511 is presented on the VENV corresponding to 1.1 V nominal dc voltage at the VENV pin. pin as a single-ended buffered output with low output imped- ance. To achieve high envelope bandwidth, this output is not The VRMS buffered output can source a maximum current of ground referenced, unlike the VRMS output, which is ground 3 mA, but is not designed to sink any appreciable amount of referenced. current. If current sink capability is desired at this pin, a shunt resistance to ground can be connected. The VRMS output has an The VENV output has a no signal dc value of about 1.1 V. This on-chip series resistance of 100 Ω, to allow a low-pass filtering of dc reference is temperature dependent and is presented as a the residual ripple using a single shunt capacitor at this pin. Large standalone reference voltage on the EREF pin and as a buffered shunt capacitors at this pin may also require a shunt resistor to output. The true envelope at any instant of time is simply (V − ENV be placed to allow fast discharging of the capacitor. The internal V ), but these two pins do not constitute a differential output. EREF shunt resistance on the VRMS pin is 10 kΩ. Note that any shunt EREF is a fixed dc voltage and V carries all the envelope ENV resistance placed on this pin creates a resistive divider with the information. on-chip 100 Ω series resistance. The VENV output is capable of supporting a parallel load of The EREF output buffer also has 3 mA current sourcing capability. 500 Ω and 10 pF at full-scale envelope output and maximum The internal shunt resistance on this pin through which any bandwidth. Lighter loads (higher R and lower C) are always current must be sunk, is 12 kΩ. A capacitor to ground can be recommended whenever possible to minimize power consumption placed on this pin to eliminate any RF or envelope ripple at this and achieve maximum possible bandwidth. The maximum source/ pin to ensure that voltage at this pin acts as a clean reference for sink current capacity of the VNEV output is 15 mA peak and the VENV output for all possible carrier and envelope frequencies. load conditions should be such that this is not exceeded. The maximum output voltage at this pin is approximately Viewing the Envelope on an Oscilloscope (VPOS − 1.5) V. When viewing the VENV output on an oscilloscope, use a low For the case of ac coupling only, the VENV output can drive a capacitive FET probe. This reduces the capacitance presented to 50 Ω load, as long as the maximum signal swing does not exceed the VENV output and avoids the corresponding effects of larger an amplitude of approximately 1.5 V p-p. This corresponds to capacitive loads. the peak signal current of 15 mA into the 50 Ω load. If a 50 Ω drive capability is desired, the maximum input signal to ADL5511 should be adjusted, such that this output swing condition is not exceeded. Rev. D | Page 18 of 27

Data Sheet ADL5511 APPLICATIONS INFORMATION C14 +5V 0.1µF C13 100pF VPOS 15 ADL5511 C17 400Ω 20pF 0.1µF BIAS AND POWER- FLT4 ENBL 4 DOWN CONTROL 14 VPOS 10C01pF RMS G = 1.7 100Ω 11 VRMS ROMUTSPUT RFIN 2 75RΩ5 FLT1 10kΩ 250Ω ENVELOPE G = 1.5 10 VENV EONUVTEPLUOTPE 3 C2 5pF 250Ω EREF ENVELOPE 100pF 9 REFERENCE 0.4pF 400Ω 0.8pF VPOS VPOS 13 6 7 8 12 16 1 5 FLT2 FLT3 COMM NC C10 C6 (SEE TEXT) (SEEV TPEOXST) 09602-050 Figure 49. Basic Connections BASIC CONNECTIONS The internal 5 pF capacitance can be augmented by connecting a ground referenced capacitor to Pin 3 (FLT1). The value of the Basic connections for operation of the ADL5511 are shown in external capacitance is set using the following equation: Figure 49. The ADL5511 requires a single supply of 5 V. The supply is connected to the VPOS supply pin. Decouple this 1 C  5pF (3) pin using two capacitors with values equal or similar to those FLT1 (2π f 10,000) 3dB shown in Figure 49. Place these capacitors as close as possible For example, a 100 pF capacitance on FLT1 will reduce the to the VPOS pin. corner frequency to 150 kHz. As a general guideline, this An external 75 Ω resistor combines with the relatively high corner frequency should be set to be at least one tenth of the RF input impedance of the ADL5511 to provide a broadband minimum expected carrier frequency. This ensures a flat 50 Ω match. Place an ac coupling capacitor between this resistor frequency response around the frequency of interest. and RFIN. The envelope detection path of the ADL5511 includes internal The envelope output is available on Pin 10 (VENV) and is carrier-suppression low-pass filtering. With the FLT2 and FLT3 referenced to the 1.1 V dc voltage on Pin 9 (EREF). pins not connected, two internal 1 GHz and 800 MHz low-pass The rms output voltage is available at the VRMS pin with rms filters (operating in series) remove the RF carrier from the envelope averaging provided by the supply-referenced capacitance on output signal. Pin 14 (FLT4). The equations for these filters are as follows: OPERATION BELOW 1 GHZ/ENVELOPE FILTERING 1 1GHz (4) To operate the ADL5511 at frequencies below 1 GHz, a number (2π0.4pF400) of external capacitors must be added to the FLT3, FLT2, and and FLT1 pins. These changes are in addition to the choice of an appropriate rms averaging capacitor, see the Choosing a Value 1 800MHz (5) for the RMS Averaging Capacitor (CFLT4) section. (2π0.8pF250) As part of the internal signal processing algorithm, the RF input Because the envelope detection circuitry includes a full-wave signal passes through a low-pass filter comprising of a 10 kΩ rectifier, this filter has to primarily suppress the signal at twice resistor and a 5 pF capacitor (see Figure 49). This corresponds the original input frequency. to a corner frequency of approximately 3.2 MHz. If the carrier frequency is less than approximately ten times this value (32 MHz), this corner frequency must be reduced. Rev. D | Page 19 of 27

ADL5511 Data Sheet For input frequencies in the 900 MHz range, there will still be For adequate rms filtering, connect an external filter capacitor significant carrier content on the envelope output. With the between FLT4 (Pin 14) and VPOS (Pin 15). This capacitance acts two filters providing a combined 6 dB roll-off at approximately on the internal 400 Ω resistor to yield a new corner frequency 900 MHz and with the residual carrier at 1.8 GHz, carrier for the rms filter given by the following equation: filtering of approximately 18 dB can be expected (the two 1 single-pole filters provide a combined roll-off of 12 dB per C  20pF (8) FLT4 (2π f 400) octave. FLT4 For example, a supply-referenced 0.1 μF capacitor on FLT4 The internal filtering of the carrier in the envelope detection reduces the corner frequency of the rms averaging circuit to path can be augmented by adding additional supply-referenced approximately 4 kHz. capacitance to the FLT2 and FLT3 pins. The required capaci- tance can be calculated using the following equations: The size of the rms filtering capacitor has a direct impact on the rms accuracy up to a point. For most accurate detection, the 1 C  0.4pF (6) rms filter corner should be low enough to filter out most of the FLT2 (2π f 400) FLT2 modulation content. This corresponds to a corner frequency and that is significantly less than the bandwidth of the signal being measured. 1 C  0.8pF (7) FLT3 (2π f 250) Table 4 shows recommended minimum values of CFLT4 for FLT3 popular modulation schemes. Using smaller capacitor values where f and f are the desired corner frequencies. LT2 LT3 than these will result in rms measurement errors; using higher For example, to set the corner frequency to 200 MHz, CFLT2 and values will not further improve rms accuracy but will reduce the CFLT3 should be set to 1.6 pF and 2.4 pF, respectively. The two corner output noise on VRMS at the expense of increased rise and fall frequencies should be set so that they are approximately equal. times. In Table 4, rise and fall times are also shown along with residual output noise. Care should be taken not to set the corner frequency of this carrier suppression filter too low as it will start to degrade envelope The recommended minimum values for C were experimen- FLT4 bandwidth. The ADL5511 has an envelope bandwidth of 130 MHz. tally determined by starting out with a large capacitance value Thus, if the capacitors on FLT2 and FLT3 are so big that the carrier- on the FLT4 pin (for example, 10 μF). The value of V was RMS suppression corner frequency approaches 130 MHz, the carrier noted for a fixed input power level (for example, 0 dBm). The filtering effort will directly impact the envelope bandwidth. Thus, value of C was then progressively reduced (this can be done FLT4 the corner frequency should be set low enough so that the RF with press-down capacitors) until the value of V started to RMS carrier is adequately removed from the envelope output while deviate from its original value (this indicates that the accuracy still maintaining the desired envelope bandwidth. An alternative of the rms computation is degrading and that C is becoming FLT4 option would be to filter the carrier at the VENV output using too small). a higher order filter. The recommended minimum value for C is roughly inversely FLT4 CHOOSING A VALUE FOR THE RMS AVERAGING proportional to the bandwidth of the input signal, that is, wider CAPACITOR (C ) bandwidth signals tend to require smaller minimum filter FLT4 capacitances. As already noted, the value of C sets up an internal C provides the averaging function for the internal rms FLT4 FLT4 low pass corner frequency, which filters the rms voltage. As carrier computation, the result of which is available at the VRMS output. bandwidth increases, a larger proportion of the residual noise As already noted, the on-chip rms filtering corner is internally (which has been effectively mixed down to baseband) is filtered set by a 400 Ω resistor and a 20 pF capacitor, yielding a corner away. This results in smaller capacitances being required as frequency of approximately 20 MHz. carrier bandwidths increase. Table 4. Recommended Minimum CFLT4 Values for Various Modulation Schemes (Pin = 0 dBm) PEP to RMS Signal C FLT4 Modulation/Standard Ratio Bandwidth (Min) Output Noise Rise/Fall Time (10% to 90%) W-CDMA, One-Carrier, TM1-64 9.83 dB 3.84 MHz 220 nF 98 mV p-p 82 μs/310 μs W-CDMA Four-Carrier, TM1-64, TM1-32, 12.08 dB 18.84 MHz 100 nF 140 mV p-p 40 μs/140 μs TM1-16, TM1-8 LTE Test Model E-TM1_1_4MHz 9.83 dB 4 MHz 220 nF 135 mV p-p 82 μs/310 μs LTE Test Model E-TM1_1_10MHz 11.99 dB 10 MHz 100 nF 89 mV p-p 40 μs/140 μs LTE Test Model E-TM1_1_20MHz 11.58 dB 20 MHz 47 nF 90 mV p-p 20 μs/70 μs Rev. D | Page 20 of 27

Data Sheet ADL5511 For applications that are not response time critical, a relatively Figure 51 shows such a plot total harmonic distortion (THD) of large capacitor can be placed on the FLT4. There is no maximum the VENV output vs. RF input power for the modulation index capacitance limit for C . of 0.25. FLT4 Figure 50 shows how output noise, rise time and fall time vary As the input power level increases, the THD improves until it vs. C when the ADL5511 is driven by an 1.9 GHz LTE carrier sharply degrades at an input power level of approximately 13 FLT4 with a bandwidth of 10 MHz (LTE Test Model E-TM1_1_10MHz, dBm. This sharp decrease is caused by the clipping of the AM peak-to-average ratio = 11.99 dB). signal’s peak envelope. Figure 51 also shows carrier leakage at 800 10000000 VENV in dBc with respect to the input carrier amplitude. OUTPUT NOISE (mV p-p) 10% TO 90% RISE TIME (µs) This measurement, when conducted over the full input power 700 90% TO 10% FALL TIME (µs) 1000000 range of the ADL5511, suffers from measurement inaccuracies p) 600 100000 of the input modulated signal due to the spectrum analyzer’s mV p- 500 10000 E (µs) noise floor and therefore does not accurately reveal the ADL5511’s UT NOISE ( 340000 1100000 E/FALL TIM latiedmsdti it(tauiotsinion ntgos t athhte it shA, eDt hloLew5 p3er9ro 0ce enmsdsu ooltffi ptghleieen rme)r aeista isnnuogrt e apmne erAfneMtc rt a saingngndea .r lIe fnsou rl ttehdis P S UT RI in a source signal whose envelope was not harmonically pure. O 200 10 TIME DOMAIN ENVELOPE TRACKING ACCURACY 100 1 The envelope tracking accuracy of the ADL5511 can also be 0 0.1 assessed in the time domain by looking at the input peak power 1 10 CFLT4 (nF) 100 1000 09602-066 levels that cause clipping. Figure 50. Output Noise, Rise and Fall Times vs. CFLT4 Capacitance, 10 MHz The usable rms input power range of the ADL5511 varies BW LTE Carrier (LTE Test Model E-TM1_1_10MHz) at 1.9 GHz with PIN = 0 dBm depending on the desired accuracy level and the peak-to-average ENVELOPE TRACKING ACCURACY ratio of the input signal. Figure 4 shows the linear operating range of the VENV output when the RF input is driven by unmodulated The envelope tracking accuracy of the ADL5511 is measured in sine waves at various frequencies. This shows operation up to rms terms of the higher order distortion of the envelope output when input levels of approximately 19 dBm. If the signal has a peak- the RF input signal is AM modulated using a low-harmonic to-average ratio that is greater than the square root of two, the sinusoid at a given frequency. Such an input sinusoidal envelope usable input range on RFIN will decrease. In general, the maximum has been generated using the ADL5390 multiplier modulator. input power for linear operation should be determined by the This generates a double sideband AM modulated signal of a peak envelope power (PEP) of the input signal. Figure 52 shows known modulation index. In this measurement, the ADL5511 the time-domain response of the VENV output to a 900 MHz acts as free-running AM demodulator without requiring a local LTE carrier with a bandwidth of 20 MHz (Test Model E- oscillator to demodulate the signal. TM1_2_20MHz). The signal level of the carrier (7 dBm rms, 20 19 dBm PEP) was deliberately increased until clipping was 10 observed at the VENV output. 0 Note that the peak envelope power of a signal is derived based on –10 the rms level of the signal during a peak cycle, that is V p-p/2. For –20 example, a signal that achieves a peak voltage of 10 V (or 20 V p-p) has a PEP of 30 dBm. According to this definition, the PEP of a –30 sine wave is equal to its rms power level because it has a constant –40 envelope. –50 –60 THD (dBc) –70 CARRIER SUPPRESSION (dBc) ENVELOPE GAIN (dB) –80–35 –30 –25 –20 –15RF–I1N0 (dB–m5) 0 5 10 15 09602-069 Figure 51. THD on VENV vs. RF Input Level; 1900 MHz RF Input, AM Modulated by a 20 MHz Sine Wave (Modulation Index = 0.25), VENV Output AC-Coupled into a 50 Ω Spectrum Analyzer Load Rev. D | Page 21 of 27

ADL5511 Data Sheet 10000 1000 V) m (V 100 N E V 10 Figure 52.h VaEsN bVe Renes Tproigngseer teod a t o2 0C aMpHtuz rLeT tEh Ce aErnrvieerl owpiteh’s a P PeaEPk Loef v1e9l d09602-055B m that 1–40 –30 –20 INPUT –(1d0Bm) 0 10 09602-068 Figure 54. VENV Output vs. Input Level Distribution of 50 Devices, VRMS AND VENV OUTPUT OFFSET 900 MHz Frequency The 900 MHz RF power sweeps in Figure 53 and Figure 54 show distributions of the VRMS and VENV outputs voltages for multiple devices at 25°C. The VRMS output response flattens out at approximately −30 dBm while the various VENV response traces begin to fanout unpredictably (Figure 4 and Figure 7 show this behavior at other frequencies). While these plots suggest that operation at input levels down to −30 dBm is feasible, account must also be taken for variations over temperature. Figure 10 to Figure 38 show how the linearity error starts to increase below input levels of −20 dBm (the size of the error varies between VENV and VRMS and with frequency). 10000 1000 V) m (S 100 M R V 10 1 –40 –30 –20 INPUT –(d10Bm) 0 10 09602-067 Figure 53. VRMS Output vs. Input Level Distribution of 50 Devices, 900 MHz Frequency Rev. D | Page 22 of 27

Data Sheet ADL5511 DEVICE CALIBRATION AND ERROR CALCULATION 3 –40°C +25°C Because slope and intercept vary from device to device, calibration +85°C 2 must be performed to achieve high accuracy. In general, calibration is performed by applying two or more known input power levels to 1 the ADL5511 and measuring the corresponding output voltages. B) d The calibration points are generally chosen to be within the linear OR ( 0 operating range of the device. For a two-point calibration, the R R E conversion gain (or slope) and intercept are calculated for V RMS –1 and V using the following equations: ENV Slope = (V − V )/(V − V ) (9) –2 OUT2 OUT1 IN2 IN1 Intercept = V − (Slope × V ) (10) OUT1 IN1 wVhe irse t: he rms input voltage to RFIN. –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-059 IN Figure 55. VENV Linearity Error vs. Input Level and Temperature Using a VOUT is the voltage output at VRMS or VENV. Two-Point Calibration at 1900 MHz Because the gain and intercept of the rms and envelope paths By adding a third calibration point, the linearity of the ADL5511 will be different, both paths should be calibrated, that is, with a can be enhanced at lower power levels. With a three-point measured signal applied to RFIN, VENV, and VRMS. To ensure calibration, calibration coefficients (slope and intercept) are that the voltage at VENV and VRMS is a steady-state value, a calculated for each segment (thus, there will be two slopes and constant envelope signal such as a sine wave should be used as two intercepts). the source during calibration. Figure 56 shows the same data as Figure 55, but with a three- Once slope and intercept are calculated, an equation can be point calibration (calibration points at −26 dBm, −15 dBm, and written that allows calculation of the input rms or envelope level +5 dBm. This helps to extend the usable operating range of the using the following equations: ADL5511 well below −25 dBm. VINRMS = (VRMS − InterceptVRMS)/SlopeRMS (11) 3 –40°C +25°C VINENV = (VENV − InterceptVENV)/SlopeVENV (12) +85°C 2 The law conformance error, that is, the difference between the actual input level (V ) and the measured/calculated input IN_IDEAL 1 level (VMEASURED), of these calculations can be calculated using B) d the following equation: R ( 0 O R Error (dB) = R E 20 × log [(V − Intercept)/(Slope × V )] (13) –1 MEASURED IN_IDEAL Figure 55 is a plot of this error for VENV at 1900 MHz for a –2 multiple devices at +25°C, +85°C, and −40°C with calibration performed at two points, −14 dBm and +5 dBm (notice how tphloe tesr froorr aaltl 2te5m°Cp earta tthuer ecsa lairber actailocnu lpaoteidn tus siisn zge trhoe). 2T5h°Ces esl eorpreo r –3–30 –25 –20 –15 –1P0IN (d–B5m) 0 5 10 15 09602-058 Figure 56. VENV Linearity Error vs. Input Level and Temperature Using a Three- and intercept. This is consistent with calibration in a mass Point Calibration at 1900 MHz production environment where calibration at temperature is generally not practical. Rev. D | Page 23 of 27

ADL5511 Data Sheet ERROR VS. FREQUENCY 400 8 Figure 57 and Figure 58 show how the V and V output 350 6 RMS ENV voltages and error vary with input frequency when the ADL5511 is 300 4 calibrated at a single frequency. In this example, the ADL5511 hthaes obue6t0ep0nu tc avloilbtaragtee adn adt e2r5ro°Cr vaatr 1y. a9b GovHez a. nTdh bee plolowt st hailss ofr esqhuo6ewn chyo. w UTPUT (mV) 220500 02 RROR (dB) O 150 –2 E 500 4 100 VENV AT –40°C –4 VENV AT +25°C VENV AT +85°C 400 2 50 ERROR AT –40°C –6 mV) B) EERRRROORR AATT ++2855°°CC UTPUT ( 300 0 RROR (d 00 1000 200F0REQUE30N0C0Y (MHz4)000 5000 6000–8 09602-060 O 200 –2E Figure 58. VENV Output vs. Frequency for a Fixed Input Power, PIN = 0 dBm, Calibration at 1.9 GHz, 25°C VRMS AT –40°C 100 VVRRMMSS AATT ++2855°°CC –4 EVALUATION BOARD ERROR AT –40°C ERROR AT +25°C Figure 59 shows the schematic of the ADL5511 evaluation board. ERROR AT +85°C 00 1000 200F0REQU3E0N0C0Y (MHz4)000 5000 6000–6 09602-061 Ttoh 5is.2 45- lVay rearn bgoea. rTdh ies ppoowweerr esdu pbpyl ya issi ndgelceo suupplpedly biyn 1th0e0 4p.F7 5a nVd Figure 57. VRMS Output vs. Frequency for a Fixed Input Power, PIN = 0 dBm, 0.1 μF capacitors. Calibration at 1.9 GHz, 25°C Table 5 details the various configuration options of the evaluation board. Figure 60 and Figure 61 show the bottom side and top side layouts, respectively. The RF input has a broadband match of 50 Ω using a single 75 Ω resistor at R5. The VRMS output is accessible via a clip lead (a pad is also available where an SMA connector is installed). The VENV output is accessible via an SMA connector. For response- time critical measurements where stray capacitance must be minimized, R2 can be removed and a FET probe can be attached to JP1 (JP1 must be installed). Rev. D | Page 24 of 27

Data Sheet ADL5511 09602-062 Figure 59. Evaluation Board Schematic 09602-063 09602-064 Figure 60. Layout of Evaluation Board, Bottom Side Figure 61. Layout of Evaluation Board, Top Side Rev. D | Page 25 of 27

ADL5511 Data Sheet Table 5. Evaluation Board Configuration Options Component Description Default Condition VPOS, GND Ground and supply vector pins. Not applicable C13, C14 Power supply decoupling. Nominal supply decoupling of 0.01 μF and 100 pF. C13 = 100 pF (Size 0402) C14 = 0.1 μF (Size 0402) C17 RMS filter capacitor (FLT4). The internal rms averaging capacitor can be augmented by C17 = 0.1 μF (Size 0402) placing additional capacitance in C17. R5, C1 RF input interface. The 75 Ω resistor at R5 combines with the ADL5511 internal input R5 = 75 Ω (Size 0402) impedance to give a broadband input impedance of around 50 Ω. C1 is an ac coupling C1 = 100 pF (Size 0402) capacitor, which should be chosen according to nominal carrier frequency. R18, C9 RMS output and output filtering. The combination of C9 and the internal 100 Ω output R18 = 0 Ω (Size 0402) resistance can be used to form a low-pass filter to reduce the output noise on the VRMS C9 = open (Size 0402) output beyond the reduction due to C17 (capacitor on FLT4). The rms output is available VRMS clip-on test point = on the VRMS clip-on test point. To observe VRMS using an SMA cable, an SMA connector installed can be soldered on to the pad labeled VRMS1. VRMS1 SMA connector = open R19, C8, R2, VENV output and output filtering. The VENV output is available on the VENV SMA VENV SMA connector = JP1 connector. If post-envelope filtering is desired, R19 and C8 can be used to form a low-pass installed filter at the VENV output. R19, R2 = 0 Ω (Size 0402) R2 can be removed to isolate the JP1 jumper from the VENV SMA connector and JP1 can C8 = open (Size 0402) be installed and used to interface to a FET probe. This helps to eliminate any excessive JP1 = open trace and connector capacitance. R20, C7 Envelope reference output and output filtering. The EREF output is available on the EREF R20 = 0 Ω (Size 0402) clip-on test point. The dc reference voltage at Pin EREF can be filtered by the low-pass filter C7 = open (Size 0402) formed by the combination of R20 and C7. To observe the EREF voltage using an SMA EREF clip-on test point = cable, an SMA connector can be soldered onto the pad labeled EREF1. installed EREF1 SMA connector = open R1, SW1 Device enable. When the switch is set toward the SW1 label, the ENBL pin is connected to VPOS, R1 = 0 Ω (Size 0402) which enables the ADL5511. In the opposite switch position, the ENBL pin is grounded which SW1 = towards SW1 label disables the ADL5511. C6, C10 Envelope carrier-removal filters (FLT2, FLT3). The corner frequency of the internal VENV two-pole C6, C10 = open (Size 0402) carrier-removal filter can be reduced by placing additional capacitors in C6 and C10. C2 Envelope reference carrier-removal filter (FLT1). The internal filter that removes the carrier from C2 = 100 pF (Size 0402) the envelope reference dc voltage can be augmented by placing a capacitor in C2. R3, R14, R15, Alternate interface. The P2 edge connector provides an alternate access point to the R3, R14, R15, R16, R17 = open R16, R17 various ADL5511 signals. (Size 0402) Rev. D | Page 26 of 27

Data Sheet ADL5511 OUTLINE DIMENSIONS DETAIL A 3.10 0.30 (JEDEC 95) 3.00 SQ 0.23 PIN 1 2.90 0.18 INDICATOR B0.S5C0 1213 16 1 (PINSIENDE I 1DCAETTAOILR A A)REA OPTIONS 1.75 EXPPAODSED 1.60 SQ 1.45 9 4 0.50 8 5 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 TOP VIEW THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF PKG-005138 COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6. 02-23-2017-E Figure 62. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Package Ordering Model1 Temperature Range Package Description Option Quantity Branding ADL5511ACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-22 1500 Q1Y ADL5511-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09602-0-7/18(D) Rev. D | Page 27 of 27

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