30 MHz to 2200 MHz Quadrature Modulator Data Sheet ADL5385 FEATURES FUNCTIONAL BLOCK DIAGRAM Output frequency range: 30 MHz to 2200 MHz ENBL 1 dB output compression: 11 dBm at 350 MHz Noise floor: –159 dBm/Hz at 350 MHz BIAS TEMPERATURE TEMP Sideband suppression: −50 dBc at 350 MHz IBBP SENSOR Carrier feedthrough: −46 dBm at 350 MHz Single supply: 4.75 V to 5.5 V 24-lead, RoHS-compliant, LFCSP with exposed pad IBBN APPLICATIONS Radio-link infrastructure LOIP Cable modem termination systems DIVIDE-BY-2 QUADRATURE VOUT UHF/VHF radio PHASE SPLITTER Wireless infrastructure systems LOIN Wireless local loop WiMAX/broadband wireless access systems QBBP QBBN 06118-001 Figure 1. GENERAL DESCRIPTION The ADL5385 is a silicon, monolithic, quadrature modulator The ADL5385 can be used as either an IF or a direct-to-RF designed for use from 30 MHz to 2200 MHz. Its excellent phase modulator in digital communication systems. The wide accuracy and amplitude balance enable both high performance baseband input bandwidth allows for either baseband drive or intermediate frequency (IF) and direct radio frequency (RF) drive from a complex IF. Typical applications are in radio-link modulation for communication systems. transmitters, cable modem termination systems, and broadband wireless access systems. The ADL5385 takes the signals from two differential baseband inputs and modulates them onto two carriers in quadrature The ADL5385 is fabricated using the Analog Devices, Inc., with each other. The two internal carriers are derived from a advanced silicon germanium bipolar process and is packaged in single-ended, external local oscillator input signal at twice the a 24-lead, RoHS-compliant LFCSP with exposed pad. Performance frequency as the desired carrier output. The two modulated is specified over –40°C to +85°C. A RoHS-compliant evaluation signals are summed together in a differential-to-single-ended board is also available. amplifier designed to drive 50 Ω loads. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADL5385 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Baseband Inputs ......................................................................... 15 Applications ....................................................................................... 1 LO Input ...................................................................................... 15 Functional Block Diagram .............................................................. 1 RF Output .................................................................................... 15 General Description ......................................................................... 1 Optimization ............................................................................... 16 Revision History ............................................................................... 2 Applications Information .............................................................. 17 Specifications ..................................................................................... 3 DAC Modulator Interfacing ..................................................... 17 Absolute Maximum Ratings ............................................................ 7 155 Mbps (STM-1) 128 QAM Transmitter ............................. 18 ESD Caution .................................................................................. 7 CMTS Transmitter Application ................................................ 18 Pin Configuration and Function Descriptions ............................. 8 Spectral Products from Harmonic Mixing ............................. 19 Typical Performance Characteristics ............................................. 9 RF Second-Order Products ....................................................... 19 Circuit Description ......................................................................... 14 LO Generation Using PLLs ....................................................... 20 Overview ...................................................................................... 14 Transmit DAC Options ............................................................. 20 LO Interface................................................................................. 14 Modulator/Demodulator Options ........................................... 20 V-to-I Converter ......................................................................... 14 Evaluation Board ............................................................................ 21 Mixers .......................................................................................... 14 Characterization Setup .................................................................. 23 D-to-S Amplifier ......................................................................... 14 SSB Setup ..................................................................................... 23 Bias Circuit .................................................................................. 14 Outline Dimensions ....................................................................... 24 Basic Connections .......................................................................... 15 Ordering Guide .......................................................................... 24 Power Supply and Grounding ................................................... 15 REVISION HISTORY 12/2016—Rev. C to Rev. D Added Figure 47 ............................................................................. 24 Changes to Evaluation Board Section .......................................... 21 Changes to Ordering Guide .......................................................... 26 Deleted Figure 46 and Table 9; Renumbered Sequentially ....... 23 Deleted Figure 47 ............................................................................ 24 10/2012—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 24 Added 30 MHz Output Frequency ............................. Throughout Changes to Applications Section ..................................................... 1 3/2016—Rev. B to Rev. C Changes to Table 1 ............................................................................. 3 Changes to Figure 2 .......................................................................... 8 Added EPAD Notation to Figure 2 and Table 3 ............................ 8 Changes to Figure 29 ...................................................................... 15 Added Figure 8; Renumbered Sequentially ................................... 9 Changes to LO Generation Using PLLs Section and Table 7 .... 20 Added Figure 9 ................................................................................ 10 Changes to Figure 43 ...................................................................... 21 Changes to Figure 17 ...................................................................... 11 Changes to Figure 46 ...................................................................... 23 Changes to Figure 21 ...................................................................... 12 Updated Outline Dimensions ....................................................... 26 Changes to LO Input Section and RF Output Section .............. 15 Changes to Ordering Guide .......................................................... 26 Changes to LO Generation Using PLLs Section and Transmit DAC Options Section .................................................................... 20 12/2014—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 24 Changes to Output Voltage Parameter, Test Conditions/Comments Changes to Ordering Guide .......................................................... 24 Column, Table 1 ................................................................................ 6 Changes to D-to-S Amplifier Section .......................................... 14 10/2006—Revision 0: Initial Version Changes to Evaluation Board Section, Figure 43, and Table 8 ........ 21 Changes to Figure 44 ...................................................................... 22 Added Figure 45; Renumbered Sequentially .............................. 22 Added Figure 46 and Table 9......................................................... 23 Rev. D | Page 2 of 24

Data Sheet ADL5385 SPECIFICATIONS Unless otherwise noted, V = 5 V; T = 25°C; LO = −7 dBm; I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc S A bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit OUTPUT FREQUENCY RANGE 30 2200 MHz EXTERNAL LO FREQUENCY RANGE External LO frequency 2× output frequency 60 4400 MHz OUTPUT FREQUENCY = 30 MHz (LO = 0 dBm) Output Power Single (lower) sideband output 4.7 dBm Output P1dB 11 dBm Carrier Feedthrough Unadjusted (nominal drive level) −57 dBm +85°C after optimization at +25°C −68 dBm −40°C after optimization at +25°C −65 dBm Sideband Suppression Unadjusted (nominal drive level) −51 dBc +85°C after optimization at +25°C −59 dBc −40°C after optimization at +25°C −60 dBc Second Baseband Harmonic (f − (2 × f )), P = 5 dBm −88 dBc LO BB OUT Third Baseband Harmonic (f − (2 × f )), P = 5 dBm −57 dBc LO BB OUT Output IP2 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 76 dBm OUT Output IP3 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 24 dBm OUT Quadrature Phase Error 0.43 Degrees I/Q Amplitude Balance 0.015 dB Noise Floor 20 MHz offset from LO, all BB inputs at a bias of 500 mV −155 dBm/Hz 20 MHz offset from LO, output power = −5 dBm −150 dBm/Hz Output Return Loss −20 dB OUTPUT FREQUENCY = 50 MHz Output Power Single (lower) sideband output 4 5.6 8 dBm Output P1 dB 11 dBm Carrier Feedthrough Unadjusted (nominal drive level) −57 dBm +85°C after optimization at +25°C −67 dBm −40°C after optimization at +25°C −67 dBm Sideband Suppression Unadjusted (nominal drive level) −57 dBc @ +85°C after optimization at +25°C −64 dBc @ −40°C after optimization at +25°C −68 dBc Second Baseband Harmonic (f − (2 × f )), P = 5 dBm −83 dBc LO BB OUT Third Baseband Harmonic (f + (3 × f )), P = 5 dBm −58 dBc LO BB OUT Output IP2 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 69 dBm OUT Output IP3 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 26 dBm OUT Quadrature Phase Error −0.17 Degrees I/Q Amplitude Balance −0.03 dB Noise Floor 20 MHz offset from LO, all BB inputs at a bias of 500 mV −155 dBm/Hz 20 MHz offset from LO, output power = −5 dBm −150 dBm/Hz Output Return Loss −19 dB Rev. D | Page 3 of 24

ADL5385 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit OUTPUT FREQUENCY = 140 MHz Output Power Single (lower) sideband output 5.7 dBm Output P1 dB 11 dBm Carrier Feedthrough Unadjusted (nominal drive level) −52 dBm +85°C after optimization at +25°C −66 dBm −40°C after optimization at +25°C −67 dBm Sideband Suppression Unadjusted (nominal drive level) −53 dBc +85°C after optimization at +25°C −63 dBc −40°C after optimization at +25°C −68 dBc Second Baseband Harmonic (f − (2 × f )), P = 5 dBm −83 dBc LO BB OUT Third Baseband Harmonic (f + (3 × f )), P = 5 dBm −57 dBc LO BB OUT Output IP2 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 70 dBm OUT Output IP3 F1 = 3.5 MHz, F2 = 4.5 MHz, P =−3 dBm per tone 26 dBm OUT Quadrature Phase Error −0.33 Degrees I/Q Amplitude Balance −0.03 dB Noise Floor 20 MHz offset from LO, all BB inputs at a bias of 500 mV −160 dBm/Hz Output Return Loss −20 dB OUTPUT FREQUENCY = 350 MHz Output Power Single (lower) sideband output 3 5.6 7 dBm Output P1 dB 11 dBm Carrier Feedthrough Unadjusted (nominal drive level) −46 dBm +85°C after optimization at +25°C −65 dBm −40°C after optimization at +25°C −66 dBm Sideband Suppression Unadjusted (nominal drive level) −50 dBc +85°C after optimization at +25°C −63 dBc −40°C after optimization at+25°C −61 dBc Second Baseband Harmonic (f − (2 × f )), P = 5 dBm −80 dBc LO BB OUT Third Baseband Harmonic (f + (3 × f )), P = 5 dBm −53 dBc LO BB OUT Output IP2 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 71 dBm OUT Output IP3 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 26 dBm OUT Quadrature Phase Error 0.39 Degrees I/Q Amplitude Balance −0.03 dB Noise Floor 20 MHz offset from LO, all BB inputs at a bias of 500 mV −159 dBm/Hz 20 MHz offset from LO, output power = −5 dBm −157 dBm/Hz Output Return Loss −21 dB OUTPUT FREQUENCY = 860 MHz Output Power Single (lower) sideband output 2.5 5.3 6.5 dBm Output P1 dB 11 dBm Carrier Feedthrough Unadjusted (nominal drive level) −41 −35 dBm +85°C after optimization at +25°C −63 dBm −40°C after optimization at +25°C −65 dBm Sideband Suppression Unadjusted (nominal drive level) −41 −35 dBc +85°C after optimization at +25°C −58 dBc −40°C after optimization at +25°C −59 dBc Second Baseband Harmonic (f − (2 × f )), P = 5 dBm −73 −57 dBc LO BB OUT Third Baseband Harmonic (f + (3 × f )), P = 5 dBm −50 −45 dBc LO BB OUT Output IP2 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 70 dBm OUT Output IP3 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 25 dBm OUT Quadrature Phase Error 0.67 Degrees I/Q Amplitude Balance −0.03 dB Rev. D | Page 4 of 24

Data Sheet ADL5385 Parameter Test Conditions/Comments Min Typ Max Unit Noise Floor 20 MHz offset from LO, all BB inputs at a bias of 500 mV −159 dBm/Hz 20 MHz offset from LO, output power = −5 dBm −157 dBm/Hz Output Return Loss −19 dB OUTPUT FREQUENCY = 1450 MHz Output Power Single (lower) sideband output 4.4 dBm Output P1 dB 10 dBm Carrier Feedthrough Unadjusted (nominal drive level) −36 dBm +85°C after optimization at +25°C −50 dBm −40°C after optimization at +25°C −50 dBm Sideband Suppression Unadjusted (nominal drive level) −44 dBc +85°C after optimization at +25°C −61 dBc −40°C after optimization at +25°C −51 dBc Second Baseband Harmonic (f − (2 × f )), P = 4 dBm −64 dBc LO BB OUT Third Baseband Harmonic (f + (3 × f )), P = 4 dBm −52 dBc LO BB OUT Output IP2 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 63 dBm OUT Output IP3 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 24 dBm OUT Quadrature Phase Error 0.42 Degrees I/Q Amplitude Balance −0.02 dB Noise Floor 20 MHz offset from LO, all BB inputs at a bias of 500 mV −160 dBm/Hz Output Return Loss −33 dB OUTPUT FREQUENCY = 1900 MHz Output Power Single (lower) sideband output 3.4 dBm Output P1 dB 9 dBm Carrier Feedthrough Unadjusted (nominal drive level) −35 dBm +85°C after optimization at +25°C −51 dBm −40°C after optimization at +25°C −51 dBm Sideband Suppression Unadjusted (nominal drive level) −33 dBc +85°C after optimization at +25°C −43 dBc −40°C after optimization at +25°C −47 dBc Second Baseband Harmonic (f − (2 × f )), P = 3 dBm −58 dBc LO BB OUT Third Baseband Harmonic (f + (3 × f )), P = 3 dBm −47 dBc LO BB OUT Output IP2 F1 = +3.5 MHz, F2 = +4.5 MHz, P = −3 dBm per tone 57 dBm OUT Output IP3 F1 = +3.5 MHz, F2 = +4.5 MHz, P = −3 dBm per tone 22 dBm OUT Quadrature Phase Error 2.6 Degrees I/Q Amplitude Balance 0.003 dB Noise Floor 20 MHz offset from LO, all BB inputs at a bias of 500 mV −160 dBm/Hz 20 MHz offset from LO, output power = −5 dBm −156 dBm/Hz Output Return Loss −20 dB OUTPUT FREQUENCY = 2150 MHz Output Power Single (lower) sideband output 2.6 dBm Output P1 dB 8 dBm Carrier Feedthrough Unadjusted (nominal drive level) −36 dBm +85°C after optimization at +25°C −47 dBm −40°C after optimization at +25°C −48 dBm Sideband Suppression Unadjusted (nominal drive level) −37 dBc Second Baseband Harmonic (f − (2 × f )), P = 2.6 dBm −56 dBc LO BB OUT Third Baseband Harmonic (f + (3 × f )), P = 2.6 dBm −45 dBc LO BB OUT Output IP2 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 54 dBm OUT Output IP3 F1 = 3.5 MHz, F2 = 4.5 MHz, P = −3 dBm per tone 21 dBm OUT Quadrature Phase Error 1.5 Degrees I/Q Amplitude Balance <0.05 dB Rev. D | Page 5 of 24

ADL5385 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit Noise Floor 20 MHz offset from LO, all BB inputs at a bias of 500 mV −160 dBm/Hz 20 MHz offset from LO, output power = −5 dBm −156 dBm/Hz Output Return Loss −15 dB LO INPUTS Pin LOIP and Pin LOIN LO Drive Level Characterization performed at typical level −10 –7 +5 dBm f < 50 MHz 0 0 5 dBm OUT Input Impedance 50 Ω Input Return Loss 350 MHz, LOIN ac-coupled to ground −20 dB BASEBAND INPUTS Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN I and Q Input Bias Level 500 mV Input Bias Current −70 µA Bandwidth (0.1 dB) RF = 500 MHz, output power = 0 dBm 80 MHz Bandwidth (3 dB) RF = 500 MHz, output power = 0 dBm >500 MHz ENABLE INPUT ENBL Turn-On Settling Time ENBL = high (for output to within 0.5 dB of final value) 1.0 µs Turn-Off Settling Time ENBL = low (at supply current falling below 20 mA) 1.4 µs ENBL High Level (Logic 1) 1.5 V ENBL Low Level (Logic 0) 0.4 V TEMPERATURE OUTPUT TEMP Output Voltage T = 27.15°C, 300.3 K, R = 1 MΩ (after full warm up) 1.56 V A L Temperature Slope −40°C ≤ T ≤ +85°C, R = 1 MΩ 4.6 mV/°C A L Output Impedance 1.0 kΩ POWER SUPPLIES Pin VPS1 and Pin VPS2 Voltage 4.75 5.5 V Supply Current ENBL = high 215 240 mA ENBL = low 80 µA Rev. D | Page 6 of 24

Data Sheet ADL5385 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 2. Parameter Rating Supply Voltage VPOS 5.5 V IBBP, IBBN, QBBP, QBBN Range 0 V to 2.0 V LOIP and LOIN 13 dBm Internal Power Dissipation 1.375 W θ (Exposed Pad Soldered Down) 58°C/W JA Maximum Junction Temperature 164°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. D | Page 7 of 24

ADL5385 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3SP 3SP NIO PIO 3MO 3MO V V L L C C 4 3 2 1 0 9 2 2 2 2 2 1 NC1 18 QBBP NC2 17 QBBN ADL5385 NC3 16 COM2 TOP VIEW COM14 15 COM2 (Not to Scale) COM15 14 IBBN COM16 13 IBBP 7 8 9 0 1 2 1 1 1 T 1 1 P 2 L U S S M S B OV PV PV ET PV NE NOTES 12.. ENLXOCP W=O NISMOEP DCE OPDANADNN.EC SCEOT GL. RDDOEORU N NTODHT EP C LEOAXNNPNEOE.SCETD T POA TDH TISO PAIN. 06118-002 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 3 NC No Connect. Leave these pins open or tie them to ground. 4, 5, 6, 15, COM1, COM2, Power Supply Common Pins. Connect COM1, COM2, and COM3 to a ground plane via a low impedance path. 16, 19, 20 COM3 7 VOUT Device Output. Single-ended, 50 Ω internally biased RF/IF output; pin must be ac-coupled to the load. 8, 9, 11, 23, VPS1, VPS2, Power Supply Pins. Decouple each pin with a 0.1 μF capacitor; Pin 8 and Pin 9 can share a single capacitor, 24 VPS3 as can Pin 23 and Pin 24. Connect all pins to the same supply. 10 TEMP Temperature Sensor Output. Provides dc voltage proportional to die temperature. Slope is 4.6 mV/°C 12 ENBL Device Enable. Shuts device down when grounded and enables device when pulled to supply voltage. 13, 14, IBBP, IBBN, Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be externally dc- 17, 18 QBBN, QBBP biased to 500 mV dc and driven from a low impedance source. Nominal characterized ac signal swing is 700 mV p-p on each pin (150 mV to 850 mV). This results in a differential drive of 1.4 V p-p with a 500 mV dc bias. 21 LOIP Single-Ended Two-Times Local Oscillator Input. This input is internally biased and must be ac-coupled to the LO source. 22 LOIN Common for LO Input. Must be ac-coupled to ground through a low impedance path. EPAD Exposed Pad. Solder the exposed pad to a low impedance ground plane. Rev. D | Page 8 of 24

Data Sheet ADL5385 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, V = 5 V; T = 25°C; LO = −7 dBm; I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias; S A baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω. 8 14 67 VVVSSS === 554...5V7V5V 13 VVVSSS === 554...5V7V5V 12 m) 5 R (dB 4 Bm) 11 WE 3 B (d 10 O d P 2 1 9 TPUT 1 PUT P 8 OU 0 UT B O 7 S –1 S 6 –2 –3 5 –450 550 OUTPUT 1F0R5E0QUENCY (1M5H50z) 2050 06118-003 450 550OUTPUT F10R5E0QUENCY (1M5H5z0) 2050 06118-006 Figure 3. Single Sideband (SSB) Output Power (POUT) vs. Output Frequency Figure 6. Output 1 dB Compression Point (OP1dB) vs. Output Frequency and Power Supply and Power Supply 8 14 7 TTTAAA === –++428055°°°CCC 12 TTTAAA === –++428055°°°CCC m) 6 R (dB 5 Bm) 10 OWE B (d 8 T P 4 P1d OUTPU 3 UTPUT 6 SB 2 O 4 S 1 2 0 50 550 OUTPUT 1F0R5E0QUENCY (1M5H50z) 2050 06118-004 050 550OUTPUT F10R5E0QUENCY (1M5H5z0) 2050 06118-007 Figure 4. Single Sideband (SSB) Output Power (POUT) vs. Output Frequency Figure 7. Output 1 dB Compression Point (OP1dB) vs. Output Frequency and Temperature and Temperature 2.0 –20 5.5 1.5 –30 5.0 OUTPUT POWER VARIANCE (dB)––1001....05050 SECOND-ORDER DISTORTION,CARRIER FEEDTHROUGH,SIDEBAND SUPPRESSION (dB)––––76540000 SIDEBAND SUPSPSRBE SOSUIOTPNTUH (CdTIRAB PDRcO-R)OWIERERDR EF R(Ed EDBDImST)THORROTUIOGNH ((ddBBcm)) 3443....5050 SSB OUTPUT POWER (dBm) –1.5 –80 SECOND-ORDER DISTORION (dBc) 2.5 –2.0 –90 2.0 10M BASEBAND F10R0EMQUENCY (Hz) 1G 06118-005 30 40 50 6O0UTP70UT F8R0EQU9E0NCY10 (0MH1z)10 120 130 140 06118-108 Figure 5. Baseband Frequency Response Normalized to Response for 1 MHz Figure 8. SSB Output Power, Second- and Third-Order Distortion, BB Signal; Carrier Frequency = 500 MHz Carrier Feedthrough, and Sideband Suppression vs. Output Frequency; LO Amplitude = 0 dBm Rev. D | Page 9 of 24

ADL5385 Data Sheet –20 20 0 RDERGH, –30 SIDEBAND SUPPRESSION (dBc) 10 –10 TTTAAA === –++428055°°°CCC ND-ORDER DISTORTION,THIRD-OTORTION, CARRIER FEEDTHROUSIDEBAND SUPPRESSION (dBm) ––––76540000 CARRSISESBRET COFHOEUIRNETDDDP--TUOOHTRRR DPDOOEEURWRG DEDHIRIS S( Td(TdOBOBmRRmT)I)OIONN ( d(dBBcc)) ––––043210000 SSB OUTPUT POWER (dBm) SIDEBAND SUPPRESSION (dBc) ––––––765432000000 CODIS –80 –50 –80 E S –90 –60 –90 –10 –8 –6 LO A–4MPLITU–D2E (dBm0) 2 4 06118-109 50 550 OUTPUT 1F0R5E0QUENCY (1M5H50z) 2050 06118-010 Figure 9. SSB Output Power, Second- and Third-Order Distortion, Figure 12. Sideband Suppression vs. Output Frequency and Carrier Feedthrough, and Sideband Suppression vs. LO Amplitude; Temperature Output Frequency = 30 MHz –20 15 –20 SSB OUTPUT POWER (dBm) D-ORDER DISTORTION, THIRD-ORDERORTION, CARRIER FEEDTHROUGH,SIDEBAND SUPPRESSION––––65430000 CSSTHIEADICRREORDBNI-AEODNRR-D ODF RESEDEUREDP DRTPIS HRDTREISOOSTRSUOTIGORIOHNTN I (O( dd(NdBBB m(cdc))B)c) –05150 OUTPUT AMPLITUDE (dBm) DEBAND SUPPRESSION (dBc) –––––––55443325050505 CONDIST –70 –10 SI –60 SE –65 –80 –15 0.2 0.6 1B.0ASEB1A.4ND AM1P.8LITUD2E.2 (V p-p2).6 3.0 3.4 06118-008 –701M BASEBAND F1R0EMQUENCY (Hz) 100M06118-011 Figure 10. SSB Output Power, Second- and Third-Order Distortion, Figure 13. Sideband Suppression vs. Baseband Frequency; Carrier Feedthrough and Sideband Suppression vs. Differential Output Frequency = 350 MHz Baseband Input Level; Output Frequency = 350 MHz –20 15 0.7100 R SSB OUTPUT POWER (dBm) E CARRIER FEEDTHROUGH (dBm) D-ORDOUGH, –30 SSTHIEDICREODBN-AODNR-DOD RESDRUE PDRPIS RDTEIOSSTRSOTIORIONTNI O( (dNdBB (cdc))Bc) 10 0.7075 D-ORDER DISTORTION, THIRORTION, CARRIER FEEDTHRSIDEBAND SUPPRESSION–––654000 –055 OUTPUT AMPLITUDE (dBm) AMPLITUDE (V)00000.....66777990005702505050 CONDIST –70 –10 E 0.6925 S –80 –15 0.2 0.6 1B.0ASEB1A.4ND AM1P.8LITUD2E.2 (V p-p2).6 3.0 3.4 06118-009 0.690050 250 450 O6U5T0PUT8 5F0REQ10U5E0NC1Y2 5(M0Hz1)450 1650 1850 06118-012 Figure 11. SSB Output Power, Second- and Third-Order Distortion, Figure 14. Distribution of Peak Q Amplitude to Null Undesired Sideband Carrier Feedthrough and Sideband Suppression vs. Baseband Single- (Peak I Amplitude Held Constant at 0.7 V) Ended Input Level; Output Frequency = 860 MHz Rev. D | Page 10 of 24

Data Sheet ADL5385 98 –20 TA = –40°C 97 TA = +25°C TA = +85°C –30 96 m) B d s) 95 GH ( –40 gree 94 ROU PHASE (De 9923 R FEEDTH ––6500 91 E RI R 90 CA –70 89 88 –80 50 250 450 O6U5T0PUT8 5F0REQ10U5E0NC1Y2 5(M0Hz1)450 1650 1850 06118-013 50 550 OUTPUT 1F0R5E0QUENCY (1M5H50z) 2050 06118-016 Figure 15. Distribution of IQ Phase to Null Undesired Sideband Figure 18. Distribution Carrier Feedthrough vs. Output Frequency and Temperature 0 0 –10 TTTAAA === –++428055°°°CCC –10 TTTAAA === ++–428055°°°CCC c) –20 Bm) –20 B d N (d –30 GH ( –30 O U ESSI –40 HRO –40 R T UP –50 ED –50 S E AND –60 ER F –60 B RI SIDE –70 CAR –70 –80 –80 –9050 250 450 O6U5T0PUT8 5F0REQ10U5E0NC1Y2 5(0MH1z)450 1650 1850 06118-014 –9050 550 OUTPUT 1F0R5E0QUENCY (1M5H50z) 2050 06118-017 Figure 16. Sideband Suppression Distribution at Temperature Extremes, Figure 19. Carrier Feedthrough Distribution at Temperature Extremes, After Sideband Suppression Nulled to < −50 dBc at TA = +25°C After Nulling to < −65 dBm at TA = +25°C –20 0.010 30MHz 50MHz –30 350MHz 0.008 Q OFFSET Bc) 0.006 N (d –40 0.004 O SI D SUPPRES ––6500 OFFSET (V)–00..0000220 I OFFSET N A B –70 –0.004 E D SI –0.006 –80 –0.008 –90–10 –8 –6 LO A–4MPLITU–D2E (dBm0) 2 4 06118-015 –0.01050 550OUTPUT 1F0R5E0QUENCY (1M5H50z) 2050 06118-018 Figure 17. Distribution of Sideband Suppression vs. LO Input Power at Figure 20. Distribution of I and Q Offset Required to Null Carrier 30 MHz, 50 MHz, and 350 MHz Output Frequencies Feedthrough Rev. D | Page 11 of 24

ADL5385 Data Sheet –20 20 30MHz 50MHz 18 –30 350MHz m) 16 B H (d –40 S 14 G T HROU –50 F PAR 12 T O 10 R FEED –60 UMBER 8 RIE –70 N 6 R A 4 C –80 2 –90 0 –10 –8 –6 LO A–4MPLITU–D2E (dBm0) 2 4 06118-019 –156.7dB–1m5/6H.6z A–1T5 260.5M–H1z5 O6.F4F–S1E56T. 3FR–1O5M6. 2LO–1 F5R6.E1Q–U1E56N.C0Y–155.9 06118-021 Figure 21. Distribution Carrier Feedthrough vs. LO Input Power at Figure 23. 20 MHz Offset Noise Floor Distribution, 30 MHz, 50 MHz, and 350 MHz Output Frequencies Output Frequency = 350 MHz, POUT = −5 dBm, QPSK Carrier, Symbol Rate = 3.84 MSPS 80 20 TA = –40°C 70 OIP2 TTAA == ++2855°°CC 18 16 60 m) S 14 P3 (dB 50 F PART 12 OI 40 O 10 D R OIP2 AN 30 OIP3 NUMBE 86 20 4 10 2 050 550 OUTPUT 1F0R5E0QUENCY (1M5H50z) 2050 06118-020 0 –155.d2B–m15/H5z.1 A–T1 5152.M0H–z1 5O4F.9FS–1E5T4 .F8R–O1M54 L.7O– F15R4E.6QU–1E5N4C.5Y–154.4 06118-022 Figure 22. OIP3 and OIP2 vs. Output Frequency and Temperature Figure 24. 12 MHz Offset Noise Floor Distribution, Output Frequency = 860 MHz, POUT = −5 dBm, 64 QAM Carrier, Symbol Rate = 5 MSPS Rev. D | Page 12 of 24

Data Sheet ADL5385 0 0.300 VS = 5.5V VS = 5V VS = 4.75V 0.275 –5 N LOSS (dB) –10 CURRENT (A) 00..222550 RETUR –15 UPPLY 0.200 S –20 0.175 –25100 530 960 139L0OIP1 8F2R0EQ22U5E0NC2Y6 8(0MH3z1)10 3540 3970 4400 06118-023 0.150 –40 TEMPERA25TURE (°C) 85 06118-025 Figure 25. LO Port Input Return Loss vs. Frequency Figure 27. Power Supply Current vs. Temperature and Supply Voltage 90 120 60 S11 OF LOIP 4400MHz 150 30 S22 OF OUTPUT 2200MHz 180 0 50MHz 100MHz 210 330 240 300 270 06118-024 Figure 26. Output Impedance and LO Input Impedance vs. Frequency Rev. D | Page 13 of 24

ADL5385 Data Sheet CIRCUIT DESCRIPTION OVERVIEW LO INTERFACE The ADL5385 can be divided into five sections: the local The LO interface consists of a buffer amplifier followed by a oscillator (LO) interface, the baseband voltage-to-current (V-to-I) pair of frequency dividers that generate two carriers at half the converter, the mixers, the differential-to-single-ended (D-to-S) input frequency and in quadrature with each other. Each carrier amplifier, and the bias circuit. A detailed block diagram of the is then amplified and amplitude-limited to drive the double- device is shown in Figure 28. balanced mixers. ENBL V-TO-I CONVERTER The differential baseband input voltages that are applied to the BIAS TEMPERATURE TEMP baseband input pins are fed to a pair of common-emitter, IBBP SENSOR voltage-to-current converters. The output currents then modulate the two half-frequency LO carriers in the mixer stage. IBBN MIXERS The ADL5385 has two double-balanced mixers: one for the in- phase channel (I channel) and one for the quadrature channel LOIP (Q channel). These mixers are based on the Gilbert cell design QDUIAVDIDREA-BTUY-R2E VOUT of four cross-connected transistors. The output currents from PHASE the two mixers are summed together in the resistor-inductor SPLITTER LOIN (RL) loads in the D-to-S amplifier. D-TO-S AMPLIFIER QBBP The output D-to-S amplifier consists of two emitter followers driving a totem-pole output stage that converts the differential signal to a single-ended signal. Output impedance is established QBBN 06118-001 bthyi st hseta egme ictotenrn reecstiss ttoor sth ien othuetp ouutt (pVuOt tUraTn)s ipsitno.r s. The output of Figure 28. ADL5385 Block Diagram BIAS CIRCUIT The LO interface generates two LO signals at 90° of phase A band gap reference circuit generates the proportional-to- difference to drive two mixers in quadrature. Baseband signals absolute-temperature (PTAT) as well as temperature-independ- are converted into currents by the V-to-I converters that feed ent reference currents used by different sections. The band-gap into the two mixers. The outputs of the mixers are combined in circuit is turned on by a logic high at the ENBL pin, which in the differential-to-single-ended amplifier, which provides a 50 Ω turn powers up the whole device. A PTAT voltage output is output interface. Reference currents to each section are available at the TEMP pin, which can be used for temperature generated by the bias circuit. A detailed description of each monitoring as well as for temperature compensation purposes. section follows. Rev. D | Page 14 of 24

Data Sheet ADL5385 BASIC CONNECTIONS Figure 29 shows the basic connections for the ADL5385. LO INPUT POWER SUPPLY AND GROUNDING A single-ended LO signal is applied to the LOIP pin through an ac coupling capacitor. The LO return pin, LOIN, must be All the VPS pins must be connected to the same 5 V source. ac-coupled to ground though a low impedance path. Adjacent pins of the same name can be tied together and decoupled with a 0.1 µF capacitor. Locate these capacitors as close as possible The LO input can be driven differentially, in which case the user to the device. The power supply can range from 4.75 V to 5.5 V. ac couples both sides of the differential LO source through a pair of series capacitors to the LOIP and LOIN pins. The nominal LO The COM1 pin, COM2 pin, and COM3 pin are tied to the same drive of −7 dBm, which is recommended, can be increased to up ground plane through low impedance paths. The exposed pad to 5 dBm. For operation below 50 MHz, it is recommended to on the underside of the package is also soldered to a low thermal use a minimum LO drive level of 0 dBm. The effect of LO power and electrical impedance ground plane. If the ground plane spans on sideband suppression and carrier feedthrough is shown in multiple layers on the circuit board, stitch the layers together Figure 17 and Figure 21. The performance vs. LO power at with nine vias under the exposed pad. The Analog Devices 30 MHz output frequency is shown at Figure 9. AN-722 Application Note discusses the thermal and electrical grounding of the LFCSP in greater detail. RF OUTPUT BASEBAND INPUTS The RF output is available at the VOUT pin (Pin 7). This pin must also be ac-coupled. Below 150 MHz, output power decreases The baseband inputs QBBP, QBBN, IBBP, and IBBN must be due to internal ac-coupling. This is shown in Figure 8. The driven from a differential source. The nominal drive level of VOUT pin has a nominal broadband impedance of 50 Ω and 1.4 V p-p differential (700 mV p-p on each pin) is biased to a does not need further external matching. common-mode level of 500 mV dc. The dc common-mode bias level for the baseband inputs can range from 400 mV to 600 mV. This results in a reduction in the usable input ac swing range. The nominal dc bias of 500 mV allows for the largest ac swing, limited on the bottom end by the ADL5385 input range and on the top end by the output compliance range on most Analog Devices DACs. QBBP QBBN IBBN IBBP CFPQ RFPQ RFNQ CFNQ CFNI RFNI RFPI CFPI OPEN 0Ω 0Ω OPEN OPEN 0Ω 0Ω OPEN RTQ RTI OPEN OPEN R21 49.9Ω OFF ON 8 7 6 5 4 3 1 1 1 1 1 1 SW21 P N 2 2 N P BB BB OM OM BB BB ENB ENBL Q Q C C I I 19COM3 ENBL 12 R13 R22 0Ω 10kΩ 20COM3 VPS2 11 VPOS CLOP LO 0.1µF C16 C15 0.1µF OPEN 21LOIP TEMP10 ADL5385 RTEMP TEMP U1 200Ω 22LOIN VPS1 9 CLON 4×4LFCSP R12 0.1µF 0Ω 23VPS3 EXPOSEDPADDLE VPS1 8 VPOS R11 C14 C13 0Ω 0.1µF OPEN 24VPS3 VOUT 7 CO1P1EN C0.112µF M1 M1 M1 VOUT C C C O O O N N N C C C 1 2 3 4 5 6 COUT 0.1µF VPOS GND 06118-041 Figure 29. Basic Connections for the ADL5385 Rev. D | Page 15 of 24

ADL5385 Data Sheet OPTIMIZATION It is often desirable to perform a one-time carrier null calibration. This is usually performed at a single frequency. Figure 31 shows The carrier feedthrough and sideband suppression performance how carrier feedthrough varies with LO frequency over a range of the ADL5385 can be improved through the use of optimization of ±50 MHz on either side of a null at 350 MHz. techniques. –25 Carrier Feedthrough Nulling –30 Carrier feedthrough results from minute dc offsets that occur m) –35 between each of the differential baseband inputs. In an ideal dB –40 modulator, the quantities (VIOPP − VIOPN) and (VQOPP − VQOPN) GH ( –45 U are equal to zero, and this results in no carrier feedthrough. In a O –50 R H real modulator, those two quantities are nonzero and, when mixed T –55 D E with the LO, result in a finite amount of carrier feedthrough. The E –60 F ADL5385 is designed to provide a minimal amount of carrier ER –65 RI feedthrough. If even lower carrier feedthrough levels are required, R –70 A minor adjustments can be made to the (V − V ) and (V − C –75 QVQ-cOhPNa)n onfefls eotfsf.s Teth ies Iv-acrhieadn nuenlt oilf fas emt iins ihmeIOuldPmP c ocnarsIrOtiaPeNnrt fweehditleh rtQohOueP gPh ––8850 06118-027 300 310 320 330 340 350 360 370 380 390 400 level is obtained. The Q-channel offset required to achieve this OUTPUT FREQUENCY (MHz) minimum is held constant while the offset on the I-channel is Figure 31. Carrier Feedthrough vs. Frequency After Nulling at 350 MHz adjusted, until a better minimum is reached. Through two Sideband Suppression Optimization iterations of this process, the carrier feedthrough can be reduced to as low as the output noise. The ability to null is sometimes limited Sideband suppression results from relative gain and relative phase by the resolution of the offset adjustment. Figure 30 shows the offsets between the I and Q channels and can be suppressed relationship of carrier feedthrough vs. dc offset. through adjustments to those two parameters. Figure 32 illustrates how sideband suppression is affected by the gain and phase –58 imbalances. –62 0 m) B –66 d –10 UGH ( –70 Bc) –20 12..255ddBB O d HR –74 N ( –30 0.5dB T O RIER FEED ––7882 SUPRESSI ––4500 000...012525d5ddBBB R D 0.025dB CA –86 AN –60 0.0125dB B ––9940 06118-029 SIDE –70 0dB –420 –360 –300 –240 –180 V–120P-V–60N OF0FES60T (µV120) 180 240 300 360 420 ––98000.01 0.1 1 10 10006118-028 Figure 30. Carrier Feedthrough vs. DC Offset Voltage at 450 MHz PHASE ERROR (Degrees) Note that throughout the nulling process, the dc bias for the Figure 32. Sideband Suppression vs. Quadrature Phase Error for Various Quadrature Amplitude Offsets baseband inputs remains at 500 mV. When no offset is applied, Figure 32 underscores the fact that adjusting one parameter V = V = 500 mV, or IOPP IOPN improves the sideband suppression only to a point; the other V − V = V = 0 V IOPP IOPN IOS parameter must also be adjusted. For example, if the amplitude When an offset of +VIOS is applied to the I-channel inputs, offset is 0.25 dB, improving the phase imbalance better than 1° V = 500 mV + V /2, while does not yield any improvement in the sideband suppression. For IOPP IOS V = 500 mV − V /2, such that optimum sideband suppression, an iterative adjustment IOPN IOS V − V = V between phase and amplitude is required. IOPP IOPN IOS The same applies to the Q channel. The sideband suppression nulling can be performed either through adjusting the gain for each channel or through the modification of the phase and gain of the digital data coming from the digital signal processor. Rev. D | Page 16 of 24

Data Sheet ADL5385 APPLICATIONS INFORMATION DAC MODULATOR INTERFACING AD9777 ADL5385 The ADL5385 is designed to interface with minimal components 73 13 IOUTA1 IBBP to members of the Analog Devices family of digital-to-analog RBIP 50Ω RSLI converters (DAC). These DACs feature an output current swing 100Ω RBIN from 0 mA to 20 mA, and the interface described in this section 72 50Ω 14 IOUTB1 IBBN can be used with any DAC that has a similar output. Driving the ADL5385 with an Analog Devices TxDAC® 69 17 An example of the interface using the AD9777 TxDAC is shown IOUTB2 QBBN RBQN in Figure 33. The baseband inputs of the ADL5385 require a dc 50Ω RSLQ bias of 500 mV. The average output current on each of the outputs RBQP 100Ω 68 50Ω 18 ogrf otuhne dA fDro9m77 e7a cihs 1o0f tmheA D. AThCe oreuftopruet,s ar essiunlgtsle i n5 0a nΩ a vreesriasgteo rc utorr ent IOUTA2 QBBP 06118-032 of 10 mA flowing through each of the resistors, thus producing Figure 34. AC Voltage Swing Reduction Through Introduction of Shunt Resistor Between Differential Pair the desired 500 mV dc bias for the inputs to the ADL5385. The value of this ac voltage swing limiting resistor is chosen AD9777 ADL5385 based on the desired ac voltage swing. Figure 35 shows the 73 13 relationship between the swing-limiting resistor and the peak- IOUTA1 IBBP RBIP to-peak ac swing that it produces when 50 Ω bias setting 50Ω resistors are used. RBIN 72 50Ω 14 IOUTB1 IBBN 2.0 1.8 IOUTB2 69 17 QBBN V p-p) 11..64 RRBB5QQ0ΩNP WING ( 1.2 IOUTA2 68 50Ω 18 QBBP 06118-030 ENTIAL S 10..08 R Figure 33. Interface Between AD9777 and ADL5385 with 50 Ω Resistors to E 0.6 F Ground to Establish the 500 mV DC Bias for the ADL5385 Baseband Inputs DIF 0.4 T0 hmeA A tDo9 2707 7m oAu.t Wpuitt hc utrhree n50ts Ωh arvees ias tsowrsin ing tphlaatc er,a tnhgee sa cf rvoomlt age 0.20 06118-031 swing going into the ADL5385 baseband inputs ranges from 10 100 1000 10000 0 V to 1 V. A full-scale sine wave out of the AD9777 can be RL (Ω) Figure 35. Relationship Between AC Swing Limiting Resistor and described as a 1 V p-p single-ended (or 2 V p-p differential) Peak-to-Peak Voltage Swing with 50 Ω Bias Setting Resistors sine wave with a 500 mV dc bias. Filtering Limiting the AC Swing When driving a modulator from a DAC, it is necessary to There are situations in which it is desirable to reduce the introduce a low-pass filter between the DAC and the modulator ac voltage swing for a given DAC output current. This can to reduce the DAC images. The interface for setting up the be achieved through the addition of another resistor to the biasing and ac swing lends itself well to the introduction of such interface. This resistor is placed in shunt between each side of a filter. The filter can be inserted in between the dc bias setting the differential pair, as illustrated in Figure 34. It has the effect resistors and the ac swing-limiting resistor, thus establishing the of reducing the ac swing without changing the dc bias already input and output impedances for the filter. established by the 50 Ω resistors. Examples of filters are discussed in the 155 Mbps (STM-1) 128 QAM Transmitter section and the CMTS Transmitter Application section. Rev. D | Page 17 of 24

ADL5385 Data Sheet Using AD9777 Auxiliary DAC for Carrier Feedthrough Nulling 79 0.7 SNR The AD9777 features an auxiliary DAC that can be used to 77 0.6 inject small currents into the differential outputs for each 75 0.5 channel. The auxiliary DAC can produce the small offset cCuarrrreienrt sF neeedcethssraoruyg tho Nimuplllienmg esenct ttihoen .n ulling described in the NR (dB) 73 EVM WITHOUT EQUALIZATION 0.4 VM (%) S 71 0.3 E 155 Mbps (STM-1) 128 QAM TRANSMITTER EVM WITH EQUALIZATION 69 0.2 Figure 39 shows how the ADL5385 can be interfaced to the AD9777 DAC (or any Analog Devices dual DAC with an output b35ia5s MlevHezl .o Bf e0c.5a uVse) ttoh eg eTnxeDraAteC a o 1u5tp5u Mt abnpds 1th2e8 IQQA mMo cdaurlraiteorr at 6657 00.1 06118-042 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 inputs operate at the same bias levels of 0.5 V, a simple dc- CARRIER POWER (dBm) coupled connection can be implemented without any active or Figure 37. EVM and SNR vs. Output Power for 128 QAM Transmitter passive level shifting. The bias level and modulator drive level is Application set by the 50 Ω ground-referenced resistors and the 100 Ω shunt CMTS TRANSMITTER APPLICATION resistors, respectively (see the DAC Modulator Interfacing Because of its broadband operating range from 30 MHz to section). A baseband filter is placed between the bias and signal 2200 MHz, the ADL5385 can be used in direct-launch cable swing resistors. This 5-pole Chebychev filter with in-band ripple modem termination systems (CMTS) applications in the of 0.1 dB has a corner frequency of 39 MHz. 50 MHz to 860 MHz cable band. Figure 36 shows a spectral plot of the 128 QAM spectrum at The same DAC and DAC-to-modulator interface and filtering a carrier power of −6.3 dBm. Figure 37 shows how EVM circuit shown in Figure 39 was used in this application. Figure 38 (measured with the analyzer’s internal equalizer both on and shows a plot of a 4-carrier 256 QAM spectrum at an output off) and SNR, measured at 55 MHz carrier offset (2.5 times the frequency of 485 MHz. carrier bandwidth) varies with output power. –70 –70 –80 Hz) –80 m/Hz) –90 DENSITY (dBm/––11–019000 L DENSITY (dB–––111012000 SPECTRAL ––112300 R SPECTRA––113400 ER –140 WE–150 W O PO––115600 06118-044 P––116700430 440 450 460 470 480 490 500 510 520 530 54006118-043 290 300 310 320 330 340 350 360 370 380 390 400 410 420 FREQUENCY (MHz) FREQUENCY (MHz) Figure 38. Spectrum of 4-Carrier 256 QAM CMTS Signal at 485 MHz Figure 36. Spectral Plot of 128 QAM Transmitter at −6.3 dBm Output Power I CHANNEL 50Ω LINE 317.4nH 372.5nH 100Ω LINE 0Ω IBBP 1/2 50Ω 67.5pF 156.9pF 124.7pF AD9777 200Ω 50Ω LINE 317.4nH 372.5nH 100Ω LINE 0Ω IBBN 50Ω 67.5pF 156.9pF 124.7pF ADL5385 Q CHANNEL 50Ω LINE 317.4nH 372.5nH 100Ω LINE 0Ω QBBP 1/2 50Ω 67.5pF 156.9pF 124.7pF AD9777 200Ω 50Ω LINE 317.4nH 372.5nH 100Ω LINE 0Ω QBBN 50Ω 67.5pF 156.9pF 124.7pF 06118-046 Figure 39. Recommended DAC-Modulator Interconnect for128 QAM Transmitter Rev. D | Page 18 of 24

Data Sheet ADL5385 Figure 40 shows how adjacent channel power (measured at 0 750 kHz, 5.25 MHz, and 12 MHz offset from the last carrier) –10 POUT and modulation error ratio (MER) vary with carrier power. –20 –50 48 Bm) –30 P7LO + BB P5LO – BB P3LO + BB d –55 47 (M –40 R A –60 ACPR2 (5.25MHz) 46 , P_UTH –50 P2LO – BB ACPR (dBc) –––776505 ACPR3 (6.00MHz)ACPR1 (750kHz) 444345 MER (dBc) PO ––––87690000 P6LO – BB P4LO + BB 06118-035 –80 42 0 100 200 300 400 500 600 700 800 900 1000 MER OUTPUT FREQUENCY (MHz) ––9805 4401 06118-045 Figure 41. Specftrroaml C 5o0m MpHonz etno t1s0 fo00r OMuHtpz ut Frequencies –24 –22 –20 –18 –16 –14 –12 –10 RF SECOND-ORDER PRODUCTS CARRIER POWER (dBm) Figure 40. ACP1, ACP2, ACP3, and Modulation Error Ratio (MER) vs. Output A two-tone RF output signal produces second-order spectral Power for 256 QAM Transmitter components at sum and difference frequencies. In broadband SPECTRAL PRODUCTS FROM HARMONIC MIXING systems, these intermodulation products fall inside the carrier or in the adjacent channels. Output second-order RF For broadband applications such as cable TV head-end intermodulation intercept is defined as modulators, special attention must be paid to harmonics of the LO. Figure 41 shows the level of these harmonics (out to 3 GHz) OIP2_RF = P + (P − P ) OUT OUT IM(RF) as a function of the output frequency from 50 MHz to 1000 MHz, where P is the level of the intermodulation product at IM(RF) in a single-sideband (SSB) test configuration, with a baseband f + f . OIP2_RF levels from a two-tone test are plotted OUT1 OUT2 signal of 1 MHz and a SSB level of approximately −5 dBm. To as a function of carrier frequency in Figure 42, where the read this plot correctly, first pick the output frequency of interest on baseband tones are 3.5 MHz and 4.5 MHz at −5 dBm each. the trace called P . The associated harmonics can be read off OUT 70 the harmonic traces at multiples of this frequency. For example, at an output frequency of 500 MHz, the fundamental power is 60 −5 dBm. The power of the second (P ) and third (P ) 2fc − BB 3fc + BB harmonics is −63 dBm (at 1000 MHz) and −16 dBm (at 1500 50 MHz), respectively. Of particular importance are the products m) dB 40 from odd-harmonics of the LO, generated from the switching F ( R operation in the mixers. P2_ 30 OI For cable TV operation at frequencies above approximately 20 500 MHz, these harmonics fall out of the band and can be f5cia0ltb0el reMe bdHa bnzy,d ta. h Tfeihsxeies dh c afarillmltse orfo.n Hri ceosiw tshteeavrre tlr it,m oa sift atalhtl ieco lfnor esoeqf u ttoeh neoc rfy ri endqsruiodepens ct bhyee l ow 100 06118-036 0 250 500 750 1000 1250 1500 1750 2000 2250 range to above 500 MHz or the use of a switchable filter bank to OUTPUT FREQUENCY (MHz) block in-band harmonics at low frequencies. Figure 42. Output Second-Order Intermodulation vs. Carrier Frequency Rev. D | Page 19 of 24

ADL5385 Data Sheet LO GENERATION USING PLLs TRANSMIT DAC OPTIONS Analog Devices has a line of phase-locked loops (PLLs) that can be The AD9777 recommended in the previous sections is by no used for generating the LO signal. Table 4 lists the PLLs together means the only DAC that can be used to drive the ADL5385. with their maximum frequency and phase noise performance. There are other appropriate DACs depending on the level of performance required. Table 6 lists the dual TxDACs that Table 4. PLL Selection Table Analog Devices offers. At 1 kHz Phase Noise Device Frequency f (MHz) dBc/Hz, 200 kHz PFD Table 6. Dual TxDAC Selection Table IN ADF4110 550 −91 at 540 MHz Device Resolution (Bits) Update Rate (MSPS Minimum) ADF4111 1200 −87 at 900 MHz AD9709 8 125 ADF4112 3000 −90 at 900 MHz AD9761 10 40 ADF4113 4000 −91 at 900 MHz AD9763 10 125 ADF4116 550 −89 at 540 MHz AD9765 12 125 ADF4117 1200 −87 at 900 MHz AD9767 14 125 ADF4118 3000 −90 at 900 MHz AD9773 12 160 AD9775 14 160 The ADF4360-0 through the ADF4360-8 (see Table 5 for the AD9777 16 160 full list of devices included in this range) come as a family of AD9776 12 1000 chips, with nine operating frequency ranges. One device can be AD9778 14 1000 chosen depending on the local oscillator frequency required. AD9779 16 1000 While the use of the integrated synthesizer might come at the AD9122 16 1200 expense of slightly degraded noise performance from the ADL5385, it can be a cheaper alternative to a separate PLL All DACs listed have nominal bias levels of 0.5 V and use the and VCO solution. Alternatively, the ADF4351 can be used, same DAC-modulator interface shown in Figure 33. which covers a frequency range of 35 MHz to 4400 MHz. MODULATOR/DEMODULATOR OPTIONS Table 5 shows the options available. Table 7 lists other Analog Devices discrete modulators and Table 5. PLL/VCO Family Operating Frequencies demodulators. Device Output Frequency Range (MHz) Table 7. Modulator/Demodulator Options ADF4351 35 to 4400 Frequency ADF4360-0 2400 to 2725 Device Mod/Demod Range (MHz) Comments ADF4360-1 2050 to 2450 AD8345 Mod 140 to 1000 ADF4360-2 1850 to 2150 AD8346 Mod 800 to 2500 ADF4360-3 1600 to 1950 AD8349 Mod 700 to 2700 ADF4360-4 1450 to 1750 ADL5390 Mod 20 to 2400 External ADF4360-5 1200 to 1400 quadrature ADF4360-6 1050 to 1250 ADL5370 Mod 300 to 1000 ADF4360-7 350 to 1800 ADL5371 Mod 500 to 1500 ADF4360-8 65 to 400 ADL5372 Mod 1500 to 2500 ADL5373 Mod 2300 to 3000 ADL5375 Mod 400 to 6000 ADL5386 Mod 50 to 2200 Includes VVA and AGC AD8347 Demod 800 to 2700 AD8348 Demod 50 to 1000 ADL5380 Demod 400 to 6000 ADL5382 Demod 700 to 2700 ADL5387 Demod 30 to 2000 AD8340 Vector mod 700 to 1000 AD8341 Vector mod 1500 to 2400 Rev. D | Page 20 of 24

Data Sheet ADL5385 EVALUATION BOARD One populated, RoHS-compliant ADL5385 evaluation board is The modulator output can be measured directly at the RF_OUT available, the ADL5385-DIFFLO-EBZ. The ADL5385-DIFFLO- SMA connector. Alternatively, by removing R40, and installing a EBZ can be configured to allow a differential LO drive through a 0 Ω resistor in the R25 pad, the modulator output can be fed to balun or direct interfacing to a PLL evaluation board. It also the RF amplifier. includes component pads in its LO path to accommodate a The ADL5385-DIFFLO-EBZ ships installed with an ADL5601 harmonic filter. The four baseband inputs are located on one amplifier (50 MHz to 4000 MHz RF/IF amplifier). The ADL5602 edge of the board to allow direct connection to a high speed can be used if more gain is needed. Figure 43, Table 8, Figure 44, DAC evaluation board. The ADL5385-DIFFLO-EBZ also and Figure 45 show the schematic, configuration options, and includes an RF/IF amplifier. layouts for the ADL5385-DIFFLO-EBZ, respectively. GND GND GND GND GND GND C76 C82 C88 C91 C85 C79 D.N.I D.N.I D.N.I D.N.I D.N.I D.N.I QNBB R2 R17 R36 R4 INBB 0Ω 0Ω 0Ω 0Ω GND DC.7N5.I DC.8N1.I CD8.N7.I DC.N9.0I DC.N84.I DC.N78.I GND R1 R6 R33 R3 QPBB IPBB 0Ω 0Ω 0Ω 0Ω GND DC.4N1.I DC.8N0.I DC.8N6.I DC.N8.9I DC.N83.I DC.N7.7I GND GND GND GND VP GND GND GND R61 GND 10kΩ O3N S1 O2FF VP QBBP QBBN COM2 COM2 IBBN IBBP 1 R496.29Ω C1090pF C0.61µF LOG_NIDP DC.N18.I DCC0.N41Ω07.I R0DC3Ω.N416.I P46RIT1 RO04ΩR3 1T2213SEC0C.11µ4F GND CCLLOOOOIMMIPN33 22212109 18 17AD 16LU511538145 13 111 0912 TVEVEPNPMSBS1LP2 R2T0E0MΩP GND GND TYEEMLGPND GNDC1050pFGNDVC0P.41µF LOG_NIDN DR.1N5.I DR.3NR02.1ΩI3 DR0Ω.1N0.I R01Ω11 0C.11µ5F VVPPSS33 2243 1EX2PO3SED4 PAD5DLE6 78 VVPOSU1T 0C.13µ1F DR.4N0.I RF_OUGTND VPORSE_DAMP R8 0Ω GND GNDVP RVEPD1 NC NC NC COM1 COM1 COM1 GND D.N.I VP (2) C3 C8 C11 R25 C45 C44 C43 10µF 0.1µF 100pF GND 0Ω 68pF 1.2nF 1µF U2 GND GND GND GND1 GND2 ADL5601 GND GND GND L8 BLACK BLACK 470nH 12SDIINFFGELREE-ENNTDIAELD L LOO D DRRIVIVININGGAATT L LOOIPIP W. ITH T1 OR T2. GND GND RFIN1 2 OUTRF3 AMP_OUT TT12 TTCC11--11--4133AM++ GND 0C.14µ7F GND 06118-143 Figure 43. ADL5385-DIFFLO-EBZ Schematic Table 8. ADL5385-DIFFLO-EBZ Configuration Options Component Description Default Value VP1, VPOS_AMP, GND1, GND2 Power supply clip leads, and ground clip leads. Red (VP1) = 5 V, red (VPOS_AMP) = GND, GND1 and GND2 = black GND Not applicable S1, R61, R62 Device enable select. Set S1 to VP to enable the device. Set S1 S1 = on, R61 = 10 kΩ, R62 = 49.9 Ω to GND to power down the device. R1, R2, R3, R4, R6, R17, Baseband input filters. These components can be used to R1, R2, R3, R4, R6, R17, R33, R36 = 0 Ω, R33, R36, C41, C75 to C91 implement a low-pass filter for the baseband signals. C41, C75 to C91 = open C14, C15 LO driving capacitor. C14, C15 = 0.1 μF R15, R32, R34, C16 to C18, C40 LO input filters. These components can be used to R15, R32 = open, R34, C40 = 0 Ω, implement a filter for the LO input signals. C16 to C18 = open Rev. D | Page 21 of 24

ADL5385 Data Sheet Component Description Default Value LO_IP SMA, R10, R11, R13, Single-ended LO input at LOIP. R11, R13, R34, R43, C40 = 0 Ω, R15, R32, R34, R43, C40, T1, T2 R10, R15, R32 = open, T1, T2 = open LO_IN SMA, R10, R11, R13, R15, Optional single-ended LO input at LOIN. R10, R11, R15, R32, R43 = 0 Ω, R32, R34, R43, C40, T1, T2 R13, R34, C40 = open, T1, T2 = open LO_IP SMA, LO_IN SMA, R10, Optional differential LO input. R11, R15, R32, R34, R43, C40 = 0 Ω, R11, R13, R15, R32, R34, R43, R10, R13 = open, T1, T2 = open C40, T1, T2 LO_IP SMA, R10, R11, R13, Optional differential LO driving with balun (T1or T2) at LOIP. R13, R34, C40 = 0 Ω, R15, R32, R34, R43, C40, T1, T2 R10, R11, R15, R32, R43 = open, T1 = TC1-1-43A+, T2 = TC1-1-13M+ C31 AC-coupling capacitor connects ADL5385 VOUT to C31 = 0.1 μF RF_OUT RF connector or to ADL5601 RF input. C47 AC-coupling capacitor connects ADL5601 RFOUT to C47 = 0.1 μF AMP_OUT connector. R40 Resistor connects ADL5385 VOUT to RF_OUT SMA. To R40 = open check ADL5385 performance itself, insert a 0 Ω at R40 and open R25. To check ADL5601 performance itself, insert a 0 Ω at R40 and be inserted 0.1 μF on R25, open C31. R25 Resistor connects ADL5385 VOUT to ADL5601 RFIN. R25 = 0 Ω RTEMP Resistor connects ADL5385 TEMP to TEMP test clip lead. RTEMP = 200 Ω L8 DC bias inductor. L8 = 470 nH C3, C4, C5, C6, C8, C9, C11, Power supply bypassing capacitors. C3 = 10 μF, C43, C44, C45 C4, C6, C8 = 0.1 μF, C5, C9, C11 = 100 pF, C43 = 1 μF, C44 = 1.2 nF, C45 = 68 pF R8 Resistor to share power supply between the ADL5385 and R8 = open the ADL5601. To turn on the ADL5601 with the power supply on VP1, install a 0 Ω resistor in this location. U1 ADL5385 quadrature modulator. ADL5385 U2 SOT-89 RF/IF gain block. ADL5601 06118-144 06118-145 Figure 44. Layout of ADL5385-DIFFLO-EBZ, Top View Figure 45. Layout of ADL5385-DIFFLO-EBZ, Bottom View Rev. D | Page 22 of 24

Data Sheet ADL5385 CHARACTERIZATION SETUP SSB SETUP Output signals are measured directly using the spectrum analyzer, and currents and voltages are measured using the Figure 46 is a diagram of the characterization test stand setup Agilent 34401A multimeter. for the ADL5385, which is intended to test the product as a single-sideband modulator. The Aeroflex IFR3416 signal generator provides the I and Q inputs as well as the LO input. AEROFLEX IFR 3416 250kHz TO 6GHz FREQ 100MHz TO 4GHz LEVEL 0dBm SIGNAL GENERATOR BIAS 0.5V BGIAAISN 00..57VV RF R&S SPECTRUM ANALYZER FSU 20Hz TO 8GHz GAIN 0.7V OUT LO 50MHz TO 2GHz +6dBm CONNECT TO BACK OF UNIT 90 DEG Q I 0 DEG RF IN OUTPUT GND AGILENT 34401A MULTIMETER VPOS ADL5385 RLM TEST RACK 1 J1(OUT) J7(LO) 0.210 ADC J3(QN) J6(IP) J4(QP) J5(IN) VPOS +5V 5.0000 0.210A AGILENT E3631A POWER SUPPLY 6V ±25V + – +COM – DELL 06118-040 Figure 46. ADL5385 Characterization Board SSB Test Setup Rev. D | Page 23 of 24

ADL5385 Data Sheet OUTLINE DIMENSIONS 4.10 4.00 SQ PIN 1 3.90 INDICATOR PIN 1 0.50 19 24 INDICATOR BSC 18 1 2.40 EXPPAODSED 2.30 SQ 2.20 6 13 0.50 12 7 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.70 0.05 MAX FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.30 0.08 PLANE 0.25 0.203 REF 0.20COMPLIANTTOJEDEC STANDARDS MO-220-WGGD-8. 01-18-2012-A Figure 47. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-14) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option Ordering Quantity ADL5385ACPZ-WP –40°C to +85°C 24-Lead LFCSP, Waffle Pack CP-24-14 64 ADL5385ACPZ-R7 –40°C to +85°C 24-Lead LFCSP, 7” Tape and Reel CP-24-14 1500 ADL5385-DIFFLO-EBZ Evaluation Board with Differential LO Input 1 1 Z = RoHS Compliant Part. ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06118-0-12/16(D) Rev. D | Page 24 of 24