500 MHz to 1700 MHz Balanced Mixer, LO Buffer and RF Balun Data Sheet ADL5367 FEATURES FUNCTIONAL BLOCK DIAGRAM RF frequency range of 500 MHz to 1700 MHz VCMI IFOP IFON PWDN COMM 20 19 18 17 16 IF frequency range of 30 MHz to 450 MHz Power conversion loss: 7.7 dB ADL5367 SSB noise figure of 8.3 dB VPMX 1 15 LOI2 SSB noise figure with 5 dBm blocker of 21 dB Input IP3 of 34 dBm Typical LO drive of 0 dBm RFIN 2 14 VPSW Single-ended, 50 Ω RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V RFCT 3 13 VGS1 Exposed paddle 5 mm × 5 mm, 20-lead LFCSP BIAS GENERATOR 1500 V HBM/500 V FICDM ESD performance COMM 4 12 VGS0 APPLICATIONS Cellular base station receivers Transmit observation receivers COMM 5 11 LOI1 Radio link downconverters 6 7 8 9 10 GENERAL DESCRIPTION NC = NO CONNVELCOT3 LGM3 VLO2 LOSW NC 08083-001 The ADL5367 uses a highly linear, doubly balanced passive Figure 1. mixer core along with integrated RF and LO balancing circuitry The ADL5367 provides two switched LO paths that can be to allow for single-ended operation. The ADL5367 incorporates used in TDD applications where it is desirable to rapidly switch an RF balun, allowing optimal performance over a 500 MHz to between two local oscillators. LO current can be externally set 1700 MHz RF input frequency range. Performance is optimized for using a resistor to minimize dc current commensurate with the RF frequencies from 500 MHz to 1200 MHz using a high-side LO desired level of performance. For low voltage applications, the and for RF frequencies from 900 MHz to 1700 MHz using a ADL5367 is capable of operation at voltages down to 3.3 V with low-side LO. The balanced passive mixer arrangement provides substantially reduced current. Under low voltage operation, an good LO to RF leakage, typically better than −35 dBm, and additional logic pin is provided to power down (<200 µA) the excellent intermodulation performance. The balanced mixer circuit when desired. core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in- The ADL5367 is fabricated using a BiCMOS high performance band blocking signals may otherwise result in the degradation IC process. The device is available in a 5 mm × 5 mm, 20-lead of dynamic performance. A high linearity IF buffer amplifier LFCSP and operates over a −40°C to +85°C temperature range. follows the passive mixer core to yield a typical power conversion An evaluation board is also available. loss of 7.7 dB and can be used with a wide range of output Table 1. Passive Mixers impedances. Single Single Mixer Dual Mixer RF Frequency (MHz) Mixer and IF Amp and IF Amp 500 to 1700 ADL5367 ADL5357 ADL5358 1200 to 2500 ADL5365 ADL5355 ADL5356 2300 to 2900 ADL5363 ADL5353 ADL5354 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADL5367 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Upconversion .............................................................................. 15 Applications ....................................................................................... 1 Spur Tables .................................................................................. 16 General Description ......................................................................... 1 Circuit Description......................................................................... 17 Functional Block Diagram .............................................................. 1 RF Subsystem .............................................................................. 17 Revision History ............................................................................... 2 LO Subsystem ............................................................................. 17 Specifications ..................................................................................... 3 Applications Information .............................................................. 19 5 V Performance ........................................................................... 4 Basic Connections ...................................................................... 19 3.3 V Performance ........................................................................ 4 IF Port .......................................................................................... 19 Absolute Maximum Ratings ............................................................ 5 Mixer VGS Control DAC .......................................................... 19 ESD Caution .................................................................................. 5 Evaluation Board ............................................................................ 20 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 23 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 23 5 V Performance ........................................................................... 7 3.3 V Performance ...................................................................... 14 REVISION HISTORY 3/16—Rev. B to Rev. C Added Thermal Resistance Section and Junction to Board Thermal Impedance Section ............................................... 5 Changes to Figure 2 .......................................................................... 6 Change to Evaluation Board Section and Figure 49 .................. 20 2/15—Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 Deleted Figure 37 and Figure 39 ................................................... 13 Deleted Bias Resistor Selection Section ....................................... 19 Changes to Figure 49 ...................................................................... 20 Changes to Table 7 .......................................................................... 21 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 10/09—Revision 0: Initial Version Rev. B | Page 2 of 24

Data Sheet ADL5367 SPECIFICATIONS V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, Z = 50 Ω, unless otherwise noted. S S A RF LO O Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RF INPUT INTERFACE Return Loss Tunable to >20 dB over a limited bandwidth 14 dB Input Impedance 50 Ω RF Frequency Range 500 1700 MHz OUTPUT INTERFACE Output Impedance Differential impedance, f = 200 MHz 34||1.9 Ω||pF IF Frequency Range 30 450 MHz DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V LO INTERFACE LO Power −6 0 +10 dBm Return Loss 12.6 dB Input Impedance 50 Ω LO Frequency Range 730 1670 MHz POWER-DOWN (PWDN) INTERFACE 2 PWDN Threshold 1.0 V Logic 0 Level 0.4 V Logic 1 Level 1.4 V PWDN Response Time Device enabled, IF output to 90% of the final level 160 ns Device disabled, supply current < 5 mA 220 ns PWDN Input Bias Current Device enabled 0.0 μA Device disabled 70 μA 1 Apply the supply voltage from the external circuit through the choke inductors. 2 PWDN function is intended for use with VS ≤ 3.6 V only. Rev. B | Page 3 of 24

ADL5367 Data Sheet 5 V PERFORMANCE V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless S S A RF LO O otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Power Conversion Loss Including 1:1 IF port transformer and printed circuit board (PCB) loss 6.5 7.7 8.5 dB Voltage Conversion Loss Z = 50 Ω, differential Z = 50 Ω differential 1.4 dB SOURCE LOAD SSB Noise Figure 8.3 dB SSB Noise Figure Under Blocking 5 dBm blocker present ±10 MHz from wanted RF input, LO source 21 dB filtered Input Third-Order Intercept (IIP3) f = 899.5 MHz, f = 900.5 MHz, f = 1103 MHz, each RF tone 28 34 dBm RF1 RF2 LO at 0 dBm Input Second-Order Intercept (IIP2) f = 950 MHz, f = 900 MHz, f = 1103 MHz, each RF tone 80 dBm RF1 RF2 LO at 0 dBm Input 1 dB Compression Point (IP1dB)1 Exceeding 20 dBm RF power results in damage to the device 25 dBm LO to IF Leakage Unfiltered IF output −15 dBm LO to RF Leakage −40 dBm RF to IF Isolation −47 dBc IF/2 Spurious 0 dBm input power −75 dBc IF/3 Spurious 0 dBm input power −72 dBc POWER SUPPLY Positive Supply Voltage 4.5 5 5.5 V Total Quiescent Current V = 5 V 97 mA S 1 Exceeding 20 dBm RF power results in damage to the device. 3.3 V PERFORMANCE V = 3.3 V, I = 56 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and Z = 50 Ω, S S A RF LO O unless otherwise noted. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Power Conversion Loss Including 4:1 IF port transformer and PCB loss 7.3 dB Voltage Conversion Loss Z = 50 Ω, differential Z = 200 Ω differential 1 dB SOURCE LOAD SSB Noise Figure 8.1 dB Input Third-Order Intercept (IIP3) f = 1949.5 MHz, f = 1950.5 MHz, f = 1750 MHz, 28.5 dBm RF1 RF2 LO each RF tone at −10 dBm Input Second-Order Intercept (IIP2) f = 1950 MHz, f = 1900 MHz, f = 1750 MHz, 75 dBm RF1 RF2 LO each RF tone at −10 dBm POWER INTERFACE Supply Voltage 3.0 3.3 3.6 V Quiescent Current Resistor programmable 56 mA Power-Down Current Device disabled 150 μA Rev. B | Page 4 of 24

Data Sheet ADL5367 ABSOLUTE MAXIMUM RATINGS Junction to Board Thermal Impedance Table 5. The junction to board thermal impedance (θ ) is the thermal Parameter Rating JB impedance from the die to or near the component lead of the Supply Voltage, V 5.5 V S ADL5367. For the ADL5367, θ is determined experimentally RF Input Level 20 dBm JB to 14.74°C/W with the device mounted on a 4-layer circuit LO Input Level 13 dBm board with two layers as ground planes in a configuration IFOP, IFON Bias Voltage 6.0 V similar to the ADL5367-EVALZ evaluation board. Board size VGS0, VGS1, LOSW, PWDN 5.5 V and complexity (number of layers) affect θ ; more layers tend to Internal Power Dissipation 1.2 W JB reduce the thermal impedance slightly. Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C If the board temperature is known, use the junction to board Storage Temperature Range −65°C to +150°C thermal impedance to calculate die temperature (also known Lead Temperature Range (Soldering, 60 sec) 260°C as junction temperature) to ensure it does not exceed the specified limit of 150°C. For example if the board temperature is 85°C, the die temperature is given by the equation Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a T = T + (P × θ ) j B DISS JB stress rating only; functional operation of the product at these where T is the junction temperature. j or any other conditions above those indicated in the operational T is the board temperature measured at or near the B section of this specification is not implied. Operation beyond component lead. the maximum operating conditions for extended periods may P is the power dissipated from the device. DISS affect product reliability. The typical worst case power dissipation for the ADL5367 is THERMAL RESISTANCE 605 mW (5.5 V × 110 mA). Therefore T is j θ is thermal resistance, junction to ambient (°C/W), and θ is JA JB T = 85°C + (0.605 W × 14.74°C/W) = 93.91°C j thermal impedance, junction to board (°C/W). ESD CAUTION Table 6. Thermal Resistance Package Type θ 1 θ 1 Unit JA JB 20-Lead LFCSP 25 14.74 °C/W 1 See the JEDEC standard, JESD51-2, for information on optimizing thermal impedance (PCB with 3 × 3 vias). Rev. B | Page 5 of 24

ADL5367 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NM IMPNDM CVOFIOFIWPOC 09876 21111 VPMX 1 15 LOI2 RFIN 2 14 VPSW ADL5367 RFCT 3 13 VGS1 TOP VIEW COMM 4 (Not to Scale) 12 VGS0 COMM 5 11 LOI1 67890 1 332WC OLVMGLOLVSOLN NOTES 12 .. ENTOXCP =GO RNSOOEU DCN OPDAN.DN.E MCUT.ST BE SOLDERED 08083-002 Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 VPMX Positive Supply Voltage for IF Amplifier. 2 RFIN RF Input. This pin must be ac-coupled. 3 RFCT RF Balun Center Tap (AC Ground). 4, 5, 16 COMM Device Common (DC Ground). 6, 8 VLO3, VLO2 Positive Supply Voltages for LO Amplifier. 7 LGM3 LO Amplifier Bias Control. 9 LOSW LO Switch. LOI1 selected for 0 V, or LOI2 selected for 3 V. 10 NC No Connect. 11, 15 LOI1, LOI2 LO Inputs. This pin must be ac-coupled. 12, 13 VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting. 14 VPSW Positive Supply Voltage for LO Switch. 17 PWDN Power Down. Connect this pin to ground for normal operation or connect this pin to 3.0 V for disable mode. 18, 19 IFON, IFOP Differential IF Outputs. 20 VCMI No Connect. This pin can be grounded. EPAD (EP) Exposed pad must be soldered to ground. Rev. B | Page 6 of 24

Data Sheet ADL5367 TYPICAL PERFORMANCE CHARACTERISTICS 5 V PERFORMANCE V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless S S A RF LO O otherwise noted. 110 100 105 90 TA =–40°C A) CURRENT (m 10905 TA = +25°C TA =–40°C T IP2 (dBm) 7800 PPLY 90 TA = +85°C INPU 60 TA = +85°C U S 85 50 TA = +25°C 80 40 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-017 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-023 Figure 3. Supply Current vs. RF Frequency Figure 6. Input IP2 vs. RF Frequency 10.0 12 9.5 11 9.0 ON LOSS (dB) 788...505 TA = +25°C TA = +85°C E FIGURE (dB) 109 TTAA == ++2855ººCC CONVERSI 67..50 TA =–40°C SSB NOIS 78 TA = –40ºC 6.0 6 5.5 5.0700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-035 5700 750 800 850RF 9F0R0EQU9E50NCY10 (0M0Hz1)050 1100 1150 1200 08083-011 Figure 4. Power Conversion Loss vs. RF Frequency Figure 7. SSB Noise Figure vs. RF Frequency 40 38 36 m) TA = +25°C B d 34 3 ( P UT I 32 P IN TA =–40°C 30 TA = +85°C 28 26 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-028 Figure 5. Input IP3 vs. RF Frequency Rev. B | Page 7 of 24

ADL5367 Data Sheet V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless S S A RF LO O otherwise noted. 110 86 84 105 VPOS = 5.25V A) VPOS = 5.25V 82 NT (m 100 Bm) 80 PPLY CURRE 9905 VPVOPSO =S 4 =.7 55VV INPUT IP2 (d 7768 VPOS = 5V VPOS = 4.75V U S 74 85 72 80 70 –40 –20 0TEMPER2A0TURE(°4C0) 60 80 08083-019 –40 –20 0TEMPER2A0TURE(°4C0) 60 80 08083-025 Figure 8. Supply Current vs. Temperature Figure 11. Input IP2 vs. Temperature 10.0 12 VPOS = 4.75V 9.5 VPOS = 5V VPOS = 5.25V 11 9.0 LOSS (dB) 88..05 GURE (dB) 109 VPOS = 5.25V NVERSION 77..05 B NOISE FI 8 VPOS = 4.75V VPOS = 5V CO 6.5 SS 7 6.0 6 5.5 5.0–40 –20 0TEMPER2A0TURE(°4C0) 60 80 08083-038 5–40 –20 0 TEMPE2R0ATURE4 (0ºC) 60 80 08083-012 Figure 9. Power Conversion Loss vs. Temperature Figure 12. SSB Noise Figure vs. Temperature 40 38 36 VPOS = 5.25V m) B d 34 P3 ( VPOS = 5V UT I 32 VPOS = 4.75V P N I 30 28 26 –40 –20 0TEMPER2A0TURE(°4C0) 60 80 08083-030 Figure 10. Input IP3 vs. Temperature Rev. B | Page 8 of 24

Data Sheet ADL5367 V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless S S A RF LO O otherwise noted. 110 85 TA = +25°C 80 105 A) TA =–40°C 75 NT (m 100 TA = +25°C Bm) PPLY CURRE 9905 TA = +85°C INPUT IP2 (d 6750 TA = +85°C SU 60 TA =–40°C 85 55 80 50 30 80 130 I1F8 0FREQ2U30ENCY2 8(M0Hz)330 380 430 08083-016 30 80 130 I1F8 0FREQ2U30ENCY2 8(M0Hz)330 380 430 08083-021 Figure 13. Supply Current vs. IF Frequency Figure 16. Input IP2 vs. IF Frequency 10.0 12 9.5 11 9.0 dB) 8.5 TA = +85°C dB) 10 LOSS ( 8.0 TA = +25°C GURE ( 9 NVERSION 77..05 TA =–40°C B NOISE FI 8 CO 6.5 SS 7 6.0 6 5.5 5.030 80 130 I1F8 0FREQ2U30ENCY2 8(M0Hz)330 380 430 08083-033 530 80 130 1IF8 0FREQ23U0ENCY28 (0MHz)330 380 430 08083-010 Figure 14. Power Conversion Loss vs. IF Frequency Figure 17. SSB Noise Figure vs. IF Frequency 40 38 TA =–40°C 36 m) B d 34 P3 ( TA = +25°C UT I 32 P N I 30 28 TA = +85°C 26 30 80 130 I1F8 0FREQ2U30ENCY2 8(M0Hz)330 380 430 08083-026 Figure 15. Input IP3 vs. IF Frequency Rev. B | Page 9 of 24

ADL5367 Data Sheet V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless S S A RF LO O otherwise noted. 10.0 –40 9.5 –50 B) 9.0 OSS (d 8.5 TA = +85°C S (dBc) –60 ON L 8.0 TA = +25°C RIOU –70 SI U R P CONVE 77..05 TA =–40°C IF/2 S –80 TA = +85°C TA =–40°C TA = +25°C –90 6.5 6.0 –100 –6 –4 –2 L0O POW2ER (dBm4) 6 8 10 08083-034 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-020 Figure 18. Power Conversion Loss vs. LO Power Figure 21. IF/2 Spurious vs. RF Frequency 40 –40 –45 38 –50 36 TA =–40°C TA = +25°C m) dBc) –55 INPUT IP3 (dB 3324 TA = +85°C F/3 SPURIOUS ( –––766050 TA =–40°C TA = +85°C 30 I –75 28 TA = +25°C –80 26 –85 –6 –4 –2 L0O POW2ER (dBm4) 6 8 10 08083-027 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-040 Figure 19. Input IP3 vs. LO Power Figure 22. IF/3 Spurious vs. RF Frequency 90 85 TA = +25°C TA =–40°C 80 m) 75 B P2 (d 70 TA = +85°C T I U NP 65 I 60 55 50 –6 –4 –2 L0O POW2ER (dBm4) 6 8 10 08083-022 Figure 20. Input IP2 vs. LO Power Rev. B | Page 10 of 24

Data Sheet ADL5367 V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless S S A RF LO O otherwise noted. 100 36.5 3.6 36.0 3.4 35.5 3.2 80 35.0 3.0 T (%) 60 CE (Ω)3344..50 22..86 CE (pF) N N N RCE STA33.5 2.4 CITA PE 40 ESI33.0 2.2 PA R32.5 2.0 CA 32.0 1.8 20 31.5 1.6 MEAN: 7.7 31.0 1.4 STANDARD DEVIATION: 0.18 07.2 7.4 CON7V.E6RSION LO7S.8S (dB) 8.0 8.2 08083-068 30.530 80 130 I1F8 0FREQ2U30ENCY2 8(M0Hz)330 380 430 1.2 08083-069 Figure 23. Conversion Loss Distribution Figure 26. IF Port Return Loss 100 0 80 5 B) d NT (%) 60 LOSS ( 10 E N C R R U PE 40 ET 15 R F R 20 20 MEAN: 34.67 STANDARD DEVIATION: 0.19 031 33 INPUT I3P53 (dBm) 37 39 08083-067 25700 750 800 850RF 9F0R0EQU9E50NCY1 0(M00Hz1)050 1100 1150 1200 08083-013 Figure 24. Input IP3 Distribution Figure 27. RF Port Return Loss, Fixed IF 100 0 90 2 80 4 GE (%) 6700 OSS (dB) 86 TA 50 N L 10 N R E U RC 40 ET 12 SELECTED E R P 30 LO 14 20 16 UNSELECTED 10 MEAN: 8.3 18 STANDARD DEVIATION: 0.05 07.8 8.0 8.2NOISE FI8G.4URE (dB8).6 8.8 9.0 08083-063 20900 950 1000 105L0O 1F1R0E0Q1U1E5N0CY1 2(0M0Hz1)250 1300 1350 1400 08083-007 Figure 25. SSB Noise Figure Distribution Figure 28. LO Return Loss, Selected and Unselected Rev. B | Page 11 of 24

ADL5367 Data Sheet V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless S S A RF LO O otherwise noted. 70 –20 65 –25 TION (dB) 60 TA = +25°C TA = –40°C GE (dBm) –30 TCH ISOLA 55 TA = +85°C RF LEAKA –35 TA =–40°C TA = +85°C WI 50 O- –40 O S O-T L L 45 –45 TA = +25°C 40 –50 700 750 800 850RF F90R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-059 900 950 1000 1050LO1 F1R00EQ1U1E5N0CY1 2(0M0Hz1)250 1300 1350 1400 08083-032 Figure 29. LO Switch Isolation vs. RF Frequency Figure 32. LO to RF Leakage vs. LO Frequency –40 0 –42 TA = +85°C –5 –44 –10 c) TA = +25°C B N (d –46 Bm) –15 2LO TO RF TIO –48 E (d –20 A G O-IF ISOL ––5520 TA =–40°C O LEAKA ––3205 RF-T –54 2L –35 2LO TO IF –56 –40 –58 –45 –60 –50 900 950 1000 1050RF 1F1R0E0Q1U1E5N0CY1 2(0M0Hz1)250 1300 1350 1400 08083-039 900 950 1000 1050LO1 F1R00EQ1U1E5N0CY1 2(0M0Hz1)250 1300 1350 1400 08083-014 Figure 30. RF to IF Isolation vs. RF Frequency Figure 33. 2LO Leakage vs. LO Frequency 0 0 –10 –5 m) E (dB –10 TA =–40°C dBm) –20 3LO TO IF AG E ( –30 K G EA –15 TA = +25°C KA O-TO-IF L –20 TA = +85°C 3LO LEA ––5400 3LO TO RF L –25 –60 –30 –70 900 950 1000 105L0O 1F1R0E0Q1U1E5N0CY1 2(0M0Hz1)250 1300 1350 1400 08083-031 900 950 1000 1050LO1 F1R00EU1Q1E5N0CY1 2(0M0Hz1)250 1300 1350 1400 08083-015 Figure 31. LO to IF Leakage vs. LO Frequency Figure 34. 3LO Leakage vs. LO Frequency Rev. B | Page 12 of 24

Data Sheet ADL5367 V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless S S A RF LO O otherwise noted. 10 15 30 9 14 CONVERSION LOSS 25 8 13 B) B) OSS (d 67 1112 URE (d E (dB) 20 L G R ONVERSION 345 NOISE FIGURE 8910 SB NOISE FI NOISE FIGU 1105 C S 2 7 VGS = 0, 0 5 VGS = 0, 1 1 VGS = 1, 0 6 VGS = 1, 1 0700 750 800 850RF F90R0EQU9E50NCY10 (0M0Hz1)050 1100 1150 12005 08083-058 0–30 –25 –20 BLO–1C5KER P–1O0WER –(d5Bm) 0 5 10 08083-003 Figure 35. Power Conversion Loss and SSB Noise Figure vs. RF Frequency Figure 37. SSB Noise Figure vs.10 MHz Offset Blocker Level 40 VGS = 0, 0 38 VGS = 0, 1 VGS = 1, 0 VGS = 1, 1 36 34 m) B 32 d P3 ( 30 T I PU 28 N I 26 24 22 20 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-062 Figure 36. Input IP3 vs. RF Frequency Rev. B | Page 13 of 24

ADL5367 Data Sheet 3.3 V PERFORMANCE V = 3.3 V, I = 56 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and Z = 50 Ω, S S A RF LO O unless otherwise noted. 85 64 80 TA = –40°C 62 75 A) RRENT (m 5680 TA = +25°C TA = –40°C P2 (dBm) 6750 TA = +25°C LY CU 56 NPUT I 60 TA = +85°C UPP TA = +85°C I 55 S 54 50 52 45 50700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-018 40700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-024 Figure 38. Supply Current vs. RF Frequency at 3.3 V Figure 41. Input IP2 vs. RF Frequency at 3.3 V 10.0 10.0 9.5 9.5 9.0 9.0 TA = +85°C VERSION LOSS (dB) 7788....0505 TA = +25°C TA = +85°C OISE FIGURE (dB) 7788....0505 TTAA == –+4205°°CC ON 6.5 N 6.5 C TA = –40°C 6.0 6.0 5.5 5.5 5.0 5.0 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-036 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-064 Figure 39. Power Conversion Loss vs. RF Frequency at 3.3 V Figure 42. SSB Noise Figure vs. RF Frequency at 3.3 V 34 32 TA = –40°C 30 m) B d 28 3 ( UT IP 26 TA = +85°C P N I TA = +25°C 24 22 20 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-029 Figure 40. Input IP3 vs. RF Frequency at 3.3 V Rev. B | Page 14 of 24

Data Sheet ADL5367 UPCONVERSION T = 25°C, f = 153 MHz, f = 1697 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and Z = 50 Ω, unless otherwise noted. A IF LO O 10.0 10.0 9.5 9.5 9.0 9.0 B) B) d 8.5 d 8.5 S ( S ( LOS 8.0 TA = +85°C LOS 8.0 ON 7.5 ON 7.5 TA = +85°C NVERSI 7.0 TA = –40°C TA = +25°C NVERSI 7.0 TA = +25°C CO 6.5 CO 6.5 TA = –40°C 6.0 6.0 5.5 5.5 5.0700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-065 5.0700 750 800 85R0F F9R0E0QU9E5N0CY1 0(M00Hz1)050 1100 1150 1200 08083-066 Figure 43. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion Figure 45. Power Conversion Loss vs. RF Frequency at 3.3 V, Upconversion 34 34 TA = –40°C TA = +25°C 32 32 TA = +85°C 30 TA = –40°C m) 30 m) B B d d 28 3 ( 28 3 ( TA = +85°C P P PUT I 26 PUT I 26 N N I I TA = +25°C 24 24 22 22 20 20 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-060 700 750 800 850RF 9F0R0EQU9E50NCY1 0(0M0Hz1)050 1100 1150 1200 08083-061 Figure 44. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion Figure 46. Input IP3 vs. RF Frequency at 3.3 V, Upconversion Rev. B | Page 15 of 24

ADL5367 Data Sheet SPUR TABLES All spur tables are (N × f ) − (M × f ) and were measured using the standard evaluation board. Mixer spurious products are measured RF LO in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm. 5 V Performance V = 5 V, I = 97 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and S S A RF LO Z = 50 Ω, unless otherwise noted. O M 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 −7.8 −24.6 −35.7 −53.0 −47.4 1 −39.7 0.0 −45.0 −27.5 −53.0 −54.4 −71.8 2 −84.6 −68.8 −77.4 −72.8 −80.2 −80.9 −87.8 −96.8 3 <−100 −78.6 −95.5 −75.9 −97.9 −91.7 <−100 <−100 4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 N 8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 3.3 V Performance V = 3.3 V, I = 56 mA, T = 25°C, f = 900 MHz, f = 1103 MHz, LO power = 0 dBm, RF power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = S S A RF LO 0 V, and Z = 50 Ω, unless otherwise noted. O M 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 −12.6 −28.8 −40.6 −43.0 −59.6 1 −40.5 0.0 −42.7 −27.1 −53.2 −50.7 −71.8 2 −78.6 −59.5 −64.8 −68.0 −65.9 −73.0 −75.4 −89.4 3 −93.9 −66.3 −90.1 −63.0 −90.5 −77.8 −96.4 −95.6 4 <−100 <−100 −95.6 −95.5 −97.0 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 −98.9 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 N 8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 Rev. B | Page 16 of 24

Data Sheet ADL5367 CIRCUIT DESCRIPTION The ADL5367 consists of two primary components: the radio The resulting balanced RF signal is applied to a passive mixer frequency (RF) subsystem and the local oscillator (LO) subsystem. that commutates the RF input with the output of the LO subsystem. The combination of design, process, and packaging technology The passive mixer is essentially a balanced, low loss switch that allows the functions of these subsystems to be integrated adds minimum noise to the frequency translation. The only into a single die, using mature packaging and interconnection noise contribution from the mixer is due to the resistive loss technologies to provide a high performance, low cost design of the switches, which is in the order of a few ohms. with excellent electrical, mechanical, and thermal properties. Because the mixer is inherently broadband and bidirectional, it In addition, the need for external components is minimized, is necessary to properly terminate all the idler (M × N product) optimizing cost and size. frequencies generated by the mixing process. Terminating the The RF subsystem consists of an integrated, low loss RF balun, mixer avoids the generation of unwanted intermodulation passive MOSFET mixer, sum termination network, and IF products and reduces the level of unwanted signals at the IF amplifier. output. This termination is accomplished by the addition of a sum network between the IF output and the mixer. The LO subsystem consists of an SPDT terminated FET switch and a three-stage limiting LO amplifier. The purpose of the LO Additionally, dc current can be saved by reducing the dc supply subsystem is to provide a large, fixed amplitude, balanced signal voltage to as low as 3.3 V, further reducing the dissipated power to drive the mixer independent of the level of the LO input. of the device. (Note that no performance enhancement is obtained by reducing the value of these resistors and excessive dc power A block diagram of the device is shown in Figure 47. dissipation may result.) VCMI IFOP IFON PWDN COMM 20 19 18 17 16 LO SUBSYSTEM ADL5367 The LO amplifier is designed to provide a large signal level to VPMX 1 15 LOI2 the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 1100 MHz. The best RFIN 2 14 VPSW operation is achieved with either high-side LO injection for RF signals in the 500 MHz to 1200 MHz range or low-side injection for RF signals in the 900 MHz to 1700 MHz range. Operation RFCT 3 13 VGS1 outside these ranges is permissible, and conversion loss is BIAS extremely wideband, easily spanning 500 MHz to 1700 MHz, GENERATOR but intermodulation is optimal over the aforementioned ranges. COMM 4 12 VGS0 The ADL5367 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are COMM 5 11 LOI1 applied to a high isolation SPDT switch that provides a constant 6 7 8 9 10 input impedance, regardless of whether the port is selected, to NC = NO CONNVELOCT3 LGM3 VLO2 LOSW NC 08083-051 aenvosuidr epsu hlliignhg itshoela LtiOon s otou rtchees .o Tffh iinsp mutu, lmtipinlei mseicztiinogn a snwyi tlcehak aalgsoe Figure 47. Simplified Schematic from the unwanted LO input that may result in undesired IF RF SUBSYSTEM responses. The single-ended, 50 Ω RF input is internally transformed to a The single-ended LO input is converted to a fixed amplitude balanced signal using a low loss (<1 dB) unbalanced to balanced differential signal using a multistage, limiting LO amplifier. (balun) transformer. This transformer is made possible by an This results in consistent performance over a range of LO input extremely low loss metal stack, which provides both excellent power. Optimum performance is achieved from −6 dBm to balance and dc isolation for the RF port. Although the port can +10 dBm, but the circuit continues to function at considerably be dc connected, it is recommended that a blocking capacitor be lower levels of LO input power. used to avoid running excessive dc current through the device. The RF balun can easily support an RF input frequency range of 500 MHz to 1700 MHz. Rev. B | Page 17 of 24

ADL5367 Data Sheet The performance of this amplifier is critical in achieving a In addition, when operating with supply voltages below 3.6 V, high intercept passive mixer without degrading the noise floor the ADL5367 has a power-down mode that permits the dc of the system. This is a critical requirement in an interferer rich current to drop to <200 µA. environment, such as cellular infrastructure, where blocking All of the logic inputs are designed to work with any logic family interferers can limit mixer performance. The bandwidth of the that provides a Logic 0 input level of less than 0.4 V and a Logic 1 intermodulation performance is somewhat influenced by the input level that exceeds 1.4 V. All logic inputs are high impedance current in the LO amplifier chain. For dc current sensitive up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection applications, it is permissible to reduce the current in the circuitry permits operation up to 5.5 V, although a small bias LO amplifier by raising the value of the external bias control current is drawn. resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. Rev. B | Page 18 of 24

Data Sheet ADL5367 APPLICATIONS INFORMATION BASIC CONNECTIONS IF PORT The ADL5367 mixer is designed to upconvert or downconvert The real part of the output impedance is approximately 50 Ω, between radio frequencies (RF) from 500 MHz to 1700 MHz and as seen in Figure 26, which matches many commonly used SAW intermediate frequencies (IF) from dc to 450 MHz. Figure 48 filters without the need for a transformer. This results in a voltage depicts the basic connections of the mixer. It is recommended conversion loss that is approximately the same as the power to ac-couple the RF and LO input ports to prevent nonzero dc conversion loss, as shown in Table 3. voltages from damaging the RF balun or LO input circuit. The MIXER VGS CONTROL DAC RFIN capacitor value of 8 pF is recommended to provide the The ADL5367 features two logic control pins, Pin 12 (VGS0) and optimized RF input return loss for the desired frequency band. Pin 13 (VGS1), that allow programmability for internal gate to For upconversion, the IF input, Pin 18 (IFON) and Pin 19 (IFOP), source voltages for optimizing mixer performance over desired must be driven differentially or using a 1:1 ratio transformer for frequency bands. The evaluation board defaults both VGS0 and single ended operation. An 8 pF capacitor is recommended for VGS1 to ground. Power conversion loss, NF, and IIP3 can be the RF output, Pin 2 (RFIN). optimized, as shown in Figure 35 and Figure 36. IF1_OUT R1 0Ω T1 C25 C24 560pF 560pF 10kΩ +5V 20 19 18 17 16 10pF 4.7µF ADL5367 22pF +5V 1 15 LO2_IN 8pF RF-IN 2 14 +5V 10pF 3 13 0.01µF 10pF BIAS GENERATOR 4 12 22pF 5 11 LO1_IN 6 7 8 9 10 RBIAS LO 10kΩ +5V 10pF 10pF 08082-052 Figure 48. Typical Application Circuit Rev. B | Page 19 of 24

ADL5367 Data Sheet EVALUATION BOARD An evaluation board is available for the family of double balanced Table 8 describes the various configuration options of the mixers. The standard evaluation board schematic is shown in evaluation board. The evaluation board layout is shown in Figure 49. The evaluation board, ADL5367-EVALZ, is fabricated Figure 50 to Figure 53. using Rogers® RO3003 material. IF1_OUT R1 0Ω T1 C25 C24 560pF 560pF PWR_UP R21 10kΩ R14 L3 0Ω 0Ω C12 IMCV POFI NOFI NDWP MMOC 22pF LO2_IN VPOS VPOS VPMX LOI2 C2 C21 C20 10µF 10pF 10pF R22 10kΩ RF-IN RFIN VPSW C1 C22 R23 8pF RFCT ADL5367 VGS1 1nF 15kΩ C5 C4 VGS1 0.01µF 10pF COMM VGS0 VGS0 COMM LOI1 3OL 3MG 2OL WSO C LO1_IN V L V L N C10 22pF VPOS LOSEL C6 R9 R4 10pF 1.7kΩ 10kΩ VPOS C108pF 08082-053 Figure 49. Evaluation Board Schematic Rev. B | Page 20 of 24

Data Sheet ADL5367 Table 8. Evaluation Board Configuration Components Description Default Conditions C2, C6, C8, Power Supply Decoupling. Nominal supply decoupling consists ofa 10 µF C2 = 10 µF (Size 0603), C20, C21 capacitor to ground in parallel with a 10 pF capacitor to ground positioned C6, C8, C20, C21 = 10 pF (Size 0402) as close to the device as possible. C1, C4, C5 RF Input Interface. The input channels are ac-coupled through C1. C1 = 3 pF (Size 0402), C4 = 10 pF (Size 0402), C4 and C5 provide bypassing for the center taps of the RF input baluns. C5 = 0.01 µF (Size 0402) T1, R1, C24, C25 IF Output Interface. T1 is a 1:1 impedance transformer that provides a T1 = TC1-1-13M+ (Mini-Circuits), single-ended IF output interface. Remove R1 for balanced output R1 = 0 Ω (Size 0402), operation. C24 and C25 block the dc bias at the IF ports. C24, C25 = 560 pF (Size 0402) C10, C12, R4 LO Interface. C10 and C12 provide ac coupling for the LO1_IN and C10, C12 = 22 pF (Size 0402), LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input R4 = 10 kΩ (Size 0402) for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is enabled when the LOSEL test point is logic low. LO2_IN is enabled when LOSEL is pulled to logic high. R21 PWDN Interface. R21 pulls the PWDN logic low and enables the device. R21 = 10 kΩ (Size 0402) The PWR_UP test point allows the PWDN interface to be exercised using the an external logic generator. Grounding the PWDN pin for nominal operation is allowed. Using the PWDN pin when supply voltages exceed 3.3 V is not allowed. C22, L3, R9, R14, Bias Control. R22 and R23 form a voltage divider to provide 3 V for logic C22 = 1 nF (Size 0402), L3 = 0 Ω (Size 0603), R22, R23, VGS0, control, bypassed to ground through C22. VGS0 and VGS1 jumpers R9 = 1.7 kΩ (Size 0402), R14 = 0 Ω (Size 0402), VGS1 provide programmability at the VGS0 and VGS1 pins. It is recommended to R22 = 10 kΩ (Size 0402), R23 = 15 kΩ (Size 0402), pull these two pins to ground for nominal operation. R9 sets the bias VGS0 = VGS1 = 3-pin shunt point for the internal LO buffers. R14 sets the bias point for the internal IF amplifier. Rev. B | Page 21 of 24

ADL5367 Data Sheet 08083-054 08083-056 Figure 50. Evaluation Board Top Layer Figure 52. Evaluation Board Power Plane, Internal Layer 2 08083-055 08083-057 Figure 51. Evaluation Board Ground Plane, Internal Layer 1 Figure 53. Evaluation Board Bottom Layer Rev. B | Page 22 of 24

Data Sheet ADL5367 OUTLINE DIMENSIONS 5.10 0.35 5.00 SQ 0.28 PIN 1 4.90 0.23 INDICATOR PIN 1 16 20 INDICATOR 0.65 BSC 15 1 EXPOSED 3.25 PAD 3.10 SQ 2.95 5 11 0.70 10 6 0.25 MIN TOP VIEW 0.60 BOTTOM VIEW 0.40 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WHHC. 111908-A Figure 54. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-20-9) Dimensions shown in millimeters ORDERING GUIDE Package Ordering Model1 Temperature Range Package Description Option Quantity ADL5367ACPZ-R7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 7” Tape and Reel CP-20-9 1,500 ADL5367-EVALZ Evaluation Board 1 1 Z = RoHS Compliant Part. Rev. B | Page 23 of 24

ADL5367 Data Sheet NOTES ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08083-0-3/16(B) Rev. B | Page 24 of 24

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