Low Voltage, 400 MHz, Quad 2:1 Mux with 3 ns Switching Time Data Sheet ADG774A FEATURES FUNCTIONAL BLOCK DIAGRAM Bandwidth: >400 MHz ADG774A Low insertion loss and on resistance: 2.2 Ω typical S1A D1 On resistance flatness: 0.3 Ω typical S1B Single 3 V/5 V supply operation S2A D2 Very low distortion: <0.3% S2B Low quiescent supply current: 1 nA typical S3A D3 Fast switching times S3B t = 6 ns S4A ON D4 tOFF = 3 ns S4B TTL-/CMOS-compatible 1 OF 2 Pb-free packages DECODER 1166--lleeaadd 3Q SmSmO P× 3 mm body LFCSP EN IN 02373-001 Figure 1. GENERAL DESCRIPTION The ADG774A is a monolithic CMOS device comprising four These switches conduct equally well in both directions when 2:1 multiplexer/demultiplexers with high impedance outputs. on. In the off condition, signal levels up to the supplies are The CMOS process provides low power dissipation yet offers blocked. The ADG774A switches exhibit break-before-make high switching speed and low on resistance. The on resistance switching action. variation is typically less than 0.5 Ω over the input signal range. PRODUCT HIGHLIGHTS The bandwidth of the ADG774A is typically 400 MHz and this, 1. Wide bandwidth data rates of >400 MHz. coupled with low distortion (typically 0.3%), makes the part 2. Ultralow power dissipation. suitable for switching of high speed data signals. 3. Low leakage over temperature. The on resistance profile is very flat over the full analog input 4. Break-before-make switching prevents channel shorting range ensuring excellent linearity and low distortion. CMOS when the switches are configured as a multiplexer. construction ensures ultralow power dissipation. 5. Crosstalk is typically −70 dB @ 10 MHz. 6. Off isolation is typically −65 dB @ 10 MHz. The ADG774A operates from a single 3.3 V/5 V supply and is 7. Available in compact 3 mm × 3 mm LFCSP. TTL logic-compatible. The control logic for each switch is shown in the truth table (see Table 5). Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2001–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADG774A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution...................................................................................5  Functional Block Diagram .............................................................. 1  Pin Configurations and Function Descriptions ............................6  General Description ......................................................................... 1  Typical Performance Characteristics ..............................................7  Product Highlights ........................................................................... 1  Test Circuits ........................................................................................9  Revision History ............................................................................... 2  Terminology .................................................................................... 11  Specifications ..................................................................................... 3  Application Circuits ....................................................................... 12  Single Supply ................................................................................. 3  Outline Dimensions ....................................................................... 13  Absolute Maximum Ratings ............................................................ 5  Ordering Guide .......................................................................... 13  REVISION HISTORY 4/16—Rev. B to Rev. C Changed CP-16-3 to CP-16-27 .................................... Throughout Changes to Figure 3 and Table 4 ..................................................... 6 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 8/06—Rev. A to Rev. B Updated Format .................................................................. Universal Added LFCSP Model .......................................................... Universal Added Lead-Free Models .................................................. Universal Changes to Table 3 ............................................................................ 5 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 4/03—Rev. 0 to Rev. A Changes to TPCs 9–11 ..................................................................... 5 Updated Outline Dimensions ......................................................... 8 7/01—Revision 0: Initial Version Rev. C | Page 2 of 14

Data Sheet ADG774A SPECIFICATIONS SINGLE SUPPLY V = 5 V ± 10%, GND = 0 V, all specifications T to T , unless otherwise noted.1 DD MIN MAX Table 1. B Version Parameter 25°C T to T Unit Test Conditions/Comments MIN MAX ANALOG SWITCH Analog Signal Range 0 to 2.5 V On Resistance, R 2.2 Ω typ V = 0 V to 1 V, I = −10 mA ON D S 3.5 4 Ω max On Resistance Match Between Channels, ∆R 0.15 Ω typ V = 0 V to 1 V, I = −10 mA ON D S 0.5 Ω max On Resistance Flatness, R 0.3 Ω typ V = 0 V to 1 V, I = −10 mA FLAT(ON) D S 0.6 Ω max LEAKAGE CURRENTS Source Off Leakage, I (OFF) ±0.001 nA typ V = 3 V/1 V, V = 1 V/3 V, see Figure 17 S D S ±0.1 ±0.25 nA max Drain Off Leakage, I (OFF) ±0.001 nA typ V = 3 V/1 V, V = 1 V/3 V, see Figure 17 D D S ±0.1 ±0.25 nA max Channel On Leakage, I , I (ON) ±0.001 nA typ V = V = 3 V/1 V, see Figure 18 D S D S ±0.1 ±0.25 nA max DIGITAL INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Current I or I 0.001 μA typ V = V or V INL INH IN INL INH ±0.1 μA max Digital Input Capacitance, C 3 pF typ IN DYNAMIC CHARACTERISTICS2 t , t (EN) 6 ns typ C = 35 pF, R = 50 Ω, V = 2 V, see Figure 22 ON ON L L S 12 ns max t , t (EN) 3 ns typ C = 35 pF, R = 50 Ω, V = 2 V, see Figure 22 OFF OFF L L S 6 ns max Break-Before-Make Time Delay, t 3 ns typ C = 35 pF, R = 50 Ω, V = V = 2 V, see Figure 23 D L L S1 S2 1 ns min Off Isolation −65 dB typ f = 10 MHz, R = 50 Ω, see Figure 20 L Channel-to-Channel Crosstalk −70 dB typ f = 10 MHz, R = 50 Ω, see Figure 21 L Bandwidth −3 dB 400 MHz typ R = 50 Ω, see Figure 19 L Distortion 0.3 % typ R = 100 Ω L Charge Injection 6 pC typ C = 1 nF, see Figure 24, V = 0 V L S C (OFF) 5 pF typ S C (OFF) 7.5 pF typ D C , C (ON) 12 pF typ D S POWER REQUIREMENTS V = 5.5 V DD Digital inputs = 0 V or V DD I 1 μA max DD 0.001 μA typ 1 Temperature range for B version is −40°C to +85°C. 2 Guaranteed by design, not subject to production test. Rev. C | Page 3 of 14

ADG774A Data Sheet V = 3 V ± 10%, GND = 0 V, all specifications T to T , unless otherwise noted.1 DD MIN MAX Table 2. B Version Parameter 25°C T to T Unit Test Conditions/Comments MIN MAX ANALOG SWITCH Analog Signal Range 0 to 1.5 V On Resistance, R 4 Ω typ V = 0 V to 1 V; I = −10 mA ON D S 6 7 Ω max On Resistance Match Between Channels, ∆RON 0.15 Ω typ VD = 0 V to 1 V, IS = −10 mA 0.5 Ω max On Resistance Flatness, R 1.5 Ω typ V = 0 V to 1 V, I = −10 mA FLAT(ON) D S 3 Ω max LEAKAGE CURRENTS Source Off Leakage, I (OFF) ±0.001 nA typ V = 2 V/1 V, V = 1 V/2 V, see Figure 17 S D S ±0.1 ±0.25 nA max Drain Off Leakage, I (OFF) ±0.001 nA typ V = 2 V/1 V, V = 1 V/2 V, see Figure 17 D D S ±0.1 ±0.25 nA max Channel On Leakage, I , I(ON) ±0.001 nA typ V = V = 2 V/1 V, see Figure 18 D S D S ±0.1 ±0.25 nA max DIGITAL INPUTS Input High Voltage, V 2.0 V min INH Input Low Voltage, V 0.4 V max INL Input Current I or I 0.001 μA typ V = V or V INL INH IN INL INH ±0.1 μA max Digital Input Capacitance, C 3 pF typ IN DYNAMIC CHARACTERISTICS2 t , t (EN) 7 ns typ C = 35 pF, R = 50 Ω, V = 1.5 V, see Figure 22 ON ON L L S 14 ns max t , t (EN) 4 ns typ C = 35 pF, R = 50 Ω, V = 1.5 V, see Figure 22 OFF OFF L L S 8 ns max Break-Before-Make Time Delay, t 3 ns typ C = 35 pF, R = 50 Ω, V = V = 1.5 V, see Figure 23 D L L S1 S2 1 ns min Off Isolation −65 dB typ f = 10 MHz, R = 50 Ω L Channel-to-Channel Crosstalk −70 dB typ f = 10 MHz, R = 50 Ω, see Figure 21 L Bandwidth −3 dB 400 MHz typ R = 50 Ω, see Figure 19 L Distortion 1.5 % typ R = 100 Ω L Charge Injection 4 pC typ C = 1 nF, see Figure 24, V = 0 V L S C (OFF) 5 pF typ S C (OFF) 7.5 pF typ D C , C (ON) 12 pF typ D S POWER REQUIREMENTS V = 3.3 V DD Digital inputs = 0 V or V DD I 1 μA max DD 0.001 μA typ 1 Temperature range for B version is −40°C to +85°C. 2 Guaranteed by design, not subject to production test. Rev. C | Page 4 of 14

Data Sheet ADG774A ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 3. stress rating only; functional operation of the product at these Parameters Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +6 V DD section of this specification is not implied. Operation beyond Analog, Digital Inputs1 −0.3 V to V + 0.3 V or 30 mA, DD the maximum operating conditions for extended periods may whichever occurs first affect product reliability. Continuous Current, S or D 100 mA Peak Current, S or D 300 mA (pulsed at 1 ms, ESD CAUTION 10% duty cycle max) Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Thermal Impedance, θ JA 16-Lead QSSOP 105.44°C/W2 16-Lead LFCSP (3 mm × 3 mm) 48.7°C/W2 Lead Temperature Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Reflow Soldering (Pb-free) Peak Temperature 260°C (+0°C/–5°C) Time at Peak Temperature 10 sec to 40 sec 1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. 2 Measured with the device soldered on a four-layer board. Rev. C | Page 5 of 14

ADG774A Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1SA NI VDD NE 6 5 4 3 IN 1 16 VDD 1 1 1 1 S1A 2 15 EN S1B 1 12 S4A S1B 3 14 S4A D1 2 ADG774A 11 S4B D1 4 TAODPG V7I7E4WA 13 S4B S2A 3 (NToOt Pto V SIEcWale) 10 D4 S2A 5 (Not to Scale) 12 D4 S2B 4 9 S3A S2B 6 11 S3A D2 7 10 S3B 5 6 7 8 2 D 3 B GND 8 9 D3 02373-002 N1 . O TTTHIEEEDS ETXOP GODNSDENGD. PADD M3SUST BE 02373-028 Figure 2. QSOP Pin Configuration Figure 3. LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. QSOP LFCSP Mnemonic Function 1 15 IN Logic Control Input. 2 16 S1A Source Terminal 1A. May be an input or output. 3 1 S1B Source Terminal 1B May be an input or output. 4 2 D1 Drain Terminal D1. May be an input or output. 5 3 S2A Source Terminal 2A. May be an input or output. 6 4 S2B Source Terminal 2B. May be an input or output. 7 5 D2 Drain Terminal D2. May be an input or output. 8 6 GND Ground (0 V) Reference. 9 7 D3 Drain Terminal D3. May be an input or output. 10 8 S3B Source Terminal 3B. May be an input or output. 11 9 S3A Source Terminal 3A. May be an input or output. 12 10 D4 Drain Terminal D4. May be an input or output. 13 11 S4B Source Terminal 4B. May be an input or output. 14 12 S4A Source Terminal 4A. May be an input or output. 15 13 EN Logic Control Input. When high, all switches are disabled. 16 14 V Most Positive Power Supply Potential. DD Not applicable 17 EPAD Exposed Pad. The exposed pad must be tied to GND. Table 5. Truth Table EN IN D1 D2 D3 D4 Function 1 X Hi-Z Hi-Z Hi-Z Hi-Z DISABLE 0 0 S1A S2A S3A S4A IN = 0 0 1 S1B S2B S3B S4B IN = 1 Rev. C | Page 6 of 14

Data Sheet ADG774A TYPICAL PERFORMANCE CHARACTERISTICS 20 20 TA = 25°C VDD = 3V 16 VDD = 5.0V 15 12 Ω) Ω) (N (N 10 RO VDD = 4.5V RO 8 +85°C +25°C 5 4 VDD = 5.5V –40°C 0 0 0 1 2 VS/VD (V) 3 4 5 02373-003 0 0.5 1.0 VS/1V.D5 (V) 2.0 2.5 3.0 02373-006 Figure 4. On Resistance as a Function of Drain (VD) or Source (VS) Voltage for Figure 7. On Resistance as a Function of Drain (VD) or Source (VS) Voltage for VDD = 5 V ± 10% Different Temperatures with 3 V Single Supplies 20 0.025 TA = 25°C VDD = 5.0V 0.020 VSS = 0V TEMP = 25°C 16 0.015 VD = VDD – VS 0.010 12 VDD = 3.0V nA) 0.005 ID (OFF) R (Ω)ON 8 URRENT (–0.0050 VDD = 2.7V C IS (OFF) IS, ID (ON) –0.010 4 –0.015 VDD = 3.3V –0.020 0 –0.025 0 0.5 1.0 VS/1V.D5 (V) 2.0 2.5 3.0 02373-004 VS 0 1 VS/V2D (V) 3 4 02373-007 Figure 5. On Resistance as a Function of Drain (VD) or Source (VS) Figure 8. Leakage Current as a Function of Drain (VD) or Source (VS) Voltage Voltage for VDD = 3 V ± 10% for VDD = 5 V 20 0.025 VDD = 5V VDD = 3.0V 0.020 VSS = 0V TEMP = 25°C 0.015 VD = VDD – VS 15 0.010 ID (OFF) nA) 0.005 R (Ω)ON 10 RRENT ( 0 +85°C CU–0.005 IS (OFF) IS, ID (ON) –0.010 5 +25°C –0.015 –40°C –0.020 0 –0.025 0 1 2 VS/VD (V) 3 4 5 02373-005 VS 0 0.5 1.0 VS/1V.D5 (V) 2.0 2.5 3.0 02373-008 Figure 6. On Resistance as a Function of Drain (VD) or Source (VS) Figure 9. Leakage Current as a Function of Drain (VD) or Source (VS) Voltage Voltage for Different Temperatures with 5 V Single Supplies for VDD = 3 V Rev. C | Page 7 of 14

ADG774A Data Sheet 0.05 0 VDD = 5.0V 0.04 VSS = 0V TEMP = 25°C 0.03 VD = 3V/1V –20 nA) 00..0021 VS = 1IVD/ 3(OVFF) IS, ID (ON) N (dB) –40 ENT ( 0 ATIO R U R N CU–0.01 IS (OFF) TE –60 T –0.02 A –0.03 –80 –0.04 –0.05 –100 5 15 25 T3E5MPERA45TURE (5°5C) 65 75 85 02373-009 0.01 0.1 FRE1QUENCY (M10Hz) 100 1000 02373-012 Figure 10. Leakage Current as a Function of Temperature, VDD = 5 V Figure 13. Crosstalk vs. Frequency 0.05 0 VDD = 3.0V 0.04 VSS = 0V TEMP = 25°C 0.03 VD = 2V/1V VS = 1V/2V IS, ID (ON) nA) 00..0021 IS (OFF) E (dB) –5 T ( NS N 0 O URRE–0.01 RESP C–0.02 ID (OFF) ON –10 –0.03 –0.04 –0.05 –15 5 15 25 T3E5MPERA45TURE (5°5C) 65 75 85 02373-010 0.01 0.1 FRE1QUENCY (M10Hz) 100 1000 02373-013 Figure 11. Leakage Current as a Function of Temperature, VDD = 3 V Figure 14. Bandwidth 0 0 –1 –20 –2 B) d ON ( –40 C) –3 VDD = 3V UATI (pNJ N QI –4 TE –60 VDD = 5V T A –5 –80 –6 –100 –7 0.01 0.1 FRE1QUENCY (M10Hz) 100 1000 02373-011 0 0.5 1V.0OLTAGE (V1.)5 2.0 2.5 02373-014 Figure 12. Off Isolation vs. Frequency Figure 15. Charge Injection vs. Source Voltage Rev. C | Page 8 of 14

Data Sheet ADG774A TEST CIRCUITS VDD 0.1µF IDS ADG774A NETWORK ANALYZER V1 S1A 50Ω S D IN VS VS RON = V1/IDS 02373-019 VIN D1 VOUT 50Ω EN GND 02373-024 Figure 16. On Resistance Figure 19. Bandwidth VDD 0.1µF ADG774A NETWORK ANALYZER IS (OFF) ID (OFF) S D A A S1A 50Ω 50Ω VS VD 02373-020 IN VS VIN D1 VOUT 50Ω EN GND 02373-025 Figure 17. Off Leakage Figure 20. Off Isolation VDD 0.1µF NETWORK ADG774A ANALYZER S1A 50Ω ID (ON) NC S D A S2A VS VOUT NC = NO CONNECT VD 02373-021 IN 5R0LΩ D2 VIN D1 EN GND 50Ω 02373-026 Figure 18. On Leakage Figure 21. Channel-to-Channel Crosstalk Rev. C | Page 9 of 14

ADG774A Data Sheet 5V 0.1µF 3V VIN VDD 50% 50% S D VOUT 90% 90% VS IN 1R0L0Ω 3C5LpF VOUT tON tOFF EN GND 02373-022 Figure 22. Switching Times 5V 0.1µF VDD 3V S1A D1 VOUT VIN 50% 50% S1B 0V VS VS 1R0L0Ω 3C5LpF VOUTVS 80% 80% DECODER EN tD tD GND 02373-023 Figure 23. Break-Before-Make Time Delay 5V VDD ADG774A RS S1A VS SS21AB 1CnLF D1 VOUT VIN3V D2 VOUT S2B CL S3A 1nF VOUT ∆VOUT S3B CL D3 VOUT QINJ= CL ×∆VOUT 1nF S4A D4 VOUT S4B CL 1nF 1 OF 2 DECODER EN IN 02373-027 Figure 24. Charge Injection Rev. C | Page 10 of 14

Data Sheet ADG774A TERMINOLOGY V V (V) DD D S Most positive power supply potential. Analog voltage on the D and S terminals. GND C (OFF) S Ground (0 V) reference. Off switch source capacitance. S C (OFF) D Source terminal. May be an input or output. Off switch drain capacitance. D C , C (ON) D S Drain terminal. May be an input or output. On switch capacitance. IN t ON Logic control input. Delay between applying the digital control input and the output switching on. See Figure 22. EN Logic control input. tOFF Delay between applying the digital control input and the output R ON switching off. Ohmic resistance between D and S. t ∆R D ON Off time or on time measured between the 80% points of both On resistance match between any two channels, that is, switches when switching from one address state to another. See R max − R min. ON ON Figure 23. R FLAT(ON) Crosstalk Flatness is defined as the difference between the maximum and A measure of unwanted signal that is coupled through from one minimum value of on resistance as measured over the specified channel to another because of parasitic capacitance. analog signal range. Off Isolation I (OFF) S A measure of unwanted signal coupling through an off switch. Source leakage current with the switch off. Bandwidth I (OFF) D Frequency response of the switch in the on state measured at Drain leakage current with the switch off. 3 dB down. I , I (ON) D S Distortion Channel leakage current with the switch on. R /R FLAT(ON) L Rev. C | Page 11 of 14

ADG774A Data Sheet APPLICATION CIRCUITS 10 BASE Tx+ Tx1 10 BASE Tx– ADG774A 100 BASE Tx+ Tx2 100 BASE Tx– RJ45 10 BASE Tx+ Rx1 10 BASE Tx– TRANSFORMER 100 BASE Tx+ Rx2 100 BASE Tx– 10 BASE Tx 100 BASE Tx 02373-015 Figure 25. Full Duplex Transceiver Tx1 120Ω 100Ω Rx1 02373-016 02373-017 02373-018 Figure 26. Loop Back Figure 27. Line Termination Figure 28. Line Clamp Rev. C | Page 12 of 14

Data Sheet ADG774A OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 1 8 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.020 (0.51) 0.065 (1.65) 0.069 (1.75) 0.006 (0.15) 0.010 (0.25) 0.049 (1.25) 0.053 (1.35) 0.010 (0.25) CO0P.0L0A4 N(0A.1R0I)TY 0.02B5S (C0.64) 0.012 (0.30) SPELAATNIENG 80°° 0.050 (1.27) 0R.E0F41 (1.04) 0.004 (0.10) 0.016 (0.41) 0.008 (0.20) COMPLIANTTO JEDEC STANDARDS MO-137-AB C(RINOEFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO IPFNRFCO HINPECRSHI;A METEQIL UFLIOIVMRAE LUTEESNRET DISNI M FDOEERNSSIGIONN.S 09-12-2014-A Figure 29. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) 3.10 0.30 3.00 SQ 0.25 PIN 1 2.90 0.20 INDICATOR PIN 1 0.50 13 16 INDICATOR BSC 12 1 EXPOSED 1.65 PAD 1.50 SQ 1.45 9 4 0.50 8 5 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO 0.70 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6. 01-26-2012-A Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-27) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADG774ABRQ-REEL7 −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 ADG774ABRQZ −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 ADG774ABRQZ-REEL −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 ADG774ABRQZ-REEL7 −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 ADG774ABCPZ-REEL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-27 ADG774ABCPZ-R2 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-27 1 Z = RoHS Compliant Part. Rev. C | Page 13 of 14

ADG774A Data Sheet NOTES ©2001–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02373-0-4/16(C) Rev. C | Page 14 of 14