a (cid:1) CMOS, 2.5 Low Voltage, Triple/Quad SPDT Switches ADG733/ADG734 FEATURES FUNCTIONAL BLOCK DIAGRAMS 1.8 V to 5.5 V Single Supply (cid:2)2.5 V Dual Supply 2.5 (cid:1) On Resistance S1B ADG733 S1A S4A 0.5 (cid:1) On Resistance Flatness D1 D1 D2 100 pA Leakage Currents S1A S3A S1B S4B 19 ns Switching Times D3 IN1 IN4 S3B Triple SPDT: ADG733 S2A ADG734 Quad SPDT: ADG734 Small TSSOP and QSOP Packages D2 IN2 IN3 S2B Low Power Consumption S2B S3B TTL/CMOS Compatible Inputs LOGIC D2 D3 S2A S3A APPLICATIONS Data Acquisition Systems A0 A1 A2 EN Communication Systems SWITCHES SHOWN FOR A “1” INPUT LOGIC Relay Replacement Audio and Video Switching Battery Powered Systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG733 and ADG734 are low voltage, CMOS devices 1. Single/Dual Supply Operation. The ADG733 and ADG734 are comprising three independently selectable SPDT (single pole, fully specified and guaranteed with 3 V and 5 V single supply double throw) switches and four independently selectable SPDT rails and ±2.5 V dual supply rails. switches respectively. 2. Low On Resistance (2.5Ω typical) Low power consumption and operating supply range of 1.8 V to 3. Low Power Consumption (<0.01 µW) 5.5 V and dual ±2.5 V make the ADG733 and ADG734 ideal for 4. Guaranteed Break-Before-Make Switching Action battery powered, portable instruments. All channels exhibit break-before-make switching action preventing momentary shorting when switching channels. An EN input on the ADG733 is used to enable or disable the device. When disabled, all channels are switched OFF. These 2–1 multiplexers/SPDT switches are designed on an enhanced submicron process that provides low power dissipation yet gives high switching speed, very low on resistance, high signal bandwidths, and low leakage currents. On resistance is in the region of a few ohms, is closely matched between switches, and is very flat over the full signal range. These parts can operate equally well in either direction and have an input signal range that extends to the supplies. The ADG733 is available in small TSSOP and QSOP packages, while the ADG734 is available in a small TSSOP package. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 under any patent or patent rights of Analog Devices. www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2014

ADG733/ADG734–SPECIFICATIONS1 (V = 5 V (cid:2) 10%, V = 0 V, GND = 0 V, unless otherwise noted.) DD SS B Version –40(cid:3)C Parameter +25(cid:3)C to +85(cid:3)C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V V DD On Resistance (R ) 2.5 Ω typ V = 0 V to V , I = 10 mA; ON S DD DS 4.5 5.0 Ω max Test Circuit 1 On Resistance Match between 0.1 Ω typ V = 0 V to V , I = 10 mA S DD DS Channels (∆R ) 0.4 Ω max ON On Resistance Flatness (R ) 0.5 Ω typ V = 0 V to V , I = 10 mA FLAT(ON) S DD DS 1.2 Ω max LEAKAGE CURRENTS V = 5.5 V DD Source OFF Leakage I (OFF) ±0.01 nA typ V = 4.5 V/1 V, V = 1 V/4.5 V; S D S ±0.1 ±0.3 nA max Test Circuit 2 Channel ON Leakage I , I (ON) ±0.01 nA typ V = V = 1 V, or 4.5 V; D S D S ±0.1 ±0.5 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Current I or I 0.005 µA typ V = V or V INL INH IN INL INH ±0.1 µA max C , Digital Input Capacitance 4 pF typ IN DYNAMIC CHARACTERISTICS2 t 19 ns typ R = 300 Ω, C = 35 pF; ON L L 34 ns max V = 3 V, Test Circuit 4 S t 7 ns typ R = 300 Ω, C = 35 pF; OFF L L 12 ns max V = 3 V, Test Circuit 4 S ADG733 t (EN) 20 ns typ R = 300 Ω, C = 35 pF; ON L L 40 ns max V = 3 V, Test Circuit 5 S t (EN) 7 ns typ R = 300 Ω, C = 35 pF; OFF L L 12 ns max V = 3 V, Test Circuit 5 S Break-Before-Make Time Delay, t 13 ns typ R = 300 Ω, C = 35 pF; D L L 1 ns min V = 3 V, Test Circuit 6 S Charge Injection ±3 pC typ V = 2 V, R = 0 Ω, C = 1 nF; S S L Test Circuit 7 Off Isolation –72 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; L L Test Circuit 8 Channel-to-Channel Crosstalk –67 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; L L Test Circuit 9 –3 dB Bandwidth 160 MHz typ R = 50 Ω, C = 5 pF, Test Circuit 10 L L C (OFF) 11 pF typ f = 1 MHz S C , C (ON) 34 pF typ f = 1 MHz D S POWER REQUIREMENTS V = 5.5 V DD I 0.001 µA typ Digital Inputs = 0 V or 5.5 V DD 1.0 µA max NOTES 1Temperature range is as follows: B Version: –40°C to +85°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. B

ADG733/ADG734 SPECIFICATIONS1 (V = 3 V (cid:2) 10%, V = 0 V, GND = 0 V, unless otherwise noted.) DD SS B Version –40(cid:3)C Parameter +25(cid:3)C to +85(cid:3)C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V V DD On Resistance (R ) 6 Ω typ V = 0 V to V , I = 10 mA; ON S DD DS 11 12 Ω max Test Circuit 1 On Resistance Match between 0.1 Ω typ V = 0 V to V , I = 10 mA S DD DS Channels (∆R ) 0.4 Ω max ON On Resistance Flatness (R ) 3 Ω typ V = 0 V to V , I = 10 mA FLAT(ON) S DD DS LEAKAGE CURRENTS V = 3.3 V DD Source OFF Leakage I (OFF) ±0.01 nA typ V = 3 V/1 V, V = 1 V/3 V; S S D ±0.1 ±0.3 nA max Test Circuit 2 Channel ON Leakage I , I (ON) ±0.01 nA typ V = V = 1 V or 3 V; D S S D ±0.1 ±0.5 nA max Test Circuit 3 DIGITAL INPUTS Input High Voltage, V 2.0 V min INH Input Low Voltage, V 0.8 V max INL Input Current I or I 0.005 µA typ V = V or V INL INH IN INL INH ±0.1 µA max C , Digital Input Capacitance 4 pF typ IN DYNAMIC CHARACTERISTICS2 t 28 ns typ R = 300 Ω, C = 35 pF; ON L L 55 ns max V = 2 V, Test Circuit 4 S t 9 ns typ R = 300 Ω, C = 35 pF; OFF L L 16 ns max V = 2 V, Test Circuit 4 S ADG733 t (EN) 29 ns typ R = 300 Ω, C = 35 pF; ON L L 60 ns max V = 2 V, Test Circuit 5 S t (EN) 9 ns typ R = 300 Ω, C = 35 pF; OFF L L 16 ns max V = 2 V, Test Circuit 5 S Break-Before-Make Time Delay, t 22 ns typ R = 300 Ω, C = 35 pF; D L L 1 ns min V = 2 V, Test Circuit 6 S Charge Injection ±3 pC typ V = 1 V, R = 0 Ω, C = 1 nF; S S L Test Circuit 7 Off Isolation –72 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; L L Test Circuit 8 Channel-to-Channel Crosstalk –67 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; L L Test Circuit 9 –3 dB Bandwidth 160 MHz typ R = 50 Ω, C = 5 pF, Test Circuit 10 L L C (OFF) 11 pF typ f = 1 MHz S C , C (ON) 34 pF typ f = 1 MHz D S POWER REQUIREMENTS V = 3.3 V DD I 0.001 µA typ Digital Inputs = 0 V or 3.3 V DD 1.0 µA max NOTES 1Temperature ranges are as follows: B Version: –40°C to +85°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. B –3–

ADG733/ADG734–SPECIFICATIONS1 DUAL SUPPLY (V = +2.5 V (cid:2) 10%, V = –2.5 V (cid:2) 10%, GND = 0 V, unless otherwise noted.) DD SS B Version –40(cid:3)C Parameter +25(cid:3)C to +85(cid:3)C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V SS DD On Resistance (R ) 2.5 Ω typ V = V to V , I = 10 mA; ON S SS DD DS 4.5 5.0 Ω max Test Circuit 1 On Resistance Match between 0.1 Ω typ V = V to V , I = 10 mA S SS DD DS Channels (∆R ) 0.4 Ω max ON On Resistance Flatness (R ) 0.5 Ω typ V = V to V , I = 10 mA FLAT(ON) S SS DD DS 1.2 Ω max LEAKAGE CURRENTS V = +2.75 V, V = –2.75 V DD SS Source OFF Leakage I (OFF) ±0.01 nA typ V = +2.25 V/–1.25 V, V = –1.25 V/+2.25 V; S S D ±0.1 ±0.3 nA max Test Circuit 2 Channel ON Leakage I , I (ON) ±0.01 nA typ V = V = +2.25 V/–1.25 V, Test Circuit 3 D S S D ±0.1 ±0.5 nA max DIGITAL INPUTS Input High Voltage, V 1.7 V min INH Input Low Voltage, V 0.7 V max INL Input Current I or I 0.005 µA typ V = V or V INL INH IN INL INH ±0.1 µA max C , Digital Input Capacitance 4 pF typ IN DYNAMIC CHARACTERISTICS2 t 21 ns typ R = 300 Ω, C = 35 pF; ON L L 35 ns max V = 1.5 V, Test Circuit 4 S t 10 ns typ R = 300 Ω, C = 35 pF; OFF L L 16 ns max V = 1.5 V, Test Circuit 4 S ADG733 t (EN) 21 ns typ R = 300 Ω, C = 35 pF; ON L L 40 ns max V = 1.5 V, Test Circuit 5 S t (EN) 10 ns typ R = 300 Ω, C = 35 pF; OFF L L 16 ns max V = 1.5 V, Test Circuit 5 S Break-Before-Make Time Delay, t 13 ns typ R = 300 Ω, C = 35 pF; D L L 1 ns min V = 1.5 V, Test Circuit 6 S Charge Injection ±5 pC typ V = 0 V, R = 0 Ω, C = 1 nF; S S L Test Circuit 7 Off Isolation –72 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; L L Test Circuit 8 Channel-to-Channel Crosstalk –67 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; L L Test Circuit 9 –3 dB Bandwidth 200 MHz typ R = 50 Ω, C = 5 pF, Test Circuit 10 L L C (OFF) 11 pF typ f = 1 MHz S C , C (ON) 34 pF typ f = 1 MHz D S POWER REQUIREMENTS V = 2.75 V DD I 0.001 µA typ Digital Inputs = 0 V or 2.75 V DD 1.0 µA max I 0.001 µA typ V = –2.75 V SS SS 1.0 µA max Digital Inputs = 0 V or 2.75 V NOTES 1Temperature range is as follows: B Version: –40°C to +85°C. 2Guaranteed by design, not subject to production test. Specifications subject to change without notice. –4– REV. B

ADG733/ADG734 ABSOLUTE MAXIMUM RATINGS1 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C (TA = 25°C, unless otherwise noted.) 16-Lead TSSOP, θJA Thermal Impedance . . . . . . . 150.4°C/W VVVDDDD t ttooo G GVNSNSDD .. ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ..+ . 0–. .0.3 .. 3 V. V .t o. t .o– . 3+ .775 VVV L2106e--aLLdee Taadde mQTpSSeSOrOaPtPu, ,rθ eJθA,J AST oThlhdereemrrminalga l I (mI1m0p pesdeedacna)nce c.e .. ... ... ... ... ... ... .. 1.. 4.. 9 .1 ..94 733°°0CC0//°WWC ASnSalog Inputs2 . . . . . . . . . . . . . . V – 0.3 V to V + 0.3 V or IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C SS DD 30 mA, Whichever Occurs First NOTES Digital Inputs2 . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V or 1Stresses above those listed under Absolute Maximum Ratings may cause perma- DD 30 mA, Whichever Occurs First nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA sections of this specification is not implied. Exposure to absolute maximum rating (Pulsed at 1 ms, 10% Duty Cycle max) conditions for extended periods may affect device reliability. Only one absolute Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA maximum rating may be applied at any one time. Operating Temperature Range 2Overvoltages at A, EN, IN, S, or D will be clamped by internal diodes. Current Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C should be limited to the maximum ratings given. Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG733/ADG734 feature proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS TSSOP/QSOP TSSOP IN1 1 20 IN4 S2B 1 16 VDD S1A 2 19 S4A S2A 2 15 D2 D1 3 18 D4 S3B 3 ADG733 14 D1 S1B 4 ADG734 17 S4B D3 4 TOP VIEW 13 S1B VSS 5 TOP VIEW 16 VDD (Not to Scale) (Not to Scale) S3A 5 12 S1A GND 6 15 NC EN 6 11 A0 S2B 7 14 S3B VSS 7 10 A1 D2 8 13 D3 GND 8 9 A2 S2A 9 12 S3A IN210 11 IN3 NC = NO CONNECT REV. B –5–

ADG733/ADG734 Table I. ADG733 Truth Table Table II. ADG734 Truth Table A2 A1 A0 EN ON Switch Logic Switch A Switch B X X X 1 None 0 OFF ON 0 0 0 0 D1-S1A, D2-S2A, D3-S3A 1 ON OFF 0 0 1 0 D1-S1B, D2-S2A, D3-S3A 0 1 0 0 D1-S1A, D2-S2B, D3-S3A 0 1 1 0 D1-S1B, D2-S2B, D3-S3A 1 0 0 0 D1-S1A, D2-S2A, D3-S3B 1 0 1 0 D1-S1B, D2-S2A, D3-S3B 1 1 0 0 D1-S1A, D2-S2B, D3-S3B 1 1 1 0 D1-S1B, D2-S2B, D3-S3B X = Don’t Care. TERMINOLOGY V Most Positive Power Supply Potential DD V Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to SS ground close to the device. I Positive Supply Current DD I Negative Supply Current SS GND Ground (0 V) Reference S Source Terminal. May be an input or output. D Drain Terminal. May be an input or output. A Logic Control Input X EN Active low device enable V (V ) Analog Voltage on Terminals D and S D S R Ohmic Resistance between D and S ON ∆R On Resistance Match between any Two Channels (i.e., R max and R min) ON ON ON R Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over FLAT(ON) the specified analog signal range. I (OFF) Source Leakage Current with the Switch “OFF” S I , I (ON) Channel Leakage Current with the Switch “ON” D S V Maximum Input Voltage for Logic “0” INL V Minimum Input Voltage for Logic “1” INH I (I ) Input Current of the Digital Input INL INH C (OFF) “OFF” Switch Source Capacitance. Measured with reference to ground. S C , C (ON) “ON” Switch Capacitance. Measured with reference to ground. D S C Digital Input Capacitance IN t Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch “ON” Condition ON t Delay Time Measured between the 50% and 90% Points of the Digital Input and the Switch “OFF” Condition OFF t (EN) Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “ON” Condition ON t (EN) Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “OFF” Condition OFF t “OFF” Time Measured between the 80% Points of Both Switches when Switching from One Address State to OPEN Another Charge A Measure of the Glitch Impulse Transferred Injection from the Digital Input to the Analog Output during Switching Off Isolation A Measure of Unwanted Signal Coupling through an “OFF” Switch. Crosstalk A Measure of Unwanted Signal that Is Coupled through from One Channel to Another as a Result of Para- sitic Capacitance On Response The Frequency Response of the “ON” Switch Insertion Loss The Loss Due to the On Resistance of the switch –6– REV. B

Typical Performance Characteristics–ADG733/ADG734 8 8 8 TA = 25(cid:3)C TA = 25(cid:3)C VDD = 5V 7 VSS = 0V 7 7 VSS = 0V (cid:1) 6 VDD = 2.7V (cid:1) 6 (cid:1) 6 CE – 5 VDD = 3.3V CE – 5 CE – 5 RESISTAN 43 VDD = 4.5V RESISTAN 43 VVDSDS == –+22..55VV RESISTAN43 +85(cid:3)C +25(cid:3)C N N N O 2 O 2 O2 VDD = 5.5V –40(cid:3)C 1 1 1 0 0 0 0 1 2 3 4 5 –3 –2 –1 0 1 2 3 0 1 2 3 4 5 VD, VS, DRAIN OR SOURCE VOLTAGE – V VD, VS, DRAIN OR SOURCE VOLTAGE – V VD, OR VS DRAIN OR SOURCE VOLTAGE – V TPC 1. On Resistance as a Function of TPC 2. On Resistance as a Function of TPC 3. On Resistance as a Function of VD (VS) for Single Supply VD (VS) for Dual Supply VD (VS) for Different Temperatures, Single Supply 8 8 0.1 VDD = 3V VDD = +2.5V VDD = 5V 7 VSS = 0V 7 VSS = –2.5V 0.05 TVAS S= = 2 5G(cid:3)NCD (cid:1)ON RESISTANCE – 65432 –40(cid:3)C ++2855(cid:3)(cid:3)CC (cid:1)ON RESISTANCE – 46532 +85(cid:3)C +25(cid:3)C CURRENT – nA–0.050 ISIS (,O IDF F(O)N) –40(cid:3)C –0.1 1 1 0 0 –0.15 0 0.5 1.0 1.5 2.0 2.5 3.0 –3 –2 –1 0 1 2 3 0 1 2 3 4 5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V VD, VS, DRAIN OR SOURCE VOLTAGE – V VS, (VD = VDD – VS) – V TPC 4. On Resistance as a Function of TPC 5. On Resistance as a Function of TPC 6. Leakage Currents as a VD (VS) for Different Temperatures, VD (VS) for Different Temperatures, Function of VD (VS) Single Supply Dual Supply 0.10 0.15 0.25 VDD = 3V VDD = +2.5V VDD = +2.5V VDD = 5V 00..0086 TVAS S= = 2 5G(cid:3)NCD 0.10 TVAS S= = 2 5–(cid:3)2C.5V 0.20 VVSDS = = + –22.2.55VV/–1.25V VVSDS = = 4 G.5NVD/1.0V VS = –1.25V/+2.25V VS = 1.0V/4.5V 0.04 0.15 A A 0.05 A ENT – n 0.020 IS, ID (ON) ENT – n 0 IS, ID (ON), VD = VS ENT – n 0.10 URR–0.02 URR URR 0.05 IS, ID (ON) C C–0.05 C –0.04 0 –0.06 IS (OFF) –0.10 IS (OFF) –0.05 IS (OFF) –0.08 –0.10 –0.15 –0.10 0 0.5 1.0 1.5 2.0 2.5 3.0 –3 –2 –1 0 1 2 3 5 20 35 50 65 80 VS, (VD = VDD – VS) – V VS, (VD = VDD –VS) – V TEMPERATURE – (cid:3)C TPC 7. Leakage Currents as a TPC 8. Leakage Currents as a TPC 9. Leakage Currents as a Function of VD (VS) Function of VD (VS) Function of Temperature REV. B –7–

ADG733/ADG734 0 0.25 40 VDD = 3V VSS = GND 00..2105 VVVSDSS == = 12 GV.7/NV2D./71VV 3350 tON, VDD = 3V dB ––42 VTAD D= =2 55(cid:3)VC nA 25 E– –6 CURRENT – 00..1005 IS, ID (ON) TIME – ns 2105 tON, VDD = 5V NRESPONS ––180 0 10 tOFF, VDD = 3V O–12 –0.05 5 tOFF, VDD = 5V –14 IS (OFF) –0.10 0 –16 5 20 35 50 65 80 –20 0 20 40 60 80 10k 100k 1M 10M 100M TEMPERATURE – (cid:3)C TEMPERATURE – (cid:3)C FREQUENCY – HZ TPC 10.Leakage Currents as a TPC 11.t /t Times vs. TPC 12.On Response vs. Frequency ON OFF Function of Temperature Temperature 10m TA = 25(cid:3)C 0 VTAD D= =2 55(cid:3)VC 0 VTAD D= =2 55(cid:3)VC 1m –20 –20 VDD = 5V CURRENT – A101001(cid:4)(cid:4)(cid:4) VVDSSD == –+22..55VV VSS = GND ATTENUATION – dB –––468000 ATTENUATION – dB –––468000 VSS = 3V 100n VDD = GND –100 –100 10n –120 –120 0.1 1 10 100 1000 10000 30k 100k 1M 10M 100M 30k 100k 1M 10M 100M FREQUENCY – kHz FREQUENCY – kHz FREQUENCY – kHz TPC 13.Input Current, I vs. TPC 14.Off Isolation vs. Frequency TPC 15.Crosstalk vs. Frequency DD Switching Frequency 30 VDD = +2.5V TA = 25(cid:3)C VSS = –2.5V 20 VDD = 3V C VSS = GND p – 10 NJ QI 0 VDD = 5V VSS = GND –10 –3 –2 –1 0 1 2 3 4 5 VOLTAGE – V TPC 16.Charge Injection vs. Source Voltage –8– REV. B

ADG733/ADG734 Test Circuits IDS V1 S D IS (OAFF) S D NC S D ID (AON) VS VS VD VD RON = V1/IDS Test Circuit 1.On Resistance Test Circuit 2.IS (OFF) Test Circuit 3.ID (ON) VDD 0.1(cid:4)F VDD ADDRESS S1B DRIVE 50% 50% VS1B D1 VOUT S1A VS1A RL CL VS1A 90% 90% 300(cid:1) 35pF VOUT IN/EN VS1B GND VSS tON tOFF 0.1(cid:4)F VSS Test Circuit 4.Switching Times, t , t ON OFF VDD VSS 0.1(cid:4)F 3V VDD VSS ENABLE 50% 50% A2 S1A VS DRIVE (VIN) A1 S1B 0V A0 ADG733 tOFF(EN) EN D1 VO VO 0.9V0 0.9V0 VIN 50(cid:1) GND R30L0(cid:1) C35LpF OUTPUT 0V tON(EN) Test Circuit 5.Enable Delay, t (EN), t (EN) ON OFF VDD 0.1(cid:4)F 3V VDD ADDRESS ADDRESS* SA VS VIN 50(cid:1) SB 0V ADG733/ ADG734 VS D1 VOUT GND VSS R30L0(cid:1) 3C5LpF VOUT 80% 80% 0.1(cid:4)F tOPEN VSS *A0, A1, A2 FOR ADG733, IN1-4 FOR ADG734 Test Circuit 6.Break-Before-Make Delay, t OPEN REV. B –9–

ADG733/ADG734 VDD VSS VDD VSS 3V ADG733/ LOGIC ADG734 INPUT (VIN) RS S D 0V VOUT VS EN* C1nLF VOUT VIN GND VOUT QINJ = CL (cid:5) VOUT * IN1–4 FOR ADG734 Test Circuit 7.Charge Injection VDD VSS VDD VSS 0.1(cid:4)F 0.1(cid:4)F 0.1(cid:4)F 0.1(cid:4)F NETWORK NETWORK VDD VSS ANALYZER VDD VSS ANALYZER S 50(cid:1) S 50(cid:1) IN 50(cid:1) VS IN VS D D VIN RL VOUT VIN RL VOUT 50(cid:1) 50(cid:1) GND GND OFF ISOLATION = 20 LOGVVOSUT INSERTION LOSS = 20 LOG VOVUOTU WT IWTHITOHU STW SIWTCITHCH Test Circuit 8.Off Isolation Test Circuit 10.Bandwidth VDD VSS 0.1(cid:4)F 0.1(cid:4)F NETWORK ANALYZER VDD VSS VOUT RL SA 50(cid:1) SB D R 50(cid:1) 50(cid:1) IN VS GND CHANNEL-TO-CHANNEL CROSSTALK = 20 LOGVVOSUT Test Circuit 9.Channel-to-Channel Crosstalk –10– REV. B

Data Sheet ADG733/ADG734 OUTLINE DIMENSIONS 0.197(5.00) 0.193(4.90) 0.189(4.80) 16 9 0.158(4.01) 0.154(3.91) 0.150(3.81) 0.244(6.20) 1 0.236(5.99) 8 0.228(5.79) 0.010(0.25) 0.020(0.51) 0.065(1.65) 0.069(1.75) 0.006(0.15) 0.010(0.25) 0.049(1.25) 0.053(1.35) 0.010(0.25) CO0P.0L0A4N(0A.1R0I)TY 0.02B5S(C0.64) 0.012(0.30) SPELAATNIENG 80°° 0.050(1.27) 0R.E04F1(1.04) 0.004(0.10) 0.016(0.41) 0.008(0.20) COMPLIANTTOJEDECSTANDARDSMO-137-AB C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POIPNFRFCOHINPECRSHI;AMTEEQILUFLOIIVMRAELUTEESNRETDISNIMFDOEERNSSIGIONN.S 01-28-2008-A Figure 11. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 0.65 0.19 SEATING 0° 0.45 BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 12. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters REV. B --11--

ADG733/ADG734 Data Sheet 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 0.15 1.20 MAX 0.20 0.05 0.09 0.75 0.30 8° 0.60 COPLANARITY 0.19 SEATING 0° 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 13. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADG733BRQZ −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 ADG733BRQZ-REEL −40°C to +85°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 ADG733BRU-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG733BRUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG733BRUZ-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG733BRUZ-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG734BRU −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 ADG734BRU-REEL −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 ADG734BRUZ −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 ADG734BRUZ-REEL −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 ADG734BRUZ-REEL7 −40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 Z = RoHS Compliant Part. REVISION HISTORY 4/14—Rev. A to Rev. B Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 12 11/02—Data Sheet changed from REV. 0 to REV. A. Changes to FEATURES ................................................................... 1 Changes to PRODUCT HIGHLIGHTS ........................................ 1 Changes to SPECIFICATIONS ...................................................... 2 Changes to ABSOLUTE MAXIMUM RATINGS Note 2 ........... 5 Changes to TERMINOLOGY table ............................................... 6 Replaced TPCs 2, 5, 8, and 9 ........................................................... 7 Edits to TPCs 6 and 7 ....................................................................... 7 Replaced TPC 12............................................................................... 8 Edits to TPCs 13 and 16 ................................................................... 8 Replaced Test Circuits 8 and 9 ...................................................... 10 Added Test Circuit 10 .................................................................... 10 Updated OUTLINE DIMENSIONS ............................................ 11 ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01602-0-4/14(B) --12-- REV. B

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADG733BRUZ ADG733BRUZ-REEL ADG733BRUZ-REEL7 ADG733BRU-REEL7 ADG734BRU ADG734BRUZ ADG733BRQZ ADG734BRUZ-REEL ADG734BRU-REEL ADG733BRQZ-REEL ADG734BRUZ-REEL7