LC2MOS 8-/16-Channel High Performance Analog Multiplexers ADG406/ADG407/ADG426 FEATURES FUNCTIONAL BLOCK DIAGRAMS 44 V supply maximum ratings ADG406 V to V analog signal range SS DD S1 Low on resistance (80 Ω maximum) Low power Fast switching D t < 160 ns ON t < 150 ns OFF Break-before-make switching action S16 APPLICATIONS 1 OF 16 DECODER Audio and video routing ADuattao macaqtuici stietsiot ne qsuysiptemmesn t A0 A1 A2 A3EN 00026-001 Battery powered systems Figure 1. Sample hold systems Communication systems ADG407 Avionics S1A DA S8A PRODUCT HIGHLIGHTS 1. Extended Signal Range. 2. The ADG406/ADG407/ADG426 are fabricated on an S1B enhanced LC2MOS process giving an increased signal DB S8B range which extends to the supply rails. 3. Low Power Dissipation. 1 OF 8 DECODER 4. Low R . ON 56.. SSiinnggllee /SDuupapll yS uOpppelyr aOtiponer. ation. A0 A1 A2 EN 00026-002 7. For applications where the analog signal is unipolar, the Figure 2. ADG406/ADG407/ADG426 can be operated from a single rail power supply. The parts are fully specified with a single ADG426 +12 V power supply and remain functional with single S1 supplies as low as +5 V. D S16 DECODER/ WR LATCHES A0 A1 A2 A3 ENRS 00026-003 Figure 3. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1994–2010 Analog Devices, Inc. All rights reserved.

ADG406/ADG407/ADG426 TABLE OF CONTENTS Features .............................................................................................. 1  ADG426 Timing Diagrams ..........................................................7  Applications ....................................................................................... 1  Absolute Maximum Ratings ............................................................8  Product Highlights ........................................................................... 1  ESD Caution...................................................................................8  Functional Block Diagrams ............................................................. 1  Pin Configurations and Function Descriptions ............................9  Revision History ............................................................................... 2  Typical Performance Characteristics ........................................... 12  General Description ......................................................................... 3  Test Circuits ..................................................................................... 15  Specifications ..................................................................................... 4  Terminology .................................................................................... 18  Dual Supply ................................................................................... 4  Outline Dimensions ....................................................................... 19  Single Supply ................................................................................. 6  Ordering Guide .......................................................................... 20  REVISION HISTORY 5/10—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 20 6/09—Rev. 0 to Rev. A Updated Format .................................................................. Universal Removed T Grade ............................................................... Universal Added Table 4 .................................................................................... 9 Added Table 6 .................................................................................. 10 Added Table 8 .................................................................................. 11 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 4/94—Revision 0: Initial Version Rev. B | Page 2 of 20

ADG406/ADG407/ADG426 GENERAL DESCRIPTION The ADG406, ADG407, and ADG426 are monolithic CMOS The ADG406/ADG407/ADG426 are designed on an enhanced analog multiplexers. The ADG406 and ADG426 switch one of LC2MOS process that provides low power dissipation yet gives sixteen inputs to a common output as determined by the 4-bit high switching speed and low on resistance. These features make binary address lines: A0, A1, A2, and A3. The ADG426 has the parts suitable for high speed data acquisition systems and on-chip address and control latches that facilitate microprocessor audio signal switching. Low power dissipation makes the parts interfacing. The ADG407 switches one of eight differential suitable for battery powered systems. Each channel conducts inputs to a common differential output as determined by the equally well in both directions when on and has an input signal 3-bit binary address lines A0, A1 and A2. An EN input on all range which extends to the supplies. In the off condition, signal devices is used to enable or disable the device. When disabled, levels up to the supplies are blocked. All channels exhibit break- all channels are switched off. before-make switching action preventing momentary shorting when switching channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. Rev. B | Page 3 of 20

ADG406/ADG407/ADG426 SPECIFICATIONS DUAL SUPPLY V = +15 V ± 10%, V = −15 V ± 10%, GND = 0 V, unless otherwise noted. DD SS Table 1. Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V SS DD R 50 Ω typ V = ±10 V, I = −1 mA ON D S 80 125 Ω max V = +13.5 V, V = −13.5 V DD SS R Match 4 Ω typ V = 0 V, I = −1 mA ON D S LEAKAGE CURRENTS V = +16.5 V, V = −16.5 V DD SS Source Off Leakage I (Off) ±0.5 ±20 nA max V = ±10 V, V = +10 V, see Figure 26 S D S Drain Off Leakage I (Off) V = ±10 V, V = +10 V; see Figure 27 D D S ADG406, ADG426 ±1 ±20 nA max ADG407 ±1 ±20 nA max Channel On Leakage I , I (On) V = V = ±10 V; see Figure 28 D S S D ADG406, ADG426 ±1 ±20 nA max ADG407 ±1 ±20 nA max DIGITAL INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Current I or I ±1 μA max V = 0 or V INL INH IN DD C , Digital Input Capacitance 8 pF typ f = 1 MHz IN DYNAMIC CHARACTERISTICS2 t 120 ns typ R = 300 Ω, C = 35 pF; V = ±10 V, V = +10 V; see Figure 29 TRANSITION L L 1 2 150 250 ns max Break Before Make Delay, t 10 10 ns min R = 300 Ω, C = 35 pF; V = +5 V, see Figure 30 OPEN L L S t (EN, WR) 120 175 ns typ R = 300 Ω, C = 35 pF; V = 5 V, see Figure 31 ON L L S 160 225 ns max t (EN, RS) 110 130 ns typ R = 300 Ω, C = 35 pF; V = 5 V, see Figure 31 OFF L L S 150 180 ns max ADG426 Only t , Write Pulse Width 100 ns min W t, Address, Enable Setup Time 100 ns min S t , Address, Enable Hold Time 10 ns min H t , Reset Pulse Width 100 ns min V = +5 V RS S Charge Injection 8 pC typ V = 0 V, R = 0 Ω, C = 1 nF; S S L See Figure 34 Off Isolation −75 dB typ R = 1 k Ω, f = 100 kHz; L V = 0 V, see Figure 35 EN Channel-to-Channel Crosstalk 85 dB typ R = 1 k Ω, f = 100 kHz, see Figure 36 L C (Off) 5 pF typ f = 1 MHz S C (Off) f = 1 MHz D ADG406, ADG426 50 pF typ ADG407 25 pF typ C , C (On) f = 1 MHz D S ADG406, ADG426 60 pF typ ADG407 40 pF typ Rev. B | Page 4 of 20

ADG406/ADG407/ADG426 Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments POWER REQUIREMENTS V = +16.5 V, V = −16.5 V DD SS I 1 μA typ V = 0 V, V = 0 V DD IN EN 5 μA max I 1 μA typ SS 5 μA max I 100 μA typ V = 0 V, V = 2.4 V DD IN EN 200 500 μA max I 1 μA typ SS 5 μA max 1 Temperature ranges is −40°C to +85°C. 2 Guaranteed by design, not subject to production test. Rev. B | Page 5 of 20

ADG406/ADG407/ADG426 SINGLE SUPPLY V = +12 V ± 10%, V = 0 V, GND = 0 V, unless otherwise noted. DD SS Table 2. Parameter1 +25°C −40°C to +85°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to V V DD R 90 Ω typ V = +3 V, +8.5 V, I = −1 mA; ON D S 125 200 Ω max V = +10.8 V DD LEAKAGE CURRENTS V = +13.2 V DD Source Off Leakage I (Off) ±0.5 ±20 nA max V = 8 V/0.1 V, V = 0.1 V/8 V; see Figure 26 S D S Drain Off Leakage I (Off) V = 8 V/0.1 V, V = 0.1 V/8 V; see Figure 27 D D S ADG406, ADG426 ±1 ±20 nA max ADG407 ±1 ±20 nA max Channel On Leakage I , I (On) V = V = 8 V/0.1 V, see Figure 28 D S S D ADG406, ADG426 ±1 ±20 nA max ADG407 ±1 ±20 nA max DIGITAL INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Current I or I ±1 μA max V = 0 or V INL INH IN DD C , Digital Input Capacitance 8 pF typ f = 1 MHz IN DYNAMIC CHARACTERISTICS2 t 180 ns typ R = 300 Ω, C = 35 pF; V = 8 V/0 V, V = 0 V/8 V; see Figure 29 TRANSITION L L 1 2 220 350 ns max Break Before Make Delay, t 10 ns typ R = 300 Ω, C = 35 pF; V = 5 V, see Figure 30 OPEN L L S t (EN, WR) 180 ns typ R = 300 Ω, C = 35 pF; ON L L 240 350 ns max V = +5 V, see Figure 31 S t (EN, RS) 135 ns typ R = 300 Ω, C = 35 pF; V = 5 V, see Figure 31 OFF L L S 180 220 ns max ADG426 Only t , Write Pulse Width 100 ns min W t, Address, Enable Setup Time 100 ns min S t , Address, Enable Hold Time 10 ns min H t , Reset Pulse Width 100 ns min V = +5 V RS S Charge Injection 5 pC typ V = 6 V, R = 0 Ω, C = 1 nF; see Figure 34 S S L Off Isolation −75 dB typ R = 1 kΩ, f = 100 kHz; see Figure 35 L Channel-to-Channel Crosstalk 85 dB typ R = 1 kΩ, f = 100 kHz; see Figure 36 L C (Off) 8 pF typ f = 1 MHz S C (Off) f = 1 MHz D ADG406, ADG426 80 pF typ ADG407 40 pF typ f = 1 MHz C , C (On) D S ADG406, ADG426 100 pF typ ADG407 50 pF typ POWER REQUIREMENTS V = +13.2 V DD I 1 μA typ V = 0 V, V = 0 V DD IN EN 5 μA max I 100 μA typ V = 0 V, V = 2.4 V DD IN EN 200 500 μA max 1 Temperature range is −40°C to +85°C. 2 Guaranteed by design, not subject to production test. Rev. B | Page 6 of 20

ADG406/ADG407/ADG426 ADG426 TIMING DIAGRAMS 3V 3V WR 50% 50% RS 50% 50% 0V 0V tW tW tS tH tOFF(RS) 3V FAig0,u Are1E ,4 AN. 2T,i 0m(AVi3n)g Sequence for Latch2inVg the Switch A0d.8dVress and Enable Inpu00026-009ts OSUWTITPCUHT 0VV0 0.8V0 00026-010 Figure 5. Reset Pulse Width and Reset Turn Off Time Figure 4 shows the timing sequence for latching the switch Figure 5 shows the reset pulse width, t , and the reset turn off address and enable inputs. The latches are level sensitive; rs time, t (RS). therefore, while WR is held low, the latches are transparent and OFF the switches respond to the address and enable inputs. This Note that all digital input signals rise and fall times are input data is latched on the rising edge of WR. measured from 10% to 90% of 3 V; tR = tF = 20 ns. Rev. B | Page 7 of 20

ADG406/ADG407/ADG426 ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to V 44 V DD SS section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +25 V DD maximum rating conditions for extended periods may affect V to GND +0.3 V to −25 V SS device reliability. Analog, Digital Inputs1 V − 2 V to V + 2 V or 20 mA, SS DD whichever occurs first ESD CAUTION Continuous Current, S or D 20 mA Peak Current, S or D 40 mA (Pulsed at 1 ms, 10% duty cycle max) Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Plastic Package θ , Thermal Impedance 75°C/W JA Lead Temperature, Soldering 260°C (10 sec) PLCC Package θ , Thermal Impedance 80°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C SSOP Package θ , Thermal Impedance 122°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 Overvoltages at A, S, D, WR, or RS will be clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B | Page 8 of 20

ADG406/ADG407/ADG426 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VNDCD 12 2287 DVSS S16 NC NC VDD D VSS S8 NC 3 26 S8 4 3 2 1 28 27 26 S16 4 25 S7 S15 5 PIN 1 25 S7 S15 5 ADG406 24 S6 S14 6 INDENTFIER 24 S6 S14 6 TOP VIEW 23 S5 S13 7 (Not to Scale) 22 S4 S13 7 ADG406 23 S5 S12 8 21 S3 S12 8 TOP VIEW 22 S4 S11 9 20 S2 S11 9 (Not to scale) 21 S3 S10 10 19 S1 S10 10 20 S2 S9 11 18 EN S9 11 19 S1 GND 12 17 A0 NAC3 11N43C = NO CONNEC11T65 AA12 00026-004 1GND2NC1NC3 = 1NA34O 1CA25ON1A16NE1A0C7T1EN8 00026-005 Figure 6. 28-Lead PDIP Figure 7. 28-Lead PLCC Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 V Most Positive Power Supply Potential. DD 2, 3, 13 NC No Connect. 4 to 11 S16 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs. 12 GND Ground (0 V) Reference. 14 to 17 A3 to A0 Logic Control Input. 18 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 to 26 S1 to 8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs. 27 V Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. SS 28 D Drain Terminal. This pin can be an input or an output. Table 5. Truth Table (ADG406) A3 A2 A1 A0 EN On Switch X X X X 0 None 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 Rev. B | Page 9 of 20

ADG406/ADG407/ADG426 VDDBD 21 2287 DVSAS S8B NC DB VDD DA VSS S8A NC 3 26 S8A 4 3 2 1 28 27 26 S8B 4 25 S7A S7B 5 PIN 1 25 S7A S7B 5 ADG407 24 S6A S6B 6 INDENTFIER 24 S6A S6B 6 TOP VIEW 23 S5A S5B 7 (Not to Scale) 22 S4A S5B 7 ADG407 23 S5A S4B 8 21 S3A S4B 8 TOP VIEW 22 S4A S3B 9 20 S2A S3B 9 (Not to scale) 21 S3A S2B 10 19 S1A S2B 10 20 S2A S1B 11 18 EN S1B 11 19 S1A GND 12 17 A0 NNCC 11N34C = NO CONNEC11T65 AA12 00026-006 1GND2N1CNC3 = 1NNC4O 1CA25ON1A16NE1A0C7T1EN8 00026-007 Figure 8. 28-Lead PDIP Figure 9. 28-Lead PLCC Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 V Most Positive Power Supply Potential. DD 2 DB Drain Terminal B. This pin can be an input or an output. 3, 13, 14 NC No Connect. 4 to 11 S8B to S1B Source Terminal 8B to Source Terminal 1B. These pins can be inputs or outputs. 12 GND Ground (0 V) Reference. 15 to 17 A2 to A0 Logic Control Input. 18 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 to 26 S1A to S8A Source Terminal 1A to Source Terminal 8A. These pins can be inputs or outputs. 27 V Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. SS 28 DA Drain Terminal A. This pin can be an input or an output. Table 7. Truth Table (ADG407) A2 A1 A0 EN On Switch Pair X X X 0 None 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 Rev. B | Page 10 of 20

ADG406/ADG407/ADG426 VDD 1 28 D NC 2 27 VSS RS 3 26 S8 S16 4 25 S7 S15 5 24 S6 ADG426 S14 6 23 S5 TOP VIEW S13 7 (Not to Scale) 22 S4 S12 8 21 S3 S11 9 20 S2 S10 10 19 S1 S9 11 18 EN GND 12 17 A0 WR 13 16 A1 A3 14NC = NO CONNECT15 A2 00026-008 Figure 10. 28-Lead PDIP/SSOP Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 V Most Positive Power Supply Potential. DD 2 NC No Connect. 3 RS Active Low Logic Input. When this pin is low, all switches are open, and address and enable latches registers are cleared to 0. 4 to 11 S16 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs. 12 GND Ground (0 V) Reference. 13 WR The rising edge of the WR signal latches the state of the address control lines and the enable line. 14 to 17 A3 to A0 Logic Control Input. 18 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 to 26 S1 to S8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs. 27 V Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. SS 28 D Drain Terminal. This pin can be an input or an output. Table 9. Truth Table (ADG426) A3 A2 A1 A0 EN WR RS On switch X X X X X 1 Retains previous switch condition X X X X X X 0 None (address and enable latches cleared) X X X X 0 0 1 None 0 0 0 0 1 0 1 1 0 0 0 1 1 0 1 2 0 0 1 0 1 0 1 3 0 0 1 1 1 0 1 4 0 1 0 0 1 0 1 5 0 1 0 1 1 0 1 6 0 1 1 0 1 0 1 7 0 1 1 1 1 0 1 8 1 0 0 0 1 0 1 9 1 0 0 1 1 0 1 10 1 0 1 0 1 0 1 11 1 0 1 1 1 0 1 12 1 1 0 0 1 0 1 13 1 1 0 1 1 0 1 14 1 1 1 0 1 0 1 15 1 1 1 1 1 0 1 16 Rev. B | Page 11 of 20

ADG406/ADG407/ADG426 TYPICAL PERFORMANCE CHARACTERISTICS 150 400 TA = 25°C TA = 25°C 350 120 VDD = +5V VDD = +5V 300 VSS =0V VSS =–5V 250 (Ω)N 90 VVDSSD == –+1100VV (Ω)N 200 O O R 60 R VDD = +10V 150 VSS =0V VDD = +12V 100 VSS =0V 30 VDD = +15V VDD = +12V 0 VSS =–15V VSS =–12V 00026-011 500 VVDSSD == 0+V15V 00026-014 –15 –10 –5 0 5 10 15 0 2.5 5.0 7.5 10 12.5 15 VD (VS) (V) VD (VS) (V) Figure 11. RON as a Function of VD (VS): Dual Supplies Figure 14. RON as a Function of VD (VS): Single Supplies 100 150 VDD = +15V VDD = 12V VSS =–15V VSS =0V 80 120 125°C 125°C 60 90 Ω) Ω) 85°C R (ON 85°C R (ON 25°C 40 60 25°C 20 30 0 00026-012 0 00026-015 –15 –10 –5 0 5 10 15 0 2 4 6 8 10 12 VD (VS) (V) VD (VS) (V) Figure 12. RON as a Function of VD (VS) for Different Temperatures Figure 15. RON as a Function of VD (VS) for Different Temperatures 0.10 0.02 0.08 VVTADSS D= ==+ –2+1515°5CVV VTVADSS D= ==+ 02+V51°2CV A) ID(ON) A) 0.01 n n T ( 0.06 T ( N N E E RR RR IS(OFF) U 0.04 U 0 C C AGE ID(OFF) AGE ID(OFF) K 0.02 K EA EA ID(ON) L L–0.01 0 –0.02 IS(OFF) 00026-013 –0.02 00026-016 –15 –10 –5 0 5 10 15 0 2 4 6 8 10 12 VD (VS) (V) VD (VS) (V) Figure 13. Leakage Currents as a Function of VD (VS) Figure 16. Leakage Currents as a Function of VD (VS) Rev. B | Page 12 of 20

ADG406/ADG407/ADG426 100 100 VDD = +15V VDD = +15V VSS =–15V VSS =–15V 10 10 1 EN = 2.4V A) A) m m I (DD EN = 2.4V I (SS 0.1 EN = 0V 1 0.01 EN = 0V 0.001 0.1 00026-017 0.0001 00026-020 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Positive Supply Current vs. Switching Frequency Figure 20. Negative Supply Current vs. Switching Frequency 160 220 tON VVDSSD == –+1155VV 200 VVDSSD == 0+V12V 140 t ON t 180 TRANSITION t TRANSITION 120 160 s) s) n n t ( t (140 100 120 80 tOFF 60 tOFF 00026-018 10800 00026-021 1 3 5 7 9 11 13 15 2 4 6 8 10 12 VIN (V) VIN (V) Figure 18. Switching Time vs. VIN (Bipolar Supply) Figure 21. Switching Time vs. VIN (Single Supply) 300 500 VIN = +5V VIN = +5V 400 t TRANSITION t 200 ON 300 t (ns) tON t (ns) t 200 TRANSITION 100 tOFF t OFF 100 0 00026-019 0 00026-022 ±5 ±7 ±9 ±11 ±13 ±15 ±17 ±19 ±21 5 7 9 11 13 15 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 19. Switching Time vs. Bipolar Supply Figure 22. Switching Time vs. Single Supply Rev. B | Page 13 of 20

ADG406/ADG407/ADG426 140 140 VDD = +15V VDD = +15V VSS =–15V VSS =–15V 120 120 ON (dB)100 K (dB)100 ATI AL F ISOL 80 ROSST 80 F C O 60 60 40 00026-023 40 00026-024 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Off Isolation vs. Frequency Figure 24. Crosstalk vs. Frequency Rev. B | Page 14 of 20

ADG406/ADG407/ADG426 TEST CIRCUITS IDS VDD VSS V1 S1 VDD VSS S2 D ID (OFF) A S D S16 VD VS RON = V1/IDS 00026-025 VS EN +0.8V 00026-027 Figure 25. On Resistance Figure 27. ID (Off) VDD VSS VDD VSS IS (OFF) S1 VDD VSS VDD VSS A S2 D S1 D ID (ON) A VS S16 S16 VD VD EN +0.8V00026-026 VS EN +2.4V 00026-028 Figure 26. IS (Off) Figure 28. ID (On) VDD VSS 3V VDD VSS ADDRESS A3 S1 V1 DRIVE (VIN) 50% 50% VIN 50Ω A2 S2 THRU S15 A1 S16 V2 A0 ADG4261 2.4V ERNS D RL CL VOUT VOUT 90% 300Ω 35pF GND WR 1SIMILAR CONNECTION FOR ADG406/ADG407 tTRANSITION 90% tTRANSITION 00026-029 Figure 29. Switching Time of Multiplexer, tTRANSITION VDD VSS 3V VDD VSS ADDRESS A3 S1 VS DRIVE (VIN) VIN 50Ω A2 S2 THRU S15 A1 S16 A0 ADG4261 RS D VOUT 2.4V EN RL CL OUTPUT 80% 80% GND WR 300Ω 35pF 0V 1SIMILAR CONNECTION FOR ADG406/ADG407 tOPEN 00026-030 Figure 30. Break-Before-Make Delay, tOPEN Rev. B | Page 15 of 20

ADG406/ADG407/ADG426 VDD VSS 3V VDD VSS A3 S1 VS DREIVNEA (BVLINE) 50% 50% A2 S2 THRU S16 A1 0V A0 ADG4261 tOFF(EN) VO 90% 90% 2.4V RS D VOUT OUTPUT EN RL CL VIN 50Ω GND WR 300Ω 35pF 0V 1SIMILAR CONNECTION FOR ADG406/ADG407 tON(EN) 00026-031 Figure 31. Enable Delay, tON (EN), tOFF (EN) VDD VSS VDD VSS 3V A3 S1 VS A2 S2 THRU S16 WR 50% A1 0V A0 ADG426 V0 2.4V EN D VOUT tON(WR) RS R30L0Ω C35LpF OUTPUT 0.2V0 VRS WR GND 0V VWR 00026-032 Figure 32. Write Turn-On Time, tON (WR) VDD VSS VDD VSS 3V A3 S1 VS A2 S2 THRU S16 RS 50% A1 0V ADG426 A0 tOFF(RS) 2.4V EN D VOUT V0 RS R30L0Ω C35LpF 0.8V0 OUTPUT VIN GND WR 0V 00026-033 Figure 33. Reset Turn-Off Time, tOFF (RS) Rev. B | Page 16 of 20

ADG406/ADG407/ADG426 VDD VSS VDD VSS A3 RS 2.4V 3V A2 LOGIC A1 INPUT ADG4261 (VIN) A0 RS S D VOUT VS EN C1nLF ΔVOUT VIN GND WR VOUT QINJ = CL×ΔVOUT 1SIMILAR CONNECTION FOR ADG406/ADG407. 00026-034 Figure 34. Charge Injection VDD S16 VDD VDD VIN S2 D VOUT 1kΩ 1kΩ S1 VDD A3 S1 A0 A2 ADG4261 A1 S16 VIN A1 A0 ADG4261 A2 A3 2.4V RS D VOUT 2.4V EN EN R1kLΩ RS GND WR VSS GND WR VSS 1SIMILAR CONNECTION FORV ASDSG406/ADG407. 00026-035 1SIMILAR CONNECTION FOR ADG406V/SASDG407. 00026-036 Figure 35. Off Isolation Figure 36. Crosstalk Rev. B | Page 17 of 20

ADG406/ADG407/ADG426 TERMINOLOGY t (EN) V OFF DD Delay time between the 50% and 90% points of the digital input Most positive power supply potential. and switch off condition. V SS t Most negative power supply potential in dual supplies. In single TRANSITION Delay time between the 50% and 90% points of the digital supply applications, it may be connected to ground. inputs and the switch on condition when switching from GND one address state to another. Ground (0 V) reference. t OPEN R ON Off time measured between 80% points of both switches when Ohmic resistance between the D and S terminals. switching from one address state to another. R Match ON V INL Difference between the R of any two channels. Maximum input voltage for Logic 0. ON I (Off) V S INH Source leakage current when the switch is off. Minimum input voltage for Logic 1. I (Off) I (I ) D INL INH Drain leakage current when the switch is off. Input current of the digital input. I , I (On) Crosstalk D S Channel leakage current when the switch is on. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. V (V) D S Analog voltage on Terminal D, Terminal S. Off Isolation A measure of unwanted signal coupling through an off channel. C (Off) S Channel input capacitance for off condition. Charge Injection A measure of the glitch impulse transferred from the digital C (Off) D input to the analog output during switching. Channel output capacitance for off condition. I C , C (ON) DD D S Positive supply current. On switch capacitance. I C SS IN Negative supply current. Digital input capacitance. t (EN) ON Delay time between the 50% and 90% points of the digital input and switch on condition. Rev. B | Page 18 of 20

ADG406/ADG407/ADG426 OUTLINE DIMENSIONS 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 1 14 0.625 (15.88) 0.100 (2.54) 0.600 (15.24) BSC 0.195 (4.95) 0.250 (6.35) 0.015 (0.38) MAX GAUGE 0.125 (3.17) 0.015 PLANE (0.38) 0.200 (5.08) MIN 0.115 (2.92) SEATING 0.015 (0.38) PLANE 0.008 (0.20) 0.700 (17.78) 0.022 (0.56) 0.005 (0.13) MAX 0.014 (0.36) MIN 0.070 (1.78) 0.050 (1.27) COMPLIANTTO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPEANRREEREN NLCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VLRAE LAUEDSNSET. ISN FDOERSIGN. 071006-A Figure 37. 28-Lead Plastic Dual In-Line Package {PDIP} Wide Body (N-28-2) Dimensions shown in inches and (millimeters) 0.180 (4.57) 0.048 (1.22) 0.165 (4.19) 0.042 (1.07) 0.056 (1.42) 0.020 (0.51) 0.042 (1.07) MIN 4 26 0.048 (1.22) 5 PIN 1 25 0.021 (0.53) 0.042 (1.07) IDENTIFIER 0.013 (0.33) BOTTOM TOP VIEW 0.050 0.430 (10.92) VIEW (PINS DOWN) (1.27) 0.390 (9.91) (PINS UP) BSC 0.032 (0.81) 0.026 (0.66) 11 19 12 18 0.045 (1.14) 00..445560 ((1111..548320))SQ 0.120 (3.04) 0.025 (0.64) R 0.090 (2.29) 0.495 (12.57) SQ 0.485 (12.32) COMPLIANT TO JEDEC STANDARDS MO-047-AB C(RINOE FNPETARRREOENLNCLTEIHN EOGSN DELISYM) EAANNRSDEI OARNROSEU ANNRDOEET D IAN-OP IPFNRFC OHINPECRSHI;A METQIELU LFIIOVMAREL TUEESNRET DSINI MF DOEENRSSIGIONN.S 042508-A Figure 38. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown in inches and (millimeters) Rev. B | Page 19 of 20

ADG406/ADG407/ADG426 10.50 10.20 9.90 28 15 5.60 5.30 5.00 8.20 7.80 1 7.40 14 1.85 0.25 2.00 MAX 1.75 0.09 1.65 COPLA0N.0A5R MITIYN 0.65 BSC 00..3282 SPLEAATNIENG 840°°° 000...975555 0.10 COMPLIANTTO JEDEC STANDARDS MO-150-AH 060106-A Figure 39. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option2 ADG406BN −40°C to +85°C 28-Lead PDIP N-28-2 ADG406BNZ −40°C to +85°C 28-Lead PDIP N-28-2 ADG406BP −40°C to +85°C 28-Lead PLCC P-28 ADG406BP-REEL −40°C to +85°C 28-Lead PLCC P-28 ADG406BPZ −40°C to +85°C 28-Lead PLCC P-28 ADG406BPZ-REEL −40°C to +85°C 28-Lead PLCC P-28 ADG407BN −40°C to +85°C 28-Lead PDIP N-28-2 ADG407BNZ −40°C to +85°C 28-Lead PDIP N-28-2 ADG407BP −40°C to +85°C 28-Lead PLCC P-28 ADG407BP-REEL −40°C to +85°C 28-Lead PLCC P-28 ADG407BPZ −40°C to +85°C 28-Lead PLCC P-28 ADG407BPZ-RL −40°C to +85°C 28-Lead PLCC P-28 ADG407BCHIPS −40°C to +85°C DIE ADG426BN −40°C to +85°C 28-Lead PDIP N-28-2 ADG426BNZ −40°C to +85°C 28-Lead PDIP N-28-2 ADG426BRS −40°C to +85°C 28-Lead SSOP RS-28 ADG426BRS-REEL −40°C to +85°C 28-Lead SSOP RS-28 ADG426BRS-REEL7 −40°C to +85°C 28-Lead SSOP RS-28 ADG426BRSZ −40°C to +85°C 28-Lead SSOP RS-28 ADG426BRSZ-REEL −40°C to +85°C 28-Lead SSOP RS-28 1 Z = RoHS Compliant Part. 2 N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small Outline Package (SSOP). ©1994–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00026-0-5/10(B) Rev. B | Page 20 of 20