LC2MOS Quad SPST Switches Data Sheet ADG211A/ADG212A FEATURES FUNCTIONAL BLOCK DIAGRAM 44 V supply maximum rating ADG211A ±15 V analog signal range S1 IN1 Low R : 115 Ω maximum ON D1 Low leakage: 0.5 nA typical S2 Break-before-make switching IN2 Single supply operation possible D2 Extended plastic temperature range: −40°C to +85°C S3 TTL/CMOS compatible IN3 D3 Available in 16-lead PDIP/SOIC and 20-pead PLCC packages S4 Pin compatible to DG211/DG212 IN4 D4 N1.O STWEISTCHES SHOWN FOR A LOGIC 1 INPUT. 10950-001 Figure 1. ADG212A S1 IN1 D1 S2 IN2 D2 S3 IN3 D3 S4 IN4 D4 N1.O STWEISTCHES SHOWN FOR A LOGIC 1 INPUT. 10950-002 Figure 2. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG211A and ADG212A are monolithic CMOS devices 1. Extended Signal Range. comprising four independently selectable switches. They are These switches are fabricated on an enhanced LC2MOS designed on an enhanced LC2MOS process, which gives an process, resulting in high breakdown and an increased increased signal handling capability of ±15 V. These switches analog signal range of ±15 V. also feature high switching speeds and low RON. 2. Single Supply Operation. For applications where the analog signal is unipolar (0 V to The ADG211A and ADG212A consist of four SPST switches. 15 V), the switches can be operated from a single 15 V They differ only in that the digital control logic is inverted. In supply. multiplexer applications, all switches exhibit break-before-make 3. Low Leakage. switching action when driven simultaneously. Inherent in the Leakage currents in the range of 500 pA make these design is low charge injection for minimum transients when switches suitable for high precision circuits. The added switching the digital inputs. feature of break-before-make allows for multiple outputs to be tied together for multiplexer applications while keeping leakage errors to a minimum. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADG211A/ADG212A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................4 Functional Block Diagram .............................................................. 1 Pin Configurations and Function Descriptions ............................5 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................6 Product Highlights ........................................................................... 1 Terminology .......................................................................................9 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 10 Specifications ..................................................................................... 3 Outline Dimensions ....................................................................... 12 Absolute Maximum Ratings ............................................................ 4 Ordering Guide .......................................................................... 13 REVISION HISTORY 10/12—Rev. B to Rev. C Updated Format .................................................................. Universal Added Pin Descriptions, Table 3 .................................................... 5 Moved Table 4 ................................................................................... 5 Changes to Figure 5, Figure 6, Figure 8, and Figure 9 ................. 6 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 9/02—Rev. A to Rev. B Rev. C | Page 2 of 16

Data Sheet ADG211A/ADG212A SPECIFICATIONS V = +15 V, V = −15 V, V = 5 V, unless otherwise noted. DD SS L Table 1. 25°C −40°C to +85°C Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range ±15 ±15 V R 115 175 Ω −10 V ≤ V ≤ +10 V, I = 1 mA, see Figure 21 ON S DS R vs. V (V) 20 % ON D S R Drift 0.5 %/°C ON R Match 5 % V = 0 V, I = 1 mA ON S DS LEAKAGE CURRENTS IS (Off) 0.5 nA VD = ±14 V; VS = 14 V; see Figure 22 Off Input Leakage 5 100 nA ID (Off) 0.5 nA VD = ±14 V; VS = 14 V; see Figure 22 Off Output Leakage 5 100 nA I (On) 0.5 nA V = V = ±14 V; see Figure 23 D D S On Channel Leakage 5 200 nA DIGITAL CONTROL V , Input High Voltage 2.4 V TTL compatibility is independent of V INH L V , Input Low Voltage 0.8 V INL I or I 1 µA NL NH C , Digital Input Capacitance 5 pF IN DYNAMIC CHARACTERISTICS t 1 30 ns See Figure 24 OPEN t 1 600 ns See Figure 25 ON t 1 450 ns See Figure 25 OFF Off Isolation 80 dB V = 10 V (p-p); f = 100 kHz; S R = 75 Ω; see Figure 26 L Channel-to-Channel Crosstalk 80 dB See Figure 27 C (Off) 5 pF S C (Off) 5 pF D C, C (On) 16 pF S D Q , Charge Injection 20 pC R = 0 Ω; C = 1000 pF; V = 0 V; see Figure 28 INJ S L S POWER SUPPLY I 0.6 mA Digital inputs = V or V DD INL INH I 1 mA DD I 0.1 mA SS I 0.2 mA SS I 0.9 mA L 1 Sample tested at 25°C to ensure compliance. Rev. C | Page 3 of 16

ADG211A/ADG212A Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise stated. Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 2. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational VDD to VSS 44 V section of this specification is not implied. Exposure to absolute VDD to GND 25 V maximum rating conditions for extended periods may affect VSS to GND −25 V device reliability. V to GND −0.3 V, 25 V L Analog Inputs1 Voltage at S, D V − 0.3 V to V + 0.3 V ESD CAUTION SS DD Continuous Current, S or D 30 mA Pulsed Current S or D 1 ms Duration, 10% Duty Cycle 70 mA Digital Inputs1 Voltage at IN V − 2 V to V + 2 V or SS DD 20 mA, Whichever Occurs First Power Dissipation (Any Package) Up to +75°C 470 mW Derates above +75°C by 6 mW/°C Operating Temperature −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 10 sec) +300°C 1 Overvoltage at IN, S, or D will be clamped by diodes. Current should be limited to the Maximum Rating listed in Table 2. Rev. C | Page 4 of 16

Data Sheet ADG211A/ADG212A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D1 IN1 NIC IN2 D2 3 2 1 20 19 S1 4 PIN 1 18 S2 INDENTFIER IN1 1 16 IN2 VSS 5 ADG211A/ 17 VDD D1 2 15 D2 NIC 6 ADG212A 16 NIC S1 3 ADG211A/ 14 S2 GND 7 TOP VIEW 15 VL ADG212A (Not to Scale) VSS 4 13 VDD S4 8 14 S3 GNSD4 56 (NToOt Pto V SIEcaWle) 1112 VSL3 9 10 11 12 13 4 4 C 3 3 IDN44 78 190 DIN33 10950-003 N1.O NTIECS = NOD INTINERNNIAL IMCONDNECTION. 10950-004 Figure 3. PDIP, SOIC Pin Configuration Figure 4. PLCC Pin Configuration Table 3. Pin Function Descriptions Pin No. PDIP, SOIC PLCC Mnemonic Description 1 2 IN1 Logic Control Input. 2 3 D1 Drain Terminal. Can be an input or output. 3 4 S1 Source Terminal. Can be an input or output. 4 5 V Most Negative Power Supply Potential. SS 5 7 GND Ground (0 V) Reference. 6 8 S4 Source Terminal. Can be an input or output. 7 9 D4 Drain Terminal. Can be an input or output. 8 10 IN4 Logic Control Input. 9 12 IN3 Logic Control Input. 10 13 D3 Drain Terminal. Can be an input or output. 11 14 S3 Source Terminal. Can be an input or output. 12 15 V Logic Supply Voltage. L 13 17 V Most Positive Power Supply Potential. DD 14 18 S2 Source Terminal. Can be an input or output. 15 19 D2 Drain Terminal. Can be an input or output. 16 20 IN2 Logic Control Input. 1, 6, 11, 16 NIC No Internal Connection. Table 4. Truth Table ADG211A In ADG212A In Switch Condition 0 1 On 1 0 Off Rev. C | Page 5 of 16

ADG211A/ADG212A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS The switches can comfortably operate anywhere in the 10 V to 15 V single or dual supply range, with only a slight degradation in performance. The following graphs show the relevant performance curves. The test circuits and test conditions are given in a following section, Test Circuits. 120 120 VDD = +15V VDD = 15V VSS = –15V VSS = 0V 90 90 70°C 25°C Ω) Ω) 0°C (N 60 (N 60 RO 70°C RO 25°C 0°C 30 30 0–15 –10 –5 VD (V0S) (V) 5 10 15 10950-005 00 5 VD (VS) (V) 10 15 10950-008 Figure 5. RON as a Function of VD (VS), Dual ±15 V Supplies Figure 8. RON as a Function of VD (VS), Single +15 V Supply 120 150 VDD = +10V VDD = 10V VSS = –10V VSS = 0V 120 70°C 90 25°C 70°C 90 Ω) Ω) 0°C (N 60 25°C (N O O R R 0°C 60 30 30 0 0 –10 –5 VD (V0S) (V) 5 10 10950-006 0 VD (V5S) (V) 10 10950-009 Figure 6. RON as a Function of VD (VS), Dual ±10 V Supplies Figure 9. RON as a Function of VD (VS), Single +10 V Supply 100 2.5 VDD = +15V TEMP = 0°C TO 70°C VSS = –15V 2.0 10 V) A) L ( T (n ID (ON) EVE 1.5 EN 1 R L CURR IS (OFF) RIGGE 1.0 ID (OFF) T 0.1 0.5 0.0120 30 40 TEMP50ERATUR6E0 (°C) 70 80 90 10950-007 010 11 SUP1P2LY VOLTAG13E (V) 14 15 10950-010 Figure 7. Leakage Current as a Function of Temperature Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply (Note That Leakage Current Reduces as the Supply Voltages Reduce) Voltage Rev. C | Page 6 of 16

Data Sheet ADG211A/ADG212A 220 220 200 200 180 180 70°C s) 160 s) 160 (nN 70°C (nN 25°C O O t 140 t 140 25°C 0°C 120 120 0°C 100 100 8010 11 SUPP12LY VOLTAG1E3 (±V) 14 15 10950-011 8010 11 SUP1P2LY VOLTAG13E (V) 14 15 10950-014 Figure 11. tON vs. Supply Voltage (Dual Supply) Figure 14. tON vs. Supply Voltage (Single Supply) 80 80 70°C 25°C 60 60 0°C 25°C 70°C s) s) n n (OFF 40 (OFF 40 0°C t t 20 20 010 11 SUPP12LY VOLTAG1E3 (±V) 14 15 10950-012 010 11 SUP1P2LY VOLTAG13E (V) 14 15 10950-015 Figure 12. tOFF vs. Supply Voltage (Dual Supply) Figure 15. tOFF vs. Supply Voltage (Single Supply) 50 60 40 60 C) VDD = +15V ON (dB) TION (p 20 VSS = –15V OFF ISOLATI 70 HARGE INJEC 0 VVDSSD == 0+V15V 80 SINGLE SUPPLY C –20 DUAL SUPPLY 9010 11 SUP1P2LY VOLTAG13E (V) 14 15 10950-013 –40–16 –12 –8 –4 VS0 (V) 4 8 12 16 10950-016 Figure 13. Off Isolation and Channel-to-Channel Crosstalk vs. Supply Voltage Figure 16. Charge Injection vs. Source Voltage (VS) for Dual and Single 15 V Supplies Rev. C | Page 7 of 16

ADG211A/ADG212A Data Sheet 60 0.7 0.6 40 0°C C) VDD = +10V N (p VSS = –10V 0.5 GE INJECTIO 200 VVDSSD == 0+V10V I (mA)DD 0.4 2750°°CC AR 0.3 H C –20 0.2 –40–16 –12 –8 –4 VS0 (V) 4 8 12 16 10950-017 0.110 11 SUPP12LY VOLTAG1E3 (±V) 14 15 10950-019 Figure 17. Charge Injection vs. Source Voltage for Dual and Single 10 V Figure 19. IDD vs. Supply Voltage, (Dual Supply) Supplies 0.4 0.7 0.6 0°C 0.3 0°C 0.5 25°C (µA)S 0.2 (mA)D 0.4 70°C IS ID 0.3 0.1 0.2 70°C 25°C 010 11 SUPP12LY VOLTAG1E3 (±V) 14 15 10950-018 0.110 11 SUP1P2LY VOLTAG13E (V) 14 15 10950-020 Figure 18. ISS vs. Supply Voltage (Dual Supply) Figure 20. IDD vs. Supply Voltage (Single Supply) Rev. C | Page 8 of 16

Data Sheet ADG211A/ADG212A TERMINOLOGY t R OFF ON Delay time between the 50% and 90% points of the digital input Ohmic resistance between the out and S terminals. and switch off condition. R Match ON t Difference between the R of any two channels. OPEN ON Off time measured between 50% points of both switches, which I (Off) S are connected as a multiplexer when switching from one Source terminal leakage current when the switch is off. address state to another. I (Off) D V INL Drain terminal leakage current when the switch is off. Maximum input voltage for a logic low. I (On) D V INH Leakage current that flows from the closed switch into the body. Minimum input voltage for a logic high. V (V) D S I (I ) INL INH Analog voltage on the D, S terminals. Input current of the digital input. C (Off) S V DD Switch input capacitance off condition. Most positive voltage supply. C (Off) D V SS Switch output capacitance off condition. Most negative voltage supply. C IN V L Digital input capacitance. Logic supply voltage. C , C (On) D S I DD Input or output capacitance when the switch is on. Positive supply current. t ON I SS Delay time between the 50% and 90% points of the digital input Negative supply current. and switch on condition. Rev. C | Page 9 of 16

ADG211A/ADG212A Data Sheet TEST CIRCUITS IDS V1 ID (ON) S D S D VS RON = V1/IDS 10950-021 VS A VD 10950-023 Figure 21. Figure 23. IS (OFF) ID (OFF) S D VS A A VD 10950-022 Figure 22. +5V +15V 3V ADG211A VL VDD VIN S1 D1 VOUT 2V S2 D2 3V 14pF 330Ω VIN ADG212A * IN1 VIN * VOUT IN2 50% GND VSS *HBAOVTEH TTHHEE SBAUMFFEE PRR AONPDA GIN–A1VT5EIVORTNE DRE SLHAOY.ULD tOPEN 10950-024 Figure 24. 3V +5V VDD ADG211A VIN 50% 50% VL VDD S D VOUT 3V 2V IN 330Ω 14pF ADG212A VIN 50% 50% VIN GND VSS 90% 90% VSS VOUT tON tOFF 10950-025 Figure 25. Rev. C | Page 10 of 16

Data Sheet ADG211A/ADG212A +5V VDD VL VDD S D 75Ω +5V VDD VIN VL VDD VS S D VOUT VIN D S RL VOUT NC VS VIN 75Ω R75LΩ GND VSS GND VSS AADDGG221121AA:: VVIINN == 50VV VSS O20F ×F lIoSgO L|VAST/VIOONUT =| 10950-026 AADDGG221112AA:: VVIINN == 05VV VSS CCHRAONSNSETAL-LTKO =-C 2H0A ×N lNoEgL |VS/VOUT| 10950-027 Figure 26. Off Isolation Figure 27. Channel-to-Channel Crosstalk +5V VDD 5V VL VDD RS S D AD711 VIN VOUT 0V VS C1µLF VIN VOUT ΔVOUT GND VSS QINJ = CL × ΔVOUT VSS 10950-028 Figure 28. Charge Injection Rev. C | Page 11 of 16

ADG211A/ADG212A Data Sheet OUTLINE DIMENSIONS 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 16 9 0.280 (7.11) 0.250 (6.35) 1 8 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPENARERERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 073106-B Figure 29. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-16) Dimensions shown in inches and (millimeters) 10.00 (0.3937) 9.80 (0.3858) 16 9 4.00 (0.1575) 6.20 (0.2441) 3.80 (0.1496) 1 8 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AC C(RINOEFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 30.16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. C | Page 12 of 16

Data Sheet ADG211A/ADG212A 0.180 (4.57) 0.048 (1.22 ) 0.165 (4.19) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 0M.2IN0 (0.51) 0.020R (0.50) 3 19 0.021 (0.53) 00..004482 ((11..2027)) 4 IDEPNITNI F1IER 18 (01..02570) 0.013 (0.33)0.330 (8.38) BOTTOM TOP VIEW BSC 0.032 (0.81)0.290 (7.37) VIEW (PINS DOWN) 0.026 (0.66) (PINS UP) 8 14 9 13 0.020 0.045 (1.14) (0.R51) 00..335560 ((98..0849))SQ 0.025 (0.64) R 0.120 (3.04) 0.395 (10.03)SQ 0.090 (2.29) 0.385 (9.78) COMPLIANT TO JEDEC STANDARDS MO-047-AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 31. 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADG211AKN −40°C to +85°C 16-Lead PDIP N-16 ADG211AKNZ −40°C to +85°C 16-Lead PDIP N-16 ADG211AKPZ −40°C to +85°C 20-Lead PLCC P-20 ADG211AKR −40°C to +85°C 16-Lead SOIC_N R-16 ADG211AKRZ −40°C to +85°C 16-Lead SOIC_N R-16 ADG211AKRZ-REEL −40°C to +85°C 16-Lead SOIC_N R-16 ADG211AKRZ-REEL7 −40°C to +85°C 16-Lead SOIC_N R-16 ADG212AKNZ −40°C to +85°C 16-Lead PDIP N-16 ADG212AKPZ −40°C to +85°C 20-Lead PLCC P-20 ADG212AKPZ-REEL −40°C to +85°C 20-Lead PLCC P-20 ADG212AKR −40°C to +85°C 16-Lead SOIC_N R-16 ADG212AKRZ −40°C to +85°C 16-Lead SOIC_N R-16 ADG212AKRZ-REEL −40°C to +85°C 16-Lead SOIC_N R-16 1 Z = RoHS Compliant Part. Rev. C | Page 13 of 16

ADG211A/ADG212A Data Sheet NOTES Rev. C | Page 14 of 16

Data Sheet ADG211A/ADG212A NOTES Rev. C | Page 15 of 16

ADG211A/ADG212A Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10950-0-10/12(C) Rev. C | Page 16 of 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADG211AKNZ ADG211AKPZ ADG211AKR ADG212AKNZ ADG212AKPZ ADG212AKRZ-REEL ADG211AKRZ ADG211AKN ADG211AKRZ-REEL ADG212AKR ADG212AKRZ ADG211AKRZ-REEL7