Low Capacitance, Low Charge Injection, ±15 V/+12 V, 4:1 iCMOS Multiplexer Data Sheet ADG1204 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.5 pF off source capacitance ADG1204 <1 pC charge injection S1 33 V supply range S2 120 Ω on resistance D S3 Fully specified at ±15 V, +12 V No V supply required S4 L 3 V logic-compatible inputs 1 OF 4 Rail-to-rail operation DECODER 1Ty4p-liecaadl p ToSwSOerP c aonnds u1m2-pletaiodn L <F C0S.0P3 μW A0 A1 EN 04779-001 APPLICATIONS Figure 1. Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems GENERAL DESCRIPTION The ADG1204 is a complementary metal-oxide semiconductor The ADG1204 switches one of four inputs to a common output, D, (CMOS) analog multiplexer, comprising four single channels as determined by the 3-bit binary address lines: A0, A1, and EN. designed on an iCMOS (industrial CMOS) process. iCMOS® is a Logic 0 on the EN pin disables the device. Each switch conducts modular manufacturing process that combines high voltage CMOS equally well in both directions when on and has an input signal and bipolar technologies. It enables the development of a wide range that extends to the supplies. In the off condition, signal range of high performance analog ICs capable of 33 V operation levels up to the supplies are blocked. All switches exhibit break- in a footprint that no previous generation of high voltage devices before-make switching action. has been able to achieve. Unlike analog ICs using conventional PRODUCT HIGHLIGHTS CMOS processes, iCMOS components can tolerate high supply 1. 1.5 pF off capacitance (±15 V supply). voltages while providing increased performance, dramatically 2. <1 pC charge injection. lower power consumption, and reduced package size. 3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 The ultralow capacitance and charge injection of this multiplexer V. makes it an ideal solution for data acquisition and sample-and- 4. No VL logic power supply required. hold applications, where low glitch and fast settling are required. 5. Ultralow power dissipation: <0.03 μW. Fast switching speed coupled with high signal bandwidth makes 6. 14-lead TSSOP and 12-lead, 3 mm × 3 mm LFCSP the device suitable for video signal switching. iCMOS construction packages. ensures ultralow power dissipation, making the device ideally suited for portable and battery-powered instruments. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADG1204 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................8 Functional Block Diagram .............................................................. 1 Truth Table .....................................................................................8 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................9 Product Highlights ........................................................................... 1 Test Circuits ..................................................................................... 12 Revision History ............................................................................... 2 Terminology .................................................................................... 14 Specifications ..................................................................................... 3 Outline Dimensions ....................................................................... 15 Dual Supply ................................................................................... 3 Ordering Guide .......................................................................... 15 Single Supply ................................................................................. 5 Absolute Maximum Ratings ............................................................ 7 REVISION HISTORY 3/16—Rev. B to Rev. C 7/06—Rev. 0 to Rev. A Changed LFCSP_VQ to LFCSP ................................... Throughout Updated Format .................................................................. Universal Changes to Figure 3 .......................................................................... 8 Changes to Table 1 ............................................................................. 3 Updated Outline Dimensions ....................................................... 15 Changes to Table 2 ............................................................................. 5 Changes to Ordering Guide .......................................................... 15 Changes to the Terminology Section ........................................... 14 2/09—Rev. A to Rev. B 7/05—Revision 0: Initial Version Changes to Power Requirements, I , Digital Inputs = 5 V DD Parameter, Table 1 ............................................................................. 4 Changes to Power Requirements, I , Digital Inputs = 5 V DD Parameter, Table 2 ............................................................................. 6 Updated Outline Dimensions ....................................................... 15 Rev. C | Page 2 of 16

Data Sheet ADG1204 SPECIFICATIONS DUAL SUPPLY V = 15 V ± 10%, V = −15 V ± 10%, GND = 0 V, unless otherwise noted. DD SS Table 1. Y Version1 −40°C to −40°C to Parameter 25°C +85°C +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V DD SS On Resistance (R ) 120 Ω typ V = ±10 V, I = −1 mA; see Figure 21 ON S S 190 230 260 Ω max V = +13.5 V, V = −13.5 V DD SS On Resistance Match Between 3.5 Ω typ V = ±10 V, I = −1 mA S S Channels (ΔR ) 6 10 12 Ω max ON On Resistance Flatness (R ) 20 Ω typ V = −5 V, 0 V, +5 V; I = −1 mA FLAT(ON) S S 57 72 79 Ω max LEAKAGE CURRENTS V = +16.5 V, V = −16.5 V DD SS Source Off Leakage, IS (OFF) ±0.02 nA typ VS = ±10 V, VD = ∓10 V; see Figure 22 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, ID (OFF) ±0.02 nA typ VS = ±10 V, VD = ∓10 V; see Figure 22 ±0.1 ±0.6 ±1 nA max Channel On Leakage, I , I (ON) ±0.02 nA typ V = V = ±10 V; see Figure 23 D S S D ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, V 2.0 V min INH Input Low Voltage, V 0.8 V max INL Input Current, I or I 0.005 µA typ V = V or V INL NH IN INL INH ±0.1 µA max Digital Input Capacitance, C 2.5 pF typ IN DYNAMIC CHARACTERISTICS2 Transition Time, t 120 ns typ R = 300 Ω, C = 35 pF TRANS L L 150 180 200 ns max V = 10 V; see Figure 24 S t (EN) 70 ns typ R = 300 Ω, C = 35 pF ON L L 85 100 110 ns max V = 10 V; see Figure 26 S t (EN) 90 ns typ R = 300 Ω, C = 35 pF OFF L L 110 135 155 ns max V = 10 V; see Figure 26 S Break-Before-Make Time Delay, t 25 ns typ R = 300 Ω, C = 35 pF D L L 10 ns min V = V = 10 V; see Figure 25 S1 S2 Charge Injection −0.7 pC typ V = 0 V, R = 0 Ω, C = 1 nF; see Figure 27 S S L Off Isolation 85 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; see Figure 28 L L Channel-to-Channel Crosstalk 80 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; see Figure 30 L L Total Harmonic Distortion + Noise 0.15 % typ R = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz; L see Figure 31 Bandwidth −3 dB 800 MHz typ R = 50 Ω, C = 5 pF; see Figure 29 L L C (OFF) 1.2 pF typ f = 1 MHz, V = 0 V S S 1.5 pF max f = 1 MHz, V = 0 V S C (OFF) 3.6 pF typ f = 1 MHz, V = 0 V D S 4.2 pF max f = 1 MHz, V = 0 V S C , C (ON) 5.5 pF typ f = 1 MHz, V = 0 V D S S 6.5 pF max f = 1 MHz, V = 0 V S Rev. C | Page 3 of 16

ADG1204 Data Sheet Y Version1 −40°C to −40°C to Parameter 25°C +85°C +125°C Unit Test Conditions/Comments POWER REQUIREMENTS V = +16.5 V, V = −16.5 V DD SS I 0.001 µA typ Digital inputs = 0 V or V DD DD 1.0 µA max I 170 µA typ Digital inputs = 5 V DD 285 µA max I 0.001 µA typ Digital inputs = 0 V or V SS DD 1.0 µA max I 0.001 µA typ Digital inputs = 5 V SS 1.0 µA max 1 Y version temperature range is −40°C to +125°C. 2 Guaranteed by design, not subject to production test. Rev. C | Page 4 of 16

Data Sheet ADG1204 SINGLE SUPPLY V = 12 V ± 10%, V = 0 V, GND = 0 V, unless otherwise noted. DD SS Table 2. Y Version1 −40°C to −40°C to Parameter 25°C +85°C +125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V V DD On Resistance (R ) 300 Ω typ V = 0 V to 10 V, I = −1 mA; ON S S see Figure 21 475 567 625 Ω max V = 10.8 V, V = 0 V DD SS On Resistance Match Between Channels 5 Ω typ V = 0 V to 10 V, I = −1 mA S S (ΔR ) 16 26 27 Ω max ON On Resistance Flatness (R ) 60 Ω typ V = 3 V, 6 V, 9 V; I = −1 mA FLAT(ON) S S LEAKAGE CURRENTS V = 13.2 V DD Source Off Leakage, I (OFF) ±0.02 nA typ V = 1 V/10 V, V = 10 V/1 V; S S D ±0.1 ±0.6 ±1 nA max see Figure 22 Drain Off Leakage, I (OFF) ±0.02 nA typ V = 1 V/10 V, V = 10 V/1 V; D S D ±0.1 ±0.6 ±1 nA max see Figure 22 Channel On Leakage, I , I (ON) ±0.02 nA typ V = V = 1 V or 10 V; see Figure 23 D S S D ±0.2 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, V 2.0 V min INH Input Low Voltage, V 0.8 V max INL Input Current, I or I 0.001 µA typ V = V or V INL INH IN INL INH ±0.1 µA max Digital Input Capacitance, C 2.5 pF typ IN DYNAMIC CHARACTERISTICS2 Transition Time, t 150 ns typ R = 300 Ω, C = 35 pF TRANS L L 190 240 265 ns max V = 8 V; see Figure 24 S t (EN) 95 ns typ R = 300 Ω, C = 35 pF ON L L 120 150 170 ns max V = 8 V; see Figure 26 S t (EN) 100 ns typ R = 300 Ω, C = 35 pF OFF L L 125 155 170 ns max V = 8 V; see Figure 26 S Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF 10 ns min V = V = 8 V; see Figure 25 S1 S2 Charge Injection −0.4 pC typ V = 6 V, R = 0 Ω, C = 1 nF; S S L see Figure 27 Off Isolation 85 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; L L see Figure 28 Channel-to-Channel Crosstalk 80 dB typ R = 50 Ω, C = 5 pF, f = 1 MHz; L L see Figure 30 Bandwidth −3 db 550 MHz typ R = 50 Ω, C = 5 pF; see Figure 29 L L C (OFF) 1.2 pF typ f = 1 MHz; V = 6 V S S 1.5 pF max f = 1 MHz; V = 6 V S C (OFF) 3.6 pF typ f = 1 MHz; V = 6 V D S 4.2 pF max f = 1 MHz; V = 6 V S C , C (ON) 5.5 pF typ f = 1 MHz; V = 6 V D S S 6.5 pF max f = 1 MHz; V = 6 V S Rev. C | Page 5 of 16

ADG1204 Data Sheet Y Version1 −40°C to −40°C to Parameter 25°C +85°C +125°C Unit Test Conditions/Comments POWER REQUIREMENTS V = 13.2 V DD I 0.001 µA typ Digital inputs = 0 V or V DD DD 1.0 µA max I 170 µA typ Digital inputs = 5 V DD 285 µA max 1 Y version temperature range is −40°C to +125°C. 2 Guaranteed by design, not subject to production test. Rev. C | Page 6 of 16

Data Sheet ADG1204 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 3. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to V 35 V DD SS section of this specification is not implied. Operation beyond V to GND −0.3 V to +25 V DD the maximum operating conditions for extended periods may V to GND +0.3 V to −25 V SS affect product reliability. Analog Inputs1 V − 0.3 V to V + 0.3 V or SS DD 30 mA, whichever occurs first Only one absolute maximum rating can be applied at any one time. Digital Inputs1 GND − 0.3 V to V + 0.3 V or DD ESD CAUTION 30 mA, whichever occurs first Peak Current, S or D 100 mA (pulsed at 1 ms, 10% duty cycle maximum) Continuous Current 45 mA Operating Temperature Range Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 14-Lead TSSOP, θ Thermal 112°C/W JA Impedance (4-Layer Board) 12-Lead LFCSP, 80°C/W θ Thermal Impedance JA Reflow Soldering Peak 260°C Temperature, Pb Free 1 Overvoltages at IN, S, or D are clamped by internal diodes. Current must be limited to the maximum ratings given. Rev. C | Page 7 of 16

ADG1204 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS N 0 1 E A A 21 11 01 A0 1 14 A1 VSS1 ADG1204 9 GND EN 2 13 GND S1 2 TOP VIEW 8 VDD (Not to Scale) VSS 3 ADG1204 12 VDD S23 7 S3 S1 4 TOP VIEW 11 S3 S2 5 (Not to Scale) 10 S4 4D 5C 64 N S D 6 9 NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT NC 7NC = NO CONNECT8 NC 04779-002 2 . TTTHOOE TS EHUXIBSPS OPTISRNEA.DT EP,A VDS SM.UST BE TIED 04779-003 Figure 2. TSSOP Pin Configuration Figure 3. LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 1 11 A0 Logic Control Input. 2 12 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 3 1 V Most Negative Power Supply Potential. SS 4 2 S1 Source Terminal. Can be an input or an output. 5 3 S2 Source Terminal. Can be an input or an output. 6 4 D Drain Terminal. Can be an input or an output. 7 to 9 5 NC No Connection. 10 6 S4 Source Terminal. Can be an input or an output. 11 7 S3 Source Terminal. Can be an input or an output. 12 8 V Most Positive Power Supply Potential. DD 13 9 GND Ground (0 V) Reference. 14 10 A1 Logic Control Input. TRUTH TABLE Table 5. EN A1 A0 S1 S2 S3 S4 0 X X Off Off Off Off 1 0 0 On Off Off Off 1 0 1 Off On Off Off 1 1 0 Off Off On Off 1 1 1 Off Off Off On Rev. C | Page 8 of 16

Data Sheet ADG1204 TYPICAL PERFORMANCE CHARACTERISTICS 200 250 TA = +25°C VDD = +15V 180 VSS = –15V VDD = +13.5V 160 VSS = –13.5V 200 Ω) 140 Ω) TA = +125°C E ( E ( C 120 C 150 N N STA 100 STA TA = +85°C N RESI 80 VVDSSD == –+1155VV VVDSSD == –+1166..55VV N RESI 100 O 60 O TA = –40°C TA = +25°C 40 50 200 04779-010 0 04779-006 –18 –15 –12 –9 –6 –3 0 3 6 9 12 15 18 –15 –10 –5 0 5 10 15 SOURCE OR DRAIN VOLTAGE (V) SOURCE OR DRAIN VOLTAGE (V) Figure 4. On Resistance as a Function of VD (VS), Dual Supply Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply 450 600 TA = +25°C VDD = +12V 400 VSS = 0V 500 TA = +125°C 350 TA = +85°C E (Ω) 300 VVDSSD == –+55..55VV E (Ω) 400 C C AN 250 AN ST ST 300 SI 200 SI E E R R ON 150 ON 200 TA = –40°C 100 TA = +25°C 100 500 04779-004 0 04779-007 –5 –4 –3 –2 –1 0 1 2 3 4 5 0 2 4 6 8 10 12 SOURCE OR DRAIN VOLTAGE (V) SOURCE OR DRAIN VOLTAGE (V) Figure 5. On Resistance as a Function of VD (VS), Dual Supply Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply 450 0.30 TA = 25°C VDD = +16.5V 400 0.25 VSS = –16.5V VDD = 10.8V VDD = 12V VBIAS = +10V/–10V 350 VSS = 0V VSS = 0V 0.20 CE (Ω) 300 nA) 0.15 ID, IS (ON) AN 250 E ( ST VDD = 13.2V AG 0.10 ON RESI 125000 VSS = 0V LEAK 0.05 IS (OFF) 100 0 ID (OFF) 500 04779-005 ––00..0150 04779-008 0 2 4 6 8 10 12 14 0 20 40 60 80 100 120 SOURCE OR DRAIN VOLTAGE (V) TEMPERATURE (°C) Figure 6. On Resistance as a Function of VD (VS), Single Supply Figure 9. Leakage Currents as a Function of Temperature, Dual Supply Rev. C | Page 9 of 16

ADG1204 Data Sheet 0.20 250 VDD = 13.2V 0.15 VSS = 0V VBIAS = 10V/1V 200 0.10 ID, IS (ON) VDD = +12V, VSS = 0V A) 0.05 AKAGE (n 0 ID (OFF) TIME (ns) 150 VDD = +15V, VSS = –15V LE–0.05 100 IS (OFF) –0.10 50 ––00..1250 04779-009 0 04779-015 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 10. Leakage Currents as a Function of Temperature, Single Supply Figure 13. Transition Times vs. Temperature 60 0 ITDAD =P +E2R5 °CCHANNEL –10 VVDSSD == –+1155VV 50 –20 TA = +25°C 40 VDD = +15V, VSS = –15V dB) –30 N ( –40 A) O I (µDD 30 SOLATI ––5600 20 FF I –70 O –80 10 VDD = +12V, VSS = 0V –90 0 04779-011 ––110100 04779-016 0 2 4 6 8 10 12 14 10k 100k 1M 10M 100M 1G LOGIC, INX (V) FREQUENCY (Hz) Figure 11. IDD vs. Logic Level Figure 14. Off Isolation vs. Frequency 6 0 4 SDTAOR AU= IR+NC2 T5EO° CT SOO DURRACINE ––1200 VVTADSS D= = =+ –2+1515°5CVV C) –30 p N ( 2 B) –40 O d ARGE INJECTI –20 VDD = +5V, VSS = –5V VDD = +12V, VSS = 0V CROSSTALK ( ––––56780000 S1 TO S2 S2 TO S4 H C –90 –4 VDD = +15V, VSS = –15V –100 –6 04779-014 ––112100 04779-017 –15 –10 –5 0 5 10 15 10k 100k 1M 10M 100M 1G VS (V) FREQUENCY (Hz) Figure 12. Charge Injection vs. Source Voltage Figure 15. Crosstalk vs. Frequency Rev. C | Page 10 of 16

Data Sheet ADG1204 0 6.5 VDD = +15V VDD = +15V VSS = –15V 6.3 VSS = –15V –5 TA = +25°C TA = +25°C 6.1 dB) –10 pF) 5.9 S1 E ( E ( 5.7 S C N N S3 SPO –15 CITA 5.5 S4 RE PA 5.3 ON –20 CA S2 5.1 4.9 –25 –30 04779-018 44..75 04779-032 10k 100k 1M 10M 100M 1G 10G –10 –8 –6 –4 –2 0 2 4 6 8 10 FREQUENCY (Hz) VBIAS (V) Figure 16. On Response vs. Frequency Figure 19. On Capacitance vs. Source Voltage 9 10.00 LOAD = +10kΩ 8 VVTADSS D= = =2 501°V2CV TA = +25°C SOURCE/DRAIN ON 7 pF) 6 1.00 E ( D + N (%) VDD = +5V, VSS = –5V, VS = +3.5Vrms PACITANC 54 DRAIN OFF TH VDD = +15V, VSS = –15V, VS = +5Vrms CA 3 0.10 2 0.0110 100 1k 10k 10004779-019k 100 2 4 SOUVRBCIAE6S O (VF)F 8 10 1204779-033 FREQUENCY (Hz) Figure 17. THD + N vs. Frequency Figure 20. Capacitance vs. Source Voltage, Single Supply 4.5 4.0 D 3.5 VDD = +15V VSS = –15V pF) 3.0 TA = +25°C E ( NC 2.5 A T CI 2.0 PA S1 A C 1.5 S3 1.0 S2 0.50 S4 04779-031 –10 –8 –6 –4 –2 0 2 4 6 8 10 VBIAS (V) Figure 18. Off Capacitance vs. Source Voltage Rev. C | Page 11 of 16

ADG1204 Data Sheet TEST CIRCUITS V S D IDS VS 04779-020 Figure 21. On Resistance IS (OFF) ID (OFF) S D A A VS VD 04779-021 Figure 22. Off Leakage ID(ON) S D NC A NC = NO CONNECT VD 04779-022 Figure 23. On Leakage VDD VSS 0.1µF 0.1µF 3V ADDRESS A1VDD VSSS1 VS1 DRIVE (VIN)) 0V 50% 50% VS A0 S2 S3 S4 VS4 VOUT 90% 90% 2.4V EN D VOUT GND 3R0L0Ω C35LpF tTRANSITION tTRANSITION 04779-023 Figure 24. Address to Output Switching Times VDD VSS 0.1µF 0.1µF VDD VSS ADDRESS 3V VS 50Ω AA10 SSS321 VS1 DRIVE (VIN) 0V S4 2.4V EN D VOUT VOUT 80% 80% GND R30L0Ω C35LpF tBBM 04779-024 Figure 25. Break-Before-Make Time Delay VDD VSS 0.1µF 0.1µF 3V ENABLE A1VDD VSSS1 VS DRIVE (VIN) 0V 50% 50% A0 S2 S3 S4 OUTPUT VO 0.9VO 0.9VO EN D VOUT 0V VS 50Ω GND R30L0Ω C35LpF tON(EN) tOFF(EN) 04779-025 Figure 26. Enable-to-Output Switching Delay Rev. C | Page 12 of 16

Data Sheet ADG1204 VDD VSS VOUT ΔVOUT VDD VSS QINJ = CL ×ΔVOUT RS S D VOUT VIN SW OFF SW OFF VS 1CnLF DECODER SW ON GND SW ON A1A2 EN VIN SW OFF SW OFF 04779-026 Figure 27. Charge Injection VDD VSS VDD VSS 0.1µF 0.1µF 0.1µF 0.1µF NETWORK NETWORK VDD VSS ANALYZER ANALYZER VDD VSS VOUT RL S1 S 50Ω 50Ω 50Ω VS D R S2 50Ω D VOUT RL VS 50Ω GND GND OFF ISOLATION = 20 logVVOSUT 04779-027 CHANNEL-TO-CHANNEL CROSSTALK = 20 logVVOSUT 04779-029 Figure 28. Off Isolation Figure 30. Channel-to-Channel Crosstalk VDD VSS VDD VSS 0.1µF 0.1µF 0.1µF 0.1µF NETWORK AUDIO PRECISION VDD VSS ANALYZER VDD VSS RS S 50Ω S VS IN VS D D V p-p GND INSERTION LOSS = 20 logVOVUOTR5UW0TLΩIWTHIVTOOHUU STTW SIWTCITHCH 04779-028 VIN GND Figure 31. THD +R1 N0LkoΩise VOUT 04779-030 Figure 29. Bandwidth Rev. C | Page 13 of 16

ADG1204 Data Sheet TERMINOLOGY I C , C (On) DD D S The positive supply current. The on switch capacitance, measured with reference to ground. I C SS IN The negative supply current. The digital input capacitance. V (V) t (EN) D S ON The analog voltage on Terminal D and Terminal S. The delay between applying the digital control input and the output switching on. R ON The ohmic resistance between D and S. t (EN) OFF The delay between applying the digital control input and the R FLAT(ON) output switching off. Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified t TRANS analog signal range. The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one I (OFF) S address state to another. The source leakage current with the switch off. Charge Injection I (OFF) D A measure of the glitch impulse transferred from the digital The drain leakage current with the switch off. input to the analog output during switching. I , I (ON) D S Off Isolation The channel leakage current with the switch on. A measure of unwanted signal coupling through an off switch. V INL Crosstalk The maximum input voltage for Logic 0. A measure of unwanted signal that is coupled through from one V INH channel to another as a result of parasitic capacitance. The minimum input voltage for Logic 1. Bandwidth I (I ) INL INH The frequency at which the output is attenuated by −3 dB. The input current of the digital input. On Response C (OFF) S The frequency response of the on switch. The off switch source capacitance, which is measured with Insertion Loss reference to ground. The loss due to the on resistance of the switch. C (OFF) D Total Harmonic Distortion + Noise (THD + N) The off switch drain capacitance, which is measured with The ratio of the harmonic amplitude plus noise of the signal to reference to ground. the fundamental. Rev. C | Page 14 of 16

Data Sheet ADG1204 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.A20X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 3.10 0.30 3.00 SQ 0.23 PIN 1 2.90 0.18 INDICATOR PIN 1 0.50 10 12 INDICATOR BSC 9 1 EXPOSED 1.45 PAD 1.30 SQ 1.15 7 3 0.70 6 4 0.25 MIN TOP VIEW 0.60 BOTTOM VIEW 0.50 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WEED. 111808-A Figure 33. 12-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-12-4) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADG1204YRUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1204YRUZ-REEL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1204YRUZ-REEL7 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADG1204YCPZ-500RL7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP] CP-12-4 ADG1204YCPZ-REEL7 −40°C to +125°C 12-Lead Lead Frame Chip Scale Package [LFCSP] CP-12-4 1 Z = RoHS Compliant Part. Rev. C | Page 15 of 16

ADG1204 Data Sheet NOTES ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04779-0-3/16(C) Rev. C | Page 16 of 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADG1204YRUZ-REEL7 ADG1204YRUZ-REEL ADG1204YCPZ-500RL7 ADG1204YCPZ-REEL7 ADG1204YRUZ