Low Phase Noise, Fast Settling PLL Frequency Synthesizer Data Sheet ADF4193 FEATURES GENERAL DESCRIPTION New, fast settling, fractional-N PLL architecture The ADF4193 frequency synthesizer can be used to implement Single PLL replaces ping-pong synthesizers local oscillators in the upconversion and downconversion Frequency hop across GSM band in 5 µs with phase settled sections of wireless receivers and transmitters. Its architecture by 20 µs is specifically designed to meet the GSM/EDGE lock time 0.5° rms phase error at 2 GHz RF output requirements for base stations. It consists of a low noise, digital Digitally programmable output phase phase frequency detector (PFD), and a precision differential RF input range up to 3.5 GHz charge pump. There is also a differential amplifier to convert 3-wire serial interface the differential charge pump output to a single-ended voltage On-chip, low noise differential amplifier for the external voltage-controlled oscillator (VCO). Phase noise figure of merit: −216 dBc/Hz The Σ-Δ based fractional interpolator, working with the N Loop filter design possible using ADIsimPLL™ divider, allows programmable modulus fractional-N division. Qualified for automotive applications Additionally, the 4-bit reference (R) counter and on-chip APPLICATIONS frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop GSM/EDGE base stations (PLL) can be implemented if the synthesizer is used with an PHS base stations Instrumentation and test equipment external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures. FUNCTIONAL BLOCK DIAGRAM SDVDD DVDD1 DVDD2 DVDD3 AVDD1 VP1 VP2 VP3 RSET REFERENCE REFIN DOU×B2LER C O4-UBNITT ERR DIV÷ID2ER +FREPQHAUSEENCY CHARGE+ SCWPO1UT+ –DETECTOR PUMP – CPOUT– VDD SW2 HIGH Z DGND CMR LOCK DETECT DIFFERENTIAL AMPLIFIER – AIN– OUTPUT MUXOUT MUX RDIV + AIN+ NDIV AOUT N COUNTER SW3 FRACTIONAL INTERPOLATOR CLK 24-BIT RFIN+ DATA DATA RFIN– LE REGISTER FRACTION MODULUS INTEGER REG REG REG ADF4193 AGND1 AGND2 DGND1 DGND2 DGND3 SDGND SWGND 05328-001 Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADF4193 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register (R3) .............................................................. 19 Applications ....................................................................................... 1 Charge Pump Register (R4) ...................................................... 20 General Description ......................................................................... 1 Power-Down Register (R5) ....................................................... 21 Functional Block Diagram .............................................................. 1 Mux Register (R6) ...................................................................... 22 Revision History ............................................................................... 3 Programming .................................................................................. 23 Specifications ..................................................................................... 4 Worked Example ........................................................................ 23 Timing Characteristics ................................................................ 5 Spur Mechanisms ....................................................................... 23 Absolute Maximum Ratings ............................................................ 6 Power-Up Initialization ............................................................. 24 ESD Caution .................................................................................. 6 Changing the Frequency of the PLL and the Phase Look-Up Pin Configuration and Function Descriptions ............................. 7 Table ............................................................................................. 24 Typical Performance Characteristics ............................................. 9 Applications Information .............................................................. 26 Theory of Operation ...................................................................... 12 Local Oscillator for A GSM Base Station ................................ 26 Reference Input Section ............................................................. 12 Interfacing ................................................................................... 28 RF Input Stage ............................................................................. 12 PCB Design Guidelines for Chip Scale Package .................... 28 Register Map .................................................................................... 15 Outline Dimensions ....................................................................... 29 FRAC/INT Register (R0) ........................................................... 16 Ordering Guide .......................................................................... 29 MOD/R Register (R1) ................................................................ 17 Automotive Products ................................................................. 29 Phase Register (R2) .................................................................... 18 Rev. G | Page 2 of 29

Data Sheet ADF4193 REVISION HISTORY 1/15—Rev. F to Rev. G 6/06—Rev A. to Rev. B Moved Revision History Section ..................................................... 3 Changes to Table 1 ............................................................................ 3 Changes to Figure 3........................................................................... 7 Changes to Figure 32 ...................................................................... 18 Changes to PCB Design Guidelines for Chip Scale Changes to Power-Up Initialization Section ............................... 23 Package Section ............................................................................... 28 Changes to Timer Values for Tx Section and Timer Values for Deleted CP-32-2, Figure 40 ............................................................ 29 Rx Section ........................................................................................ 25 Updated Outline Dimensions ........................................................ 29 Changes to Ordering Guide ........................................................... 29 11/05—Rev 0. to Rev. A Updated Format ................................................................. Universal 3/13—Rev. E to Rev. F Changes to Features Section ............................................................ 1 Added CP-32-2 Package .................................................... Universal Changes to Table 1 ............................................................................ 3 Added Figure 40 .............................................................................. 28 Changes to Reference Input Section ............................................. 11 Changes to Ordering Guide ........................................................... 28 Changes to RF N Divider Section ................................................. 11 Changes to the Lock Detect Section ............................................. 13 2/13—Rev. D to Rev. E Changes to Figure 29 ...................................................................... 15 Changes to Phase Detector Frequency Parameter, Version C, Changes to the 8-Bit INT Value Section ...................................... 15 Table 1 ................................................................................................. 3 Changes to Figure 33 ...................................................................... 19 Changes to Worked Example Section ........................................... 22 Replaced Figure 35 .......................................................................... 21 Changes to Avoid Integer Boundary Channels Section ............. 24 Changes to the Σ-Δ and Lock Detect Modes Section ................ 21 Changes to the Power-Up Initialization Section ......................... 23 3/12—Rev. C to Rev. D Changes to Table 8 .......................................................................... 23 Changes to Noise Characteristics Parameter, Table 1 .................. 4 Changes to the Local Oscillator for a GSM Change to Table 4 .............................................................................. 6 Base Station Section ........................................................................ 25 Updated Outline Dimensions ........................................................ 28 Changes to the Timer Values for Rx Section ............................... 25 Changes to Ordering Guide ........................................................... 28 Changes to Figure 36 ...................................................................... 26 Updates to the Outline Dimensions ............................................. 28 1/11—Rev. B to Rev. C Changes to the Ordering Guide .................................................... 28 Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 3 4/05—Revision 0: Initial Version Changes to Table 2 ............................................................................ 4 Changes to Ordering Guide ........................................................... 28 Added Automotive Products Paragraph ...................................... 28 Rev. G | Page 3 of 29

ADF4193 Data Sheet SPECIFICATIONS AV = DV = SDV = 3 V ± 10%, V 1, V 2 = 5 V ± 10%, V 3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, R = 2.4 kΩ, dBm DD DD DD P P P SET referred to 50 Ω, T = T to T , unless otherwise noted. A MIN MAX Table 1. Parameter B Version1 C Version2 Unit Test Conditions/Comments RF CHARACTERISTICS RF Input Frequency (RF ) 0.4/3.5 0.4/3.5 GHz min/max See Figure 21 for input circuit IN RF Input Sensitivity −10/0 −10/0 dBm min/max Maximum Allowable Prescaler 470 470 MHz max Output Frequency3 REF CHARACTERISTICS IN REF Input Frequency 10/300 10/300 MHz min/max For f > 120 MHz, set REF/2 bit = 1. For f < IN 10 MHz, use a dc-coupled square wave REF Edge Slew Rate 300 300 V/µs min IN REF Input Sensitivity 0.7/V 0.7/V V p-p min/max AC-coupled IN DD DD 0 to V 0 to V V max CMOS-compatible DD DD REF Input Capacitance 10 10 pF max IN REF Input Current ±100 ±100 µA max IN PHASE DETECTOR Phase Detector Frequency 26 30 MHz max CHARGE PUMP I Up/Down CP High Value 6.6 6.6 mA typ With R = 2.4 kΩ SET Low Value 104 104 µA typ With R = 2.4 kΩ SET Absolute Accuracy 5 5 % typ R Range 1/4 1/4 kΩ min/max Nominally R = 2.4 kΩ SET SET I Three-State Leakage 1 1 nA typ CP I Up vs. Down Matching 0.1 0.1 % typ 0.75 V ≤ V ≤ V – 1.5 V CP CP P I vs. V 1 1 % typ 0.75 V ≤ V ≤ V – 1.5 V CP CP CP P I vs. Temperature 1 1 % typ 0.75 V ≤ V ≤ V – 1.5 V CP CP P DIFFERENTIAL AMPLIFIER Input Current 1 1 nA typ Output Voltage Range 1.4/(V3 − 0.3) 1.4/(V3 − 0.3) V min/max P P VCO Tuning Range 1.8/(V3 − 0.8) 1.8/(V3 − 0.8) V min/max P P Output Noise 7 7 nV/√Hz typ At 20 kHz offset LOGIC INPUTS V , Input High Voltage 1.4 1.4 V min IH V , Input Low Voltage 0.7 0.7 V max IL I , I , Input Current ±1 ±2 µA max INH INL C , Input Capacitance 10 10 pF max IN LOGIC OUTPUTS V , Output High Voltage V − 0.4 V − 0.4 V min I = 500 µA OH DD DD OH V , Output Low Voltage 0.4 0.4 V max I = 500 µA OL OL POWER SUPPLIES AV 2.7/3.3 2.7/3.3 V min/V max DD DV AV AV DD DD DD V1, V2 4.5/5.5 4.5/5.5 V min/V max AV ≤ V1, V2 ≤ 5.5 V P P DD P P V3 5.0/5.65 5.0/5.65 V min/V max V1, V2 ≤ V 3 ≤ 5.65 V P P P P I (AV + DV + SDV ) 27 35 mA max 22 mA typ DD DD DD DD I (V1 + V2) 27 30 mA max 22 mA typ DD P P I (V3) 30 35 mA max 24 mA typ DD P I Power-Down 10 10 µA typ DD Rev. G | Page 4 of 29

Data Sheet ADF4193 Parameter B Version1 C Version2 Unit Test Conditions/Comments SW1, SW2, and SW3 R (SW1 and SW2) 65 65 Ω typ ON R SW3 75 75 Ω typ ON NOISE CHARACTERISTICS Output 900 MHz4 −108 −108 dBc/Hz typ At 5 kHz offset and 26 MHz PFD frequency 1800 MHz5 −102 −102 dBc/Hz typ At 5 kHz offset and 13 MHz PFD frequency Phase Noise Normalized Phase Noise −216 −216 dBc/Hz typ At VCO output with dither off, PLL loop Floor (PN )6 bandwidth = 500 kHz SYNTH Normalized 1/f Noise (PN )7 −110 −110 dBc/Hz typ Measured at 10 kHz offset, normalized to 1 GHz 1_f 1 Operating temperature range is from −40°C to +85°C. 2 Operating temperature range is from −40°C to +105°C 3 The prescaler value is chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 fREFIN = 26 MHz; fSTEP = 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz. 5 fREFIN = 13 MHz; fSTEP = 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(fPFD). PNSYNTH = PNTOT − 10 log(fPFD) − 20 log(N). 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. TIMING CHARACTERISTICS AV = DV = 3 V ± 10%, V 1, V 2 = 5 V ± 10%, V 3 = 5.35 V ± 5%, AGND = DGND = GND = 0 V, R = 2.4 kΩ, dBm referred to DD DD P P P SET 50 Ω, T = T to T , unless otherwise noted. A MIN MAX Table 2. Parameter Limit (B Version)1 Limit (C Version) 2 Unit Test Conditions/Comments t 10 10 ns min LE setup time 1 t 10 10 ns min DATA to CLOCK setup time 2 t 10 10 ns min DATA to CLOCK hold time 3 t 15 15 ns min CLOCK high duration 4 t 15 15 ns min CLOCK low duration 5 t 10 10 ns min CLOCK to LE setup time 6 t 15 15 ns min LE pulse width 7 1 Operating temperature is from −40°C to +85°C. 2 Operating temperature is from −40°C to +105°C. t4 t5 CLK t2 t3 DATA (DMBS2B3) DB22 DB2 (CONTRDOBL1 BIT C2) (CONDTBR0O (LLS BBIT) C1) t7 LE t1 t6 LE 05238-002 Figure 2. Timing Diagram Rev. G | Page 5 of 29

ADF4193 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum A Ratings may cause permanent damage to the product. This is a Table 3. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational AV to GND −0.3 V to +3.6 V DD section of this specification is not implied. Operation beyond AV to DV , SDV −0.3 V to +0.3 V DD DD DD the maximum operating conditions for extended periods may V to GND −0.3 V to +5.8 V P affect product reliability. V to AV −0.3 V to +5.8 V P DD This device is a high performance RF integrated circuit with an Digital I/O Voltage to GND −0.3 V to V + 0.3 V DD ESD rating of <2 kV, and it is ESD sensitive. Proper precautions Analog I/O Voltage to GND −0.3 V to V + 0.3 V P need to be taken for handling and assembly. REF , RF , RF to GND −0.3 V to V + 0.3 V IN IN+ IN− DD Operating Temperature Range Transistor Count Industrial (B Version) −40°C to +85°C 75,800 (MOS), 545 (BJT). Operating Temperature Range −40°C to +105°C Automotive (W Version) Storage Temperature Range −65°C to +125°C ESD CAUTION Maximum Junction Temperature 150°C LFCSP θ Thermal Impedance 27.3°C/W JA (Paddle Soldered) Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 40 sec Rev. G | Page 6 of 29

Data Sheet ADF4193 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V3PAIN+CPOUT+SW1SWGNDSW2CPOUT–AIN– 21098765 33322222 CMR 1 24 VP2 AOUT 2 23 RSET ARRGSFFNWIIDNN13+– 3456 (NAToDOt PFto V4 SI1Ec9Wal3e) 22212109 ADVLEPGG1NNDD23 AVDD1 7 18 DATA DVDD1 8 17 CLK 910111213141516 D1GNDDV2DDREFIND2GNDDV3DDSDGNDSDVDDUXOUT N1.O TTHEES E:XPOSEDPAD MUST BE CONMNECTEDTOAGND. 05328-003 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CMR Common-Mode Reference Voltage for the Differential Amplifier’s Output Voltage Swing. Internally biased to three-fifths of V3. Requires a 0.1 μF capacitor to ground. P 2 A Differential Amplifier Output to Tune the External VCO. OUT 3 SW3 Fast-Lock Switch 3. Closed while SW3 timeout counter is active. 4 A 1 Analog Ground. This is the ground return pin for the differential amplifier and the RF section. GND 5 RF Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass IN− capacitor, typically 100 pF. 6 RF Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. IN+ 7 AV 1 Power Supply Pin for the RF Section. Nominally 3 V. A 100 pF decoupling capacitor to the ground plane should be DD placed as close as possible to this pin. 8 DV 1 Power Supply Pin for the N Divider. Should be the same voltage as AV 1. A 0.1 μF decoupling capacitor to ground DD DD should be placed as close as possible to this pin. 9 D 1 Ground Return Pin for DV 1. GND DD 10 DV 2 Power Supply Pin for the REF Buffer and R Divider. Nominally 3 V. A 0.1 μF decoupling capacitor to ground DD IN should be placed as close as possible to this pin. 11 REF Reference Input. This is a CMOS input with a nominal threshold of V /2 and a dc equivalent input resistance of IN DD 100 kΩ (see Figure 15). This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. 12 D 2 Ground Return Pin for DV 2 and DV 3. GND DD DD 13 DV 3 Power Supply Pin for the Serial Interface Logic. Nominally 3 V. DD 14 SD Ground Return Pin for the Σ-Δ Modulator. GND 15 SDV Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. A 0.1 μF decoupling capacitor to the ground plane DD should be placed as close as possible to this pin. 16 MUX Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference OUT frequency to be accessed externally (see Figure 35). 17 CLK Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 18 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOS input. 19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is selected by the three LSBs. 20 V1 Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, should be at the same voltage at V2. P P A 0.1 μF decoupling capacitor to ground should be placed as close as possible to this pin. 21 D 3 Ground Return Pin for V1. GND P 22 A 2 Ground Return Pin for V2. GND P Rev. G | Page 7 of 29

ADF4193 Data Sheet Pin No. Mnemonic Description 23 R Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at SET the R pin is 0.55 V. The relationship between I and R is SET CP SET I = 0.25/R CP SET So, with R = 2.4 kΩ, I = 104 µA. SET CP 24 V2 Power Supply Pin for the Charge Pump. Nominally 5 V, should be at the same voltage at V1. A 0.1 µF decoupling P P capacitor to ground should be placed as close as possible to this pin. 25 AIN− Differential Amplifier’s Negative Input Pin. 26 CP Differential Charge Pump’s Negative Output Pin. Should be connected to AIN− and the loop filter. OUT− 27 SW2 Fast Lock Switch 2. This switch is closed to SW while the SW1/SW2 timeout counter is active. GND 28 SW Common for SW1 and SW2 Switches. Should be connected to the ground plane. GND 29 SW1 Fast Lock Switch 1. This switch is closed to SW while the SW1/SW2 timeout counter is active. GND 30 CP Differential Charge Pump’s Positive Output Pin. Should be connected to AIN+ and the loop filter. OUT+ 31 AIN+ Differential Amplifier’s Positive Input Pin. 32 V3 Power Supply Pin for the Differential Amplifier. This can range from 5.0 V to 5.5 V. A 0.1 µF decoupling capacitor to P ground should be placed as close as possible to this pin. Also requires a 10 µF decoupling capacitor to ground. EP Exposed Pad. The exposed pad must be connected to AGND. Rev. G | Page 8 of 29

Data Sheet ADF4193 TYPICAL PERFORMANCE CHARACTERISTICS FREQ. UNIT GHzKEYWORD R 0 PARAM TYPES IMPEDANCE50 DATA FORMAT MA –5 FREQ. MAGS11 ANGS11 FREQ. MAGS11 ANGS11 4/5 PRESCALER 0.5 0.8897 –16.6691 2.3 0.67107 –75.8206 0.6 0.87693 –19.9279 2.4 0.66556 –77.6851 –10 0.7 0.85834 –23.561 2.5 0.6564 –80.3101 m) 8/9 PRESCALER 0.8 0.85044 –26.9578 2.6 0.6333 –82.5082 B 01..90 00..8831479148 ––3304..89240919 22..78 00..651947076 ––8857..35561233 EL (d –15 1.1 0.80229 –39.0436 2.9 0.5655 –89.7605 EV 1.2 0.78917 –42.3623 3.0 0.5428 –93.0239 L –20 1.3 0.77598 –46.322 3.1 0.51733 –95.9754 F IN 1.4 0.75578 –50.3484 3.2 0.49909 –99.1291 R 1.5 0.74437 –54.3545 3.3 0.47309 –102.208 –25 1.6 0.73821 –57.3785 3.4 0.45694 –106.794 1.7 0.7253 –60.695 3.5 0.44698 –111.659 11222.....89012 00000.....777661009736327698815947 –––––6677636038.....94774139045683525683 33334.....67890 00000.....4444432110541098775892553 –––––111111234475307.....9625982987615 05328-038 ––33500 1000 RFIN2 0F0R0EQUENC3Y0 0(M0Hz) 4000 500005328-005 Figure 4. S Parameter Data for the RF Input Figure 7. RF Input Sensitivity –30 –30 GSM900 Rx SETUP, 40kHz LOOP BW, DITHER OFF DCS1800 Tx SETUP, 60kHz LOOP BW, DITHER OFF –40 –40 RF = 1092.8MHz, FREF = 26MHz, MOD = 130 RF = 1842.6MHz, FREF = 13MHz, MOD = 65 –50 N = 42 4/130 –50 DSB INTEGRATED PHASE ERROR = 0.46° RMS –60 INTEGER BOUNDARY SPUR: –103dBc @ 800kHz –60 SIRENZA 1843T VCO Hz) –70 Hz) –70 c/ –80 c/ –80 B B E (d –90 E (d –90 S–100 S–100 OI OI N–110 N–110 E E AS–120 AS–120 H H P–130 P–130 –140 –140 –150 –150 ––117600 05328-006 ––117600 05328-007 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 5. SSB Phase Noise Plot at 1092.8 MHz (GSM900 Rx Setup) vs. Figure 8. SSB Phase Noise Plot at 1842.6 MHz (DCS1800 Tx Setup) Free Running VCO Noise –60 –60 DCS1800 Tx SETUP WITH DITHER OFF, DCS1800 Tx SETUP WITH DITHER OFF, 60kHz LOOP BW, 13MHz PFD. 60kHz LOOP BW, 13MHz PFD. MEASURED ON EVAL-ADF4193-EB1 BOARD MEASURED ON EVAL-ADF4193-EB1 BOARD –70 –70 400kHz SPURS @ 25C c) –80 c) –80 B B 600kHz SPURS @ 25C d d L ( L ( E E V –90 V –90 E E L L R R U U SP–100 SP–100 –110 –110 –120 400kHz SPURS @ 85C 05328-010 –120 600kHz SPURS @ 85C 05328-011 1846 1859 1872 1846 1859 1872 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. 400 kHz Fractional Spur Levels Across All DCS1800 Tx Channels Figure 9. 600 kHz Fractional Spur Levels Across All DCS1800 Tx Channels Over Two-Integer Multiples of the PFD Reference Over Two-Integer Multiples of the PFD Reference Rev. G | Page 9 of 29

ADF4193 Data Sheet 5 5 DCS1800 Tx SETUP, 60kHz LOOP BW. MEASURED ON EVAL-ADF4193-EB1 EVALUATION BOARD. TIMERS: ICP = 28, SW1/SW2, SW3 = 35. 4 4 FREQUENCY LOCK IN WIDE BW MODE @ 5s. VTUNE 3 3 CPOUT– V) CPOUT+ V) ( ( 2 2 VTUNE CPOUT– 1 DMCESA1S8U0R0E TDx OSENT EUVPA, L6-0AkDHFz4 L1O93O-PE BB1W. 1 CPOUT+ 0 ETFIRVMEAEQLRUUSAE:T NICICOPYN = LB O2O8CA, KSR WIDN.1 W/SIWDE2, BSWW 3M =O 3D5E. @ 4s. 05328-040 0 05328-041 –1 0 1 2 3 4 5 6 7 8 9 –1 0 1 2 3 4 5 6 7 8 9 TIME (s) TIME (s) Figure 10. VTUNE Settling Transient for a 75 MHz Jump from 1818 MHz to Figure 13. VTUNE Settling Transient for a 75 MHz Jump Down from 1893 MHz to 1893 MHz with Sirenza 1843T VCO 1818 MHz, the Bottom of the Allowed Tuning Range with the Sirenza 1843T VCO 50 50 DCS1800 Tx SETUP, 60kHz LOOP BW. DCS1800 Tx SETUP, 60kHz LOOP BW. 40 MEASURED ON EVAL-ADF4193-EB1 40 MEASURED ON EVAL-ADF4193-EB1 EVALUATION BOARD WITH AD8302 EVALUATION BOARD WITH AD8302 PHASE DETECTOR. PHASE DETECTOR. 30 TIMERS: ICP = 28, SW1/SW2, SW3 = 35. 30 TIMERS: ICP = 28, SW1/SW2, SW3 = 35. s) +25C PEAK PHASE ERROR < 5 @ 17.8s s) +25C PEAK PHASE ERROR < 5 @ 19.2s e 20 e 20 e e gr gr De 10 De 10 R ( R ( O 0 O 0 R R R R HASE E ––1200 –40C +85C HASE E ––1200 –40C +85C P P –30 –30 ––5400 05328-008 ––5400 05328-009 –5 0 5 10 15 20 25 30 35 40 45 –5 0 5 10 15 20 25 30 35 40 45 TIME (s) TIME (s) Figure 11. Phase Settling Transient for a 75 MHz Jump from 1818 MHz to Figure 14. Phase Settling Transient for a 75 MHz Jump from 1893 MHz to 1893 MHz (VTUNE 1.8 V to 3.7 V with Sirenza 1843T VCO) 1818 MHz (VTUNE = 3.7 V to 1.8 V with Sirenza 1843T VCO) 8 2.0 6 ICPOUT+ P, ICPOUT – P 1.5 5 VVPP13 == V5.P52V = 5V VCMR = 3.3V AOUT (= VTUNE) 4 IUP= | ICPOUT+ P | + | ICPOUT – N | 1.0 IDOWN= | ICPOUT– P | + | ICPOUT + N | 4 2 0.5 %) (mA)CP 0 CHARGE PUMP MISMATCH (%) 0 MATCH ( (V) 3 CPOUT+ (= AIN+) I S –2 NORMAL OPERATING RANGE –0.5MI 2 –4 –1.0 1 ––86 ICPOUT+ N, ICPOUT – N ––21..05 05328-012 0 CPOUT– (= AIN–) 05328-013 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1780 1800 1820 1840 1860 1880 1900 1920 1940 CPOUT+ / CPOUT – VOLTAGE (V) FREQUENCY (MHz) Figure 12. Differential Charge Pump Output Compliance Range and Figure 15. Tuning Range with a Sirenza 1843T VCO and a 5.5 V Differential Charge Pump Mismatch with VP1 = VP2 = 5 V Amplifier Power Supply Voltage Rev. G | Page 10 of 29

Data Sheet ADF4193 1000 1.8 MEASURED USING AD8302 PHASE DETECTOR Y-AXIS SCALE: 10mV/DEGREE RF = 1880MHz, PFD = 26MHz, MOD = 130 1.5 X-AXIS SCALE: 2.77/STEP V) T ( U Hz) 100 OUTP 1.2 E (nV/ CTOR 0.9 S E NOI 10 7nV/ Hz @ 20kHz E DET 0.6 S A H P 0.3 1 05328-042 0 05328-044 1k 10k 100k 1M 10M 0 13 26 39 52 65 78 91 104 117 130 FREQUENCY (Hz) PHASE CODE Figure 16. Voltage Noise Density Measured at the Differential Amplifier Output Figure 18. Detected RF Output Phase for Phase Code Sweep from 0 to MOD 100 ADF4193 SW3 104MHz EVAL BOARD 90 5dBm SW1/ +85°C REFIN RFOUT 80 SW2 +85°C +25°C 1805 1880MHz 70 +25°C INPA 60 –40°C Ω) AGILENT TEKTRONIX (ON 50 –40°C SHIPG8. 6G6E3AN. VPHS OSCTILDLSO71S4CLOPE R 40 TUNING VOLTAGE RANGE INPB AD8302 EVB 30 10MHz EXT REF 1880MHz 20 R&S 1000 1 D2RAIN VOLT3AGE (V) 4 5 05328-014 IRNETFEERRVEANLC BEE CTYWCELEENS R(50Sµ ISWsG)M R.F TGIOT0EE3RNS C. SOHHOEURLEDN TB EP HAA MSUEL MTEIPALSEU ORFE MMEONDTS 05328-045 Figure 17. On Resistance of Loop Filter Switches SW1/SW2 and SW3 Figure 19. Test Setup for Phase Lock Time Measurement Rev. G | Page 11 of 29

ADF4193 Data Sheet THEORY OF OPERATION The ADF4193 is targeted at GSM base station requirements, RF INPUT STAGE specifically to eliminate the need for ping-pong solutions. It The RF input stage is shown in Figure 21. It is followed by a works based on fast lock, using a wide loop bandwidth during a 2-stage limiting amplifier to generate the CML clock levels frequency change and narrowing the loop bandwidth once needed for the prescaler. Two prescaler options are selectable: a frequency lock is achieved. Widening the loop bandwidth is 4/5 and an 8/9. The 8/9 prescaler is selected for N divider values achieved by increasing the charge pump current. Switches are greater than 80. included to change the loop filter component values to maintain stability with the changing charge pump current. The narrow BIAS 1.6V AVDD loop bandwidth ensures that phase noise and spur specifications GENERATOR are met. A differential charge pump and loop filter topology are 500 500 used to ensure that the fast lock time benefit from widening the loop bandwidth is maintained when the loop is restored to RFIN+ narrow bandwidth mode for normal operation. REFERENCE INPUT SECTION RFIN– The reference input stage is shown in Figure 20. Switches S1 and Sd2o warne, nSo3 rims callolys ecdlo, saendd, San1 da nSd3 iSs2 n aorrem oaplelyn eodp eton .e Dnsuurrien gth paot wer- AGND 05328-017 Figure 21. RF Input Stage there is no loading of the REF pin. The falling edge of REF is IN IN RF N Divider the active edge at the positive edge triggered PFD. The RF N divider allows a fractional division ratio in the PLL POWER-DOWN CONTROL feedback path. The integer and fractional parts of the division are programmed using separate registers, as shown in Figure 22 NC 100k and described in the INT, FRAC, and MOD Relationship S2 REFIN NC TO R COUNTER section. Integer division ratios from 26 to 255 are allowed and a BUFFER S1 third-order, Σ-Δ modulator interpolates the fractional value NO S3 05328-016 between the integer steps. Figure 20. Reference Input Stage RF N DIVIDER N = INT + FRAC/MOD FROM RF R Counter and Doubler INPUT STAGE TO PFD N COUNTER The 4-bit R counter allows the input reference frequency to be THIRD-ORDER divided down to produce the reference clock to the phase FRACTIONAL INTERPOLATOR frequency detector (PFD). A toggle flip-flop can be optionally inserted after the R counter to give a further divide-by-2. Using INT MOD FRAC this option has the additional advantage of ensuring that the REG REG VALUE PgiFvDes rtehfee rmenacxeim cluomck sheapsa raa 5ti0o/n5 0b emtwareke-ns pthacee f arastt iloo.c Tkh tiism reart io 05328-018 clock, which is generated off the falling edge of the PFD Figure 22. Fractional-N Divider reference, and the rising edge, which is the active edge in the INT, FRAC, and MOD Relationship PFD. It is recommended that this toggle flip-flop be enabled for The INT, FRAC, and MOD values, programmed through the all even R divide values greater than 2. It must be enabled if serial interface, make it possible to generate RF output frequencies dividing down a REF frequency that is greater than 120 MHz. IN that are spaced by fractions of the PFD reference frequency. An optional doubler before the 4-bit R counter can be used for The N divider value, shown inside the brackets of the following low REFIN frequencies, up to 20 MHz. With these programmable equation for the RF VCO frequency (RFOUT), is made up of an options, reference division ratios from 0.5 to 30 between REFIN integer part (INT) and a fractional part (FRAC/MOD): and the PFD are possible. RF = F × [INT + (FRAC/MOD)] OUT PFD where: RF is the output frequency of the external VCO. OUT F is the PFD reference frequency. PFD Rev. G | Page 12 of 29

Data Sheet ADF4193 The value of MOD is chosen to give the desired channel step NMOS current sinks in through CP , which decreases the OUT+ with the available reference frequency. Thereafter, program the (CP , CP ) differential voltage. The charge pump up/ OUT+ OUT− INT and FRAC words for the desired RF output frequency. See down matching is improved by an order of magnitude over the the Worked Example section for more information. conventional single-ended charge pump that depended on the matching of two different device types. The up/down matching PFD and Charge Pump in this structure depends on how a PMOS matches a PMOS and The PFD takes inputs from the R divider and N divider and an NMOS matches an NMOS. produces up and down outputs with a pulse width difference proportional to the phase difference between the inputs. The VBIAS P charge pump outputs a net up or down current pulse of a width P P equal to this difference, to pump up or pump down the voltage UP DOWN that is integrated onto the loop filter, which in turn increases or CPOUT+ CPOUT– decreases the VCO output frequency. If the N divider phase lags the R divider phase, a net up current pulse is produced that increases the VCO frequency (and thus the phase). If the N divider phase leads the R divider edge, then a net down pulse is produced to reduce the VCO frequency and phase. Figure 23 is DOWN UP a simplified schematic of the PFD and charge pump. The charge VBIAS N pump is made up of an array of 64 identical cells, each of which N N is fully differential. All 64 cells are active during fast lock, but 05328-035 only one is active during normal operation. Because a single- Figure 24. Differential Charge Pump Cell with External Loop Filter Components ended control voltage is required to tune the VCO, an on-chip, Fast Lock Timeout Counters differential-to-single-ended amplifier is provided for this purpose. Timeout counters, clocked at one quarter the PFD reference In addition, because the phase-lock loop only controls the frequency, are provided to precisely control the fast locking differential voltage generated across the charge pump outputs, operation (see Figure 25). Whenever a new frequency is an internal common-mode feedback (CMFB) loop biases the programmed, the fast lock timers start and the PLL locks into charge pump outputs at a common-mode voltage of approximately wide BW mode with the 64 identical 100 μA charge pump cells 2 V. active (6.4 mA total). When the ICP counter times out, the charge pump current is reduced to 1× by deselecting cells in D Q CPOUT+ binary steps over the next six timer clock cycles, until just one R DIVIDER 100 μA cell is active. The charge pump current switching from CLR 6.4 mA to 100 μA equates to an 8-to-1 change in loop bandwidth. CHPUAMRGPE CMFB The loop filter must be changed to ensure stability when this ARRAY [64:1] happens. That is the job of the SW1, SW2, and SW3 switches. The application circuit (shown in Figure 36) shows how they can be CLR used to reconfigure the loop filter time constants. The application D Q CPOUT– circuits close to short out external loop filter resistors during fast N DIVIDER EN[64:1] 05328-019 ltoimcke acnodn ostpaennt sw thoe tnh tehire inr ocromunatle vras ltuimese f oour tt htoe r1e0st0o μreA t hceh afirlgteer Figure 23. PFD and Differential Charge Pump Simplified Schematic pump current. Because it takes six timer clock cycles to reduce Differential Charge Pump the charge pump current to 1×, it is recommended that both The charge pump cell (see Figure 24) has a fully differential switch timers be programmed to the value of the ICP timer + 7. design for best up-to-down current matching. Good matching WRITE START TO R0 is essential to minimize the phase offset created when switching the charge pump current from its high value (in fast lock mode) ICP SW1/SW2 SW3 TIMEOUT TIMEOUT TIMEOUT to its nominal value (in normal mode). COUNTER COUNTER COUNTER To pump up, the up switches are on and PMOS current is FPFD ÷4 SW3 sourced out through CP ; this increases the voltage on the OUT+ CHARGE PUMP external loop filter capacitors connected to CPOUT+. Similarly, ENABLE LOGIC AOUT the NMOS current sink on CPOUT− decreases the voltage on the SW1 SW2 tehxete drnifafel rleonotpia fli lvtoerlt acagpe abceittowrese cno CnnPeOcUtTe+d a ntod CCPPOOUUTT−−. iTnhcerereafsoerse. , EN[64:1] SWGND 05328-036 To pump down, PMOS current sources out through CP and OUT− Figure 25. Fast Lock Timeout Counters Rev. G | Page 13 of 29

ADF4193 Data Sheet Differential Amplifier DVDD The internal, low noise, differential-to-single-ended amplifier is LOGIC LOW used to convert the differential charge pump output to a single- SERIAL DATA OUTPUT R DIVIDER OUTPUT ended control voltage for the tuning port of the VCO. Figure 26 shows a simplified schematic of the differential amplifier. The N DIVIDER OUTPUT MUX CONTROL MUXOUT THREE-STATE OUTPUT output voltage is equal to the differential voltage, offset by the TIMER OUTPUTS voltage on the CMR pin, according to DIGITAL LOCK DETECT V = (V − V ) + V LOGIC HIGH AOUT AIN+ AIN− CMR VThP3e, CthMe Rd iofffefrseent tvioallt aamgep ilsi fiinetre prnowalelyr bsuiapspeldy tvoo tlthargeee,- afisf tshhso owfn in NNOOTTE A:LL MUXOUT MODES SHOWN REFER TO MUX REGISTERDGND 05328-021 Figure 26. Connect a 0.1 µF capacitor to ground to the CMR pin Figure 27. MUXOUT Circuit to roll off the thermal noise of the biasing resistors. Lock Detect As can be seen in Figure 15, the differential amplifier output MUX can be programmed to provide a digital lock detect OUT voltage behaves according to the previous equation over a 4 V signal. Digital lock detect is active high. Its output goes high if range from approximately 1.2 V minimum up to VP3 − 0.3 V. there are 40 successive PFD cycles with an input error of less However, fast settling is guaranteed only over a tuning voltage than 3 ns. For reliable lock detect operation with RF frequencies range from 1.8 V up to VP3 − 0.8 V. This is to allow sufficient <2 GHz, it is recommended that this threshold be increased to room for overshoot in the PLL frequency settling transient. 10 ns by programming Register R6. The digital lock detect goes Noise from the differential amplifier is suppressed inside the low again when a new channel is programmed or when the PLL bandwidth. For loop bandwidths >20 kHz, the 1/f noise has error at the PFD input exceeds 30 ns for one or more cycles. a negligible effect on the PLL output phase noise. Outside the Input Shift Register loop bandwidth, the differential amplifier’s noise FM modulates The ADF4193 serial interface section includes a 24-bit input the VCO. The passive filter network following the differential shift register. Data is clocked in MSB first on each rising edge amplifier, shown in Figure 36, suppresses this noise contribution of CLK. Data from the shift register is latched into one of eight to below the VCO noise from offsets of 400 kHz and above. control registers, R0 to R7, on the rising edge of latch enable This network has a negligible effect on lock time because it is (LE). The destination register is determined by the state of bypassed when SW3 is closed while the loop is locking. the three control bits (Control Bit C3, Control Bit C2, and AIN– Control Bit C1) in the shift register. The three LSBs are Bit DB2, Bit DB1, and Bit DB0, as shown in the timing diagram of Figure 2. 500Ω 500Ω AOUT The truth table for these bits is shown in Table 5. Figure 28 shows a summary of how the registers are programmed. VP3 AIN+ 20kΩ Table 5. C3, C2, and C1 Truth Table CMR 500Ω 500Ω Control Bits 30kΩ C0. 1EµXFT = 05328-020 C0 3 C0 2 C0 1 NFRaAmCe/I NT RR0e gister Figure 26. Differential Amplifier Block Diagram 0 0 1 MOD/R R1 0 1 0 Phase R2 MUX and Lock Detect OUT 0 1 1 Function R3 The output multiplexer on the ADF4193 allows the user to 1 0 0 Charge Pump R4 access various internal points on the chip. The state of MUX OUT 1 0 1 Power-Down R5 is controlled by M4 to M1 in the MUX register. Figure 35 shows 1 1 0 Mux R6 the full truth table. Figure 27 shows the MUX section in OUT 1 1 1 Test Mode R7 block diagram form. Rev. G | Page 14 of 29

Data Sheet ADF4193 REGISTER MAP FRAC/INT REGISTER (R0) D E V SER 8-BIT RF INT VALUE 12-BIT RF FRAC VALUE COBNITTRSOL E R DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3 (0) C2 (0) C1 (0) MOD/R REGISTER (R1) DBB DBB DBB DBB DBB CP ADJ REF/2 RESERVED PRESCALER DOUBLERENABLE 4C-OBIUTN RTFE RR 12-BIT MODULUS COBNITTRSOL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F5 F4 0 F2 F1 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3 (0) C2 (0) C1 (1) PHASE REGISTER (R2) D DBB E RV 12-BIT PHASE CONTROL E BITS S E R DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3 (0) C2 (1) C1 (0) FUNCTION REGISTER (R3) RESERVED CPO GND RESERVED PFDPOLARITY COBNITTRSOL DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 F3 1 F1 C3 (0) C2 (1) C1 (1) CHARGE PUMP REGISTER (R4) RESERVED 9-BIT TIMEOUT COUNTER STEIMLEECRT COBNITTRSOL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 C9 C8 C7 C6 C5 C4 C3 C2 C1 F2 F1 C3 (1) C2 (0) C1 (0) POWER-DOWN REGISTER (R5) PDDIFF AMP PDCHARGEPUMP CP3-STATE COUNTERRESET COBNITTRSOL DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F5 F4 F3 F2 F1 C3 (1) C2 (0) C1 (1) MUX REGISTER (R6) SIGMAAN-DDELTA RESERVED MUXOUT COBNITTRSOL LOCK DETECT MODES DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M13 M12 M11 M10 0 0 0 0 0 M4 M3 M2 M1 C3 (1) C2 (1) C1 (0) TEST MODE REGISTER (R7) RESERVED COBNITTRSOL DBB = DOUBLE BUFFERED BIT(S) DB015 DB014 DB013 DB012 DB011 DB010 DB09 DB08 DB07 DB06 DB05 DB04 DB03 CD3B (21) CD2B (11) CD1B (01) 05328-022 Figure 28. Register Map Rev. G | Page 15 of 29

ADF4193 Data Sheet FRAC/INT REGISTER (R0) D E V SER 8-BIT RF INT VALUE 12-BIT RF FRAC VALUE COBNITTRSOL E R DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3 (0) C2 (0) C1 (0) F12 F11 F10 F3 F2 F1 FRACTIONAL VALUE (FRAC) 0 0 0 .......... 0 0 0 0 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 0 = < FRAC < MOD N8 N7 N6 N5 N4 N3 N2 N1 INTEGER VALUE (INT) 0 0 0 1 1 0 1 0 26 . . . . . . . . . . . . . . . . . . .1 .1 .1 .1 .1 .1 .1 .1 .255 05328-023 Figure 29. FRAC/INT Register (R0) R0, the FRAC/INT register, is used to program the synthesizer Control Bits output frequency. On the next PFD cycle following a write to The three LSBs, Control Bit C3, Control Bit C2, and Control Bit C1, R0, the N divider section is updated with the new INT and should be set to 0, 0, 0, respectively, to select R0, the FRAC/INT FRAC values. At the same time, the PLL automatically enters register. fast lock mode and the charge pump current is increased to its Reserved Bit maximum value and stays at this value until the ICP timeout counter times out, and switches SW1, SW2, and SW3 closed Bit DB23 is reserved and must be set to 0. and remains closed until the SW1, SW2, and SW3 timeout 8-Bit INT Value counters time out. These eight bits set the INT value, which determines the integer Once all registers are programmed during the initialization part of the feedback division factor. All integer values from 26 sequence (see Table 8), all that is required thereafter to program to 255 are allowed. See the Worked Example section. a new channel is a write to R0. However, as described in the 12-Bit FRAC Value Programming section, it can also be desirable to program R1 The 12 FRAC bits set the numerator of the fraction that is input and R2 register settings on a channel-by-channel basis. These to the Σ-Δ modulator. This, along with INT, specifies the new settings are double buffered by the write to R0. This means frequency channel that the synthesizer locks to, as shown in the that while the data is loaded through the serial interface on the Worked Example section. FRAC values from 0 to MOD − 1 respective R1 and R2 write cycles, the synthesizer is not updated cover channels over a frequency range equal to the PFD reference with their data until the next write to Register R0. frequency. Rev. G | Page 16 of 29

Data Sheet ADF4193 MOD/R REGISTER (R1) CPADJ REF/2 RESERVED PRESCALER DOUBLERENABLE R 4C-OBUITN RTFER 12-BIT MODULUS COBNITTRSOL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F5 F4 0 F2 F1 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3 (0) C2 (0) C1 (1) F4 REF/2 0 DISABLE 1 ENABLE F2 PRESCALER F1 DOUBLER ENABLE M12 M11 M10 M3 M2 M1 INTERPOLATOR MODULUS VALUE (MOD) 0 4/5 0 DOUBLER DISABLED 0 0 0 .......... 1 0 1 13 1 8/9 1 DOUBLER ENABLED 0 0 0 .......... 1 1 0 14 0 0 0 .......... 1 1 1 15 F5 CP ADJ . . . .......... . . . . . . . .......... . . . . 0 NOMINAL 1 ADJUSTED . . . .......... . . . . 1 1 1 .......... 1 0 0 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 R4 R3 R2 R1 RF R COUNTER DIVIDE RATIO 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 . . . . . . . . . . . . . . . 1 1 0 0 12 111 111 011 101 111345 05328-024 Figure 30. MOD/R Register (R1) This register is used to set the PFD reference frequency and the Reserved Bit channel step size, which is determined by the PFD frequency Reserved Bit DB21 must be set to 0. divided by the fractional modulus. Note that the MOD, R Doubler Enable counter, REF/2, CP ADJ, and doubler enable bits are double buffered. They do not take effect until the next write to R0 Setting this bit to 1 inserts a frequency doubler between REFIN (FRAC/INT register) is complete. and the 4-bit R counter. Setting this bit to 0 bypasses the doubler. Control Bits 4-Bit RF R Counter With C3, C2, and C1 set to 0, 0, 1, respectively, the MOD/R It allows the REFIN frequency to be divided down to produce the register (R1) is programmed. reference clock to the PFD. All integer values from 1 to 15 are allowed. See the Worked Example section. CP ADJ 12-Bit Interpolator Modulus When this bit is set to 1, the charge pump current is scaled up 25% from its nominal value on the next write to R0. When this For a given PFD reference frequency, the fractional deno- bit is set to 0, the charge pump current stays at its nominal value minator or modulus sets the channel step resolution at the on the next write to R0. See the Programming section for more RF output. All integer values from 13 to 4095 are allowed. information on how this feature can be used. See the Programming section for additional information and guidelines for selecting the value of MOD. REF/2 Setting this bit to 1 inserts a divide-by-2, toggle flip-flop between the R counter and PFD, which extends the maximum REF IN input rate. Rev. G | Page 17 of 29

ADF4193 Data Sheet PHASE REGISTER (R2) D E V ER 12-BIT PHASE COBNITTRSOL S E R DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C3 (0) C2 (1) C1 (0) P12 P11 P10 P3 P2 P1 PHASE VALUE1 0 0 0 .......... 0 0 0 0 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 10 1= < PHAS40E9 V5ALUE < MOD 05328-025 Figure 31. Phase Register (R2) 12-Bit Phase If it is desired to keep the output at the same phase offset with respect to the reference, each time that particular output The phase word sets the seed value of the Σ-Δ modulator. It can frequency is programmed, then the interval between writes to be programmed to any integer value from 0 to MOD. As the R0 must be an integer multiple of MOD reference cycles. phase word is swept from 0 to MOD, the phase of the VCO output sweeps over a 360° range in steps of 360°/MOD. If it is desired to keep the outputs of two ADF4193-based synthesizers phase coherent with each other, but not necessarily Note that the phase bits are double buffered. They do not take with their common reference, then it is only required to ensure effect until the LE of the next write to R0 (FRAC/INT register). that the write to R0 on both chips is performed during the same Therefore, if it is desired to change the phase of the VCO output reference cycle. The interval between R0 writes in this case does frequency, it is necessary to rewrite the INT and FRAC values to not have to be an integer multiple of the MOD cycles. R0, following the write to R2. Reserved Bit The output of a fractional-N PLL can settle to any one of the MOD possible phase offsets with respect to the reference, where The reserved bit, Bit DB15, should be set to 0. MOD is the fractional modulus. Rev. G | Page 18 of 29

Data Sheet ADF4193 FUNCTION REGISTER (R3) RESERVED CPO GND RESERVED PFDPOLARITY COBNITTRSOL DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 F3 1 F1 C3 (0) C2 (1) C1 (1) F1 PFD POLARITY 0 NEGATIVE 1 POSITIVE F3 CPO GND 01 CNPOOR/MCAPLO GND 05328-026 Figure 32. Function Register (R3) R3, the function register (C3, C2, C1 set to 0, 1, 1, respectively), PFD Polarity only needs to be programmed during the initialization sequence This bit should be set to 1 for positive polarity and set to 0 for (see Table 8). negative polarity. CPO GND Reserved Bits When the CPO GND bit is low, the charge pump outputs The Bit DB15 to Bit DB6 are reserved bits and should be are internally pulled to ground. This is invoked during the programmed to hex code 001, and Reserved Bit DB4 should be initialization sequence to discharge the loop filter capacitors. set to 1. For normal operation, this bit should be high. Rev. G | Page 19 of 29

ADF4193 Data Sheet CHARGE PUMP REGISTER (R4) RESERVED 9-BIT TIMEOUT COUNTER STEIMLEECRT COBNITTRSOL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 C9 C8 C7 C6 C5 C4 C3 C2 C1 F2 F1 C3 (1) C2 (0) C1 (0) F2 F1 TIMER SELECT 0 0 SW1/SW2 0 1 SW3 1 0 ICP 1 1 NOT USED C9 C8 C7 C3 C2 C1 TIMEOUT COUNTER xPFD CYCLES DELAY µs1 0 0 0 .......... 0 0 0 0 0 0 0 0 0 .......... 0 0 1 1 4 0.15 0 0 0 .......... 0 1 0 2 8 0.30 0 0 0 .......... 0 1 1 3 12 0.46 . . . .......... . . . . . . . . . .......... . . . . . . . . . .......... . . . . . . 1 1 1 .......... 1 0 0 508 2032 78.15 1 1 1 .......... 1 0 1 509 2036 78.30 1 1 1 .......... 1 1 0 510 2040 78.46 1 1 1 .......... 1 1 1 511 20441DELAY WITH7 286.6M1Hz PFD 05328-027 Figure 33. Charge Pump Register (R4) Reserved Bits Table 6. Recommended Values for a GSM Tx LO Bit DB23 to Bit DB14 are reserved and should be set to hex Time (μs) with code 001 for normal operation. Timer Select Timeout Counter Value PFD = 13 MHz 10 ICP 28 8.6 9-Bit Timeout Counter 01 SW1/2 35 10.8 These bits are used to program the fast lock timeout counters. 00 SW3 35 10.8 The counters are clocked at one-quarter the PFD reference frequency, therefore, their time delay scales with the PFD On each write to R0, the timeout counters start. Switch SW3 frequency according to closes until the SW3 counter times out. Similarly, switches SW1/SW2 close until the SW1/SW2 counter times out. When Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency) the ICP counter times out, the charge pump current is ramped For example, if 35 were loaded with timer select (00) with a down from 64× to 1× in six binary steps. It is recommended 13 MHz PFD, then SW1/SW2 would be switched after that the SW1, SW2, and SW3 timeout counter values are set (35 × 4)/13 MHz = 10.8 μs equal to the ICP timeout counter value plus 7, as in the example of Table 6. Timer Select These two address bits select the timeout counter to be programmed. Note that to set up the ADF4193 correctly requires setup of these three timeout counters; therefore, three writes to this register are required in the initialization sequence. Table 6 shows example values for a GSM Tx synthesizer with a 60 kHz final loop BW. See the Applications section for more information. Rev. G | Page 20 of 29

Data Sheet ADF4193 POWER-DOWN REGISTER (R5) DIFFP DAMP PDCHARGEPUMP CP3-STATE COUNTERRESET COBNITTRSOL DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F5 F4 F3 F2 F1 C3 (1) C2 (0) C1 (1) F1 COUNTER RESET 0 NORMAL OPERATION 1 COUNTER RESET CHARGE PUMP F2 3-STATE 0 NORMAL OPERATION 1 3-STATE ENABLED CHARGE PUMP F3 POWER-DOWN 0 DISABLED 1 ENABLED DIFF AMP F5F4 POWER-DOWN 01 01 DENISAABBLLEEDD 05328-028 Figure 34. Power-Down Register (R5) R5, the power-down register (C3, C2, C1 set to 1, 0, 1, respectively) For normal operation, Bit DB5 should be set to 0, followed by a can be used to software power down the PLL and differential write to R0. amplifier sections. After power is initially applied, there must be CP Three-State writes to R5 to clear the power-down bits and to R2, R1, and R0 When this bit is set high, the charge pump outputs are put into before the ADF4193 comes out of power-down. three-state. With the bit set low, the charge pump outputs are Power-Down Differential Amplifier enabled. When Bit DB6 and Bit DB7 are set high, the differential Counter Reset amplifier is put into power-down. When Bit DB6 and Bit DB7 When this bit is set to 1, the counters are held in reset. For normal are set low, normal operation is resumed. operation, this bit should be 0, followed by a write to R0. Power-Down Charge Pump Setting Bit DB5 high activates a charge pump power-down and the following events occur:  All active dc current paths are removed, except for the differential amplifier.  The R and N divider counters are forced to their load state conditions.  The charge pump is powered down with its outputs in three- state mode.  The digital lock detect circuitry is reset.  The RFIN input is debiased.  The reference input buffer circuitry is disabled.  The serial interface remains active and capable of loading and latching data. Rev. G | Page 21 of 29

ADF4193 Data Sheet MUX REGISTER (R6) SIGMAAN-DDELTA RESERVED MUXOUT COBNITTRSOL LOCK DETECT MODES DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M13 M12 M11 M10 0 0 0 0 0 M4 M3 M2 M1 C3 (1) C2 (1) C1 (0) M13 M12 M11 M10 SIGMA-DELTA MODES M4 M3 M2 M1 MUXOUT 0 0 0 0 INIT STATE, DITHER OFF, 0 0 0 0 3-STATE 3ns LOCK DETECT THRESHOLD 0 0 0 1 DIGITAL LOCK DETECT 0 0 1 1 DITHER ON 0 0 1 0 N DIVIDER OUTPUT 1 0 0 1 10ns LOCK DETECT THRESHOLD 0 0 1 1 LOGIC HIGH ALL OTHER STATES RESERVED 0 1 0 0 R COUNTER 0 1 0 1 RESERVED 0 1 1 0 SERIAL DATA OUT 0 1 1 1 LOGIC LOW 1 0 0 0 R DIVIDER/2 OUTPUT 1 0 0 1 N DIVIDER/2 OUTPUT 1 0 1 0 RESERVED 1 0 1 1 RESERVED 1 1 0 0 ICP TIMEOUT SIGNAL 1 1 0 1 SW1/2 TIMEOUT SIGNAL 11 11 11 01 SRWES3E TRIMVEEDOUT SIGNAL 05328-029 Figure 35. MUX Register (R6) With C3, C2, and C1 set to 1, 1, 0, respectively, the MUX MUX Modes OUT register is programmed. These bits control the on-chip multiplexer. See Figure 35 for the Σ-Δ and Lock Detect Modes truth table. This pin is useful for diagnosis because it allows the user to look at various internal points of the chip, such as the Bit DB15 to Bit DB12 are used to reconfigure certain PLL R divider and INT divider outputs. operating modes. In the initialization sequence after power is applied to the chip, the four bits must first be programmed to In addition, it is possible to monitor the programmed timeout all zeros. This initializes the PLL to a known state with dither counter intervals on MUX . For example, if the ICP timeout OUT off in the Σ-Δ modulator and a 3 ns PFD error threshold in the counter was programmed to 65 (with a 26 MHz PFD), then lock detect circuit. following the next write to R0, a pulse width of 10 μs would be observed on the MUX pin. To turn on dither in the Σ-Δ modulator, an additional write OUT should be made to Register R6 to program bits [DB15:DB12] = Digital lock detect is available via the MUX pin. OUT [0011]. However, for lowest noise operation, it is best to leave dither off. To change the lock detect threshold from 3 ns to 10 ns, a separate write to R6 should be performed to program bits [DB15:DB12] = [1001]. This should be done for reliable lock detect operation when the RF frequency is <2 GHz. A write to R6 that programs bits [DB15:DB12] = [0000] returns operation to the default state with both dither off and a 3 ns lock detect threshold. Reserved Bits The reserved bits must all be set to 0 for normal operation. Rev. G | Page 22 of 29

Data Sheet ADF4193 PROGRAMMING The ADF4193 can synthesize output frequencies with a channel SPUR MECHANISMS step or resolution that is a fraction of the input reference frequency. The Fractional Spurs, Integer Boundary Spurs, and Reference For a given input reference frequency and a desired output Spurs sections describe the three different spur mechanisms frequency step, the first choice to make is the PFD reference that arise with a fractional-N synthesizer and how the ADF4193 frequency and the MOD. Once these are chosen, the desired can be programmed to minimize them. output frequency channels are set by programming the INT Fractional Spurs and FRAC values. The fractional interpolator in the ADF4193 is a third-order, Σ-Δ WORKED EXAMPLE modulator (SDM) with a modulus (MOD) that is programmable to In this example of a GSM900 RX system, it is required to any integer value from 13 to 4095. If dither is enabled, then the generate RF output frequencies with channel steps of 200 kHz. minimum allowed value of MOD is 50. The SDM is clocked at A 104 MHz reference frequency input (REF ) is available. The IN the PFD reference rate (f ) that allows PLL output frequencies PFD R divider setting that set the PFD reference is shown in to be synthesized at a channel step resolution of f /MOD. PFD Equation 1. With dither turned off, the quantization noise from the Σ-Δ F = REF × [(1 + D)/(R × (1 + T))] (1) PFD IN modulator appears as fractional spurs. The interval between where: spurs is fPFD/L, where L is the repeat length of the code sequence REF is the input reference frequency. in the digital Σ-Δ modulator. For the third-order modulator IN used in the ADF4193, the repeat length depends on the value of D is the doubler enable bit (0 or 1). MOD, as shown in Table 7. R is the 4-bit R counter code (0…15). T is the REF/2 bit (0 or 1). Table 7. Fractional Spurs with Dither Off A PFD frequency of 26 MHz is chosen and the following settings Condition (Dither Off) Repeat Length Spur Interval are programmed to give an R divider value of 4: If MOD is divisible by 2, 2 × MOD Channel step/2 but not 3 Doubler enable = 0 If MOD is divisible by 3, 3 × MOD Channel step/3 R = 2 but not 2 REF/2 = 1 If MOD is divisible by 6 6 × MOD Channel step/6 Otherwise MOD Channel step Next, the modulus is chosen to allow fractional steps of 200 kHz. MOD = 26 MHz/200 kHz = 130 (2) With dither enabled, the repeat length is extended to 221 cycles, regardless of the value of MOD, which makes the quantization Once the channel step is defined, the following equation shows error spectrum look like broadband noise. This can degrade how output frequency channels are programmed: the in-band phase noise at the PLL output by as much as 10 dB. RFOUT = [INT + (FRAC/MOD] × [FPFD] (3) Therefore, for the lowest noise, dither off is a better choice, where: particularly when the final loop BW is low enough to attenuate even the lowest frequency fractional spur. The wide loop RF is the desired RF output frequency. OUT bandwidth range available with the ADF4193 makes this INT is the integer part of the division. possible in most applications. FRAC is the numerator part of the fractional division. Integer Boundary Spurs MOD is the modulus or denominator part of the fractional Another mechanism for fractional spur creation involves division. interactions between the RF VCO frequency and the reference For example, the frequency channel at 962.4 MHz is synthesized frequency. When these frequencies are not integer related, spur by programming the following values: sidebands appear on the VCO output spectrum at an offset INT = 37 frequency that corresponds to the beat note or difference FRAC = 2 frequency between an integer multiple of the reference and the VCO frequency. These spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the refer- ence where the difference frequency can be inside the loop bandwidth, thus the name integer boundary spurs. Rev. G | Page 23 of 29

ADF4193 Data Sheet The 8:1 loop bandwidth switching ratio of the ADF4193 makes The ADF4193 powers up after Step 13. It locks to the programmed it possible to attenuate all spurs to sufficiently low levels for most channel frequency after Step 14. applications. The final loop BW can be chosen to ensure that all CHANGING THE FREQUENCY OF THE PLL AND THE spurs are far enough out of band while meeting the lock time PHASE LOOK-UP TABLE requirements with the 8× bandwidth boost. Once the ADF4193 is initialized, a write to Register R0 is all that is The ADF4193 programmable modulus and R divider can also required to program a new output frequency. The N divider is be used to avoid integer boundary channels. This option is updated with the values of INT and FRAC on the next PFD cycle described in the Avoiding Integer Boundary Channels section. following the LE edge that latches in the R0 word. However, the Reference Spurs settling time and spurious performance of the synthesizer can Reference spurs are generally not a problem in fractional-N be further optimized by modifying R1 and R2 register settings synthesizers as the reference offset is far outside the loop on a channel-by-channel basis. These settings are double buffered bandwidth. However, any reference feedthrough mechanism that by the write to R0. This means that while the data is loaded in bypasses the loop can cause a problem. One such mechanism is through the serial interface on the respective R1 and R2 write feedthrough of low levels of on-chip reference switching noise cycles, the synthesizer is not updated with their data until the out through the RF pin back to the VCO, resulting in reference next write to Register R0. IN spur levels as high as –90 dBc. These spurs can be suppressed The R2 register can be used to digitally adjust the phase of the VCO below –110 dBc by inserting sufficient reverse isolation, for output relative to the reference edge. The phase can be adjusted example, through an RF buffer between the VCO and RFIN pin. over the full 360° range at RF with a resolution of 360°/MOD. In In addition, care should be taken in the printed circuit board most frequency synthesizer applications, the actual phase offset (PCB) layout to ensure that the VCO is well separated from the of the VCO output with respect to the reference is unknown and input reference to avoid a possible feedthrough path on the board. does not matter. In such applications, the phase adjustment POWER-UP INITIALIZATION capability of the R2 register can instead be used to optimize the settling time performance, as described in the Phase Look-Up After applying power to the ADF4193, a 14-step sequence is Table section. recommended, as described in Table 8. Phase Look-Up Table The divider and timer setting used in the example in Table 8 is The ADF4193’s fast lock sequence is initiated following the write to for a DCS1800 Tx synthesizer with a 104 MHz REF frequency. IN Register R0. The fast lock timers are programmed so that after the Table 8. Power-Up Initialization Sequence PLL has settled in wide BW mode, the charge pump current is Register Hex reduced and loop filter resistor switches are opened to reduce the Step Bits Codes Description loop BW. The reference cycle on which these events occur is deter- 1 R5 [7:0] FD Set all power-down bits. mined by the values preprogrammed into the timeout counters. 2 R3 [15:0] 005B PD polarity = 1, ground CP / OUT+ Figure 10 and Figure 13 show that the lock time to final phase is CP –. OUT dominated by the phase swing that occurs when the BW is reduced. Wait Allow time for loop filter 10 ms capacitors to discharge. Once the PLL has settled to final frequency and phase, in wide 3 R7 [15:0] 0007 Clear test modes. BW mode, this phase swing is the same, regardless of the size of 4 R6 [15:0] 000E Initialize PLL modes, digital lock the synthesizer’s frequency jump. The amplitude of the phase detect on MUX . swing is related to the current flowing through the loop filter OUT 5 R6 [15:0] 900E 10 ns lock detect threshold, zero resistors on the PFD reference cycle that the SW1/SW2 digital lock detect on MUXOUT. switches are opened. In an integer-N PLL, this current is zero 6 R4 [23:0] 004464 SW1/SW2 timer = 10.8 µs. once the PLL has settled. In a fractional-N PLL, the current is 7 R4 [23:0] 00446C SW3 timer = 10.8 µs. zero on average but varies from one reference cycle to the next, 8 R4 [23:0] 004394 ICP timer = 8.6 µs. depending on the quantization error sequence output from the 9 R2 [15:0] 00D2 Phase = 26. digital Σ-Δ modulator. Because the Σ-Δ modulator is all digital 10 R1 [23:0] 520209 8/9 prescaler, doubler disabled, logic, clocked at the PFD reference rate, for a given value of MOD, R = 4, toggle FF on, MOD = 65. the actual quantization error on any given reference cycle is 11 R0 [23:0] 480140 INT = 144, FRAC = 40 for determined by the value of FRAC and the PHASE word that the 1880 MHz output frequency. modulator is seeded with, following the write to R0. By choosing 12 R3 [15:0] 007B PD polarity = 1, release CP +/ OUT an appropriate value of PHASE, corresponding to the value of CP –. OUT FRAC, that is programmed on the next write to R0, the size of 13 R5 [7:0] 05 Clear all power-down bits. the error current on the PFD reference cycle the SW1/SW2 14 R0 [23:0] 480140 INT = 144, FRAC = 40 for switches opened, and thus the phase swing that occurs when the 1880 MHz output frequency. BW is reduced can be minimized. Rev. G | Page 24 of 29

Data Sheet ADF4193 With dither off, the fractional spur pattern due to the SDM’s compensates for the 25% increase in N with the change to the quantization noise also depends on the phase word the modulator 20.8 MHz PFD frequency. This maintains constant loop dynamics is seeded with. Tables of optimized FRAC and phase values for and settling time performance for jumps between the two PFD popular SW1/SW2 and ICP timer settings can be down-loaded frequencies. The CP ADJ bit should be cleared again when jumping from the ADF4193 product page. If making use of a phase table, back to 26 MHz-based channels. first write phase to double buffered Register R2, then write the The Register R1 settings necessary for integer boundary spur INT and FRAC to R0. avoidance are all double buffered and do not become active on Avoiding Integer Boundary Channels the chip until the next write to Register R0. Register R0 should always be the last register written to when programming a new A further option when programming a new frequency involves frequency. a write to Register R1 to avoid integer boundary spurs. If it is found that the integer boundary spur level is too high, an Serial Interface Activity option is to move the integer boundary away from the desired The serial interface activity when programming the R2 or R1 channel by reprogramming the R divider to select a different registers causes no noticeable disturbance to the synthesizers PFD frequency. For example, if REF = 104 MHz and R = 4 for IN settled phase or degradation in its frequency spectrum. Therefore, a 26 MHz PFD frequency and MOD = 130 for 200 kHz steps, in a GSM application, it can be performed during the active the frequency channel at 910.2 MHz has a 200 kHz integer part of the data burst. Because it takes just 10.2 µs to program boundary spur because it is 200 kHz offset from 35 × 26 MHz. the three registers, R2, R1, and R0, with the 6.5 MHz serial An alternative way to synthesize this channel is to set R = 5 for a interface clock rate typically used, this programming can also be 20.8 MHz PFD reference and MOD = 104 for 200 kHz steps. performed during the previous guard period with the LE edge The 910.2 MHz channel is now 5 MHz offset from the nearest to latch in the R0 data delayed until it’s time to switch integer multiple of 20.8 MHz and the 5 MHz beat note spurs are frequency. well attenuated by the loop. Setting double buffered Bit R1 [23] = 1 (CP ADJ bit) increases the charge pump current by 25%, which Rev. G | Page 25 of 29

ADF4193 Data Sheet APPLICATIONS INFORMATION Timer Values for Tx LOCAL OSCILLATOR FOR A GSM BASE STATION To comply with the GSM spectrum due to switching require- Figure 36 shows the ADF4193 being used with a VCO to ments, the Tx synthesizer should not switch frequency until the produce the LO for a GSM1800 base station. For GSM, the PA output power has ramped down by at least 50 dB. If it takes REF signal can be any integer multiple of 13 MHz, but the IN 10 µs to ramp down to this level, then only the last 20 µs of the main requirement is that the slew rate is at least 300 V/µs. 30 µs guard period is available for the Tx synthesizer to lock to The 5 dBm, 104 MHz input sine wave shown satisfies this final frequency and phase. requirement. In fast lock mode, the Tx loop BW is widened by a factor-of-8 Recommended parameters for the various GSM/PCS/DCS to 480 kHz, and therefore, the PLL achieves frequency lock for synthesizers are given in Table 9. a jump across the entire band in <6 µs. After this, the PA power Table 9. Recommended Setup Parameters can start to ramp up again, and the loop BW can be restored to GSM900 DCS1800/PCS1900 the final value. With the ICP timer = 28, the charge pump current Parameter Tx Rx Tx Rx reduction begins at ~8.6 µs. When SW1, SW2, and SW3 timers = Loop BW 60 kHz 40 kHz 60 kHz 40 kHz 35, the current reaches its final value before the loop filter PFD (MHz) 13 26 13 13 switches open at ~10.8 µs. MOD 65 130 65 65 With these timer values, the phase disturbance created when Dither Off Off Off Off the bandwidth is reduced settles back to its final value by 20 µs, Prescaler 4/5 4/5 8/9 8/9 in time for the start of the active part of the GSM burst. If faster ICP Timer 28 78 28 38 phase settling is desired with the 60 kHz BW setting, then the timer SW1, SW2, 35 85 35 45 values can be reduced further but should not be brought less than SW3 Timers the 6 µs it takes to achieve frequency lock in wide BW mode. VCO K 18 MHz/V 18 MHz/V 38 MHz/V 38 MHz/V V Timer Values for Rx Loop BW and PFD Frequency The 40 kHz Rx loop BW is increased by a factor-of-8 to A 60 kHz loop BW is narrow enough to attenuate the PLL phase approximately 320 kHz during fast lock. With the Rx timer noise and spurs to the required level for a Tx low. A 40 kHz BW values shown, the BW is reduced after ~12 µs, which allows is necessary to meet the GSM900 Rx synthesizer’s particularly sufficient time for the phase disturbance to settle back before tough phase noise and spur requirements at ±800 kHz offsets. the start of the active part of the Rx time slot at 30 µs. As in the To get the lowest spur levels at ±800 kHz offsets for Rx, the Σ-Δ Tx case, faster Rx settling can be achieved by reducing these modulator should be run at the highest oversampling rate timer values, their lower limit being determined by the time it possible. Therefore, for GSM900 Rx, a 26 MHz PFD frequency takes to achieve frequency lock in wide BW mode. In addition, is chosen and MOD = 130 is required for 200 kHz steps. the PCS and DCS Rx synthesizers have relaxed 800 kHz blocker Because this value of MOD is divisible by two, certain FRAC specifications and thus can tolerate a wider loop BW, which channels have a 100 kHz fractional spur. This is attenuated by allows correspondingly faster settling. the 40 kHz loop filter and therefore is not a concern. However, VCO K the 60 kHz loop filter recommended for Tx has a closed-loop V response that peaks close to 100 kHz. Therefore, a 13 MHz PFD In general, the VCO gain, KV, should be set as low as possible to with MOD = 65, which avoids the 100 kHz spur, is the best minimize the reference and integer boundary spur levels that arise choice for a Tx synthesizer. due to feedthrough mechanisms. When deciding on the optimum VCO K , a good choice is to allow 2 V to tune across the desired Dither V band, centered on the available tuning range. With V3 regulated P Dither off should be selected for the lowest rms phase error. to 5.5 V ± 100 mV, the tuning range available is 2.8 V. Prescaler Loop Filter Components The 8/9 prescaler should be selected for the PCS and DCS It is important for good settling performance that capacitors bands. The 4/5 prescaler allows an N divider range low enough with low dielectric absorption are used in the loop filter. to cover the GSM900 Tx and Rx bands with either a 13 MHz or Ceramic NPO COG capacitors are a good choice for this 26 MHz PFD frequency. application. A 2% tolerance is recommended for loop filter capacitors and 1% for resistors. A 10% tolerance is adequate for the inductor, L1. Rev. G | Page 26 of 29

Data Sheet ADF4193 ADIsimPLL Support Also available is a technical note (ADF4193-TN-001) that outlines a loop filter design procedure that takes full advantage The ADF4193 loop filter design is supported on ADIsimPLL of the new degree of freedom in the filter design that the v2.7 or later. Example files for popular applications are available differential amplifier and loop filter switches provide. for download from the applications section of the ADF4193 product page. 10pF 18Ω 18Ω100pF RF OUT 5V 18Ω + 10µF 3V + 5.5V 10µF 100nF 100nF 100nF 100nF 100pF 100nF 15 8, 10, 13 20 24 7 32 SVD VDD DVDD VP1 VP2 AVDD VP3 + 100pF CPOUT+ 30 C2A C1A 10µF 6 RFIN+ 1.20nF 120pF INTEGRATED 51Ω 5 RFIN– SW1 29 R8210AΩ2 DIAFMFEPRLEIFNIETRIAL 3 6R23Ω 100nF 100pF ADF4193 R6.12A0k2Ω AIN+ SW3 R2 31 1.80kΩ 1nF 1nF 11 REFIN SWSGWND2 2287 R6.12B0k2Ω 25 AIN– CMRAOUT 2 2.2Lm1H C4730pF C30tpF 10R4EMFHEzR, E+N5dCBEm 51Ω 19 LE R8210BΩ1 1100nF SIRENZA38 VMCHOz1/V90-1843T 18 DATA C2B 17 CLK CPOUT– 26 1.20nF C1B 23 RSET MUXOUT 16 120pF 2.4R0SkEΩT SDGND AGND DGND 14 4, 22 9, 12, 21 LOCK DETECT OUT 05328-037 Figure 36. Local Oscillator for DCS1800 Tx Using the ADF4193 Rev. G | Page 27 of 29

ADF4193 Data Sheet INTERFACING ADSP-21xx Interface The ADF4193 has a simple SPI®-compatible serial interface for Figure 38 shows the interface between the ADF4193 and the writing to the device. CLK, DATA, and LE control the data ADSP-21xx digital signal processor. The ADF4193 needs a transfer. When LE goes high, the 24 bits that have been clocked 24-bit serial word for some writes. The easiest way to accom- into the input register on each rising edge of CLK are latched plish this using the ADSP-21xx family is to use the autobuffered into the appropriate register. See Figure 2 for the timing transmit mode of operation with alternate framing. This diagram and Table 5 for the register address table. provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for The maximum allowable serial clock rate is 33 MHz. eight bits and use three memory locations for each 24-bit word. ADuC812 Interface To program each 24-bit word, store the three 8-bit bytes, enable Figure 37 shows the interface between the ADF4193 and the the autobuffered mode, and then write to the transmit register ADuC812 MicroConverter®. Because the ADuC812 is based on of the DSP. This last operation initiates the autobuffer transfer. an 8051 core, this interface can be used with any 8051-based ADSP-21xx ADF4193 microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port SCLK CLK driving LE is brought low. Some registers of the ADF4193 DT DATA require a 24-bit programming word. This is accomplished by TFS LE writing three 8-bit bytes from the MicroConverter to the device. When the third byte is written, the LE input should be brought I/O FLAGS MUXOUT hAing hI/ tOo cpoomrtp lilentee othne t htrea AnsDfeur.C 812 can also be used to detect (LOCK DETECT) 05328-034 Figure 38. ADSP-21xx to ADF4193 Interface lock (MUX configured as lock detect and polled by the OUT port input). PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE ADuC812 ADF4193 The lands on the chip scale package (CP-32-7) are rectangular. SCLOCK CLK The PCB pad for these must be 0.1 mm longer than the package MOSI DATA land length and 0.05 mm wider than the package land width. LE Center the land on the pad to ensure that the solder joint size is I/O PORTS maximized. The bottom of the chip scale package has a central MUXOUT thermal pad. (LOCK DETECT) 05328-033 The thermal pad on the PCB must be at least as large as the Figure 37. ADuC812 to ADF4193 Interface exposed pad. On the PCB, there must be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to avoid shorting. Thermal vias can be used on the PCB thermal pad to improve the thermal performance of the package. If vias are used, they must be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter must be between 0.3 mm and 0.33 mm, and the via barrel must be plated with one ounce copper to plug the via. Connect the PCB thermal pad to A . GND Rev. G | Page 28 of 29

Data Sheet ADF4193 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN 1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.25 PAD 3.10 SQ 2.95 17 8 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option ADF4193BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7 ADF4193BCPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7 ADF4193BCPZ-RL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7 ADF4193WCCPZ-RL7 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7 EV-ADF4193SD1Z Evaluation Board (1.8 GHz VCO and GSM Loop Filter) EV-ADF4193SD2Z Evaluation Board (No VCO or Loop Filter) 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADF4193W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05328-0-1/15(G) Rev. G | Page 29 of 29