RF PLL Frequency Synthesizers Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 FEATURES GENERAL DESCRIPTION ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz; The ADF4110 family of frequency synthesizers can be used to ADF4113: 4.0 GHz implement local oscillators in the upconversion and downcon- 2.7 V to 5.5 V power supply version sections of wireless receivers and transmitters. They Separate charge pump supply (V ) allows extended tuning P voltage in 3 V systems consist of a low noise digital PFD (phase frequency detector), a Programmable dual-modulus prescaler 8/9, 16/17, 32/33, precision charge pump, a programmable reference divider, 64/65 programmable A and B counters, and a dual-modulus prescaler Programmable charge pump currents (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction Programmable antibacklash pulse width with the dual-modulus prescaler (P/P + 1), implement an N 3-wire serial interface divider (N = BP + A). In addition, the 14-bit reference counter Analog and digital lock detect (R counter) allows selectable REFIN frequencies at the PFD Hardware and software power-down mode input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage APPLICATIONS controlled oscillator (VCO). Base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA) Control of all the on-chip registers is via a simple 3-wire Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) interface. The devices operate with a power supply ranging Wireless LANS from 2.7 V to 5.5 V and can be powered down when not in use. Communications test equipment CATV equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP CPGND RSET REFERENCE 14-BIT REFIN R COUNTER PHASE CHARGE FREQUENCY PUMP CP 14 DETECTOR R COUNTER LATCH CLK 24-BIT FUNCTION DATA INPUT REGISTER 22 LATCH LOCK CURRENT CURRENT LE DETECT SETTING 1 SETTING 2 A, B COUNTER SDOUT LATCH CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 19 FROM FUNCTION HIGH Z LATCH 13 AVDD N = BP + A MUX MUXOUT 13-BIT RFINA PRESCALER LBO ACDOUNTER SDOUT RFINB P/P +1 LOAD 6-BIT A COUNTER M3 M2 M1 ADF4110/ADF4111 CE AGND DGND 6 ADF4112/ADF4113 03496-0-001 Figure 1. Functional Block Diagram Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector (PFD) and Charge Pump ............ 13 Applications ....................................................................................... 1 Muxout and Lock Detect ........................................................... 13 General Description ......................................................................... 1 Input Shift Register .................................................................... 13 Functional Block Diagram .............................................................. 1 Function Latch ............................................................................ 19 Revision History ............................................................................... 2 Initialization Latch ..................................................................... 20 Specifications ..................................................................................... 3 Device Programming after Initial Power-Up ......................... 20 Timing Characteristics ..................................................................... 5 Resynchronizing the Prescaler Output .................................... 21 Absolute Maximum Ratings ............................................................ 6 Applications ..................................................................................... 22 Transistor Count ........................................................................... 6 Local Oscillator for GSM Base Station Transmitter .............. 22 ESD Caution .................................................................................. 6 Using a D/A Converter to Drive the R Pin ......................... 23 SET Pin Configurations and Function Descriptions ........................... 7 Shutdown Circuit ....................................................................... 23 Typical Performance Characteristics ............................................. 8 Wideband PLL ............................................................................ 23 Circuit Description ......................................................................... 12 Direct Conversion Modulator .................................................. 25 Reference Input Section ............................................................. 12 Interfacing ................................................................................... 26 RF Input Stage ............................................................................. 12 PCB Design Guidelines for Chip Scale Package .................... 26 Prescaler (P/P + 1) ...................................................................... 12 Outline Dimensions ....................................................................... 27 A and B Counters ....................................................................... 12 Ordering Guide ............................................................................... 28 R Counter .................................................................................... 12 REVISION HISTORY 1/13—Rev. E to Rev. F 3/03—Data sheet changed from Rev. A to Rev. B. Changes to Table 1 ............................................................................. 4 Edits to Specifications ....................................................................... 2 Changes to Ordering Guide ........................................................... 28 Updated OUTLINE DIMENSIONS ............................................. 24 8/12—Rev. D to Rev. E 1/01—Data sheet changed from Rev. 0 to Rev. A. Changed CP-20-1 to CP-20-6 ........................................... Universal Changes to DC Specifications in B Version, B Chips, Updated Outline Dimensions ........................................................ 28 Unit, and Test Conditions/Comments Columns ..................... 2 Changes to Ordering Guide ........................................................... 28 Changes to Absolute Maximum Rating ......................................... 4 Changes to FR A Function Test ..................................................... 5 IN 5/12—Rev. C to Rev. D Changes to Figure 8 ........................................................................... 7 Changes to Figure 2 ........................................................................... 5 New Graph Added—TPC 22 ........................................................... 9 Changes to Figure 4 and Table 4 ...................................................... 7 Change to PD Polarity Box in Table V ......................................... 15 Updated Outline Dimensions ........................................................ 28 Change to PD Polarity Box in Table VI ........................................ 16 Changes to Ordering Guide ........................................................... 28 Change to PD Polarity Paragraph ................................................. 17 Addition of New Material 3/04—Data sheet changed from Rev. B to Rev. C. (PCB Design Guidelines for Chip–Scale package) ................ 23 Updated Format .................................................................. Universal Replacement of CP-20 Outline with CP-20 [2] Outline ............ 24 Changes to Specifications ................................................................. 2 Changes to Figure 32 ....................................................................... 22 Changes to the Ordering Guide ..................................................... 28 Rev. F | Page 2 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 SPECIFICATIONS AV = DV = 3 V ± 10%, 5 V ± 10%; AV ≤V ≤ 6.0 V; AGND = DGND = CPGND = 0 V; R = 4.7 kΩ; dBm referred to 50 Ω; DD DD DD P SET T = T to T , unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C. A MIN MAX Table 1. Parameter B Version B Chips1 Unit Test Conditions/Comments RF CHARACTERISTICS (3 V) See Figure 29 for input circuit. RF Input Sensitivity −15/0 −15/0 dBm min/max RF Input Frequency ADF4110 80/550 80/550 MHz min/max For lower frequencies, ensure slew rate (SR) > 30 V/µs. ADF4110 50/550 50/550 MHz min/max Input level = −10 dBm. ADF4111 0.08/1.2 0.08/1.2 GHz min/max For lower frequencies, ensure SR > 30 V/µs. ADF4112 0.2/3.0 0.2/3.0 GHz min/max For lower frequencies, ensure SR > 75 V/µs. ADF4112 0.1/3.0 0.1/3.0 GHz min/max Input level = −10 dBm. ADF4113 0.2/3.7 0.2/3.7 GHz min/max Input level = −10 dBm. For lower frequencies, ensure SR > 130 V/µs. Maximum Allowable Prescaler Output Frequency2 165 165 MHz max RF CHARACTERISTICS (5 V) RF Input Sensitivity −10/0 −10/0 dBm min/max RF Input Frequency ADF4110 80/550 80/550 MHz min/max For lower frequencies, ensure SR > 50 V/µs. ADF4111 0.08/1.4 0.08/1.4 GHz min/max For lower frequencies, ensure SR > 50 V/µs. ADF4112 0.1/3.0 0.1/3.0 GHz min/max For lower frequencies, ensure SR > 75 V/µs. ADF4113 0.2/3.7 0.2/3.7 GHz min/max For lower frequencies, ensure SR > 130 V/µs. ADF4113 0.2/4.0 0.2/4.0 GHz min/max Input level = −5 dBm. Maximum Allowable Prescaler Output Frequency2 200 200 MHz max REFIN CHARACTERISTICS REFIN Input Frequency 5/104 5/104 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs. Reference Input Sensitivity 0.4/AV 0.4/AV V p-p min/max AV = 3.3 V, biased at AV /2. See Note 3. DD DD DD DD 3.0/AVDD 3.0/AVDD V p-p min/max AVDD = 5 V, biased at AVDD/2. See Note 3. REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 µA max PHASE DETECTOR FREQUENCY4 55 55 MHz max CHARGE PUMP ICP Sink/Source Programmable (see Table 9). High Value 5 5 mA typ With R = 4.7 kΩ. SET Low Value 625 625 µA typ Absolute Accuracy 2.5 2.5 % typ With R = 4.7 kΩ. SET RSET Range 2.7/10 2.7/10 kΩ typ See Table 9. I 3-State Leakage Current 1 1 nA typ CP Sink and Source Current Matching 2 2 % typ 0.5 V ≤ V ≤ V – 0.5 V. CP P I vs. V 1.5 1.5 % typ 0.5 V ≤ V ≤ V – 0.5 V. CP CP CP P I vs. Temperature 2 2 % typ V = V/2. CP CP P LOGIC INPUTS V , Input High Voltage 0.8 × DV 0.8 × DV V min INH DD DD V , Input Low Voltage 0.2 × DV 0.2 × DV V max INL DD DD I /I , Input Current ±1 ±1 µA max INH INL C , Input Capacitance 10 10 pF max IN LOGIC OUTPUTS V , Output High Voltage DV – 0.4 DV – 0.4 V min I = 500 µA. OH DD DD OH V , Output Low Voltage 0.4 0.4 V max I = 500 µA. OL OL Rev. F | Page 3 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Parameter B Version B Chips1 Unit Test Conditions/Comments POWER SUPPLIES AV 2.7/5.5 2.7/5.5 V min/V max DD DV AV AV DD DD DD VP AVDD/6.0 AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V. See Figure 25 and Figure 26. I 5 (AI + DI ) DD DD DD ADF4110 5.5 4.5 mA max 4.5 mA typical. ADF4111 5.5 4.5 mA max 4.5 mA typical. ADF4112 7.5 6.5 mA max 6.5 mA typical. ADF4113 11 8.5 mA max 8.5 mA typical. I 0.5 0.5 mA max T = 25°C. P A Low Power Sleep Mode 1 1 µA typ NOISE CHARACTERISTICS ADF4113 Normalized Phase Noise Floor6 −215 −215 dBc/Hz typ Phase Noise Performance7 @ VCO output. ADF4110: 540 MHz Output8 −91 −91 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4111: 900 MHz Output9 −87 −87 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4112: 900 MHz Output9 −90 −90 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 900 MHz Output9 −91 −91 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4111: 836 MHz Output10 −78 −78 dBc/Hz typ @ 300 Hz offset and 30 kHz PFD frequency. ADF4112: 1750 MHz Output11 −86 −86 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4112: 1750 MHz Output12 −66 −66 dBc/Hz typ @ 200 Hz offset and 10 kHz PFD frequency. ADF4112: 1960 MHz Output13 −84 −84 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 1960 MHz Output13 −85 −85 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency. ADF4113: 3100 MHz Output14 −86 −86 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency. Spurious Signals ADF4110: 540 MHz Output9 −97/−106 −97/−106 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4111: 900 MHz Output9 −98/−110 −98/−110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4112: 900 MHz Output9 −91/−100 −91/−100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 900 MHz Output9 −100/−110 −100/−110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4111: 836 MHz Output10 −81/−84 −81/−84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD frequency. ADF4112: 1750 MHz Output11 −88/−90 −88/−90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4112: 1750 MHz Output12 −65/−73 −65/−73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD frequency. ADF4112: 1960 MHz Output13 −80/−84 −80/−84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 1960 MHz Output13 −80/−84 −80/−84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency. ADF4113: 3100 MHz Output14 −80/−82 −82/−82 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency. 1The B chip specifications are given as typical values. 2This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 3AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit. 4Guaranteed by design. 5 TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN. 7 The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7). 8 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz. 9 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz. 10 fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz. 11 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz 12 fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz. 13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop B/W = 20 kHz. 14 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz. Rev. F | Page 4 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 TIMING CHARACTERISTICS Guaranteed by design but not production tested. AV = DV = 3 V ± 10%, 5 V ± 10%; AV ≤ V ≤ 6 V; DD DD DD P AGND = DGND = CPGND = 0 V; R = 4.7 kΩ; T = T to T , unless otherwise noted. SET A MIN MAX Table 2. Parameter Limit at T to T (B Version) Unit Test Conditions/Comments MIN MAX t 10 ns min DATA to CLOCK setup time 1 t 10 ns min DATA to CLOCK hold time 2 t 25 ns min CLOCK high duration 3 t 25 ns min CLOCK low duration 4 t 10 ns min CLOCK to LE setup time 5 t 20 ns min LE pulse width 6 t3 t4 CLOCK t1 t2 DB1 DB0 (LSB) DATA DB23 (MSB) DB22 DB2 (CONTROL BIT C2) (CONTROL BIT C1) t6 LE t5 LE Figure 2. Timing Diagram 03496-002 Rev. F | Page 5 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Rating other conditions above those listed in the operational sections AV to GND1 −0.3 V to +7 V of this specification is not implied. Exposure to absolute DD AV to DV −0.3 V to +0.3 V maximum rating conditions for extended periods may affect DD DD V to GND −0.3 V to +7 V device reliability. P V to AV −0.3 V to +5.5 V P DD This device is a high performance RF integrated circuit with an Digital I/O Voltage to GND −0.3 V to V + 0.3 V DD ESD rating of <2 kV, and it is ESD sensitive. Proper precautions Analog I/O Voltage to GND −0.3 V to V + 0.3 V P should be taken for handling and assembly. REF , RF A, RF B to GND −0.3 V to V + 0.3 V IN IN IN DD RFINA to RFINB ±320 mV TRANSISTOR COUNT Operating Temperature Range 6425 (CMOS) and 303 (Bipolar). Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOP θ Thermal Impedance 150.4°C/W JA LFCSP θ Thermal Impedance 122°C/W JA (Paddle Soldered) LFCSP θ Thermal Impedance 216°C/W JA (Paddle Not Soldered) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 GND = AGND = DGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F | Page 6 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS P TES P VDD VDD C R V D D 0 9 8 7 6 2 1 1 1 1 RSET 1 16 VP CP 2 ADF4110 15 DVDD CPGND 1 ADF4110 15 MUXOUT CPGND 3 ADF4111 14 MUXOUT AGND 2 ADF4111 14 LE AGND 4 ADF4112 13 LE AGND 3 AADDFF44111123 13DATA RFINB 5 ADF4113 12 DATA RFINB 4 TOP VIEW 12 CLK RFINA 5 (Not to Scale) 11 CE RFINA 6 TOP VIEW 11 CLK RAEVFDIDN 78 (Not to S cale)190 CDEGND 03496-0-003 N1.O TTHEES EXPOSED PADD6VALDDE 7VASDDHO8FERNIUL9DNGDD B01DNGDE CONNECTED TO AGND. 03496-0-004 Figure 3. TSSOP Pin Configuration Figure 4. LFCSP Pin Configuration Table 4. Pin Function Descriptions TSSOP LFCSP Pin No. Pin No. Mnemonic Function 1 19 R Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. SET The nominal voltage potential at the R pin is 0.56 V. The relationship between I and R is SET CP SET 23.5 I = CPmax R SET So, with R = 4.7 kΩ, I = 5 mA. SET CPmax 2 20 CP Charge Pump Output. When enabled, this provides ±I to the external loop filter, which in turn CP drives the external VCO. 3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 5 4 RF B Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with IN a small bypass capacitor, typically 100 pF. See Figure 29. 6 5 RF A Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO. IN 7 6, 7 AV Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground DD plane should be placed as close as possible to this pin. AV must be the same value as DV . DD DD 8 8 REF Reference Input. This is a CMOS input with a nominal threshold of V /2, and an equivalent input IN DD resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled. 9 9, 10 DGND Digital Ground. 10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high powers up the device depending on the status of the power- down Bit F2. 11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. 13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. 14 15 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. 15 16, 17 DV Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground DD plane should be placed as close as possible to this pin. DV must be the same value as AV . DD DD 16 18 V Charge Pump Power Supply. This should be greater than or equal to V . In systems where V is 3 V, P DD DD V can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. 1 P EPAD Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND. Rev. F | Page 7 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 FREQ PARAM DATA KEYWORD IMPEDANCE –GUHNzIT –TSYPE –FOMRAMAT R –5O0HMS –10 RLEEVFEELR E=N–C4.E2dBm VICDPD = = 5 3mVA, VP = 5V FREQ MAGS11 ANGS11 FREQ MAGS11 ANGS11 –20 PFD FREQUENCY = 200kHz 0.05 0.89207 –2.0571 1.05 0.9512 –40.134 LOOP BANDWIDTH = 20kHz 0.10 0.8886 –4.4427 1.10 0.93458 –43.747 0.15 0.89022 –6.3212 1.15 0.94782 –44.393 B) –30 RES. BANDWIDTH = 10Hz 000...223050 000...999600353260367 –––211.231..3159323 111...223050 000...999623827715565 –––445691...9683874 ER (d –40 VSIWDEEEOP B =A 1N.D9 WsIDTH = 10Hz 0.35 0.89318 –15.746 1.35 0.96178 –51.21 W AVERAGES = 19 0000....44550505 0000....88889989855606396589 ––––11228924....062359436366 1111....44550505 0000....99994578316658414979 ––––55563680....57755884615 PUT PO ––6500 0.60 0.89927 –25.948 1.60 0.95459 –61.43 UT 0.65 0.87797 –28.457 1.65 0.97945 –61.241 O –70 –92.5dBc/Hz 0.70 0.90765 –29.735 1.70 0.98864 –64.051 0.75 0.88526 –31.879 1.75 0.97399 –66.19 0.80 0.81267 –32.681 1.80 0.97216 –63.775 –80 0001....89905050 0000....99990223390755887478 ––––33331469....529322642213 03496-0-005 –1–0900 –2.0kHz –1.0kHz FR9E0Q0UMEHNzCY 1.0kHz 2.0kHz 03496-0-008 Figure 5. S-Parameter Data for the ADF4113 RF Input (up to 1.8 GHz) Figure 8. ADF4113 Phase Noise (900 MHz, 200kHz, 20 kHz) with DLY and SYNC Enabled 0 –40 –5 VDD = 3V –50 VP = 3V –60 m) –10 RMS NOISE = 0.52° OWER (dB –15 TA = +25°C E (dBc/Hz) ––8700 RL =–40dBc/Hz UT P –20 TA = +85°C NOIS –90 RF INP –25 PHASE ––111000 –120 –30 –130 –350 1 RF TINAP =U2–T4 F0R°CEQUEN3CY (GHz) 4 5 03496-0-006 –140100 FREQUEN1kCY OFFSET FR10OkM 900MHz CA1R00RkIER (Hz) 1M 03496-0-009 Figure 6. Input Sensitivity (ADF4113) Figure 9. ADF4113 Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 µs) 0 –40 –10 RLEEVFEELR E=N–C4.E2dBm VICDPD = = 5 3mVA, VP = 5V –50 –20 PFD FREQUENCY = 200kHz –60 LOOP BANDWIDTH = 20kHz T POWER (dB) –––543000 RVSAIWEVDSEEE.RE OBAP ABG =NAE 1DNS.WD9 = WsI D1I9TDHT H= =1 01H0zHz OISE (dBc/Hz) –––987000 RRML =S –N4O0IdSBEc =/H 0z.62° OUTPU ––7600 –91.0dBc/Hz PHASE N––111000 –80 –120 –90 –130 –100 –2.0kHz –1.0kHz FR9E0Q0MUEHNzCY 1.0kHz 2.0kHz 03496-0-007 –140100 FREQUEN1kCY OFFSET FR1O0kM 900MHz CA1R0R0IkER (Hz) 1M 03496-0-010 Figure 7. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz) Figure 10. ADF4113 Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 µs) Rev. F | Page 8 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 0 –40 –10 RLEEVFEELR E=N–C4.E2dBm IVCDPD = = 5 3mVA, VP = 5V –50 –20 PFD FREQUENCY = 200kHz –60 LOOP BANDWIDTH = 20kHz RMS NOISE = 1.6° B) –30 RES. BANDWIDTH = 1kHz Hz) –70 RL =–40dBc/Hz WER (d –40 VSAIWVDEEEREOAP BG =AE 2NS.D5 =sW 3I0DTH = 1kHz E (dBc/ –80 T PO –50 NOIS –90 OUTPU ––7600 PHASE ––111000 –80 –90.2dBc/Hz –120 –90 –130 –100 –400kHz –200kHz FR9E0Q0UMEHNzCY 200kHz 400kHz 03496-0-011 –140100 FREQUEN1CkY OFFSET FR1O0Mk 1750MHz CA1R00RkIER (Hz) 1M 03496-0-014 Figure 11. ADF4113 Reference Spurs (900 MHz, 200 kHz, 20 kHz) Figure 14. ADF4113 Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz) 0 0 ––2100 RLEEVFEELR E=N–C4.E2dBm VIPCDFPDD = =F 5 R3mVEA,Q VUPE =N 5CVY = 200kHz –10 RLEEVFEELR E=N–C5.E7dBm VICDPD = = 5 3mVA, VP = 5V LOOP BANDWIDTH = 35kHz –20 PFD FREQUENCY = 30kHz B) –30 RES. BANDWIDTH = 1kHz LOOP BANDWIDTH = 3kHz WER (d –40 VSAIWVDEEEREOAP BG =AE 2NS.D5 =sW 3I0DTH = 1kHz ER (dB) ––4300 RVSIWEDSEE.E OBP AB =NA 2DN5WD5WsIDITDHT H= =3 H3zHz T PO –50 POW –50 PMOOSDIETIVE PEEK DETECT OUTPU ––7600 UTPUT –60 O –70 –79.6dBc/Hz –80 –89.3dBc/Hz –80 –90 –90 –100 –400kHz –200kHz FR9E0Q0UMEHNzCY 200kHz 400kHz 03496-0-012 –100 –80kHz –40kHz FR1E7Q50UMEHNzCY 40kHz 80kHz 03496-0-015 Figure 12. ADF4113 (900 MHz, 200 kHz, 35 kHz) Figure 15. ADF4113 Reference Spurs (1750 MHz, 30 kHz, 3 kHz) 0 0 –10 RLEEVFEELR E=N–C8.E0dBm VICDPD = = 5 3mVA, VP = 5V –10 RLEEVFEELR E=N–C4.E2dBm VICDPD = = 5 3mVA, VP = 5V –20 PFD FREQUENCY = 30kHz –20 PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 3kHz LOOP BANDWIDTH = 100kHz B) –30 RES. BANDWIDTH = 10kHz B) –30 RES. BANDWIDTH = 10Hz ER (d –40 VSIWDEEEOP B =A 4N7D7WmIsDTH = 10kHz ER (d –40 VSIWDEEEOP B =A 1N.D9sWIDTH = 10Hz W AVERAGES = 10 W AVERAGES = 45 PO –50 PO –50 T T PU –60 PU –60 UT UT –86.6dBc/Hz O –70 O –70 –80 –75.2dBc/Hz –80 –90 –90 –100 –400Hz –200Hz FR1E75Q0UMEHNzCY 200Hz 400Hz 03496-0-013 –100 –2.0kHz –1.0kHz FR3E1Q00UMEHNzCY 1.0kHz 2.0kHz 03496-0-016 Figure 13. ADF4113 Phase Noise (1750 MHz, 30 kHz, 3 kHz) Figure 16. ADF4113 Phase Noise (3100 MHz, 1 MHz, 100 kHz) Rev. F | Page 9 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet –40 –60 –50 VDD = 3V –60 VP = 3V RMS NOISE = 1.7° –70 Hz) –70 RL = 40dBc/Hz Hz) dBc/ –80 dBc/ E ( E ( OIS –90 OIS –80 N N E –100 E S S A A PH–110 PH –90 –120 –130 –140102 FREQUEN1C0Y3 OFFSET FR1O0M4 3100MHz CA1R05RIER (Hz) 106 03496-0-017 –100–40 –20 0 TEMP20ERATUR4E0 (°C) 60 80 100 03496-0-020 Figure 17. ADF4113 Integrated Phase Noise Figure 20. ADF4113 Phase Noise vs. Temperature (3100 MHz, 1 MHz, 100 kHz) (900 MHz, 200 kHz, 20 kHz) 0 –60 ––2100 RLEEVFEELR E=N–C17E.2dBm VIPCDFPDD = =F 5 R3mVEA,Q VUPE =N 5CVY = 1MHz c) VVDP D= =5 V3V LOOP BANDWIDTH = 100kHz dB –70 B) –30 RES. BANDWIDTH = 1kHz R ( WER (d –40 VSAIWVDEEEREOAP BG =AE 1NS3D s=W 1IDTH = 1kHz CE SPU PO –50 EN –80 T R PU –60 FE T E U R O –70 –80.6dBc/Hz T RS –90 –80 FI –90 –100 –2.0MHz –1.0MHz FR3E1Q00UMEHNzCY 1.0MHz 2.0MHz 03496-0-018 –100–40 –20 0 TEMP20ERATUR4E0 (°C) 60 80 100 03496-0-021 Figure 18. Reference Spurs (3100 MHz, 1 MHz, 100 kHz) Figure 21. ADF4113 Reference Spurs vs. Temperature (900 MHz, 200 kHz, 20 kHz) –120 –5 –130 VVDP D= =5 V3V c) ––2155 VVDP D= =5 V3V B E (dBc/Hz)–140 E SPUR (d ––4355 SE NOIS–150 FERENC ––5655 HA–160 RE P T –75 S R –170 FI –85 –95 –1801 PH1A0SE DETECTO1R0 0FREQUENCY1 (0k0H0z) 10000 03496-0-019 –1050 1 TUN2ING VOLTAG3E (V) 4 5 03496-0-022 Figure 19. ADF4113 Phase Noise (Referred to CP Output) Figure 22. ADF4113 Reference Spurs (200 kHz) vs. VTUNE vs. Phase Detector Frequency (900 MHz, 200 kHz, 20 kHz) Rev. F | Page 10 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 –60 3.0 VDD = 3V VDD = 3V VP = 3V VP = 5V 2.5 –70 c/Hz) 2.0 B E (d mA) E NOIS –80 DI (DD 1.5 S HA 1.0 P –90 0.5 –100–40 –20 0 TEMP20ERATUR4E0 (°C) 60 80 100 03496-0-023 00 PRE5S0CALER OUTP1U0T0 FREQUENCY1 5(M0Hz) 200 03496-0-026 Figure 23. ADF4113 Phase Noise vs. Temperature Figure 26. DIDD vs. Prescaler Output Frequency (836 MHz, 30 kHz, 3 kHz) (ADF4110, ADF4111, ADF4112, ADF4113) –60 6 5 c) VVDP D= =5 V3V 4 VICPPP = = 5 5mVA dB –70 3 R ( U 2 P E S 1 ENC –80 mA) 0 ER (P –1 F C E I R –2 T RS –90 –3 FI –4 –5 –100–40 –20 0 TEMP20ERATUR4E0 (°C) 60 80 100 03496-0-024 –60 0.5 1.0 1.5 2.0VC2P. 5(V) 3.0 3.5 4.0 4.5 5.0 03496-0-027 Figure 24. ADF4113 Reference Spurs vs. Temperature Figure 27. Charge Pump Output Characteristics for ADF4110 Family (836 MHz, 30 kHz, 3 kHz) 10 9 8 ADF4113 7 A) 6 m (D 5 AID 4 ADF4112 3 2 ADF4110 1 ADF4111 00 8/9 PRESCA16L/E1R7VALUE 32/33 64/65 03496-0-025 Figure 25. AIDD vs. Prescaler Value Rev. F | Page 11 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet CIRCUIT DESCRIPTION REFERENCE INPUT SECTION A AND B COUNTERS The reference input stage is shown in Figure 28. SW1 and SW2 The A and B CMOS counters combine with the dual-modulus are normally closed switches. SW3 is normally open. When prescaler to allow a wide ranging division ratio in the PLL power-down is initiated, SW3 is closed and SW1 and SW2 are feedback counter. The counters are specified to work when the opened. This ensures that there is no loading of the REF pin prescaler output is 200 MHz or less. Thus, with an RF input IN on power-down. frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not. POWER-DOWN Pulse Swallow Function CONTROL The A and B counters, in conjunction with the dual-modulus NC 100k prescaler, make it possible to generate output frequencies that SW2 REFIN NC TO R COUNTER are spaced only by the reference frequency divided by R. The SW1 BUFFER equation for the VCO frequency is NO SW3 03496-0-028 fVCO = [(P × B) + A]fREFIN/R Figure 28. Reference Input Stage where: RF INPUT STAGE f = output frequency of external voltage controlled oscillator VCO (VCO) The RF input stage is shown in Figure 29. It is followed by a P = preset modulus of dual-modulus prescaler two-stage limiting amplifier to generate the current mode logic B = preset divide ratio of binary 13-bit counter(3 to 8191) (CML) clock levels needed for the prescaler. A = preset divide ratio of binary 6-bit swallow counter (0 to 63) f = output frequency of the external reference frequency REFIN BIAS 1.6V oscillator GENERATOR AVDD R = preset divide ratio of binary 14-bit programmable reference 500 500 counter (1 to 16383) RFINA R COUNTER The 14-bit R counter allows the input reference frequency to be RFINB divided down to produce the reference clock to the phase AGND 03496-0-029 farleloqwueedn.c y detector (PFD). Division ratios from 1 to 16,383 are Figure 29. RF Input Stage PRESCALER (P/P + 1) N = BP + A TO PFD 13-BIT B Along with the A and B counters, the dual-modulus prescaler COUNTER FROM RF (P/P + 1) enables the large division ratio, N, to be realized (N = INPUT STAGE PRESCALER LOAD P/P + 1 BP + A). The dual-modulus prescaler, operating at CML levels, LOAD takes the clock from the RF input stage and divides it down to a MODULUS 6-BIT A mpraenscaagleearb ilse p frroegqruaemncmy afbolre t; hite c CanM bOeS s eAt iann dso Bft wcoauren tteor s8./ T9,h e CONTFRiOguLre 30. A and B CoCuOnUteNrTsE R 03496-0-030 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. Rev. F | Page 12 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 PHASE FREQUENCY DETECTOR (PFD) AND Lock Detect CHARGE PUMP MUXOUT can be programmed for two types of lock detect: The PFD takes inputs from the R counter and N counter (N = digital lock detect and analog lock detect. BP + A) and produces an output proportional to the phase and Digital lock detect is active high. When LDP in the R counter frequency difference between them. Figure 31 is a simplified latch is set to 0, digital lock detect is set high when the phase schematic. The PFD includes a programmable delay element error on three consecutive phase detector (PD) cycles is less that controls the width of the antibacklash pulse. This pulse than 15 ns. With LDP set to 1, five consecutive cycles of less ensures that there is no dead zone in the PFD transfer function than 15 ns are required to set the lock detect. It stays high until and minimizes phase noise and reference spurs. Two bits in the a phase error greater than 25 ns is detected on any subsequent reference counter latch, ABP2 and ABP1, control the width of PD cycle. the pulse. See Table 7. The N-channel open-drain analog lock detect should be VP operated with a 10 kΩ nominal external pull-up resistor. When CHARGE PUMP lock has been detected, this output is high with narrow low- HI D1 Q1 UP going pulses. U1 R DIVIDER DVDD CLR1 PROGRAMMABLE U3 CP ANALOG LOCK DETECT DELAY DIGITAL LOCK DETECT R COUNTER OUTPUT MUX CONTROL MUXOUT N COUNTER OUTPUT ABP1 ABP2 SDOUT CLR2 HI D2 U2 Q2 DOWN DGND 03496-0-032 N DIVIDER Figure 32. MUXOUT Circuit CPGND INPUT SHIFT REGISTER R DIVIDER The ADF4110 family digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter comprised of N DIVIDER a 6-bit A counter and a 13-bit B counter. Data is clocked into CP OUTPUT 03496-0-031 tDhaet a2 4is- btirta snhsiffetr rreedgi sfrteorm o nth eea schhi frti srienggis etedrg eto o of nCeL oKf fMouSrB l afitrcsht.e s Figure 31. PFD Simplified Schematic and Timing (In Lock) on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. MUXOUT AND LOCK DETECT These are the two LSBs, DB1 and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. The output multiplexer on the ADF4110 family allows the user to access various internal points on the chip. The state of Table 6 shows a summary of how the latches are programmed. MUXOUT is controlled by M3, M2, and M1 in the function latch. Table 9 shows the full truth table. Figure 32 shows the Table 5. C2, C1 Truth Table MUXOUT section in block diagram form. Control Bits C2 C1 Data Latch 0 0 R Counter 0 1 N Counter (A and B) 1 0 Function Latch (Including Prescaler) 1 1 Initialization Latch Rev. F | Page 13 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Table 6. ADF4110 Family Latch Summary REFERENCE COUNTER LATCH D N E TO VRES KCOLCETEISICE TEST BAACNKTLIA-SH CONTROL ER DLY SYNC DRP MODE BITS WIDTH 14-BIT REFERENCE COUNTER, R BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X DLY SYNC LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) X = DON'T CARE N COUNTER LATCH N IA G P CONTROL RESERVED C 13-BIT B COUNTER 6-BIT A COUNTER BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) X = DON'T CARE FUNCTION LATCH PREVSACLUAELER -REWOP2NWOD CSUERT2RTIENNGT CSUERT1RTIENNGT TIMECRO NCTORUONLTER KCOLTSAFEDOM KCOLTSAFELBANE CP-EERHTETATS DPYTIRALOP CMOUNXTORUOTL -REWOP1NWOD RETNUOCTESER COBNITTRSOL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) INITIALIZATION LATCH E PREVSACLUAELER -REWOP2NWOD CSUERT2RTIENNGT CSUERT1RTIENNGT TIMECRO NCTORUONLTER KCOLTSAFEDOM KCOLTSAFELBANE CPTATS-EERH DPYTIRALOP CMOUNXTORUOTL -REWOP1NWOD RETNUOCTESER COBNITTRSOL T DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1) 03496-0-033 Rev. F | Page 14 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Table 7. Reference Counter Latch Map D N E TO VRE KCOCETISIC ANTI- S LEE TEST BACKLASH CONTROL ER DLY SYNC DRP MODE BITS WIDTH 14-BIT REFERENCE COUNTER BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X DLY SYNC LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) X = DON'T CARE R14 R13 R12 •••••••••• R3 R2 R1 DIVIDE RATIO 0 0 0 •••••••••• 0 0 1 1 0 0 0 •••••••••• 0 1 0 2 0 0 0 •••••••••• 0 1 1 3 0 0 0 •••••••••• 1 0 0 4 • • • •••••••••• • • • • • • • •••••••••• • • • • • • • •••••••••• • • • • 1 1 1 •••••••••• 1 0 0 16380 1 1 1 •••••••••• 1 0 1 16381 1 1 1 •••••••••• 1 1 0 16382 1 1 1 •••••••••• 1 1 1 16383 ABP2 ABP1 ANTIBACKLASH PULSE WIDTH 0 0 3.0ns 0 1 1.5ns 1 0 6.0ns 1 1 3.0ns TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION LDP OPERATION 0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. DLY SYNC OPERATION 0 0 NORMAL OPERATION 0 1 OUTPUT OF PRESCALER IS RESYNCHRONIZED WITH NONDELAYED VERSION OF RF INPUT 1 0 NORMAL OPERATION 1 1 OWUITTHP UDTE LOAFY PERDE VSECRASLIEORN IOS FR REFS YINNPCUHTRONIZED 03496-0-034 Rev. F | Page 15 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Table 8. AB Counter Latch Map N AI G P CONTROL RESERVED C 13-BIT B COUNTER 6-BIT A COUNTER BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) X = DON'T CARE A COUNTER A6 A5 •••••••••• A2 A1 DIVIDE RATIO 0 0 •••••••••• 0 0 0 0 0 •••••••••• 0 1 1 0 0 •••••••••• 1 0 2 0 0 •••••••••• 1 1 3 • • •••••••••• • • • • • •••••••••• • • • • • •••••••••• • • • 1 1 •••••••••• 0 0 60 1 1 •••••••••• 0 1 61 1 1 •••••••••• 1 0 62 1 1 •••••••••• 1 1 63 B13 B12 B11 •••••••••• B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 0 •••••••••• 0 0 0 NOT ALLOWED 0 0 0 •••••••••• 0 0 1 NOT ALLOWED 0 0 0 •••••••••• 0 1 0 NOT ALLOWED 0 0 0 •••••••••• 0 1 1 3 0 0 0 •••••••••• 1 0 0 4 • • • •••••••••• • • • • • • • •••••••••• • • • • • • • •••••••••• • • • • 1 1 1 •••••••••• 1 0 0 8188 1 1 1 •••••••••• 1 0 1 8189 1 1 1 •••••••••• 1 1 0 8190 1 1 1 •••••••••• 1 1 1 8191 F4 (FUNCTION LATCH) CP GAIN OPERATION FASTLOCK ENABLE* 0 0 CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED. 0 1 CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED. 1 0 CHARGE PUMP CURRENT SETTING 1 IS USED. 1 1 CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT UPON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION. N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH, B MUST BE GREATER THAN OR *SEE TABLE 9 EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (NXFREF), AT THE OUTPUT, NMIN IS (P2–P). TBDHYOE NTS'HTEE CB DAITERSVE IA CBREITE AS NNODT A URSEED 03496-0-035 Rev. F | Page 16 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Table 9. Function Latch Map E PREVSACLUAELER R-EWOP2NODW CSUERTR2TIENNGT CSUERTR1TIENNGT TIMECRO NCTORUONLTER COAFKLTSEDOM KCOLTSAFAELBNE PCEEATS-RHTT DPYTILOPRA CMOUNXTORUOTL -PREWONWO1D RETONUCTERES COBNITTRSOL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2(1) C1(0) F1 OCPOEURNATTEIORN F2 PHASE DETECTOR 0 NORMAL POLARITY 1 R, A, B COUNTERS 0 NEGATIVE HELD IN RESET 1 POSITIVE F3 CHARGE PUMP OUTPUT 0 NORMAL 1 THREE-STATE F4 F5 FASTLOCK MODE 0 X FASTLOCK DISABLED 1 0 FASTLOCK MODE 1 1 1 FASTLOCK MODE 2 TIMEOUT TC4 TC3 TC2 TC1 (PFD CYCLES) 0 0 0 0 3 0 0 0 1 7 0 0 1 0 11 0 0 1 1 15 0 1 0 0 19 0 1 0 1 23 0 1 1 0 27 0 1 1 1 31 1 0 0 0 35 M3 M2 M1 OUTPUT 1 0 0 1 39 0 0 0 THREE-STATE OUTPUT 1 0 1 0 43 0 0 1 DIGITAL LOCK DETECT 1 0 1 1 47 (ACTIVE HIGH) 1 1 0 0 51 0 1 0 N DIVIDER OUTPUT 1 1 0 1 55 0 1 1 DVDD 1 1 1 0 59 1 0 0 R DIVIDER OUTPUT 1 1 1 1 63 1 0 1 ANALOG LOCK DETECT CPI6 CPI5 CPI4 ICP (mA) STIEMEE FRU CNOCUTNIOTNE RL ACTOCNHT,ROL (N-CHANNEL OPEN-DRAIN) CPI3 CPI2 CPI1 2.7kΩ 4.7kΩ 10kΩ SECTION 1 1 0 SERIAL DATA OUTPUT 0 0 0 1.09 0.63 0.29 1 1 1 DGND 0 0 1 2.18 1.25 0.59 0 1 0 3.26 1.88 0.88 0 1 1 4.35 2.50 1.76 1 0 0 5.44 3.13 1.47 1 0 1 6.53 3.75 1.76 1 1 0 7.62 4.38 2.06 1 1 1 8.70 5.00 2.35 CE PIN PD2 PD1 MODE 0 X X ASYNCHRONOUS POWER-DOWN 1 X 0 NORMAL OPERATION 1 0 1 ASYNCHRONOUS POWER-DOWN 1 1 1 SYNCHRONOUS POWER-DOWN P2 P1 PRESCALER VALUE 0 0 8/9 0 1 16/17 11 01 3624//3635 03496-0-036 Rev. F | Page 17 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Table 10. Initialization Latch Map E PREVSACLUAELER -REWOP2NWOD CSUERTRT2IENNGT CSUERTRT1IENNGT TIMECRO NCTORUONLTER KCOLTSAFEDOM KCOLTSAFELBAEN PCTASEERTT-H DPYATIRLOP CMOUNXTORUOTL -REWOP1NWOD RENUOCTETSER COBNITTRSOL DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1) COUNTER F1 OPERATION PHASE DETECTOR 0 NORMAL F2 POLARITY 1 R, A, B COUNTERS 0 NEGATIVE HELD IN RESET 1 POSITIVE F3 CHARGE PUMP 0 OUTPUT NORMAL 1 THREE-STATE F4 F5 FASTLOCK MODE 0 X FASTLOCK DISABLED 1 0 FASTLOCK MODE 1 1 1 FASTLOCK MODE 2 TIMEOUT TC4 TC3 TC2 TC1 (PFD CYCLES) 0 0 0 0 3 0 0 0 1 7 0 0 1 0 11 0 0 1 1 15 0 1 0 0 19 0 1 0 1 23 0 1 1 0 27 0 1 1 1 31 1 0 0 0 35 M3 M2 M1 OUTPUT 1 0 0 1 39 0 0 0 THREE-STATE OUTPUT 1 0 1 0 43 0 0 1 DIGITAL LOCK DETECT 1 0 1 1 47 (ACTIVE HIGH) 1 1 0 0 51 0 1 0 N DIVIDER OUTPUT 1 1 0 1 55 1 1 1 0 59 0 1 1 DVDD 1 1 1 1 63 1 0 0 R DIVIDER OUTPUT SEE FUNCTION LATCH, 1 0 1 ANALOG LOCK DETECT CPI6 CPI5 CPI4 ICP (mA) TIMER COUNTER CONTROL (N-CHANNEL OPEN-DRAIN) CPI3 CPI2 CPI1 2.7kΩ 4.7kΩ 10kΩ SECTION 1 1 0 SERIAL DATA OUTPUT 0 0 0 1.09 0.63 0.29 1 1 1 DGND 0 0 1 2.18 1.25 0.59 0 1 0 3.27 1.88 0.88 0 1 1 4.35 2.50 1.76 1 0 0 5.44 3.13 1.47 1 0 1 6.53 3.75 1.76 1 1 0 7.62 4.38 2.06 1 1 1 8.70 5.00 2.35 CE PIN PD2 PD1 MODE 0 X X ASYNCHRONOUS POWER-DOWN 1 X 0 NORMAL OPERATION 1 0 1 ASYNCHRONOUS POWER-DOWN 1 1 1 SYNCHRONOUS POWER-DOWN P2 P1 PRESCALER VALUE 0 0 8/9 0 1 16/17 11 01 3624//3635 03496-0-037 Rev. F | Page 18 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 FUNCTION LATCH The on-chip function latch is programmed with C2, C1 set to 1. Fastlock Mode Bit Table 9 shows the input data format for programming the DB10 of the function latch is the fastlock enable bit. When function latch. fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if Counter Reset the fastlock mode bit is 1, fastlock mode 2 is selected. DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter and the AB counters are reset. For normal operation, this bit Fastlock Mode 1 should be 0. Upon powering up, the F1 bit must be disabled, The charge pump current is switched to the contents of Current and the N counter resumes counting in “close” alignment with Setting 2. the R counter. (The maximum error is one prescaler cycle.) The device enters fastlock by having a 1 written to the CP gain Power-Down bit in the AB counter latch. The device exits fastlock by having a DB3 (PD1) and DB21 (PD2) on the ADF411x provide 0 written to the CP gain bit in the AB counter latch. program-mable power-down modes. They are enabled by the Fastlock Mode 2 CE pin. The charge pump current is switched to the contents of Current When the CE pin is low, the device is immediately disabled Setting 2. The device enters fastlock by having a 1 written to the regardless of the states of PD2, PD1. CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period In the programmed asynchronous power-down, the device determined by the value in TC4 through TC1, the CP gain bit in powers down immediately after latching a 1 into Bit PD1, the AB counter latch is automatically reset to 0 and the device provided PD2 has been loaded with a 0. reverts to normal mode instead of fastlock. See Table 9 for the In the programmed synchronous power-down, the device timeout periods. power-down is gated by the charge pump to prevent unwanted Timer Counter Control frequency jumps. Once power-down is enabled by writing a 1 into Bit PD1 (provided a 1 has also been loaded to PD2), the The user has the option of programming two charge pump cur- device goes into power-down on the next charge pump event. rents. Current Setting 1 is meant to be used when the RF output is stable and the system is in a static state. Current Setting 2 is When a power-down is activated (either synchronous or meant to be used when the system is dynamic and in a state of asynchronous mode including CE pin activated power-down), change (i.e., when a new output frequency is programmed). the following events occur: The normal sequence of events is as follows: • All active dc current paths are removed. The user initially decides what the preferred charge pump • The R, N, and timeout counters are forced to their load currents are going to be. For example, they may choose 2.5 mA state conditions. as Current Setting 1 and 5 mA as Current Setting 2. • The charge pump is forced into three-state mode. At the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary • The digital clock detect circuitry is reset. current. This is controlled by the timer counter control bits, DB14 through DB11 (TC4 through TC1) in the function latch. • The RFIN input is debiased. The truth table is given in Table 10. • The reference input buffer circuitry is disabled. A user can program a new output frequency simply by pro- • The input register remains active and capable of loading gramming the AB counter latch with new values for A and B. At and latching data. the same time, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6–CPI4 for a period deter- MUXOUT Control mined by TC4 through TC1. When this time is up, the charge The on-chip multiplexer is controlled by M3, M2, and M1 on pump current reverts to the value set by CPI3–CPI1. At the the ADF4110 family. Table 9 shows the truth table. same time, the CP gain bit in the AB counter latch is reset to 0 and is ready for the next time the user wishes to change the Fastlock Enable Bit frequency. DB9 of the function latch is the fastlock enable bit. Fastlock is enables only when this is 1. Rev. F | Page 19 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet Note that there is an enable feature on the timer counter. It is When the initialization latch is loaded, the following occurs: enabled when Fastlock Mode 2 is chosen by setting the fastlock 1. The function latch contents are loaded. mode bit (DB10) in the function latch to 1. Charge Pump Currents 2. An internal pulse resets the R, A, B, and timeout counters to load state conditions and three-states the charge pump. CPI3, CPI2, and CPI1 program Current Setting 1 for the charge Note that the prescaler band gap reference and the oscil- pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the lator input buffer are unaffected by the internal reset pulse, charge pump. The truth table is given in Table 10. allowing close phase alignment when counting resumes. Prescaler Value 3. Latching the first AB counter data after the initialization P2 and P1 in the function latch set the prescaler values. The word activates the same internal reset pulse. Successive AB prescaler value should be chosen so that the prescaler output loads do not trigger the internal reset pulse unless there is frequency is always less than or equal to 200 MHz. Thus, with another initialization. an RF frequency of 2 GHz, a prescaler value of 16/17 is valid but CE Pin Method a value of 8/9 is not. 1. Apply V . PD Polarity DD This bit sets the phase detector polarity bit. See Table 10. 2. Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately. CP Three-State This bit controls the CP output pin. With the bit set high, the 3. Program the function latch (10). Program the R counter CP output is put into three-state. With the bit set low, the CP latch (00). Program the AB counter latch (01). output is enabled. 4. Bring CE high to take the device out of power-down. The R INITIALIZATION LATCH and AB counters now resume counting in close alignment. When C2, C1 = 1, 1, the initialization latch is programmed. After CE goes high, a duration of 1 µs may be required for the This is essentially the same as the function latch (programmed prescaler band gap voltage and oscillator input buffer bias to when C2, C1 = 1, 0). reach steady state. However, when the initialization latch is programmed, an addi- CE can be used to power the device up and down in order to tional internal reset pulse is applied to the R and AB counters. check for channel activity. The input register does not need to This pulse ensures that the AB counter is at load point when the be reprogrammed each time the device is disabled and enabled AB counter data is latched, and the device begins counting in as long as it has been programmed at least once after V was DD close phase alignment. initially applied. If the latch is programmed for synchronous power-down (CE Counter Reset Method pin high; PD1 bit high; PD2 bit low), the internal pulse also 1. Apply V . DD triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, 2. Do a function latch load (10 in 2 LSBs). As part of this, so close phase alignment is maintained when counting resumes. load 1 to the F1 bit. This enables the counter reset. When the first AB counter data is latched after initialization, the 3. Do an R counter load (00 in 2 LSBs). Do an AB counter internal reset pulse is again activated. However, successive AB load (01 in 2 LSBs). Do a function latch load (10 in 2 counter loads after this will not trigger the internal reset pulse. LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. DEVICE PROGRAMMING AFTER INITIAL POWER-UP This sequence provides the same close alignment as the initiali- zation method. It offers direct control over the internal reset. After initial power-up of the device, there are three ways to Note that counter reset holds the counters at load point and program the device. three states the charge pump but does not trigger synchronous Initialization Latch Method power-down. The counter reset method requires an extra function latch load compared to the initialization latch method. Apply V . Program the initialization latch (11 in 2 LSBs of DD input word). Make sure the F1 bit is programmed to 0. Then, do an R load (00 in 2 LSBs). Then do an AB load (01 in 2 LSBs). Rev. F | Page 20 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 RESYNCHRONIZING THE PRESCALER OUTPUT Table 7 (the Reference Counter Latch Map) shows two bits, If the SYNC feature is used on the synthesizer, some care must DB22 and DB21, which are labeled DLY and SYNC, be taken. At some point, (at certain temperatures and output respectively. These bits affect the operation of the prescaler. frequencies), the delay through the prescaler coincides with the active edge on RF input; this causes the SYNC feature to break With SYNC = 1, the prescaler output is resynchronized with the down. It is important to be aware of this when using the SYNC RF input. This has the effect of reducing jitter due to the feature. Adding a delay to the RF signal, by programming prescaler and can lead to an overall improvement in synthesizer DLY = 1, extends the operating frequency and temperature phase noise performance. Typically, a 1 dB to 2 dB somewhat. Using the SYNC feature also increases the value of improvement is seen in the ADF4113. The lower bandwidth the AI for the device. With a 900 MHz output, the ADF4113 DD devices can show an even greater improvement. For example, AI increases by about 1.3 mA when SYNC is enabled and by DD the ADF4110 phase noise is typically improved by 3 dB when an additional 0.3 mA if DLY is enabled. SYNC is enabled. All the typical performance plots in this data sheet, except for With DLY = 1, the prescaler output is resynchronized with a Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza- delayed version of the RF input. tion or delay enabled. Rev. F | Page 21 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet APPLICATIONS LOCAL OSCILLATOR FOR GSM BASE STATION TRANSMITTER Figure 33 shows the ADF4111/ADF4112/ADF4113 being used All of these specifications are needed and used to come up with with a VCO to produce the LO for a GSM base station the loop filter component values shown in Figure 33. transmitter. The loop filter output drives the VCO, which in turn is fed back The reference input signal is applied to the circuit at FREF to the RF input of the PLL synthesizer. It also drives the RF out- IN and, in this case, is terminated in 50 Ω. A typical GSM system put terminal. A T-circuit configuration provides 50 Ω matching would have a 13 MHz TCXO driving the reference input with- between the VCO output, the RF output, and the RF terminal IN out any 50 Ω termination. In order to have channel spacing of of the synthesizer. 200 kHz (GSM standard), the reference input must be divided In a PLL system, it is important to know when the system is in by 65, using the on-chip reference divider of the ADF4111/ lock. In Figure 33, this is accomplished by using the MUXOUT ADF4112/ADF4113. signal from the synthesizer. The MUXOUT pin can be pro- The charge pump output of the ADF4111/ADF4112/ADF4113 grammed to monitor various internal signals in the synthesizer. (Pin 2) drives the loop filter. In calculating the loop filter One of these is the LD or lock-detect signal. component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45 degrees. Other PLL system specifications are K = 5 mA D K = 12 MHz/V V Loop Bandwidth = 20 kHz F = 200 kHz REF N = 4500 Extra Reference Spur Attenuation = 10 dB VDD VP RFOUT 100pF 7 15 16 18Ω 1000pF 1000pF AVDD DVDD CVPP 2 3.3kΩ C VCBC P 100pF 18Ω FREFIN 51Ω1 8 REFIN 1nF 5.6kΩ 620pF VCO190-902T 18Ω ADF4111 ADF4112 ADF4113 8.2nF CE CLK MUXOUT 14 LOCK DETECT DATA LE S 100pF U L B RFINA 6 TIBLE SERIA 4.7kΩ 1 CPGNDRSETAGND DGNDRFINB 5 100pF 51Ω2 A 3 4 9 P M CO 1TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50Ω. PI 2OPTIONAL MATCHING RESISTOR DEPENDING ON RFOUT FREQUENCY. S DAOENMCDITO OTUENPD TL FHINREGO P MCOA STPHITAEICV DEITI AOSGURRPSPA OLMNY T AOOVF ID NTDHC, ERD EVVADCDSO,E 1A 9CN0LD-A9 0VR2PITT O YHF.A TVHEE B AEDEFN411x 03496-0-038 Figure 33. Local Oscillator for GSM Base Station Rev. F | Page 22 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 RFOUT 100pF 18Ω VCO 100pF 18Ω LOOP CP 2 FREFIN 8 REFIN FILTER INPUT OUTPUT 18Ω ADF4111 GND ADF4112 ADF4113 CE CLK DATA MUXOUT14 LOCK LE DETECT 1 RSET 100pF 2.7kΩ RFINA 6 RFINB 5 51Ω 100pF AD5320 POWER SUPPLY CONNECTIONS AND DECOUPLING 12-BIT CAPACITORS ARE OMITTED FOR CLARITY. V-OUT DAC SPI COMPATIBLE SERIAL BUS 03496-0-039 Figure 34. Driving the RSET Pin with a D/A Converter USING A D/A CONVERTER TO DRIVE THE R PIN a tuning range as wide as an octave. For example, cable TV SET tuners have a total range of about 400 MHz. Figure 36 shows an A D/A converter can be used to drive the R pin of the SET application where the ADF4113 is used to control and program ADF4110 family, thus increasing the level of control over the the Micronetics M3500-2235. The loop filter was designed for charge pump current, I . This can be advantageous in wide- CP an RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD band applications where the sensitivity of the VCO varies over frequency of 1 MHz, I of 10 mA (2.5 mA synthesizer I CP CP the tuning range. To compensate for this, the I may be varied CP multiplied by the gain factor of 4), VCO K of 90 MHz/V D to maintain good phase margin and ensure loop stability. See (sensitivity of the M3500-2235 at an output of 2900 MHz), and Figure 34. a phase margin of 45°C. SHUTDOWN CIRCUIT In narrow-band applications, there is generally a small variation The attached circuit in Figure 35 shows how to shut down both in output frequency (generally less than 10%) and a small the ADF4110 family and the accompanying VCO. The ADG701 variation in VCO sensitivity over the range (typically 10% to switch goes closed circuit when a Logic 1 is applied to the IN 15%). However, in wideband applications, both of these input. The low cost switch is available in both SOT-23 and parameters have a much greater variation. In Figure 36, for MSOP packages. example, there is a −25% and +17% variation in the RF output from the nominal 2.9 GHz. The sensitivity of the VCO can vary WIDEBAND PLL from 120 MHz/V at 2750 MHz to 75 MHz/V at 3400 MHz Many of the wireless applications for synthesizers and VCOs in (+33%, −17%). Variations in these parameters change the loop PLLs are narrow band in nature. These applications include the bandwidth. This in turn can affect stability and lock time. By various wireless standards like GSM, DSC1800, CDMA, and changing the programmable I , it is possible to get compensa- CP WCDMA. In each of these cases, the total tuning range for the tion for these varying loop conditions and ensure that the loop local oscillator is less than 100 MHz. However, there are also is always operating close to optimal conditions. wideband applications for which the local oscillator could have Rev. F | Page 23 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet VP POWER-DOWN CONTROL S VDD VDD IN ADG701 RFOUT D GND 100pF 7 15 16 10 18Ω AVDDDVDD VPCE LOOP VCC 100pF18Ω FREFIN 8REFIN RCSEPT 12 FILTER VCO 18Ω GND 4.7kΩ ADF4110 ADF4111 ADF4112 ADF4113 100pF RFINA 6 DN D D RFINB 5 51Ω G N N P G G C A D 3 4 9 100pF DBEECENO UOPMLIITNTGE DC AFPRAOCMIT TOHRES D AIANGDR INATME TROF AINCCER SEIAGSNEA LCSL AHRAIVTEY. 03496-0-040 Figure 35. Local Oscillator Shutdown Circuit 20V RFOUT 12V VDD VP 3kΩ 100pF 7 15 16 1kΩ VCC OUT 100pF 18Ω 18Ω 1000pF 1000pF AVDD DVDD VCPP2 3.3kΩ AD820 VM_T35U0N0E-2235 18Ω FREFIN 51Ω 8 REFIN RSET 1 2.8nF 19nF 130pF GND 4.7kΩ 680Ω ADF4113 CE CDLAKTA MUXOUT14 LDOECTEKCT S LE UBL RFINA 6 100pF A IRESELB DNGPC DNGARFDNGDINB 5 51Ω ITA 3 4 9 100pF P M O C -IPS DATHENECD O DOUINAP GVLRICNACGM O C TFAO TP HAAEICD IM TCO3L5RA0SR0 -IO2T2NY5. A0 VHDADV, ED VBDEDE, NV POOMFIT TTHEED AFDRFO4M113 03496-0-041 Figure 36. Wideband Phase-Locked Loop Rev. F | Page 24 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 DIRECT CONVERSION MODULATOR Typical phase noise performance from this LO is −85 dBc/Hz at In some applications, a direct conversion architecture can be a 1 kHz offset. used in base station transmitters. Figure 37 shows the combina- tion available from ADI to implement this solution. The LO port of the AD8346 is driven in single-ended fashion. LOIN is ac-coupled to ground with the 100 pF capacitor; LOIP The circuit diagram shows the AD9761 being used with the is driven through the ac coupling capacitor from a 50 Ω source. AD8346. The use of dual integrated DACs such as the AD9761 An LO drive level of between −6 dBm and −12 dBm is required. with specified ±0.02 dB and ±0.004 dB gain and offset matching The circuit of Figure 37 gives a typical level of −8 dBm. characteristics ensures minimum error contribution (over temperature) from this portion of the signal chain. The RF output is designed to drive a 50 Ω load but must be ac- coupled as shown in Figure 37. If the I and Q inputs are driven The local oscillator (LO) is implemented using the ADF4113. In in quadrature by 2 V p-p signals, the resulting output power is this case, the OSC 3B1-13M0 provides the stable 13 MHz around −10 dBm. reference frequency. The system is designed for a 200 kHz channel spacing and an output center frequency of 1960 MHz. The target application is a WCDMA base station transmitter. REFIO IOUTA IBBP 100pF LOW-PASS FILTER VOUT RFOUT IOUTB IBBN MODULATED AD9761 DIGITAL TxDAC AD8346 DATA QOUTA QBBP LOW-PASS FS ADJ QOUTB FILTER QBBN 2kΩ LOIN LOIP 4.7kΩ 100pF 100pF OSC 3B1-13M0 18Ω TCXO REFINRSET CP 3.3kΩ 100pF 18Ω ADF4113 910pF 3.9kΩ VCO190-1960T SERIAL 620pF DIGITAL 9.1nF INTERFACE RFINB RFINA 18Ω 100pF 100pF 51ΩPAOREW EORM ISTUTPEPDL FYR COOMN DNIEACGTRIOAMNS T AON INDC DREECAOSUEP CLLINAGR ICTAYP.ACITORS 03496-0-042 Figure 37. Direct Conversion Transmitter Solution Rev. F | Page 25 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet INTERFACING The ADF4110 family has a simple SPI® compatible serial inter- ADSP-2181 Interface face for writing to the device. SCLK, SDATA, and LE control the Figure 39 shows the interface between the ADF4110 family and data transfer. When latch enable (LE) goes high, the 24 bits that the ADSP-21xx digital signal processor. The ADF4110 family have been clocked into the input register on each rising edge of needs a 24-bit serial word for each latch write. The easiest way SCLK get transferred to the appropriate latch. See Figure 2 for to accomplish this using the ADSP-21xx family is to use the the timing diagram and Table 5 for the latch truth table. auto buffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block The maximum allowable serial clock rate is 20 MHz. This of serial data before an interrupt is generated. means that the maximum update rate possible for the device is 833 kHz, or one update every 1.2 µs. This is certainly more than adequate for systems that have typical lock times in the SCLK SCLK hundreds of microseconds. DT SDATA ADSP-21xx ADF4110 ADuC812 Interface TFS LE ADF4111 ADF4112 Figure 38 shows the interface between the ADF4110 family and I/O FLAGS CE ADF4113 tohne aAnD 8u05C18 1co2r Me, itchriosC inotnevrfearcteer c®.a nSi nbec eu tsheed AwDithu Can81y2 8 i0s5 b1a bsaedse d M(LUOXCOKU DTETECT) 03496-0-044 microcontroller. The MicroConverter is set up for SPI master Figure 39. ADSP-21xx to ADF4110 Family Interface mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4110 family Set up the word length for 8 bits and use three memory needs a 24-bit word. This is accomplished by writing three 8-bit locations for each 24-bit word. To program each 24-bit latch, bytes from the MicroConverter to the device. When the third store the three 8-bit bytes, enable the auto buffered mode, and byte has been written, the LE input should be brought high to then write to the transmit register of the DSP. This last opera- complete the transfer. tion initiates the autobuffer transfer. When power is first applied to the ADF4110 family, three writes PCB DESIGN GUIDELINES FOR CHIP SCALE are needed (one each to the R counter latch, N counter latch, PACKAGE and initialization latch) for the output to become active. The lands on the chip scale package (CP-20) are rectangular. I/O port lines on the ADuC812 are also used to control power- The printed circuit board pad for these should be 0.1 mm down (CE input), and to detect lock (MUXOUT configured as longer than the package land length and 0.05 mm wider than lock detect and polled by the port input). the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. When the ADuC812 is operating in the mode described above, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This The bottom of the chip scale package has a central thermal pad. means that the maximum rate at which the output frequency The thermal pad on the printed circuit board should be at least can be changed is 166 kHz. as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that SCLOCK SCLK shorting is avoided. ADuC812 MOSI SDATA ADF4110 Thermal vias may be used on the printed circuit board thermal I/O PORTS LE AADDFF44111112 pad to improve thermal performance of the package. If vias are CE ADF4113 used, they should be incorporated in the thermal pad at 1.2 mm M(LUOXCOKU DTETECT) 03496-0-043 p0to.i3t pc3hl um ggrm tihd, e.a Tnvhdiae .t hveia v diaia bmarerteelr sshhoouulldd bbee pbleattwede ewni t0h.3 1 m ozm. caonpdp er Figure 38. ADuC812 to ADF4110 Family Interface The user should connect the printed circuit board thermal pad to AGND. Rev. F | Page 26 of 28

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 OUTLINE DIMENSIONS 4.10 0.30 4.00SQ 0.25 PIN1 3.90 0.18 INDICATOR PIN1 16 20 INDICATOR 0.50 BSC 15 1 EXPOSED 2.30 PAD 2.10SQ 2.00 11 5 0.65 10 6 0.20MIN TOPVIEW 0.60 BOTTOMVIEW 0.55 0.80 FORPROPERCONNECTIONOF 0.75 THEEXPOSEDPAD,REFERTO 0.05MAX THEPINCONFIGURATIONAND 0.70 0.02NOM FUNCTIONDESCRIPTIONS SECTIONOFTHISDATASHEET. COPLANARITY SEATING 0.08 PLANE COMPLIANTTOJED0E.2C0SRTEAFNDARDSMO-220-WGGD-1. 08-16-2010-B Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-20-6) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 0.65 0.19 SEATING 0° 0.45 BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. F | Page 27 of 28

ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet ORDERING GUIDE Model1 Temperature Range Package Description Package Option2 ADF4110BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4110BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4110BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4110BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRU-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRU-REEL7 -40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRUZ-RL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4110BRUZ-RL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4111BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4111BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4111BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4111BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4111BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4111BRUZ-RL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4111BRUZ-RL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4112BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4112BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4112BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BRU-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BRUZ-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4112BRUZ-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4113BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4113BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6 ADF4113BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BRU-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BRUZ-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BRUZ-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADF4113BCHIPS –40°C to +85°C DIE EVAL-ADF4113EBZ1 Evaluation Board EVAL-ADF4113EBZ2 Evaluation Board EV-ADF411XSD1Z Evaluation Board 1 Z = RoHS Compliant Part. 2 CP-20-6 package was formerly CP-20-1 package. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03496-0-1/13(F) Rev. F | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EV-ADF411XSD1Z ADF4110BRUZ ADF4113BRUZ ADF4112BCPZ ADF4112BRUZ-REEL ADF4111BCPZ ADF4111BCPZ-RL ADF4113BRUZ-REEL ADF4110BRUZ-RL ADF4112BRUZ-REEL7 ADF4111BRUZ ADF4111BCPZ-RL7 ADF4110BRU ADF4113BRUZ-REEL7 ADF4112BRU ADF4111BRU ADF4110BRU-REEL7 ADF4113BCPZ-RL ADF4110BRUZ-RL7 ADF4113BCPZ-RL7 ADF4111BRUZ-RL ADF4110BCPZ-RL7 ADF4112BCPZ-RL7 ADF4112BRU-REEL7 ADF4110BCPZ ADF4113BRU ADF4113BCPZ ADF4113BRU-REEL7 ADF4112BRUZ ADF4110BCPZ-RL ADF4110BRU-REEL ADF4112BCPZ-RL ADF4111BRUZ-RL7