Dual High Speed PECL Comparators Data Sheet ADCMP561/ADCMP562 FEATURES FUNCTIONAL BLOCK DIAGRAM Differential PECL-compatible outputs HYS* 700 ps propagation delay input to output NONINVERTING Q OUTPUT 75 ps propagation delay dispersion INPUT Input common-mode range: –2.0 V to +3.0 V ADCMP561/ ADCMP562 Robust input protection INVERTING Q OUTPUT Differential latch control INPUT Internal latch pull-up resistors P7o0w0 eprs smuipnpimlyu rmeje pcutilosen wgridetahte r than 85 dB LINAPTUCTH ENABLE *ALINDAPCTUMCTHP5 E6N2 AOBNLLEY 04687-0-001 1.5 GHz equivalent input rise time bandwidth Figure 1. Typical output rise/fall time of 500 ps ESD protection > 4 kV HBM, >200 V MM QA 1 16 QB Programmable hysteresis QA 2 15 QB APPLICATIONS VDD 3 14 GND ADCMP561 Automatic test equipment LEA 4 13 LEB TOP VIEW High speed instrumentation LEA 5 (Not to Scale) 12 LEB Scope and logic analyzer front ends VEE 6 11 VCC WHiignhd ospwe ceodm lipnaer raetcoerisv ers +–IINNAA 78 190 –+IINNBB 04687-0-002 Threshold detection Figure 2. ADCMP561 16-Lead QSOP Pin Configuration Peak detection High speed triggers VDD 1 20 VDD Patient diagnostics QA 2 19 QB Disk drive read channel detection QA 3 18 QB Hand-held test instruments VDD 4 ADCMP562 17 GND Zero-crossing detectors LEA 5 (NToOt Pto V SIEcaWle) 16 LEB Line receivers and signal restoration LEA 6 15 LEB Clock drivers VEE 7 14 VCC –INA 8 13 –INB H+YINSAA 190 1121 +HIYNSBB 04687-0-003 Figure 3. ADCMP562 20-Lead QSOP Pin Configuration GENERAL DESCRIPTION The ADCMP561/ADCMP562 are high speed comparators to +3.0 V. Outputs are complementary digital signals that are fully fabricated on Analog Devices, Inc., proprietary XFCB process. The compatible with PECL 10 K and 10 KH logic families. The outputs devices feature a 700 ps propagation delay with less than 75 ps provide sufficient drive current to directly drive transmission lines overdrive dispersion. Dispersion, a measure of the difference in terminated in 50 Ω to V − 2 V. A latch input, which is included, DD propagation delay under differing overdrive conditions, is a permits tracking, track-and-hold, or sample-and-hold modes of particularly important characteristic of comparators. A separate operation. The latch input pins contain internal pull-ups that set programmable hysteresis pin is available on the ADCMP562. the latch in tracking mode when left open. A differential input stage permits consistent propagation delay with The ADCMP561/ADCMP562 are specified over the industrial a wide variety of signals in the common-mode range from −2.0 V temperature range (−40°C to +85°C). Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADCMP561/ADCMP562 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timing Information ....................................................................... 10 Applications ....................................................................................... 1 Applications Information ............................................................... 11 Functional Block Diagram .............................................................. 1 Clock Timing Recovery .............................................................. 11 General Description ......................................................................... 1 Optimizing High Speed Performance ...................................... 11 Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ............................ 11 Specifications ..................................................................................... 3 Comparator Hysteresis .............................................................. 12 Absolute Maximum Ratings ............................................................ 5 Minimum Input Slew Rate Requirement ................................ 12 Thermal Considerations .............................................................. 5 Typical Application Circuits .......................................................... 13 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 14 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 14 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 2/2017—Data Sheet Changed from Rev. A to Rev. B Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 7/2004—Data Sheet Changed from Rev. 0 to Rev. A Changes to Specification Table ....................................................... 4 Changes to Figure 14 ........................................................................ 9 Changes to Figure 21 ...................................................................... 12 Changes to Figure 23 ...................................................................... 13 4/2004—Revision 0: Initial Version Rev. B | Page 2 of 14

Data Sheet ADCMP561/ADCMP562 SPECIFICATIONS V = +5.0 V, V = −5.2 V, V = +3.3 V, T = −40°C to +85°C. Typical values are at T = +25°C, unless otherwise noted. CC EE DD A A Table 1. Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit DC INPUT CHARACTERISTICS Input Voltage Range −2.0 3.0 V Input Differential Voltage −5 +5 V Input Offset Voltage V V = 0 V −10.0 ±2.0 +10.0 mV OS CM Input Offset Voltage Channel Matching ±2.0 mV Offset Voltage Tempco ΔV /d 2.0 µV/°C OS T Input Bias Current I −IN = −2 V, +IN = +3 V −10.0 ±3 +10.0 µA IN Input Bias Current Tempco 0.5 nA/°C Input Offset Current ±1.0 µA Input Capacitance C 0.75 pF IN Input Resistance, Differential Mode 750 kΩ Input Resistance, Common Mode 1800 kΩ Active Gain A 63 dB V Common-Mode Rejection Ratio CMRR V = −2.0 V to +3.0 V 80 dB CM Hysteresis R = ∞ ±1.0 mV HYS LATCH ENABLE CHARACTERISTICS Latch Enable Voltage Range V − 2.0 V V DD DD Latch Enable Differential Voltage Range 0.4 2.0 V Latch Enable Input High Current @ V −300 +300 µA DD Latch Enable Input Low Current @ V −2.0 V −300 +300 µA DD LE Voltage, Open Latch inputs not connected V − 0.2 V V + 0.1 V DD DD DD LE Voltage, Open Latch inputs not connected VDD/2 − 0.2 VDD/2 VDD/2 + 0.2 V Latch Setup Time t V = 250 mV 250 ps S OD Latch Hold Time t V = 250 mV 250 ps H OD Latch-to-Output Delay t , t V = 250 mV 600 ps PLOH PLOL OD Latch Minimum Pulse Width t V = 250 mV 500 ps PL OD DC OUTPUT CHARACTERISTICS Output Voltage—High Level V PECL 50 Ω to V − 2.0 V V − 1.15 V − 0.81 V OH DD DD DD Output Voltage—Low Level V PECL 50 Ω to V − 2.0 V V − 1.95 V − 1.54 V OL DD DD DD Rise Time t 10% to 90% 550 ps R Fall Time t 10% to 90% 470 ps F AC PERFORMANCE Propagation Delay t V = 1 V 700 ps PD OD V = 20 mV 830 ps OD Propagation Delay Tempco Δt /d V = 1 V 0.25 ps/°C PD T OD Prop Delay Skew—Rising Transition to Falling Transition V = 1 V 50 ps OD Within Device Propagation Delay Skew— Channel-to-Channel V = 1 V 50 ps OD Overdrive Dispersion 20 mV ≤ V ≤ 100 mV 75 ps OD Overdrive Dispersion 100 mV ≤ V ≤ 1.5 V 75 ps OD Slew Rate Dispersion 0.4 V/ns ≤ SR ≤ 1.33 V/ns 50 ps Pulse Width Dispersion 700 ps ≤ PW ≤ 10 ns 25 ps Duty Cycle Dispersion 33 MHz, 1 V/ns, 0.5 V 15 ps Common-Mode Voltage Dispersion 1 V swing, −1.5 V ≤ V ≤ +2.5 V 10 ps CM Rev. B | Page 3 of 14

ADCMP561/ADCMP562 Data Sheet Parameter Symbol Conditions Min Typ Max Unit AC PERFORMANCE (continued) Equivalent Input Rise Time Bandwidth1 BW 0 V to 1 V swing, 2 V/ns 1500 MHz EQ Maximum Toggle Rate >50% output swing 800 MHz Minimum Pulse Width PW Δt < 25 ps 700 ps MIN PD RMS Random Jitter V = 400 mV, 1.3 V/ns, 312 MHz, 1.0 ps OD 50% duty cycle Unit-to-Unit Propagation Delay Skew 100 ps POWER SUPPLY Positive Supply Current I @ +5.0 V 2 3.2 5 mA VCC Negative Supply Current I @ −5.2 V 10 22 28 mA VEE Logic Supply Current I @ 3.3 V without load 6 9 13 mA VDD Logic Supply Current @ 3.3 V with load 45 60 70 mA Positive Supply Voltage V Dual 4.75 5.0 5.25 V CC Negative Supply Voltage V Dual −4.96 −5.2 −5.45 V EE Logic Supply Voltage V Dual 2.5 3.3 5.0 V DD Power Dissipation P Dual, without load 130 160 190 mW D Power Dissipation Dual, with load 180 220 250 mW DC Power Supply Rejection Ratio—V PSRR 85 dB CC VCC DC Power Supply Rejection Ratio—V PSRR 85 dB EE VEE DC Power Supply Rejection Ratio—V PSRR 85 dB DD VDD HYSTERESIS (ADCMP562 Only) Hysteresis R = 19.5 kΩ 20 mV HYS R = 8.0 kΩ 70 mV HYS 1 Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√ (trCOMP2 – trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input. Rev. B | Page 4 of 14

Data Sheet ADCMP561/ADCMP562 ABSOLUTE MAXIMUM RATINGS Table 2. THERMAL CONSIDERATIONS Parameter Rating Supply Voltages The ADCMP561 QSOP 16-lead package option has a θJA Positive Supply Voltage (V to GND) −0.5 V to +6.0 V (junction-to-ambient thermal resistance) of 104°C/W in CC Negative Supply Voltage (V to GND) −6.0 V to +0.5 V still air. EE Logic Supply Voltage (V to GND) −0.5 V to +6.0 V DD The ADCMP562 QSOP 20-lead package option has a θ JA Ground Voltage Differential −0.5 V to +0.5 V (junction-to-ambient thermal resistance) of 80°C/W in Input Voltages still air. Input Common-Mode Voltage −3.0 V to +4.0 V Differential Input Voltage −7.0 V to +7.0 V Input Voltage, Latch Controls −0.5 V to +5.5 V ESD CAUTION Output Output Current 30 mA Temperature Operating Temperature, Ambient −40°C to +85°C Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 5 of 14

ADCMP561/ADCMP562 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 20 VDD QA 1 16 QB QA 2 19 QB QA 2 15 QB QA 3 18 QB VDD 3 ADCMP561 14 GND VDD 4 ADCMP562 17 GND LEA 4 13 LEB LEA 5 (NToOt Pto V SIEcaWle) 12 LEB LEA 5 (NToOt Pto V SIEcaWle) 16 LEB LEA 6 15 LEB VEE 6 11 VCC VEE 7 14 VCC +–IINNAA 78 190 –+IINNBB 04687-0-002 H+–YIINNSAAA 1890 111321 –+HIIYNNSBBB 04687-0-003 Figure 4. ADCMP561 16-Lead QSOP Pin Configuration Figure 5. ADCMP562 20-Lead QSOP Pin Configuration Table 3. Pin Function Descriptions Pin No. ADCMP561 ADCMP562 Mnemonic Function 1 V Logic Supply Terminal. DD 1 2 QA One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEA for more information. 2 3 QA One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEA for more information. 3 4 V Logic Supply Terminal. DD 4 5 LEA One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In the latch mode (logic low), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 5 6 LEA One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 6 7 V Negative Supply Terminal. EE 7 8 −INA Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. 8 9 +INA Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. 10 HYSA Programmable Hysteresis Input. 11 HYSB Programmable Hysteresis Input. 9 12 +INB Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. 10 13 −INB Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. 11 14 V Positive Supply Terminal. CC 12 15 LEB One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to placing the comparator in the latch mode. LEB must be driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode. Rev. B | Page 6 of 14

Data Sheet ADCMP561/ADCMP562 Pin No. ADCMP561 ADCMP562 Mnemonic Function 13 16 LEB One of two complementary inputs for Channel B Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to placing the comparator in the latch mode. LEB must be driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode. 14 17 GND Analog Ground. 15 18 QB One of two complementary outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of PIN LEB for more information. 16 19 QB One of two complementary outputs for Channel B. QB is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEB for more information. 20 V Logic Supply Terminal. DD Rev. B | Page 7 of 14

ADCMP561/ADCMP562 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = +5.0 V, V = –5.2 V, V = +3.3 V, T = 25°C, unless otherwise noted. CC EE DD A 3.0 2.80 2.78 2.5 A) 2.76 µBIAS CURRENT (A) 0112....5050 µT BIAS CURRENT (N = 3V,–IN = 0V)2222....77764208 INPUT 0 +IN INPU(+I22..6664 ––10..05 04687-0-013 22..6620 04687-0-016 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 –40 –20 0 20 40 60 80 NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0V) TEMPERATURE (°C) Figure 6. Input Bias Current vs. Input Voltage Figure 9. Input Bias Current vs. Temperature 2.00 2.6 1.95 2.4 1.90 V) mV)1.85 LL ( 2.2 GE (1.80 D FA A N OLT1.75 E A 2.0 V S T 1.70 RI OFFSE1.65 UTPUT 1.8 O 1.60 1.6 11..5550 04687-0-014 1.4 04687-0-017 –40 –20 0 20 40 60 80 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TEMPERATURE (°C) TIME (ns) Figure 7. Input Offset Voltage vs. Temperature Figure 10. Rise and Fall of Outputs vs. Time 575 500 570 495 565 490 560 485 555 480 s) s) p p E ( 550 E ( 475 M M TI 545 TI 470 540 465 535 460 552350 04687-0-015 445505 04687-0-018 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Rise Time vs. Temperature Figure 11. Fall Time vs. Temperature Rev. B | Page 8 of 14

Data Sheet ADCMP561/ADCMP562 715 708 710 706 s) s) p 705 p 704 Y ( Y ( A A L L DE 700 DE 702 N N O O ATI 695 ATI 700 G G A A P P O 690 O 698 R R P P 668805 04687-0-019 669964 04687-0-022 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –2 –1 0 1 2 3 TEMPERATURE (°C) INPUT COMMON-MODE VOLTAGE (V) Figure 12. Propagation Delay vs. Temperature Figure 15. Propagation Delay vs. Common-Mode Voltage 140 25 120 s) s) 20 p p R ( R ( O 100 O RR RR 15 E E AY 80 AY L L E E 10 D D N 60 N O O TI TI A A 5 AG 40 AG P P O O PR 200 04687-0-020 PR –50 04687-0-023 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.7 1.7 2.7 3.7 4.7 5.7 6.7 7.7 8.7 9.7 OVERDRIVE VOLTAGE (V) PULSE WIDTH (ns) Figure 13. Propagation Delay vs. Overdrive Voltage Figure 16. Propagation Delay Error vs. Pulse Width 160 160 140 140 V) V) m m S ( 120 S ( 120 SI SI E E R 100 R 100 E E T T S S HY 80 HY 80 D D E E M 60 M 60 M M A A R R G 40 G 40 O O R R P 200 04687-0-021 P 200 04687-0-024 50 40 30 20 10 0 0 50 100 150 RHYS (kΩ) IHYS (µA) Figure 14. Comparator Hysteresis vs. RHYS Figure 17. Comparator Hysteresis vs. IHYS Rev. B | Page 9 of 14

ADCMP561/ADCMP562 Data Sheet TIMING INFORMATION Figure 18 shows the compare and latch features of the ADCMP561/ADCMP562. Table 4 describes the terms in the diagram. LATCH ENABLE 50% LATCH ENABLE tS tPL tH INDPIUFFTE VROELNTTAIAGLE VIN VOD VREF± VOS tPDL tPLOH Q OUTPUT 50% tF tPDH 50% Q OUTPUT tR tPLOL 04687-0-004 Figure 18. System Timing Diagram Table 4. Timing Descriptions Symbol Timing Description t Input to Output High Delay Propagation delay measured from the time the input signal crosses the reference (± the PDH input offset voltage) to the 50% point of an output low-to-high transition. t Input to Output Low Delay Propagation delay measured from the time the input signal crosses the reference (± the PDL input offset voltage) to the 50% point of an output high-to-low transition. t Latch Enable to Output High Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high PLOH transition to the 50% point of an output low-to-high transition. t Latch Enable to Output Low Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high PLOL transition to the 50% point of an output high-to-low transition. t Minimum Hold Time Minimum time after the negative transition of the latch enable signal that the input signal H must remain unchanged to be acquired and held at the outputs. t Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change. PL t Minimum Setup Time Minimum time before the negative transition of the latch enable signal that an input S signal change must be present to be acquired and held at the outputs. t Output Rise Time Amount of time required to transition from a low to a high output as measured at the 20% R and 80% points. t Output Fall Time Amount of time required to transition from a high to a low output as measured at the 20% F and 80% points. V Voltage Overdrive Difference between the differential input and reference input voltages. OD Rev. B | Page 10 of 14

Data Sheet ADCMP561/ADCMP562 APPLICATIONS INFORMATION The ADCMP561/ADCMP562 comparators are very high speed CLOCK TIMING RECOVERY devices. Consequently, high speed design techniques must be Comparators are often used in digital systems to recover clock employed to achieve the best performance. The most critical timing signals. High speed square waves transmitted over a aspect of any ADCMP561/ADCMP562 design is the use of a low distance, even tens of centimeters, can become distorted due to impedance ground plane. A ground plane, as part of a multi- stray capacitance and inductance. Poor layout or improper layer board, is recommended for proper high speed performance. termination can also cause reflections on the transmission line, Using a continuous conductive plane over the surface of the further distorting the signal waveform. A high speed comparator circuit board can create this, allowing breaks in the plane only can be used to recover the distorted waveform while maintaining a for necessary signal paths. The ground plane provides a low minimum of delay. inductance ground, eliminating any potential differences at OPTIMIZING HIGH SPEED PERFORMANCE different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the As with any high speed comparator amplifier, proper design effects of stray capacitance on the circuit board. and layout techniques should be used to ensure optimal perfor- mance from the ADCMP561/ADCMP562. The performance It is also important to provide bypass capacitors for the power limits of high speed circuitry can be a result of stray capaci- supply in a high speed application. A 1 µF electrolytic bypass tance, improper ground impedance, or other layout issues. capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential Minimizing resistance from source to the input is an important voltage ripples from the power supply. In addition, a 10 nF consideration in maximizing the high speed operation of the ceramic capacitor should be placed as close as possible from the ADCMP561/ADCMP562. Source resistance in combination power supply pins on the ADCMP561/ADCMP562 to ground. with equivalent input capacitance could cause a lagged response These capacitors act as a charge reservoir for the device during at the input, thus delaying the output. The input capacitance of high frequency switching. the ADCMP561/ADCMP562, in combination with stray capaci- tance from an input pin to ground, could result in several The LATCH ENABLE input is active low (latched). If the picofarads of equivalent capacitance. A combination of 3 kΩ latching function is not used, the LATCH ENABLE input may source resistance and 5 pF of input capacitance yields a time be left open or may be attached to V (V is a PECL logic DD DD constant of 15 ns, which is significantly slower than the 750 ps high). The complementary input, LATCH ENABLE, may be left capability of the ADCMP561/ADCMP562. Source impedances open or may be tied to V − 2.0 V. Leaving the latch inputs DD should be significantly less than 100 Ω for best performance. unconnected or providing the proper voltages disables the latching function. Sockets should be avoided due to stray capacitance and induct- ance. If proper high speed techniques are used, the devices Occasionally, one of the two comparator stages within the should be free from oscillation when the comparator input ADCMP561/ADCMP562 is not used. The inputs of the unused signal passes through the switching threshold. comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the COMPARATOR PROPAGATION DELAY comparator that is being used) unless the output is forced into a DISPERSION fixed state. This is easily accomplished by ensuring that the two The ADCMP561/ADCMP562 have been specifically designed inputs are at least one diode drop apart, while also appropriately to reduce propagation delay dispersion over an input overdrive connecting the LATCH ENABLE and LATCH ENABLE inputs range of 100 mV to 1.5 V. Propagation delay overdrive dispersion as described previously. is the change in propagation delay that results from a change in The best performance is achieved with the use of proper PECL the degree of overdrive (how far the switching point is exceeded terminations. The open emitter outputs of the ADCMP561/ by the input). The overall result is a higher degree of timing ADCMP562 are designed to be terminated through 50 Ω accuracy because the ADCMP561/ADCMP562 are far less resistors to V − 2.0 V, or any other equivalent PECL termina- sensitive to input variations than most comparator designs. DD tion. If high speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. Rev. B | Page 11 of 14

ADCMP561/ADCMP562 Data Sheet Propagation delay dispersion is a specification that is important A current source can also be used with the HYS pin. The in critical timing applications such as ATE, bench instruments, relationship between the current applied to the HYS pin and the and nuclear instrumentation. Overdrive dispersion is defined resulting hysteresis is shown in Figure 17. as the variation in propagation delay as the input overdrive –VH +VH 2 2 conditions are changed (Figure 19). For the ADCMP561 and 0V ADCMP562, overdrive dispersion is typically 75 ps as the INPUT overdrive is changed from 100 mV to 1.5 V. This specification 1 applies for both positive and negative overdrive because the ADCMP561/ADCMP562 have equal delays for positive and negative going inputs. 1.5V OVERDRIVE INPUT VOLTAGE 0 20mV OVERDRIVE VREF± VOS OUTPUT 04687-0-006 Figure 20. Comparator Hysteresis Transfer Function Q OUTPUT DISPERSION 04687-0-005 160 140 Figure 19. Propagation Delay Dispersion V) m COMPARATOR HYSTERESIS S ( 120 SI E R 100 The addition of hysteresis to a comparator is often useful in a E T S noisy environment, or where it is not desirable for the compara- HY 80 D tor to toggle between states when the input signal is at the E M 60 switching threshold. The transfer function for a comparator AM R with hysteresis is shown in Figure 20. If the input voltage OG 40 R acpomprpoaarcahteosr tshwei ttchhreessh foroldm f rao 0m t oth ae 1n weghaetniv eth dei rinecptuiot nc,r othssee s P 200 04687-0-021 +VH/2. The new switching threshold becomes −VH/2. The 50 40 30 20 10 0 comparator remains in a 1 state until the threshold −VH/2 is RHYS (kΩ) crossed, coming from the positive direction. In this manner, Figure 21. Comparator Hysteresis vs. RHYS noise centered on 0 V input does not cause the comparator to MINIMUM INPUT SLEW RATE REQUIREMENT switch states unless it exceeds the region bounded by ±V /2. H As for all high speed comparators, a minimum slew rate must Positive feedback from the output to the input is often used to be met to ensure that the device does not oscillate when the produce hysteresis in a comparator (Figure 24). The major input crosses the threshold. This oscillation is due in part to the problem with this approach is that the amount of hysteresis high input bandwidth of the comparator and the parasitics of varies with the output logic levels, resulting in a hysteresis that the package. Analog Devices recommends a slew rate of 1 V/µs is not symmetrical around zero. or faster to ensure a clean output transition. If slew rates less In the ADCMP562, hysteresis is generated through the than 1 V/µs are used, hysteresis should be added to reduce the programmable hysteresis pin. A resistor from the HYS pin to oscillation. GND creates a current into the part that is used to generate hysteresis. Hysteresis generated in this manner is independent of output swing and is symmetrical around the trip point. The hysteresis versus resistance curve is shown in Figure 21. Rev. B | Page 12 of 14

Data Sheet ADCMP561/ADCMP562 TYPICAL APPLICATION CIRCUITS VIN ADCMP561/ VIN OUTPUTS ADCMP562 OUTPUTS ADCMP562 VREF VREF HYS 0Ω TO 80kΩ ALEILLNN ARPATUEBCSTLHSIESTORSV 5D0DΩ– 2V 04687-0-008 FAigLuLr eR E2S4I.S ATdOdRiSn g5 0HΩy, sUteNrLeEsSisS U OsTinHgVE DRtDhWe–I SH2E.Y0 VNS OCToEnDtrol Pin 04687-0-010 Figure 22. High Speed Sampling Circuits 50Ω 50Ω ADCMP561/ +VREF ADCMP561/ VIN ADCMP562 50Ω 50Ω OUTPUTS VIN ADCMP562 100Ω 100Ω (VDD– 2V)× 2 04687-0-012 VDD–2V Figure 25. How to Interface a PECL Output to an Instrument with a 50 Ω to Ground Input ADCMP561/ ADCMP562 OUTPUTS –VREF LATCH VDD–2V ALL RESISTORS 50Ω UNLESSEIN NOPATUBHTLESERWISE NOTED 04687-0-009 Figure 23. High Speed Window Comparator Rev. B | Page 13 of 14

ADCMP561/ADCMP562 Data Sheet OUTLINE DIMENSIONS 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 16 9 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 1 8 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.020 (0.51) 0.065 (1.65) 0.069 (1.75) 0.006 (0.15) 0.010 (0.25) 0.049 (1.25) 0.053 (1.35) 0.010 (0.25) CO0P.0L0A4 N(0A.1R0I)TY 0.02B5S (C0.64) 0.012 (0.30) SPELAATNIENG 80°° 0.050 (1.27) 0R.E04F1 (1.04) 0.004 (0.10) 0.016 (0.41) 0.008 (0.20) COMPLIANTTO JEDEC STANDARDS MO-137-AB C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO IPFNRFCO HINPECRSHI;A METEQIL UFLIOIVMRAE LUTEESNRET DISNI M FDOEERNSSIGIONN.S 09-12-2014-A Figure 26. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 20 11 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 1 10 0.236 (5.99) 0.228 (5.79) 0.010 (0.25) 0.020 (0.51) 0.065 (1.65) 0.069 (1.75) 0.006 (0.15) 0.010 (0.25) 0.049 (1.25) 0.053 (1.35) CO00P..00L10A04 N((00A..21R50I))TY 0.02B5S (C0.64) 0.012 (0.30) SPELAATNIENG 80°° 0.050 (1.27) 0R.E04F1 (1.04) 0.004 (0.10) 0.008 (0.20) 0.016 (0.41) COMPLIANTTO JEDEC STANDARDS MO-137-AD C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO IPFNRFCO HINPECRSHI;A METEQIL UFLIOIVMRAE LUTEESNRET DISNI M FDOEERNSSIGIONN.S 09-12-2014-A Figure 27. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADCMP561BRQZ −40°C to +85°C 16-Lead QSOP RQ-16 ADCMP562BRQZ −40°C to +85°C 20-Lead QSOP RQ-20 ADCMP562BRQZ-RL7 −40°C to +85°C 20-Lead QSOP RQ-20 EVAL-ADCMP561BRQZ Evaluation Board EVAL-ADCMP562BRQZ Evaluation Board 1 Z = RoHS Compliant Part. ©2004–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04687-0-2/17(B) Rev. B | Page 14 of 14

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADCMP561BRQZ ADCMP562BRQ ADCMP562BRQZ ADCMP562BRQZ-RL7 EVAL-ADCMP561BRQZ EVAL- ADCMP562BRQZ