Product Sample & Technical Tools & Support & Folder Buy Documents Software Community ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 ADC128S052, ADC128S052-Q1 8-Channel, 200 kSPS to 500 kSPS, 12-Bit A/D Converter 1 Features 3 Description • QualifiedforAutomotiveApplications The ADC128S052x device is a low-power, eight- 1 channel CMOS 12-bit analog-to-digital converter • AEC-Q100QualifiedWiththeFollowingResults: specifiedforconversionthroughputratesof – DeviceTemperatureGrade1: –40°Cto 200 kSPS to 500 kSPS. The converter is based on a +125°CAmbientOperatingTemperature successive-approximation register architecture with Range an internal track-and-hold circuit. It can be configured • EightInputChannels to accept up to eight input signals at inputs IN0 throughIN7. • VariablePowerManagement The output serial data is straight binary and is • IndependentAnalogandDigitalSupplies compatible with several standards, such as SPI, • CompatibleWithSPI™,QSPI™,MICROWIRE, QSPI, MICROWIRE, and many common DSP serial andDSP interfaces. • Packagedin16-PinTSSOP The ADC128S052x may be operated with • ConversionRate200kSPSto500kSPS independent analog and digital supplies. The analog • DNL(V =V =5V)+1.3or −0.9LSB supply (V ) can range from 2.7 V to 5.25 V, and the A D A (Maximum) digital supply (V ) can range from 2.7 V to V . D A Normalpowerconsumptionusinga3-Vor • INL(V =V =5V) ±1LSB(Maximum) A D 5-V supply is 1.6 mW and 8.7 mW, respectively. The • PowerConsumption power-down feature reduces the power consumption – 3-VSupply1.6mW(Typical) to 0.06 µW using a 3-V supply and 0.25 µW using a – 5-VSupply8.7mW(Typical) 5-Vsupply. The ADC128S052x is packaged in a 16-pin TSSOP 2 Applications package. The ADC128S052 is ensured over the extended industrial temperature range of −40°C to • AutomotiveNavigation +105°C while the ADC128S052-Q1 is ensured to an • PortableSystems AECQ100 Grade-1 automotive temperature range of • MedicalInstruments −40°Cto+125°C. • MobileCommunications DeviceInformation(1) • InstrumentationandControlSystems PARTNUMBER PACKAGE BODYSIZE(NOM) ADC128S052, TSSOP(16) 4.40mm×5.00mm ADC128S052-Q1 (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic VAisusedastheReference VDcanbesetindependently “Analog”SupplyRail fortheADC ofVA “Digital”SupplyRail VA VD VIN7 IN7 IN6 IN5 VIN3 IINN43 ASADRC ONTROLLER 4-wireSPI MCU C IN2 IN1 VIN0 IN0 AGND DGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.5 Programming...........................................................17 2 Applications........................................................... 1 7.6 RegisterMaps.........................................................18 3 Description............................................................. 1 8 ApplicationandImplementation........................ 19 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................19 8.2 TypicalApplication.................................................20 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 22 6 Specifications......................................................... 4 9.1 PowerSupplySequence.........................................22 6.1 AbsoluteMaximumRatings .....................................4 9.2 PowerSupplyNoiseConsiderations.......................22 6.2 ESDRatings–Commercial......................................4 10 Layout................................................................... 23 6.3 ESDRatings–Automotive.......................................4 6.4 RecommendedOperatingConditions......................5 10.1 LayoutGuidelines.................................................23 6.5 ThermalInformation..................................................5 10.2 LayoutExample....................................................23 6.6 ElectricalCharacteristics..........................................5 11 DeviceandDocumentationSupport................. 24 6.7 TimingSpecifications ...............................................8 11.1 DeviceSupport ....................................................24 6.8 TypicalCharacteristics..............................................9 11.2 RelatedLinks........................................................25 7 DetailedDescription............................................ 15 11.3 CommunityResources..........................................26 7.1 Overview................................................................15 11.4 Trademarks...........................................................26 7.2 FunctionalBlockDiagram.......................................15 11.5 ElectrostaticDischargeCaution............................26 7.3 FeatureDescription.................................................15 11.6 Glossary................................................................26 7.4 DeviceFunctionalModes........................................16 12 Mechanical,Packaging,andOrderable Information........................................................... 26 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(March2013)toRevisionE Page • AddedDeviceInformationtable,ESDRatingstable,ThermalInformationtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection......1 ChangesfromRevisionC(March2013)toRevisionD Page • ChangedlayoutofNationalDataSheettoTIformat........................................................................................................... 23 2 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 5 Pin Configuration and Functions PWPackage 16-PinTSSOP TopView CS 1 16 SCLK VA 2 15 DOUT AGND 3 14 DIN IN0 4ADC128S05213 VD IN1 5 12 DGND IN2 6 11 IN7 IN3 7 10 IN6 IN4 8 9 IN5 PinFunctions PIN TYPE DESCRIPTION NO. NAME Chipselect.OnthefallingedgeofCS,aconversionprocessbegins.Conversionscontinue 1 CS DigitalI/O aslongasCSisheldlow. Positiveanalogsupplypin.Thisvoltageisalsousedasthereferencevoltage.Thispinmust Power 2 V beconnectedtoaquiet2.7-Vto5.25-VsourceandbypassedtoGNDwith1-µFand0.1-µF A Supply monolithicceramiccapacitorslocatedwithin1cmofthepowerpin. Power 3 AGND Thegroundreturnfortheanalogsupplyandsignals. Supply 4 5 6 7 IN0toIN7 AnalogI/O Analoginputs.Thesesignalscanrangefrom0VtoV . REF 8 9 10 11 Power 12 DGND Thegroundreturnforthedigitalsupplyandsignals. Supply Power Positivedigitalsupplypin.Thispinmustbeconnectedtoa2.7-VtoV supply,andbypassed 13 V A D Supply toGNDwitha0.1-µFmonolithicceramiccapacitorlocatedwithin1cmofthepowerpin. Digitaldatainput.ThecontrolregisteroftheADC128S052isloadedthroughthispinon 14 DIN DigitalI/O risingedgesoftheSCLKpin. Digitaldataoutput.Theoutputsamplesareclockedoutofthispinonthefallingedgesofthe 15 DOUT DigitalI/O SCLKpin. Digitalclockinput.Theensuredperformancerangeoffrequenciesforthisinputis 16 SCLK DigitalI/O 3.2MHzto8MHz.Thisclockdirectlycontrolstheconversionandreadoutprocesses. Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings See (1)(2)(3) MIN MAX UNIT AnalogSupplyVoltageV –0.3 6.5 V A DigitalSupplyVoltageV –0.3 V +0.3,max6.5 V D A VoltageonAnyPintoGND –0.3 V +0.3 V A InputCurrentatAnyPin(4) ±10 mA PackageInputCurrent(4) ±20 mA PowerDissipationatT =25°C See (5) A JunctionTemperature +150 °C StorageTemperature,T −65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) IfMilitary/Aerospacespecifieddevicesarerequired,contacttheTISalesOffice/Distributorsforavailabilityandspecifications. (3) Forsolderingspecifications:seeproductfolderatwww.ti.comandSNOA549. (4) Whentheinputvoltageatanypinexceedsthepowersupplies(thatis,V <AGNDorV >V orV ),thecurrentatthatpinmustbe IN IN A D limitedto10mA.The20-mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplies withaninputcurrentof10mAtotwo. (5) Theabsolutemaximumjunctiontemperature(T )forthisdeviceis150°C.Themaximumallowablepowerdissipationisdictatedby JMAX T ,thejunction-to-ambientthermalresistance(R ),andtheambienttemperature(T ),andcanbecalculatedusingtheformula JMAX θJA A P =(T −T )/R .Inthe16-pinTSSOP,R is110°C/W,soP =1,200mWat25°Cand625mWatthemaximum DMAX JMAX A θJA θJA DMAX operatingambienttemperatureof105°C.Notethatthepowerconsumptionofthisdeviceundernormaloperationisamaximumof 12mW.ThevaluesformaximumpowerdissipationlistedaboveisreachedonlywhentheADC128S052isoperatedinaseverefault condition(forexample,wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityisreversed). Suchconditionsmustalwaysbeavoided. 6.2 ESD Ratings – Commercial VALUE UNIT Electrostatic Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1)(2) ±2500 V V (ESD) discharge Machinemodel(MM)(3) ±250 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) Humanbodymodelisa100-pFcapacitordischargedthrougha1.5-kΩresistor. (3) Machinemodelisa220-pFdischargedthroughZEROΩ. 6.3 ESD Ratings – Automotive VALUE UNIT Electrostatic Human-bodymodel(HBM),perAECQ100-002(1) ±2500 V V (ESD) discharge Charged-devicemodel(CDM),perAECQ100-011 ±250 (1) AECQ100-002indicatesthatHBMstressingshallbeinaccordancewiththeANSI/ESDA/JEDECJS-001specification. 4 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 6.4 Recommended Operating Conditions See (1) MIN NOM MAX UNIT ADC128S052 −40 T 105 °C A OperatingTemperature ADC128S052-Q1 −40 T 125 °C A V SupplyVoltage 2.7 5.25 V A V SupplyVoltage 2.7 V V D A DigitalInputVoltage 0 V V A AnalogInputVoltage 0 V V A ClockFrequency 50 1600 kHz (1) AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified. 6.5 Thermal Information ADC128S052,ADC128S052-Q1 THERMALMETRIC(1) PW(TSSOP) UNIT 16PINS R Junction-to-ambientthermalresistance 110 °C/W θJA R Junction-to-case(top)thermalresistance 42 °C/W θJC(top) R Junction-to-boardthermalresistance 56 °C/W θJB ψ Junction-to-topcharacterizationparameter 5 °C/W JT ψ Junction-to-boardcharacterizationparameter 55 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.6 Electrical Characteristics ThefollowingspecificationsapplyforAGND=DGND=0V,f =3.2MHzto8MHz,f =200kSPSto500kSPS,C = SCLK SAMPLE L 50pF,unlessotherwisenoted.MaximumandminimumlimitsapplyforT =T toT :allotherlimitsT =25°C.(1) A MIN MAX A PARAMETER TESTCONDITIONS MIN TYP MAX(2) UNIT STATICCONVERTERCHARACTERISTICS ResolutionwithNoMissing 12 Bits Codes IntegralNon-Linearity(End VA=VD=3V ±0.3 ±1 LSB INL PointMethod) V =V =5V ±0.4 ±1 LSB A D 0.3 0.9 LSB V =V =3V A D −0.7 −0.2 LSB DNL DifferentialNon-Linearity 0.6 1.3 LSB V =V =5V A D −0.9 −0.4 LSB V =V =3V 0.8 ±2.3 LSB A D V OffsetError OFF V =V =5V 1.2 ±2.3 LSB A D V =V =3V ±0.05 ±1.5 LSB A D OEM OffsetErrorMatch V =V =5V ±0.2 ±1.5 LSB A D V =V =3V 0.6 ±2.0 LSB A D FSE FullScaleError V =V =5V 0.3 ±2.0 LSB A D V =V =3V ±0.05 ±1.5 LSB A D FSEM FullScaleErrorMatch V =V =5V ±0.2 ±1.5 LSB A D (1) Datasheetminimumandmaximumspecificationlimitsareensuredbydesign,test,orstatisticalanalysis. (2) TestedlimitsareensuredtoTI'sAOQL(AverageOutgoingQualityLevel). Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com Electrical Characteristics (continued) ThefollowingspecificationsapplyforAGND=DGND=0V,f =3.2MHzto8MHz,f =200kSPSto500kSPS,C = SCLK SAMPLE L 50pF,unlessotherwisenoted.MaximumandminimumlimitsapplyforT =T toT :allotherlimitsT =25°C.(1) A MIN MAX A PARAMETER TESTCONDITIONS MIN TYP MAX(2) UNIT DYNAMICCONVERTERCHARACTERISTICS V =V =3V 8 MHz A D FPBW FullPowerBandwidth(−3dB) V =V =5V 11 MHz A D V =V =3V, A D 70 73 dB Signal-to-NoisePlusDistortion fIN=40.2kHz,−0.02dBFS SINAD Ratio V =V =5V, A D 70 73 dB f =40.2kHz,−0.02dBFS IN V =V =3V, A D 70.8 73 dB f =40.2kHz,−0.02dBFS IN SNR Signal-to-NoiseRatio V =V =5V, A D 70.8 73 dB f =40.2kHz,−0.02dBFS IN V =V =3V, A D −90 −74 dB f =40.2kHz,−0.02dBFS IN THD TotalHarmonicDistortion V =V =5V, A D −89 −74 dB f =40.2kHz,−0.02dBFS IN V =V =3V, A D 75 92 dB f =40.2kHz,−0.02dBFS IN SFDR Spurious-FreeDynamicRange V =V =5V, A D 75 91 dB f =40.2kHz,−0.02dBFS IN V =V =3V, A D 11.3 11.8 Bits f =40.2kHz IN ENOB EffectiveNumberofBits V =V =5V, A D 11.3 11.8 Bits f =40.2kHz,−0.02dBFS IN V =V =3V, A D 81 dB f =20kHz IN ISO Channel-to-ChannelIsolation V =V =5V, A D 81 dB f =20kHz,−0.02dBFS IN V =V =3V, A D −98 dB IntermodulationDistortion, fa=19.5kHz,fb=20.5kHz SecondOrderTerms V =V =5V, A D −91 dB f =19.5kHz,f =20.5kHz a b IMD V =V =3V, A D −89 dB IntermodulationDistortion,Third fa=19.5kHz,fb=20.5kHz OrderTerms V =V =5V, A D −88 dB f =19.5kHz,f =20.5kHz a b ANALOGINPUTCHARACTERISTICS V InputRange 0 V V IN A I DCLeakageCurrent ±1 µA DCL TrackMode 33 pF C InputCapacitance INA HoldMode 3 pF DIGITALINPUTCHARACTERISTICS V =V =2.7Vto3.6V 2.1 V A D V InputHighVoltage IH V =V =4.75Vto5.25V 2.4 V A D V InputLowVoltage V =V =2.7Vto5.25V 0.8 V IL A D I InputCurrent V =0VorV ±0.01 ±1 µA IN IN D C DigitalInputCapacitance 2 4 pF IND 6 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 Electrical Characteristics (continued) ThefollowingspecificationsapplyforAGND=DGND=0V,f =3.2MHzto8MHz,f =200kSPSto500kSPS,C = SCLK SAMPLE L 50pF,unlessotherwisenoted.MaximumandminimumlimitsapplyforT =T toT :allotherlimitsT =25°C.(1) A MIN MAX A PARAMETER TESTCONDITIONS MIN TYP MAX(2) UNIT DIGITALOUTPUTCHARACTERISTICS I =200µA, V OutputHighVoltage SOURCE V −0.5 V OH V =V =2.7Vto5.25V D A D I =200µAto1.0mA, V OutputLowVoltage SINK 0.4 V OL V =V =2.7Vto5.25V A D I , Hi-ImpedanceOutputLeakage OZH V =V =2.7Vto5.25V ±1 µA I Current A D OZL Hi-ImpedanceOutput COUT Capacitance(1) 2 4 pF OutputCoding Straight(Natural)Binary POWERSUPPLYCHARACTERISTICS(C =10pF) L AnalogandDigitalSupply V ,V V ≥V 2.7 5.25 V A D Voltages A D V =V =2.7Vto3.6V, A D 0.54 1.2 mA TotalSupplyCurrent fSAMPLE=500kSPS,fIN=40kHz NormalMode(CSlow) V =V =4.75Vto5.25V, A D 1.74 2.6 mA f =500kSPS,f =40kHz SAMPLE IN I +I A D V =V =2.7Vto3.6V, A D 20 nA TotalSupplyCurrent fSCLK=0kSPS ShutdownMode(CShigh) V =V =4.75Vto5.25V, A D 50 nA f =0kSPS SCLK V =V =3V A D 1.6 3.6 mW PowerConsumption fSAMPLE=500kSPS,fIN=40kHz NormalMode(CSlow) V =V =5.0V A D 8.7 13.0 mW f =500kSPS,f =40kHz SAMPLE IN P C V =V =3V A D 0.06 µW PowerConsumption fSCLK=0kSPS ShutdownMode(CShigh) V =V =5V A D 0.25 µW f =0kSPS SCLK ACELECTRICALCHARACTERISTICS f MI SCLK MinimumClockFrequency V =V =2.7Vto5.25V 3.2 0.8 MHz N A D f MaximumClockFrequency V =V =2.7Vto5.25V 16 8 MHz SCLK A D SampleRate 200 50 kSPS f V =V =2.7Vto5.25V S ContinuousMode A D 1000 500 kSPS t SCLK CONVER Conversion(Hold)Time V =V =2.7Vto5.25V 13 A D cycles T 40% 30% DC SCLKDutyCycle V =V =2.7Vto5.25V A D 70% 60% SCLK t Acquisition(Track)Time V =V =2.7Vto5.25V 3 ACQ A D cycles AcquisitionTime+ConversionTime SCLK ThroughputTime 16 V =V =2.7Vto5.25V cycles A D t ApertureDelay V =V =2.7Vto5.25V 4 ns AD A D Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com 6.7 Timing Specifications ThefollowingspecificationsapplyforV =V =2.7Vto5.25V,AGND=DGND=0V,f =3.2MHzto8MHz,f = A D SCLK SAMPLE 200kSPSto500kSPS,andC =50pF.MaximumandminimumlimitsapplyforT =T toT ;allotherlimitsT =25°C. L A MIN MAX A SeeFigure1,Figure2,andFigure3. MIN NOM MAX(1) UNIT CSHoldTimeafterSCLK t 10 0 ns CSH RisingEdge CSSet-upTimepriortoSCLK t 10 4.5 ns CSS RisingEdge CSFallingEdgetoDOUT t 5 30 ns EN enabled DOUTAccessTimeafterSCLK t 17 27 ns DACC FallingEdge DOUTHoldTimeafterSCLK t 4 ns DHLD FallingEdge DINSet-upTimepriortoSCLK t 10 3 ns DS RisingEdge DINHoldTimeafterSCLK t 10 3 ns DH RisingEdge t SCLKHighTime 0.4×t ns CH SCLK t SCLKLowTime 0.4×t ns CL SCLK CSRisingEdgetoDOUTHigh- DOUTfalling 2.4 20 ns t DIS Impedance DOUTrising 0.9 20 ns (1) TestedlimitsareensuredtoTI'sAOQL(AverageOutgoingQualityLevel). Power Down Power Up Power Up Track Hold Track Hold CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 SCLK Control register DIN ADD2 ADD1 ADD0 ADD2 ADD1 ADD0 DOUT FOUR ZEROS DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 FOUR ZEROS DB11 DB10 DB9 Figure1. ADC128S052OperationalTimingDiagram CS tACQ tCONVERT tCH SCLK 1 2 3 4 5 6 7 8 16 tEN tCL tDACC tDHLD tDIS DOUT FOUR ZEROS DB11 DB10 DB9 DB8 DB1 DB0 tDH tDS DIN DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure2. ADC128S052SerialTimingDiagram 8 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 SCLK tCSS CS tCSH CS Figure3. SCLKand CSTimingParameters 6.8 Typical Characteristics T =25°C,f =500kSPS,f =8MHz,f =40.2kHzunlessotherwisestated A SAMPLE SCLK IN Figure4.DNL Figure5.DNL Figure6.INL Figure7.INL Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com Typical Characteristics (continued) T =25°C,f =500kSPS,f =8MHz,f =40.2kHzunlessotherwisestated A SAMPLE SCLK IN Figure8.DNLvsSupply Figure9.INLvsSupply Figure10.SNRvsSupply Figure11.THDvsSupply V =5V A Figure12.ENOBvsSupply Figure13.DNLvsV D 10 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 Typical Characteristics (continued) T =25°C,f =500kSPS,f =8MHz,f =40.2kHzunlessotherwisestated A SAMPLE SCLK IN V =5V A Figure14.INLvsV Figure15.DNLvsSCLKDutyCycle D Figure16.INLvsSCLKDutyCycle Figure17.SNRvsSCLKDutyCycle Figure18.THDvsSCLKDutyCycle Figure19.ENOBvsSCLKDutyCycle Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com Typical Characteristics (continued) T =25°C,f =500kSPS,f =8MHz,f =40.2kHzunlessotherwisestated A SAMPLE SCLK IN Figure20.DNLvsSCLK Figure21.INLvsSCLK Figure22.SNRvsSCLK Figure23.THDvsSCLK Figure24.ENOBvsSCLK Figure25.DNLvsTemperature 12 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 Typical Characteristics (continued) T =25°C,f =500kSPS,f =8MHz,f =40.2kHzunlessotherwisestated A SAMPLE SCLK IN Figure26.INLvsTemperature Figure27.SNRvsTemperature Figure28.THDvsTemperature Figure29.ENOBvsTemperature Figure30.SNRvsInputFrequency Figure31.THDvsInputFrequency Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com Typical Characteristics (continued) T =25°C,f =500kSPS,f =8MHz,f =40.2kHzunlessotherwisestated A SAMPLE SCLK IN Figure32.ENOBvsInputFrequency Figure33.PowerConsumptionvsSCLK 14 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 7 Detailed Description 7.1 Overview The ADC128S052x is a successive-approximation analog-to-digital converter designed around a charge- redistribution digital-to-analog converter. For the remainder of this document, ADC128S052x is abbreviated to ADC128S052. 7.2 Functional Block Diagram IN0 . 12-BIT VA . MUX T/H SUCCESSIVE APPROXIMATION . ADC AGND IN7 AGND VD SCLK ADC128S052 CONTROL CS LOGIC DIN DOUT DGND 7.3 Feature Description 7.3.1 Operation Simplified schematics of the ADC128S052 in both track and hold operation are shown in Figure 34 and Figure 35, respectively. In Figure 34, the ADC128S052 is in track mode: switch SW1 connects the sampling capacitor to one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs.TheADC128S052isinthisstateforthefirstthreeSCLKcyclesafter CSisbroughtlow. Figure 35 shows the ADC128S052 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC128S052 is in this state for the last thirteen SCLK cycles after CSisbroughtlow. IN0 CHARGE REDISTRIBUTION DAC MUX SAMPLING CAPACITOR SW1 + IN7 CONTROL SW2 - LOGIC AGND VA/2 Figure34. ADC128S052inTrackMode Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com Feature Description (continued) IN0 CHARGE REDISTRIBUTION DAC MUX SAMPLING CAPACITOR SW1 + IN7 CONTROL - LOGIC SW2 AGND VA/2 Figure35. ADC128S052inHoldMode 7.3.2 TransferFunction The output format of the ADC128S052 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC128S052 is V / 4096. The ideal transfer characteristic is shown A in Figure 36. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, oravoltageofV /8192.OthercodetransitionsoccuratstepsofoneLSB. A 111...111 111...110 ODE 111...000 C | DC | A 011...111 1LSB = VA/4096 000...010 000...001 000...000 | 0V 0.5LSB ANALOG INPUT +VA - 1.5LSB Figure36. IdealTransferCharacteristic 7.4 Device Functional Modes The ADC128S052 is fully powered up whenever CS is low and fully powered down whenever CS is high, with one exception. If operating in continuous conversion mode, the ADC128S052 automatically enters power-down mode between the SCLK 16th falling edge of a conversion and the SCLK 1st falling edge of the subsequent conversion(seeFigure1). In continuous conversion mode, the ADC128S052 can perform multiple conversions back-to-back. Each conversion requires 16 SCLK cycles, and the ADC128S052 performs conversions continuously as long as CS is heldlow.Continuousmodeoffersmaximumthroughput. 16 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 Device Functional Modes (continued) In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical specifications. Figure 33 in the Typical Characteristics section shows the typical power consumption of the ADC128S052. To calculate the power consumption (P ), simply multiply the fraction of time spent in the normal C mode(t )bythenormalmodepowerconsumption(P ),andaddthefractionoftimespentinshutdownmode(t ) N N S multipliedbytheshutdownmodepowerconsumption(P )asshowninEquation1. S t t P = N xP + S xP C t +t N t +t S N S N S (1) 7.5 Programming 7.5.1 SerialInterface Figure 1 shows a operational timing diagram, and Figure 2 shows a serial interface timing diagram for the ADC128S052. CS (chip select) initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversionresultissentasaserialdatastream,MSBfirst.Datatobewrittentothecontrolregisterofthedevice isplacedonDIN,theserialdatainputpin.NewdataiswrittentoDINwitheachconversion. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high andisactivewhenCSislow.Thus, CSactsasanoutputenable.Similarly,SCLKisinternallygatedoffwhen CS isbroughthigh. During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished, and the data is clocked out. SCLK falling edges 1 through 4 clock out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than one conversion in a frame (continuous conversion mode), the ADC re-enters the track mode on the falling edge of SCLK after the N × 16th rising edge of SCLK and re-enter the hold/convert mode on the N × 16 + 4th falling edgeofSCLK.Nisanintegervalue. The ADC128S052 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high, and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously, and the ADC enters trackmode.Whilethereisnotimingrestrictionwithrespecttotherisingedgesof CSandSCLK,seeFigure3 for setupandholdtimerequirementsforthefallingedgeof CSwithrespecttotherisingedgeofSCLK. While a conversion is in progress, the address of the next input for conversion is clocked into a control register throughtheDINpinonthefirst8risingedgesofSCLKafterthefallof CS.SeeTable1,Table2,Table3. There is no need to incorporate a power-up delay or dummy conversion as the ADC128S052 is able to acquire theinputsignaltofullresolutioninthefirstconversionimmediatelyfollowingpowerup.Thefirstconversionresult afterpower-upisthatofIN0. Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com 7.6 Register Maps Table1.ControlRegisterBits 7 6 5 4 3 2 1 0 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Table2.ControlRegisterBitDescriptions BITNO. SYMBOL DESCRIPTION 7,6,2,1,0 DONTC Don'tcare.Thevaluesofthesebitsdonotaffectthedevice. 5 ADD2 Thesethreebitsdeterminewhichinputchannelissampledandconvertedatthenextconversion 4 ADD1 cycle.ThemappingbetweencodesandchannelsisshowninTable3. 3 ADD0 Table3.InputChannelSelection ADD2 ADD1 ADD0 INPUTCHANNEL 0 0 0 IN0(Default) 0 0 1 IN1 0 1 0 IN2 0 1 1 IN3 1 0 0 IN4 1 0 1 IN5 1 1 0 IN6 1 1 1 IN7 18 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information 8.1.1 AnalogInputs An equivalent circuit for one of the input channels of the ADC128S052 is shown in Figure 37. Diodes D1 and D2 provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to V . Going A beyondthisrangecausestheESDdiodestoconductandresultinerraticoperation. ThecapacitorC1inFigure37hasatypicalvalueof3pFandismainlythepackagepincapacitance.ResistorR1 is the on resistance of the multiplexer and track or hold switch and is typically 500 Ω. Capacitor C2 is the ADC128S052 sampling capacitor and is typically 30 pF. The ADC128S052 delivers best performance when driven by a low-impedance source (less than 100 Ω). This is especially important when using the ADC128S052 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or low-pass filter whichreducesharmonicsandnoiseintheinput.Thesefiltersareoftenreferredtoasanti-aliasingfilters. VA D1 C2 R1 30 pF VIN C1 3 pF D2 Conversion Phase - Switch Open Track Phase - Switch Closed Figure37. EquivalentInputCircuit 8.1.2 DigitalInputsandOutputs The digital inputs (SCLK, CS, and DIN) of the ADC128S052 have an operating range of 0 V to V . They are not A prone to latch-up and may be asserted before the digital supply (V ) without any risk. The digital output (DOUT) D operatingrangeiscontrolledbyV .TheoutputhighvoltageisV –0.5V(minimum)whiletheoutputlowvoltage D D is0.4V(maximum). Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com 8.2 Typical Application AtypicalapplicationisshowninFigure38.Theanalogsupplyisbypassedwithacapacitornetworklocatedclose to the ADC128S052. The ADC128S052 uses the analog supply (V ) as its reference voltage, so it is very A importantthatV bekeptascleanaspossible.DuetothelowpowerrequirementsoftheADC128S052,itisalso A possibletouseaprecisionreferenceasapowersupply. 5V 3.3V 1uF 0.1uF 0.1uF 1uF High Impedance + 100 VA VD 100 VDD Source LMV612 IN7 SCLK GPIOa 100 33n CS GPIOb 100 MCU IN3 ADC128S102 DOUT GPIOc Schottky 100 Diode DIN GPIOd (optional) Low 100 GND Impedance IN0 Source AGND DGND 33n Figure38. TypicalApplicationCircuit 8.2.1 DesignRequirements A positive supply-only data acquisition system capable of digitizing signals ranging 0 to 5 V, BW = 10 kHz, and a throughputof125kSPS. TheADC128S052hastointerfacetoamicrocontrollerwiththesupplyissetat3.3V. 8.2.2 DetailedDesignProcedure The signal range requirement forces the design to use 5-V analog supply at V , analog supply. This follows from A thefactthatV isalsoareferencepotentialfortheADC. A Therequirementofinterfacingtothemicrocontrollerwhichispoweredbya3.3-Vsupply,forcesthechoiceof 3.3VasaV supply. D Sampling is in fact a modulation process which may result in aliasing of the input signal, if the input signal is not adequately band limited. The maximum sampling rate of the ADC128S052 when all channels are enabled is, Fs iscalculatedbyEquation2: F F = SCLK s 16´8 (2) Note that faster sampling rates can be achieved when fewer channels are sampled. Single channel can be sampledatthemaximumrateof: F F = SCLK s_single 16 (3) InordertoavoidthealiasingtheNyquistcriterionhastobemet: F BW £ s signal 2 (4) Therefore it is necessary to place anti-aliasing filters at all inputs of the ADC. These filters may be single-pole low-pass filters. The pole locations need to satisfy, assuming all channels sampled in sequence, Equation 5 and Equation6: 1 F £ SCLK p´R´C 16´8 (5) 128 R´C³ p´FSCLK (6) 20 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 Typical Application (continued) WithF =16MHz,agoodchoiceforthesinglepolefilteris: SCLK • R=100 • C=33nF This reduces the input BW = 48 kHz. The capacitor at the INx input of the device provides not only the signal filtering of the input signal, but it also absorbs the charge kick-back from the ADC. The kick-back is the result of theinternalswitchesopeningattheendoftheacquisitionperiod. TheV andV sourcesarealreadyseparatedinthisexample,duetothedesignrequirements.Thisalsobenefits A D the overall performance of the ADC, as the potentially noisy V supply does not contaminate the V . In the same D A vain, further consideration could be given to the SPI interface, especially when the master microcontroller is capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal pathmayhelpinreducingthegroundbounce,andthusimprovetheoverallnoiseperformanceofthesystem. Take care when the signal source is capable of producing voltages beyond V . In such instances the internal A ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide the desiredclampingactionuseSchottkydiodesasshowninFigure38. 8.2.3 ApplicationCurve Figure39. TypicalPerformance Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com 9 Power Supply Recommendations There are three major power supply concerns with this product: power supply sequencing, power management, andtheeffectofdigitalsupplynoiseontheanalogsupply. 9.1 Power Supply Sequence TheADC128S052isadual-supplydevice.ThetwosupplypinsshareESDresources,soexercisecaretoensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital supply (V ) D cannot exceed the analog supply (V ) by more than 300 mV, not even on a transient basis. Therefore, V must A A rampupbeforeorconcurrentlywithV . D 9.2 Power Supply Noise Considerations The charging of any output load capacitance requires current from the digital supply, V . The current pulses D requiredfromthesupplytochargetheoutputcapacitancecausesvoltagevariationsonthedigitalsupply.Ifthese variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply is coupled directly into the analog supply, causing greater performance degradation than would noise on the digital supply alone. Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current into the die substrate, which is resistive. Load discharge currents causes ground bounce noise in the substrate that degrades noise performance if that current is large enough. The larger the output capacitance, the more currentflowsthroughthediesubstrateandthegreaterthenoisecoupledintotheanalogchannel. The first solution for keeping digital noise out of the analog supply is to decouple the analog and digital supplies from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100-Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This limits the charge and discharge current of the output capacitance and improves noise performance. Because the series resistor and the load capacitor formalowfrequencypole,verifysignalintegrityoncetheseriesresistorhasbeenadded. 22 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 10 Layout 10.1 Layout Guidelines Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as shortaspossible. Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance. To avoid performance degradation of the ADC128S052 due tosupplynoise,donotusethesamesupplyfortheADC128S052thatisusedfordigitallogic. Generally, analog and digital lines must cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clocklinemustalsobetreatedasatransmissionlineandbeproperlyterminated. The analog input must be isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component (for example, a filter capacitor) connected between the input pins and ground of the converterortothereferenceinputpinandgroundmustbeconnectedtoaverycleanpointinthegroundplane. TI recommends the use of a single, uniform ground plane and the use of split power planes. The power planes must be located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, and so forth) must be placed over the analog power plane. All digital circuitry and I/O lines must be placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground must be connected together with short traces and enter the analog ground plane at a single,quietpoint. 10.2 Layout Example ANALOG SUPPLY RAIL CS SCLK VA DOUT toMCU AGND DIN IN0 VD “DIGITAL”SUPPLYRAIL IN1 DGND IN2 IN7 IN3 IN6 sigtnoaalnsoaulorgces IN4 IN5 VIAtoGROUNDPLANE GROUNDPLANE Figure40. LayoutSchematic Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 DeviceNomenclature 11.1.1.1 SpecificationDefinitions ACQUISITIONTIMEisthetimerequiredfortheADCtoacquiretheinputvoltage.Duringthistime,thehold capacitorischargedbytheinputvoltage. APERTUREDELAYisthetimebetweenthefourthfallingedgeofSCLKandthetimewhentheinputsignalis internallyacquiredorheldforconversion. CONVERSIONTIME isthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinput voltagetoadigitalword. CHANNEL-TO-CHANNELISOLATION isresistancetocouplingofenergyfromonechannelintoanother channel. CROSSTALK isthecouplingofenergyfromonechannelintoanotherchannel.ThisissimilartoChannel-to- ChannelIsolation,exceptforthesignofthedata. DIFFERENTIALNON-LINEARITY(DNL) isthemeasureofthemaximumdeviationfromtheidealstepsizeof1 LSB. DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.The specificationherereferstotheSCLK. EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS) isanothermethodofspecifyingSignal-to-Noise andDistortionorSINAD.ENOBisdefinedas(SINAD-1.76)/6.02andsaysthattheconverteris equivalenttoaperfectADCofthis(ENOB)numberofbits. FULLPOWERBANDWIDTH isameasureofthefrequencyatwhichthereconstructedoutputfundamental drops3dBbelowitslowfrequencyvalueforafullscaleinput. FULLSCALEERROR(FSE) isameasureofhowfarthelastcodetransitionisfromtheideal1½LSBbelow V +andisdefinedas: REF VFSE=Vmax+1.5LSB–VREF+ • whereV isthevoltageatwhichthetransitiontothemaximumcodeoccurs.FSEcanbeexpressed max inVolts,LSBorpercentoffullscalerange. (7) GAINERRORisthedeviationofthelastcodetransition(111...110)to(111...111)fromtheideal(V -1.5LSB), REF afteradjustingforoffseterror. INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfrom negativefullscale(½LSBbelowthefirstcodetransition)throughpositivefullscale(½ LSBabove thelastcodetransition).Thedeviationofanygivencodefromthisstraightlineismeasuredfrom thecenterofthatcodevalue. INTERMODULATIONDISTORTION(IMD) isthecreationofadditionalspectralcomponentsasaresultoftwo sinusoidalfrequenciesbeingappliedtoanindividualADCinputatthesametime.Itisdefinedas theratioofthepowerinboththesecondorthethirdorderintermodulationproductstothepowerin oneoftheoriginalfrequencies.Secondorderproductsaref ±f ,wheref andf arethetwosine a b a b waveinputfrequencies.Thirdorderproductsare(2f ±f )and(f ± 2f ).IMDisusuallyexpressed a b a b indB. MISSINGCODESarethoseoutputcodesthatneverappearsattheADCoutputs.Thesecodescannotbe reachedwithanyinputvalue.TheADC128S052isensurednottohaveanymissingcodes. OFFSETERRORisthedeviationofthefirstcodetransition(000...000)to(000...001)fromtheideal(thatis,GND +0.5LSB). SIGNAL-TO-NOISERATIO(SNR) istheratio,expressedindB,ofthermsvalueoftheinputsignaltotherms valueofthesumofallotherspectralcomponentsbelowone-halfthesamplingfrequency,not includingd.c.ortheharmonicsincludedinTHD. 24 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 www.ti.com SNAS333E–AUGUST2005–REVISEDDECEMBER2015 Device Support (continued) SIGNAL-TO-NOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueofthe inputsignaltothermsvalueofalloftheotherspectralcomponentsbelowhalftheclockfrequency, includingharmonicsbutexcludingd.c. SPURIOUSFREEDYNAMICRANGE(SFDR)isthedifference,expressedindB,betweenthedesiredsignal amplitudetotheamplitudeofthepeakspuriousspectralcomponent,whereaspuriousspectral componentisanysignalpresentintheoutputspectrumthatisnotpresentattheinputandmayor maynotbeaharmonic. TOTALHARMONICDISTORTION(THD) istheratio,expressedindBc,ofthermstotalofthefirstfiveharmonic componentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput.THD iscalculatedas Af22+(cid:22)+Af102 THD = 20(cid:135)log 10 Af12 • whereA istheRMSpoweroftheinputfrequencyattheoutputandA throughA aretheRMS f1 f2 f6 powerinthefirst5harmonicfrequencies. (8) THROUGHPUTTIME istheminimumtimerequiredbetweenthestartoftwosuccessiveconversions.Itisthe acquisitiontimeplustheconversionandreadouttimes.InthecaseoftheADC128S052,thisis16 SCLKperiods. 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table4.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY ADC128S052 Clickhere Clickhere Clickhere Clickhere Clickhere ADC128S052-Q1 Clickhere Clickhere Clickhere Clickhere Clickhere Copyright©2005–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:ADC128S052 ADC128S052-Q1

ADC128S052,ADC128S052-Q1 SNAS333E–AUGUST2005–REVISEDDECEMBER2015 www.ti.com 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks E2EisatrademarkofTexasInstruments. SPI,QSPIaretrademarksofMotorola. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 26 SubmitDocumentationFeedback Copyright©2005–2015,TexasInstrumentsIncorporated ProductFolderLinks:ADC128S052 ADC128S052-Q1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADC128S052CIMT/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 128S052 & no Sb/Br) CIMT ADC128S052CIMTX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 128S052 & no Sb/Br) CIMT ADC128S052QCMT/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 128S052 & no Sb/Br) QCMT ADC128S052QCMTX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 128S052 & no Sb/Br) QCMT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADC128S052, ADC128S052-Q1 : •Catalog: ADC128S052 •Automotive: ADC128S052-Q1 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADC128S052CIMTX/NOP TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 B ADC128S052QCMTX/NO TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 PB PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADC128S052CIMTX/NOP TSSOP PW 16 2500 367.0 367.0 35.0 B ADC128S052QCMTX/NOP TSSOP PW 16 2500 367.0 367.0 35.0 B PackMaterials-Page2

PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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