ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold CheckforSamples:ADC12030,ADC12032,ADC12034,ADC12038,ADC12H030,ADC12H032,ADC12H034,ADC12H038 FEATURES • SingleSupply5V±10% 1 • SerialI/O(MICROWIRECompatible) • Powerconsumption33mW(max) 2 • 2,4,or8ChanDifferentialorSingle-Ended – Powerdown100μW(typ) Multiplexer DESCRIPTION • AnalogInputSample/HoldFunction NOTE: Some of these devices may be obsolete • PowerDownMode and are described and shown here for reference • VariableResolutionandConversionRate only.Seeourwebsiteforproductavailability. • ProgrammableAcquisitionTime The ADC12030, and ADC12H030 families are 12-bit • VariableDigitalOutputWordLengthand plus sign successive approximation Analog-to-Digital Format Converters with serial I/O and configurable input • NoZeroorFullScaleAdjustmentRequired multiplexers. The ADC12034/ADC12H034 and ADC12038/ADC12H038 have 4 and 8 channel • FullyTestedandEnsuredwitha4.096V multiplexers, respectively. The differential multiplexer Reference outputs and ADC inputs are available on the • 0Vto5VAnalogInputRangewithSingle5V MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins. PowerSupply The ADC12030/ADC12H030 has a two channel multiplexer with the multiplexer outputs and ADC • NoMissingCodesoverTemperature inputs internally connected. The ADC12030 family is tested with a 5 MHz clock, while the ADC12H030 APPLICATIONS family is tested with an 8 MHz clock. On request, • MedicalInstruments these ADCs go through a self calibration process that adjusts linearity, zero and full-scale errors to less • ProcessControlSystems than±1LSBeach. • TestEquipment The analog inputs can be configured to operate in KEY SPECIFICATIONS various combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar • Resolution12-bitplussign analog input range (0V to +5V) can be • 12-bitplussignconversiontime accommodated with a single +5V supply. In the differential modes, valid outputs are obtained even – ADC12H30family5.5μs(max) whenthenegativeinputsaregreaterthanthepositive – ADC12030family8.8 μs(max) becauseofthe12-bitplussignoutputdataformat. • 12-bitplussignthroughputtime The serial I/O is configured to comply with NSC – ADC12H30family8.6μs(max) MICROWIRE. For voltage references see the – ADC12030family14 μs(max) LM4040,LM4050orLM4041. • IntegralLinearityError±1LSB(max) 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1999–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com ADC12038 Simplified Block Diagram Connection Diagram TopView TopView Figure1.16-PinWideBody Figure2. 20-PinWideBody SOICPackage SOICPackage SeePackageNumberDW0016B SeePackageNumberDW0020B 2 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 TopView TopView Figure3. 24-PinWideBody Figure4.28-PinWideBody SOIC,PDIP,SSOPPackages SOICPackage SeePackageNumbersDW0024B,NAM0024D, SeePackageNumberDW0028B DB0024A PINDESCRIPTIONS PinName PinDescription AnalogInputstotheMUX(multiplexer).AchannelinputisselectedbytheaddressinformationattheDIpin,which isloadedontherisingedgeofSCLKintotheaddressregister(SeeTable2,Table3,andTable4).Thevoltage CH0thruCH7 appliedtotheseinputsshouldnotexceedV +orgobelowV -orbelowGND.Exceedingthisrangeonan A A unselectedchannelmaycorruptthereadingofaselectedchannel. COM Analoginputpinthatisusedasapseudogroundwhentheanalogmultiplexerissingle-ended. MUXOUT1 MultiplexerOutputpins.Ifthemultiplexerisused,thesepinsshouldbeconnectedtotheA/DINpins,directlyor MUXOUT2 throughanamplifierand/offilter. ConverterInputpins.MUXOUT1isusuallytiedtoA/DIN1.MUXOUT2isusuallytiedtoA/DIN2.Ifexternalcircuitry A/DIN1 isplacedbetweenMUXOUT1andA/DIN1,orMUXOUT2andA/DIN2,itmaybenecessarytoprotectthesepins A/DIN2 againstvoltageoverload..ThevoltageatthesepinsshouldnotexceedV +orgobelowAGND(seeFigure60). A DataOutputpin.Thispinisanactivepush/pulloutputwhenCSislow.WhenCSishigh,thisoutputisTRI-STATE. Theconversionresult(D0–D12)andconverterstatusdataareclockedoutbythefallingedgeofSCLKonthispin. DO Thewordlengthandformatofthisresultcanvary(seeTable1).Thewordlengthandformatarecontrolledbythe datashiftedintothemultiplexeraddressandmodeselectregister(seeTable5). SerialDatainputpin.ThedataappliedtothispinisshiftedbytherisingedgeofSCLKintothemultiplexeraddress DI andmodeselectregister.Table2throughTable5showtheassignmentofthemultiplexeraddressandthemode selectdata. Thispinisanactivepush/pulloutputwhichindicatesthestatusoftheADC12030/2/4/8.Alogiclowonthispin EOC indicatesthattheADCisbusywithaconversion,AutoCalibration,AutoZeroorpowerdowncycle.Therisingedge ofEOCsignalstheendofoneofthesecycles. AlogiclowisrequiredatthispintoprogramanymodeortochangetheADC'sconfigurationaslistedinMode ProgrammingTable5.Whenthispinishigh,theADCisplacedinthereaddataonlymode.Whileinthereaddata onlymode,bringingCSlowandpulsingSCLKwillonlyclockoutthedatastoredintheADCsoutputshiftregister. CONV ThedataonDIwillbeneglected.AnewconversionwillnotbestartedandtheADCwillremaininthemodeand/or configurationpreviouslyprogrammed.Readdataonlycannotbeperformedwhileaconversion,AutoCalorAuto Zeroareinprogress. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com PINDESCRIPTIONS(continued) PinName PinDescription ChipSelectinputpin.Whenalogiclowisappliedtothispin,therisingedgeofSCLKshiftsthedataonDIintothe addressregister.ThislowalsobringsDOoutofTRI-STATE.WithCSlowthefallingedgeofSCLKshiftsthedata resultingfromthepreviousADCconversionoutattheDOoutput,withtheexceptionofthefirstbitofdata.When CSislowcontinuously,thefirstbitofthedataisclockedoutontherisingedgeofEOC(endofconversion).When CSistoggledthefallingedgeofCSalwaysclocksoutthefirstbitofdata.CSshouldbebroughtlowwhileSCLKis low.ThefallingedgeofCSinterruptsaconversioninprogressandstartsthesequenceforanewconversion. CS WhenCSisbroughtbacklowduringaconversion,thatconversionisprematurelyterminated.Thedatainthe outputlatchesmaybecorrupted.Therefore,whenCSisbroughtlowduringaconversioninprogress,thedata outputatthattimeshouldbeignored.CSmayalsobeleftcontinuouslylow.Inthiscaseitisimperativethatthe correctnumberofSCLKpulsesbeappliedtotheADCinordertoremainsynchronous.AftertheADCsupplypower isappliedthedeviceexpectstosee13clockpulsesforeachI/Osequence.ThenumberofclockpulsestheADC expectsisthesameasthedigitaloutputwordlength.Thiswordlengthcanbemodifiedbythedatashiftedinonthe DOpin.Table5detailsthedatarequired. DataOutputReadypin.Thispinisanactivepush/pulloutputwhichislowwhentheconversionresultisbeing DOR shiftedoutandgoeshightosignalthatallthedatahasbeenshiftedout. SerialDataClockinput.Theclockappliedtothisinputcontrolstherateatwhichtheserialdataexchangeoccurs. TherisingedgeloadstheinformationontheDIpinintothemultiplexeraddressandmodeselectshiftregister.This addresscontrolswhichchanneloftheanaloginputmultiplexer(MUX)isselectedandthemodeofoperationforthe ADC.WithCSlowthefallingedgeofSCLKshiftsthedataresultingfromthepreviousADCconversionoutonDO, SCLK withtheexceptionofthefirstbitofdata.WhenCSislowcontinuously,thefirstbitofthedataisclockedoutonthe risingedgeofEOC(endofconversion).WhenCSistoggledthefallingedgeofCSalwaysclocksoutthefirstbitof data.CSshouldbebroughtlowwhenSCLKislow.Theriseandfalltimesoftheclockedgesshouldnotexceed 1µs. ConversionClockinput.Theclockappliedtothisinputcontrolsthesuccessiveapproximationconversiontime CCLK intervalandtheacquisitiontime.Theriseandfalltimesoftheclockedgesshouldnotexceed1µs. Positiveanalogvoltagereferenceinput.Inordertomaintainaccuracy,thevoltagerangeofV (V =V +− REF REF REF V + V −)is1V to5.0V andthevoltageatV +cannotexceedV +.SeeFigure59forrecommended REF REF DC DC REF A bypassing. Thenegativeanalogvoltagereferenceinput.Inordertomaintainaccuracy,thevoltageatthispinmustnotgo V - REF belowGNDorexceedV +.(SeeFigure59). A PowerDownpin.WhenPDishightheADCispowereddown;whenPDislowtheADCispoweredup,oractive. PD TheADCtakesamaximumof250µstopowerupafterthecommandisgiven. V + Thesearetheanaloganddigitalpowersupplypins.VA+andVD+arenotconnectedtogetheronthechip.These VA+ pinsshouldbetiedtothesamesupplyvoltageandbypassedseparately(seeFigure59).Theoperatingvoltage D rangeofV +andV +is4.5V to5.5V . A D DC DC DGND Thedigitalgroundpin(seeFigure59). AGND Theanaloggroundpin(seeFigure59). Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 4 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Absolute Maximum Ratings (1)(2)(3) PositiveSupplyVoltage (V+=V +=V +) 6.5V A D VoltageatInputsandOutputs exceptCH0–CH7and −0.3Vto(V++0.3V) COM VoltageatAnalogInputs CH0–CH7andCOM GND−5Vto(V++5V) |V +−V +| 300mV A D InputCurrentatAnyPin (4) ±30mA PackageInputCurrent (4) ±120mA PackageDissipationat T =25°C (5) 500mW A ESDSusceptibility (6) HumanBodyModel 1500V SolderingInformation PDIPPackage(10seconds) 260°C SOICPackage (7) VaporPhase(60seconds) 215°C Infrared(15seconds) 220°C StorageTemperature −65°Cto+150°C (1) AllvoltagesaremeasuredwithrespecttoGND,unlessotherwisespecified. (2) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay degradewhenthedeviceisnotoperatedunderthelistedtestconditions. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand specifications. (4) Whentheinputvoltage(V )atanypinexceedsthepowersupplies(V <GNDorV >V +orV +),thecurrentatthatpinshouldbe IN IN IN A D limitedto30mA.The120mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepower supplieswithaninputcurrentof30mAtofour. (5) ThemaximumpowerdissipationmustbederatedatelevatedtemperaturesandisdictatedbyTmax,θ andtheambienttemperature, J JA T .ThemaximumallowablepowerdissipationatanytemperatureisP =(Tmax−T )/θ orthenumbergivenintheAbsolute A D J A JA MaximumRatings,whicheverislower. (6) Thehumanbodymodelisa100pFcapacitordischargedthrougha1.5kΩresistorintoeachpin. (7) SeeAN450“SurfaceMountingMethodsandTheirEffectonProductReliability”orthesectiontitled“SurfaceMount”foundinanypost 1986LinearDataBookforothermethodsofsolderingsurfacemountdevices. Operating Ratings (1)(2) OperatingTemperatureRange T ≤T ≤T MIN A MAX −40°C≤T ≤+85°C A SupplyVoltage(V+=V +=V +) +4.5Vto+5.5V A D |V +−V +| ≤100mV A D V + 0VtoV + REF A V − 0Vto(V +−1V) REF REF V (V +−V −) 1VtoV + REF REF REF A V CommonModeVoltageRange REF [(V +)−(V −)]/2 0.1V +to0.6V + REF REF A A A/DIN1,A/DIN2,MUXOUT1andMUXOUT2VoltageRange 0VtoV + A INCommonModeVoltageRange [(V +)−(V −)]/2 0VtoV + IN IN A (1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay degradewhenthedeviceisnotoperatedunderthelistedtestconditions. (2) AllvoltagesaremeasuredwithrespecttoGND,unlessotherwisespecified. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Package Thermal Resistance PartNumber ThermalResistance(θ ) JA ADC12(H)030CIWM 70°C/W ADC12032CIWM 64°C/W ADC12034CIN 42°C/W ADC12034CIWM 57°C/W ADC12H034CIMSA 97°C/W ADC12(H)038CIWM 50°C/W NOTE:SomeofthesedevicesmaybeobsoleteoronLifetimeBuystatus.Checkourwebsiteforproduct availability. Converter Electrical Characteristics ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign A D DC REF DC REF DC conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor CK SK CK SK theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully- S REF REF differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface CK limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C. (1)(2)(3) A J MIN MAX A J Parameter TestConditions Typical (4) Limits (5) Units (Limits) STATICCONVERTERCHARACTERISTICS ResolutionwithNoMissingCodes 12+sign Bits(min) ILE IntegralLinearityError AfterAutoCal (6)(7) ±1/2 ±1 LSB(max) DNL DifferentialNon-Linearity AfterAutoCal ±1 LSB(max) PositiveFull-ScaleError AfterAutoCal (6)(7) ±1/2 ±3.0 LSB(max) NegativeFull-ScaleError AfterAutoCal (6)(7) ±1/2 ±3.0 LSB(max) AfterAutoCal (8)(7) OffsetError ±1/2 ±2 LSB(max) V (+)=V (−)=2.048V IN IN DCCommonModeError AfterAutoCal (9) ±2 ±3.5 LSB(max) (1) Twoon-chipdiodesaretiedtoeachanaloginputthroughaseriesresistorasshownbelow.Inputvoltagemagnitudeupto5VaboveV + A or5VbelowGNDwillnotdamagethisdevice.However,errorsintheconversioncanoccur(ifthesediodesareforwardbiasedbymore than50mV)iftheinputvoltagemagnitudeofselectedorunselectedanaloginputgoaboveV +orbelowGNDbymorethan50mV.As A anexample,ifV +is4.5V ,full-scaleinputvoltagemustbe≤4.55V toensureaccurateconversions. A DC DC (2) Toensureaccuracy,itisrequiredthattheV +andV +beconnectedtogethertothesamepowersupplywithseparatebypass A D capacitorsateachV+pin. (3) WiththetestconditionforV (V +−V −)givenas+4.096V,the12-bitLSBis1.0mVandthe8-bitLSBis16.0mV. REF REF REF (4) TypicalfiguresareatT =T =25°Candrepresentmostlikelyparametricnorm. J A (5) TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel). (6) PositiveintegrallinearityErrorisdefinedasthedeviationoftheanalogvalue,expressedinLSBs,fromthestraightlinethatpasses throughpositivefull-scaleandzero.ForNegativeIntegralLinearityError,thestraightlinepassesthroughnegativefull-scaleandzero (seeFigure6andFigure7). (7) TheADC12030family'sself-calibrationtechniqueensureslinearityandoffseterrorsasspecified,butnoiseinherentintheself- calibrationprocesswillresultinamaximumrepeatabilityuncertaintyof0.2LSB. (8) Thehumanbodymodelisa100pFcapacitordischargedthrougha1.5kΩresistorintoeachpin. (9) TheDCcommon-modeerrorismeasuredinthedifferentialmultiplexermodewiththeassignedpositiveandnegativeinputchannels shortedtogether. 6 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Converter Electrical Characteristics (continued) ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign A D DC REF DC REF DC conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor CK SK CK SK theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully- S REF REF differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface CK limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C.(1)(2)(3) A J MIN MAX A J Parameter TestConditions Typical (4) Limits (5) Units (Limits) TUE TotalUnadjustedError AfterAutoCal (6)(10)(11) ±1 LSB ResolutionwithNoMissingCodes 8-bit+signmode 8+sign Bits(min) INL IntegralLinearityError 8-bit+signmode (6) ±1/2 LSB(max) DNL DifferentialNon-Linearity 8-bit+signmode ±3/4 LSB(max) PositiveFull-ScaleError 8-bit+signmode (6) ±1/2 LSB(max) NegativeFull-ScaleError 8-bit+signmode (6) ±1/2 LSB(max) 8-bit+signmode,afterAutoZero OffsetError V (+)=V (−)=+2.048V (10) ±1/2 LSB(max) IN IN 8-bit+signmodeafterAutoZero TUE TotalUnadjustedError (6)(10)(11) ±3/4 LSB(max) MultiplexerChan-to-ChanMatching ±0.05 LSB PowerSupplySensitivity V+=+5V±10%,V =+4.096V REF OffsetError ±0.5 ±1 LSB(max) +Full-ScaleError ±0.5 ±1.5 LSB(max) −Full-ScaleError ±0.5 ±1.5 LSB(max) IntegralLinearityError ±0.5 LSB OutputDatafrom“12-Bit (seeTable5) (12) +10 LSB(max) ConversionofOffset” −10 LSB(min) OutputDatafrom“12-Bit (seeTable5) (12) 4095 LSB(max) ConversionofFull-Scale” 4093 LSB(min) UNIPOLARDYNAMICCONVERTERCHARACTERISTICS f =1kHz,V =5V ,V +=5.0V 69.4 dB IN IN P-P REF S/(N+D) Signal-to-NoisePlusDistortionRatio f =20kHz,V =5V ,V +=5.0V 68.3 dB IN IN P-P REF f =40kHz,V =5V ,V +=5.0V 65.7 dB IN IN P-P REF −3dBFullPowerBandwidth V =5V ,whereS/(N+D)drops3dB 31 kHz IN P-P DIFFERENTIALDYNAMICCONVERTERCHARACTERISTICS f =1kHz,V =±5V,V +=5.0V 77.0 dB IN IN REF S/(N+D) Signal-to-NoisePlusDistortionRatio f =20kHz,V =±5V,V +=5.0V 73.9 dB IN IN REF f =40kHz,V =±5V,V +=5.0V 67.0 dB IN IN REF −3dBFullPowerBandwidth V =±5V,whereS/(N+D)drops3dB 40 kHz IN REFERENCEINPUT,ANALOGINPUTSANDMULTIPLEXERCHARACTERISTICS C ReferenceInputCapacitance 85 pF REF A/DIN1,A/DIN2AnalogInput C 75 pF A/D Capacitance A/DIN1,A/DIN2AnalogInput V =+5.0VorV =0V ±0.1 ±1.0 µA(max) LeakageCurrent IN IN GND−0.05 V(min) CH0–CH7andCOMInputVoltage (V +)+0.05 V(max) A CH0–CH7andCOMInput C 10 pF CH Capacitance C MUXOutputCapacitance 20 pF MUXOUT (10) Offseterrorisameasureofthedeviationfromthemid-scalevoltage(acodeofzero),expressedinLSB.Itistheworst-casevalueofthe codetransitionsbetween1to0and0to+1(seeFigure8). (11) Totalunadjustederrorincludesoffset,full-scale,linearityandmultiplexererrors. (12) The“12-BitConversionofOffset”and“12-BitConversionofFull-Scale”modesareintendedtotestthefunctionalityofthedevice. Therefore,theoutputdatafromthesemodesarenotanindicationoftheaccuracyofaconversionresult. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Converter Electrical Characteristics (continued) ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign A D DC REF DC REF DC conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor CK SK CK SK theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully- S REF REF differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface CK limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C.(1)(2)(3) A J MIN MAX A J Parameter TestConditions Typical (4) Limits (5) Units (Limits) OffChannelLeakageCH0–CH7 OnChannel=5VandOffChannel=0V −0.01 −0.3 µA(min) andCOMPins (13) OnChannel=0VandOffChannel=5V 0.01 0.3 µA(max) OnChannelLeakageCH0–CH7 OnChannel=5VandOffChannel=0V 0.01 0.3 µA(max) andCOMPins (13) OnChannel=0VandOffChannel=5V −0.01 −0.3 µA(min) MUXOUT1andMUXOUT2Leakage V =5.0VorV =0V 0.01 0.3 µA(max) Current MUXOUT MUXOUT R MUXOnResistance V =2.5VandV =2.4V 850 1150 Ω(max) ON IN MUXOUT R MatchingChan-to-Chan V =2.5VandV =2.4V 5 % ON IN MUXOUT Chan-to-ChanCrosstalk V =5V ,f =40kHz −72 dB IN P-P IN MUXBandwidth 90 kHz (13) Channelleakagecurrentismeasuredafterthechannelselection. DC and Logic Electrical Characteristics ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign A D DC REF DC REF DC conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor CK SK CK SK theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully- S REF REF differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface CK limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C. (1)(2)(3) A J MIN MAX A J Parameter TestConditions Typical (4) Limits (5) Units (Limits) CCLK,CS,CONV,DI,PDANDSCLKINPUTCHARACTERISTICS V Logical“1”InputVoltage V+=5.5V 2.0 V(min) IN(1) V Logical“0”InputVoltage V+=4.5V 0.8 V(max) IN(0) I Logical“1”InputCurrent V =5.0V 0.005 1.0 µA(max) IN(1) IN I Logical“0”InputCurrent V =0V −0.005 −1.0 µA(min) IN(0) IN DO,EOCANDDORDIGITALOUTPUTCHARACTERISTICS V+=4.5V,I =−360µA 2.4 V(min) OUT V Logical“1”OutputVoltage OUT(1) V+=4.5V,I =−10µA 4.25 V(min) OUT (1) Twoon-chipdiodesaretiedtoeachanaloginputthroughaseriesresistorasshownbelow.Inputvoltagemagnitudeupto5VaboveV + A or5VbelowGNDwillnotdamagethisdevice.However,errorsintheconversioncanoccur(ifthesediodesareforwardbiasedbymore than50mV)iftheinputvoltagemagnitudeofselectedorunselectedanaloginputgoaboveV +orbelowGNDbymorethan50mV.As A anexample,ifV +is4.5V ,full-scaleinputvoltagemustbe≤4.55V toensureaccurateconversions. A DC DC (2) Toensureaccuracy,itisrequiredthattheV +andV +beconnectedtogethertothesamepowersupplywithseparatebypass A D capacitorsateachV+pin. (3) WiththetestconditionforV (V +−V −)givenas+4.096V,the12-bitLSBis1.0mVandthe8-bitLSBis16.0mV. REF REF REF (4) TypicalfiguresareatT =T =25°Candrepresentmostlikelyparametricnorm. J A (5) TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel). 8 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 DC and Logic Electrical Characteristics (continued) ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign A D DC REF DC REF DC conversionmode,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f =5MHzfor CK SK CK SK theADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω,fully- S REF REF differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified.Boldface CK limitsapplyforT =T =T toT ;allotherlimitsT =T =25°C.(1)(2)(3) A J MIN MAX A J Parameter TestConditions Typical (4) Limits (5) Units (Limits) V Logical“0”OutputVoltage V+=4.5V,I =1.6mA 0.4 V(max) OUT(0) OUT V =0V −0.1 −3.0 µA(max) OUT I TRI-STATEOutputCurrent OUT V =5V 0.1 3.0 µA(max) OUT +I OutputShortCircuitSourceCurrent V =0V 14 6.5 mA(min) SC OUT −I OutputShortCircuitSinkCurrent V =V + 16 8.0 mA(min) SC OUT D POWERSUPPLYCHARACTERISTICS DigitalSupplyCurrent Awake 1.6 2.5 mA(max) ADC12030,ADC12032,ADC12034and CS=HIGH,PoweredDown,CCLKon 600 µA ADC12038 CS=HIGH,PoweredDown,CCLKoff 20 µA I + D DigitalSupplyCurrent Awake 2.3 3.2 mA ADC12H030,ADC12H032,ADC12H034 CS=HIGH,PoweredDown,CCLKon 0.9 mA andADC12H038 CS=HIGH,PoweredDown,CCLKoff 20 µA Awake 2.7 4.0 mA(max) I + PositiveAnalogSupplyCurrent CS=HIGH,PoweredDown,CCLKon 10 µA A CS=HIGH,PoweredDown,CCLKoff 0.1 µA Awake 70 µA I ReferenceInputCurrent REF CS=HIGH,PoweredDown 0.1 µA AC Electrical Characteristics ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign A D DC REF DC REF DC conversionmode,t =t =3ns,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f r f CK SK CK SK =5MHzfortheADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤ S REF REF 25Ω,fully-differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified. CK BoldfacelimitsapplyforT =T =T toT ;allotherlimitsT =T =25°C. (1) A J MIN MAX A J Typical ADC12H030/2/4/8 ADC12030/2/4/8 Units Parameter TestConditions (2) Limits (3) Limits (3) (Limits) f ConversionClock(CCLK) 10 8 5 MHz(max) CK Frequency 1 MHz(min) SerialDataClockSCLKFrequency 10 8 5 MHz(max) f SK 0 Hz(min) 40 40 %(min) ConversionClockDutyCycle 60 60 %(max) 40 40 %(min) SerialDataClockDutyCycle 60 60 %(max) 12-Bit+Signor12- 44(t ) 44(t ) (max) 44(t ) CK CK Bit CK 5.5 8.8 µs(max) t ConversionTime C 21(t ) 21(t ) (max) 8-Bit+Signor8-Bit 21(t ) CK CK CK 2.625 4.2 µs(max) (1) TimingspecificationsaretestedattheTTLlogiclevels,V =0.4VforafallingedgeandV =2.4Vforarisingedge.TRI-STATEoutput IL IH voltageisforcedto1.4V. (2) TypicalfiguresareatT =T =25°Candrepresentmostlikelyparametricnorm. J A (3) TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel). Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com AC Electrical Characteristics (continued) ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign A D DC REF DC REF DC conversionmode,t =t =3ns,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H038,f =f r f CK SK CK SK =5MHzfortheADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤ S REF REF 25Ω,fully-differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified. CK BoldfacelimitsapplyforT =T =T toT ;allotherlimitsT =T =25°C.(1) A J MIN MAX A J Typical ADC12H030/2/4/8 ADC12030/2/4/8 Units Parameter TestConditions (2) Limits (3) Limits (3) (Limits) 6(t ) 6(t ) (min) CK CK 6(t ) CK 6Cycles 7(tCK) 7(tCK) (max) Programmed 0.75 1.2 µs(min) 0.875 1.4 µs(max) 10(t ) 10(t ) (min) CK CK 10(t ) CK 10Cycles 11(tCK) 11(tCK) (max) Programmed 1.25 2.0 µs(min) 1.375 2.2 µs(max) t AcquisitionTime (4) A 18(t ) 18(t ) (min) CK CK 18(t ) CK 18Cycles 19(tCK) 19(tCK) (max) Programmed 2.25 3.6 µs(min) 2.375 3.8 µs(max) 34(t ) 34(t ) (min) CK CK 34(t ) CK 34Cycles 35(tCK) 35(tCK) (max) Programmed 4.25 6.8 µs(min) 4.375 7.0 µs(max) 4944(t ) 4944(t ) 4944(t ) (max) CK CK CK t Self-CalibrationTime CKAL 618.0 988.8 µs(max) 76(t ) 76(t ) 76(t ) (max) CK CK CK t AutoZeroTime AZ 9.5 15.2 µs(max) 2(t ) 2(t ) 2(t ) (min) CK CK CK Self-CalibrationorAutoZero 3(tCK) 3(tCK) (max) t SYNC SynchronizationTimefromDOR 0.250 0.40 µs(min) 0.375 0.60 µs(max) DORHighTimewhenCSisLow t ContinuouslyforReadDataand 9(t ) 9(t ) 9(t ) (max) DOR SK SK SK SoftwarePowerUp/Down 1.125 1.8 µs(max) 8(t ) 8(t ) 8(t ) (max) SK SK SK t CONVValidDataTime CONV 1.0 1.6 µs(max) (4) IfSCLKandCCLKaredrivenfromthesameclocksource,thent is6,10,18or34clockperiodsminimumandmaximum. A 10 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Timing Characteristics ThefollowingspecificationsapplyforV+=V +=V +=+5.0V ,V +=+4.096V ,V −=0V ,12-bit+sign A D DC REF DC REF DC conversionmode,t =t =3ns,f =f =8MHzfortheADC12H030,ADC12H032,ADC12H034andADC12H03,f =f = r f CK SK CK SK 5MHzfortheADC12030,ADC12032,ADC12034andADC12038,R =25Ω,sourceimpedanceforV +andV −≤25Ω, S REF REF fully-differentialinputwithfixed2.048Vcommon-modevoltage,and10(t )acquisitiontimeunlessotherwisespecified. CK BoldfacelimitsapplyforT =T =T toT ;allotherlimitsT =T =25°C. (1) A J MIN MAX A J Typical Limits Units Parameter TestConditions (2) (3) (Limits) HardwarePower-UpTime,TimefromPDFallingEdgeto t 140 250 µs(max) HPU EOCRisingEdge SoftwarePower-UpTime,TimefromSerialDataClock t 140 250 µs(max) SPU FallingEdgetoEOCRisingEdge t AccessTimeDelayfromCSFallingEdgetoDODataValid 20 50 ns(max) ACC Set-UpTimeofCSFallingEdgetoSerialDataClockRising t 30 ns(min) SET-UP Edge t DelayfromSCLKFallingEdgetoCSFallingEdge 0 5 ns(min) DELAY t ,t DelayfromCSRisingEdgetoDOTRI-STATE R =3k,C =100pF 40 100 ns(max) 1H 0H L L t DIHoldTimefromSerialDataClockRisingEdge 5 15 ns(min) HDI t DISet-UpTimefromSerialDataClockRisingEdge 5 10 ns(min) SDI 50 ns(max) t DOHoldTimefromSerialDataClockFallingEdge R =3k,C =100pF 25 HDO L L 5 ns(min) t DelayfromSerialDataClockFallingEdgetoDODataValid 35 50 ns(max) DDO DORiseTime,TRI-STATEtoHigh R =3k,C =100pF 10 30 ns(max) L L t RDO DORiseTime,LowtoHigh R =3k,C =100pF 10 30 ns(max) L L DOFallTime,TRI-STATEtoLow R =3k,C =100pF 12 30 ns(max) L L t FDO DOFallTime,HightoLow R =3k,C =100pF 12 30 ns(max) L L t DelayfromCSFallingEdgetoDORFallingEdge 25 45 ns(max) CD DelayfromSerialDataClockFallingEdgetoDORRising t 25 45 ns(max) SD Edge C CapacitanceofLogicInputs 10 pF IN C CapacitanceofLogicOutputs 20 pF OUT (1) TimingspecificationsaretestedattheTTLlogiclevels,V =0.4VforafallingedgeandV =2.4Vforarisingedge.TRI-STATEoutput IL IH voltageisforcedto1.4V. (2) TypicalfiguresareatT =T =25°Candrepresentmostlikelyparametricnorm. J A (3) TestedlimitsarespecifiedtoAOQL(AverageOutgoingQualityLevel). Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Figure5. TransferCharacteristic Figure6. SimplifiedErrorCurvevs.OutputCodewithoutAutoCalibrationorAutoZeroCycles 12 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Figure7. SimplifiedErrorCurvevs.OutputCodeafterAutoCalibrationCycle Figure8. OffsetorZeroErrorVoltage Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Typical Performance Characteristics (1) Thefollowingcurvesapplyfor12-bit+signmodeafterAutoCalibrationunlessotherwisespecified.Theperformancefor8-bit +signmodeisequaltoorbetterthanshown. LinearityErrorChange LinearityErrorChange vs.ClockFrequency vs.Temperature Figure9. Figure10. LinearityErrorChange LinearityErrorChange vs.ReferenceVoltage vs.SupplyVoltage Figure11. Figure12. Full-ScaleErrorChange Full-ScaleErrorChange vs.ClockFrequency vs.Temperature Figure13. Figure14. (1) WiththetestconditionforV (V +−V −)givenas+4.096V,the12-bitLSBis1.0mVandthe8-bitLSBis16.0mV. REF REF REF 14 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Typical Performance Characteristics (1) (continued) Thefollowingcurvesapplyfor12-bit+signmodeafterAutoCalibrationunlessotherwisespecified.Theperformancefor8-bit +signmodeisequaltoorbetterthanshown. Full-ScaleErrorChange Full-ScaleErrorChange vs.ReferenceVoltage vs.SupplyVoltage Figure15. Figure16. OffsetorZeroErrorChange OffsetorZeroErrorChange vs.ClockFrequency vs.Temperature Figure17. Figure18. OffsetorZeroErrorChange OffsetorZeroErrorChange vs.ReferenceVoltage vs.SupplyVoltage Figure19. Figure20. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Typical Performance Characteristics (1) (continued) Thefollowingcurvesapplyfor12-bit+signmodeafterAutoCalibrationunlessotherwisespecified.Theperformancefor8-bit +signmodeisequaltoorbetterthanshown. AnalogSupplyCurrent DigitalSupplyCurrent vs.Temperature vs.ClockFrequency Figure21. Figure22. DigitalSupplyCurrent vs.Temperature Figure23. 16 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Typical Dynamic Performance Characteristics Thefollowingcurvesapplyfor12-bit+signmodeafterAutoCalibrationunlessotherwisespecified. BipolarSpectralResponse BipolarSpectralResponse with1kHzSineWaveInput with10kHzSineWaveInput Figure24. Figure25. BipolarSpectralResponse BipolarSpectralResponse with20kHzSineWaveInput with30kHzSineWaveInput Figure26. Figure27. BipolarSpectralResponse BipolarSpectralResponse with40kHzSineWaveInput with50kHzSineWaveInput Figure28. Figure29. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Typical Dynamic Performance Characteristics (continued) Thefollowingcurvesapplyfor12-bit+signmodeafterAutoCalibrationunlessotherwisespecified. BipolarSpuriousFree UnipolarSignal-to-NoiseRatio DynamicRange vs.InputFrequency Figure30. Figure31. UnipolarSignal-to-Noise UnipolarSignal-to-Noise +DistortionRatio +DistortionRatio vs.InputFrequency vs.InputSignalLevel Figure32. Figure33. UnipolarSpectralResponse UnipolarSpectralResponse with1kHzSineWaveInput with10kHzSineWaveInput Figure34. Figure35. 18 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Typical Dynamic Performance Characteristics (continued) Thefollowingcurvesapplyfor12-bit+signmodeafterAutoCalibrationunlessotherwisespecified. UnipolarSpectralResponse UnipolarSpectralResponse with20kHzSineWaveInput with30kHzSineWaveInput Figure36. Figure37. UnipolarSpectralResponse UnipolarSpectralResponse with40kHzSineWaveInput with50kHzSineWaveInput Figure38. Figure39. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Test Circuits Figure40. DO“TRI-STATE”(t ,t ) 1H OH Figure41. DOexcept“TRI-STATE” Figure42. LeakageCurrent Timing Diagrams Figure43. DOFallingandRisingEdge Figure44. DO“TRI-STATE”FallingandRisingEdge 20 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Figure45. DIDataInputTiming Figure46. DODataOutputTimingUsingCS 0 1 2 3 4 n SCLK tSET-UP CS tHDO tDDO tACC tHDO tDDO DO 2.4V 2.4V 0.4V 0.4V 2.4V tCD tSD DOR EOC Figure47. DODataOutputTimingwithCSContinuouslyLow Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Note:DOoutputdataisnotvalidduringthiscycle. Figure48. ADC12038AutoCalorAutoZero Figure49. ADC12038ReadDatawithoutStartingaConversionUsingCS 22 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Figure50. ADC12038ReadDatawithoutStartingaConversionwithCSContinuouslyLow Figure51. ADC12038ConversionUsingCSwith8-BitDigitalOutputFormat Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Figure52. ADC12038ConversionUsingCSwith16-BitDigitalOutputFormat Figure53. ADC12038ConversionwithCSContinuouslyLowand8-BitDigitalOutputFormat 24 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Figure54. ADC12038ConversionwithCSContinuouslyLowand16-BitDigitalOutputFormat Figure55. ADC12038SoftwarePowerUp/DownUsingCSwith16-BitDigitalOutputFormat Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Figure56. ADC12038SoftwarePowerUp/DownwithCSContinuouslyLowand16-BitDigitalOutput Format Note:Hardwarepowerup/downmayoccuratanytime.IfPDishighwhileaconversionisinprogressthatconversion willbecorruptedanderroneousdatawillbestoredintheoutputshiftregister. Figure57. ADC12038HardwarePowerUp/Down 26 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Note:Inorderforall9bitsofStatusInformationtobeaccessible,thelastconversionprogrammedbeforeCycleN needstohavearesolutionof8bitsplussign,12bits,12bitsplussign,orgreater. Figure58. ADC12038ConfigurationModification—ExampleofaStatusRead VA+ ** ** 0.01 uF 0.1 uF 10 uF * ANALOG ASSIGNED INPUT (+) INPUT VOLTAGE VD+ ** ** +5.0V 0.01 uF 0.1 uF 10 uF * ADC ANIANLPOUGT ASSIGNED VREF+ 0.0*1* uF 0.1* *uF 10 uF * +4.096V (-) INPUT VOLTAGE VREF- AGND DGND ANALOG INPUT VOLTAGE GROUND REFERENCE *Tantalum **MonolithicCeramicorbetter Figure59. RecommendedPowerSupplyBypassingandGrounding Figure60. ProtectingtheMUXOUT1,MUXOUT2,A/DIN1andA/DIN2AnalogPins Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Format and Set-Up Tables Table1.DataOutFormats(1) DOFormats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 17 X X X X Sign MSB 10 9 8 7 6 5 4 3 2 1 LSB Bits MSB 13 Sign MSB 10 9 8 7 6 5 4 3 2 1 LSB First Bits 9 Sign MSB 6 5 4 3 2 1 LSB Bits withSign 17 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign X X X X Bits LSB 13 LSB 1 2 3 4 5 6 7 8 9 10 MSB Sign First Bits 9 LSB 1 2 3 4 5 6 MSB Sign Bits 16 0 0 0 0 MSB 10 9 8 7 6 5 4 3 2 1 LSB Bits MSB 12 MSB 10 9 8 7 6 5 4 3 2 1 LSB First Bits 8 MSB 6 5 4 3 2 1 LSB without Bits sign 16 LSB 1 2 3 4 5 6 7 8 9 10 MSB 0 0 0 Bits LSB 12 LSB 1 2 3 4 5 6 7 8 9 10 MSB First Bits 8 LSB 1 2 3 4 5 6 MSB Bits (1) X=HighorLowstate. Table2.ADC12038MultiplexerAddressing AnalogChannelAddressed andAssignment ADCInputPolarity MultiplexerOutput MUXAddress withA/DIN1tiedtoMUXOUT1 Assignment ChannelAssignment Mode andA/DIN2tiedtoMUXOUT2 DI0 DI1 DI2 DI3 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2 L L L L + − + − CH0 CH1 L L L H + − + − CH2 CH3 L L H L + − + − CH4 CH5 L L H H + − + − CH6 CH7 Differential L H L L − + − + CH0 CH1 L H L H − + − + CH2 CH3 L H H L − + − + CH4 CH5 L H H H − + − + CH6 CH7 H L L L + − + − CH0 COM H L L H + − + − CH2 COM H L H L + − + − CH4 COM H L H H + − + − CH6 COM Single-Ended H H L L + − + − CH1 COM H H L H + − + − CH3 COM H H H L + − + − CH5 COM H H H H + − + − CH7 COM 28 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Table3.ADC12034MultiplexerAddressing AnalogChannelAddressed andAssignment ADCInputPolarity MultiplexerOutputChannel MUXAddress withA/DIN1tiedtoMUXOUT1 Assignment Assignment Mode andA/DIN2tiedtoMUXOUT2 DI0 DI1 DI2 CH0 CH1 CH2 CH3 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2 L L L + − + − CH0 CH1 L L H + − + − CH2 CH3 Differential L H L − + − + CH0 CH1 L H H − + − + CH2 CH3 H L L + − + − CH0 COM H L H + − + − CH2 COM Single-Ended H H L + − + − CH1 COM H H H + − + − CH3 COM Table4.ADC12032andADC12030MultiplexerAddressing AnalogChannelAddressed andAssignment ADCInputPolarity MultiplexerOutput MUXAddress Mode withA/DIN1tiedtoMUXOUT1 Assignment ChannelAssignment andA/DIN2tiedtoMUXOUT2 DI0 DI1 CH0 CH1 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2 L L + − + − CH0 CH1 Differential L H − + − + CH0 CH1 H L + − + − CH0 COM Single-Ended H H + − + − CH1 COM NOTE ADC12030 and ADC12H030 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins. Table5.ModeProgramming(1) ADC12038 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 ADC12034 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DOFormat ModeSelected (nextConversion ADC12030 (Current) Cycle) and DI0 DI1 DI2 DI3 DI4 DI5 ADC12032 SeeTable2,Table3,or L L L L 12BitConversion 12or13BitMSBFirst Table4 SeeTable2,Table3,or L L L H 12BitConversion 16or17BitMSBFirst Table4 SeeTable2,Table3,or L L H L 8BitConversion 8or9BitMSBFirst Table4 L L L L L L H H 12BitConversionofFull-Scale 12or13BitMSBFirst SeeTable2,Table3,or L H L L 12BitConversion 12or13BitLSBFirst Table4 SeeTable2,Table3,or L H L H 12BitConversion 16or17BitLSBFirst Table4 SeeTable2,Table3,or L H H L 8BitConversion 8or9BitLSBFirst Table4 (1) TheADCpowersupwithnoAutoCal,noAutoZero,10CCLKacquisitiontime,12-bit+signconversion,powerup,12-or13-bitMSB first,andusermode. X=Don'tCare Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com Table5.ModeProgramming(1)(continued) ADC12038 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 ADC12034 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DOFormat ModeSelected (nextConversion ADC12030 (Current) Cycle) and DI0 DI1 DI2 DI3 DI4 DI5 ADC12032 L L L L L H H H 12BitConversionofOffset 12or13BitLSBFirst L L L L H L L L AutoCal NoChange L L L L H L L H AutoZero NoChange L L L L H L H L PowerUp NoChange L L L L H L H H PowerDown NoChange L L L L H H L L ReadStatusRegister NoChange L L L L H H L H DataOutwithoutSign NoChange H L L L H H L H DataOutwithSign NoChange L L L L H H H L AcquisitionTime—6CCLKCycles NoChange L H L L H H H L AcquisitionTime—10CCLKCycles NoChange H L L L H H H L AcquisitionTime—18CCLKCycles NoChange H H L L H H H L AcquisitionTime—34CCLKCycles NoChange L L L L H H H H UserMode NoChange TestMode H X X X H H H H NoChange (CH1–CH7becomeActiveOutputs) Table6.Conversion/ReadDataOnlyModeProgramming CS CONV PD Mode L L L SeeTable5forMode L H L ReadOnly(PreviousDOFormat).NoConversion. H X L Idle X X H PowerDown Table7.StatusRegister StatusBit DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 Location StatusBit PU PD Cal 8or9 12or13 16or17 Sign Justification TestMode DeviceStatus DOOutputFormatStatus “High” “High” “High” “High” “High” “High” “High” When“High” When“High” indicatesa indicatesa indicatesan indicatesan indicatesa indicatesa indicates the thedeviceis PowerUp Power AutoCal 8or9bit 12or13bit 16or17bit thatthe conversion intestmode. Sequence Down Sequence format format format signbitis resultwillbe When“Low” isin Sequence isin included. outputMSB thedeviceis Function progress isin progress When“Low” first.When inuser progress thesignbit “Low”the mode. isnot resultwillbe included. outputLSB first. 30 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 APPLICATIONS INFORMATION 1.0 DIGITAL INTERFACE 1.1InterfaceConcepts TheexampleinFigure61showsatypicalsequenceofeventsafterthepowerisappliedtotheADC12030/2/4/8: Figure61. TypicalPowerSupplyPowerUpSequence The first instruction input to the ADC via DI initiates Auto Cal. The data output on DO at that time is meaningless and is completely random. To determine whether the Auto Cal has been completed, a read status instruction shouldbeissuedtotheADC.AgainthedataoutputatthattimehasnosignificancesincetheAutoCalprocedure modifies the data in the output shift register. To retrieve the status information, an additional read status instruction should be issued to the ADC. At this time the status data is available on DO. If the Cal signal in the status word is low, Auto Cal has been completed. Therefore, the next instruction issued can start a conversion. Thedataoutputatthistimeisagainstatusinformation. Tokeepnoisefromcorruptingtheconversion,statuscannotbereadduringaconversion.IfCSisstrobedandis brought low during a conversion, that conversion is prematurely ended. EOC can be used to determine the end ofaconversionortheADCcontrollercankeeptrackinsoftwareofwhenitwouldbeappropriatetocommunicate to the ADC again. Once it has been determined that a conversion has completed, another instruction can be transmittedtotheADC.Thedatafromthisconversioncanbeaccessedwhenthenextinstructionisissuedtothe ADC. Note, when CS is low continuously it is important to transmit the exact number of SCLK cycles, as shown in the timing diagrams. Not doing so will desynchronize the serial communication to the ADC. (See Section 1.3 CS Low ContinuouslyConsiderations.) 1.2ChangingConfiguration The configuration of the ADC12030/2/4/8 on power up defaults to 12-bit plus sign resolution, 12- or 13-bit MSB First, 10 CCLK acquisition time, user mode, no Auto Cal, no Auto Zero, and power up mode. Changing the acquisition time and turning the sign bit on and off requires an 8-bit instruction to be issued to the ADC. This instruction will not start a conversion. The instructions that select a multiplexer address and format the output data do start a conversion. Figure 62 describes an example of changing the configuration of the ADC12030/2/4/8. During I/O sequence 1, the instruction at DI configures the ADC12030/2/4/8 to do a conversion with 12-bit +sign resolution. Notice that when the 6 CCLK Acquisition and Data Out without Sign instructions are issued to the ADC, I/O sequences 2 and 3, a new conversion is not started. The data output during these instructions is from conversion N which was started during I/O sequence 1. Figure 58 in detail the sequence of events necessary for a Data Out without Sign, Data Out with Sign, or 6/10/18/34 CCLK Acquisition time mode selection. Table 5 describes the actual data necessary to be input to the ADC to accomplish this configuration modification. The next instruction issued to the ADC, shown in Figure 62, starts conversion N+1 with 8 bits of resolution formatted MSBfirst.AgainthedataoutputduringthisI/OcycleisthedatafromconversionN. The number of SCLKs applied to the ADC during any conversion I/O sequence should vary in accord with the data out word format chosen during the previous conversion I/O sequence. The various formats and resolutions available are shown in Table 1. In Figure 62, since 8-bit without sign, MSB first format was chosen during I/O sequence 4, the number of SCLKs required during I/O sequence 5 is eight. In the following I/O sequence the format changes to 12-bit without sign MSB first; therefore the number of SCLKs required during I/O sequence 6 changesaccordinglyto12. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com 1.3CSLowContinuouslyConsiderations When CS is continuously low, it is important to transmit the exact number of SCLK pulses that the ADC expects. Not doing so will desynchronize the serial communications to the ADC. When the supply power is first applied to the ADC, it will expect to see 13 SCLK pulses for each I/O transmission. The number of SCLK pulses that the ADC expects to see is the same as the digital output word length. The digital output word length is controlled by the Data Out (DO) format. The DO format maybe changed any time a conversion is started or when the sign bit isturnedonoroff.ThetablebelowdetailsoutthenumberofclockperiodsrequiredfordifferentDOformats: DOFormat NumberofSCLKsExpected SIGNOFF 8 8-BitMSBorLSBFirst SIGNON 9 SIGNOFF 12 12-BitMSBorLSBFirst SIGNON 13 SIGNOFF 16 16-BitMSBorLSBfirst SIGNON 17 If erroneous SCLK pulses desynchronize communications, the simplest way to recover is by cycling the power supply to the device. Not being able to easily resynchronize the device is a shortcoming of leaving CS low continuously. The number of clock pulses required for an I/O exchange may be different for the case when CS is left low continuouslyvs.thecasewhenCSiscycled.TaketheI/OsequencedetailedinFigure61(TypicalPowerSupply Sequence)asanexample.ThetablebelowliststhenumberofSCLKpulsesrequiredforeachinstruction: Instruction CSLowContinuously CSStrobed AutoCal 13SCLKs 8SCLKs ReadStatus 13SCLKs 8SCLKs ReadStatus 13SCLKs 8SCLKs 12-Bit+SignConv1 13SCLKs 8SCLKs 12-Bit+SignConv2 13SCLKs 13SCLKs 1.4AnalogInputChannelSelection The data input at DI also selects the channel configuration (see Table 2, Table 3, Table 4, and Table 5). In Figure62theonlytimeswhenthechannelconfigurationcouldbemodifiedisduringI/Osequences1,4,5and6. Input channels are reselected before the start of each new conversion. Shown below is the data bit stream required at DI, during I/O sequence number 4 in Figure 62, to set CH1 as the positive input and CH0 as the negativeinputforthedifferentversionsofADCs: Part DIData(1) Number DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 ADC12H030ADC12030 L H L L H L X X ADC12H032ADC12032 L H L L H L X X ADC12H034ADC12034 L H L L L H L X ADC12H038ADC12038 L H L L L L H L (1) Xcanbealogichigh(H)orlow(L). 1.5PowerUp/Down The ADC may be powered down by taking the PD pin HIGH or by the instruction input at DI (see Table 5 and Table 6, and the Power Up/Down timing diagrams). When the ADC is powered down in this way, the ADC conversioncircuitryisdeactivatedbutthedigitalI/Ocircuitryiskeptactive. 32 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 Hardware power up/down is controlled by the state of the PD pin. Software power-up/down is controlled by the instruction issued to the ADC. If a software power up instruction is issued to the ADC while a hardware power down is in effect (PD pin high) the device will remain in the power-down state. If a software power down instruction is issued to the ADC while a hardware power up is in effect (PD pin low), the device will power down. When the device is powered down by software, it may be powered up by either issuing a software power up instructionorbytakingPDpinhighandthenlow.Ifthepowerdowncommandisissuedduringaconversion,that conversionisinterrupted,sothedataoutputafterpowerupcannotbereliedupon. Figure62. ChangingtheADC'sConversionConfiguration 1.6UserModeandTestMode An instruction may be issued to the ADC to put it into test mode, which is used by the manufacturer to verify complete functionality of the device. During test mode CH0–CH7 become active outputs. If the device is inadvertently put into the test mode with CS continuously low, the serial communications may be desynchronized. Synchronization may be regained by cycling the power supply voltage to the device. Cycling the power supply voltage will also set the device into user mode. If CS is used in the serial interface, the ADC may be queried to see what mode it is in. This is done by issuing a “read STATUS register” instruction to the ADC. When bit 9 of the status register is high, the ADC is in test mode; when bit 9 is low the ADC, is in user mode. As an alternative to cycling the power supply, an instruction sequence may be used to return the device to user mode. This instruction sequence must be issued to the ADC using CS. The following table lists the instructions required to return the device to user mode. Note that this entire sequence, including both Test Mode and User Modevalues,shouldbesenttorecoverfromthetestmode. DIData(1) Instruction DI0 DI1 DI2 DI3 DI4 DI5 DI6 D17 TESTMODE H X X X H H H H Reset L L L L H H H L TestMode L L L L H L H L Instructions L L L L H L H H USERMODE L L L L H H H H PowerUp L L L L H L H L SetDOwithorwithoutSign HorL L L L H H L H SetAcquisitionTime HorL HorL L L H H H L StartaConversion HorL HorL HorL HorL L HorL HorL HorL (1) X=Don'tCare The power up, data with or without sign, and acquisition time instructions should be resent after returning to the usermode.ThisistoensurethattheADCisintherequiredstatebeforeaconversionisstarted. 1.7ReadingtheDataWithoutStartingaConversion The data from a particular conversion may be accessed without starting a new conversion by ensuring that the CONV line is taken high during the I/O sequence. See Figure 49 and Figure 50. Table 6 describes the operation of the CONV pin. It is not necessary to read the data as soon as DOR goes low. The data will remain in the output register ifCS is brought high right after DOR goes high. A single conversion may be read as many times asdesiredbeforeCSisbroughtlow. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com 1.8BrownOutConditions When the supply voltage dips below about 2.7V, the internal registers, including the calibration coefficients and all of the other registers, may lose their contents. When this happens the ADC will not perform as expected or not at all after power is fully restored. While writing the desired information to all registers and performing a calibration might sometimes cause recovery to full operation, the only sure recovery method is to reduce the supplyvoltagetobelow0.5V,thenreprogramtheADCandperformacalibrationafterpowerisfullyrestored. 2.0 THE ANALOG MULTIPLEXER For the ADC12038, the analog input multiplexer can be configured with 4 differential channels or 8 single ended channels with the COM input as the zero reference or any combination thereof (see Figure 63). The difference between the voltages at the V + and V − pins determines the input voltage span (V ). The analog input REF REF REF voltage range is 0 to V +. Negative digital output codes result when V − > V +. The actual voltage at V − or V + A IN IN IN IN cannotgobelowAGND. 8Single-EndedChannels 4Differential withCOM Channels asZeroReference Figure63. InputMultiplexerOptions Differential Single-Ended Configuration Configuration A/DIN1andA/DIN2canbeassignedasthe+or−input A/DIN1is+input A/DIN2is−input Figure64. MUXOUTconnectionsformultiplexeroption CH0, CH2, CH4, and CH6 can be assigned to the MUXOUT1 pin in the differential configuration, while CH1, CH3, CH5, and CH7 can be assigned to the MUXOUT2 pin. In the differential configuration, the analog inputs are paired as follows: CH0 with CH1, CH2 with CH3, CH4 with CH5 and CH6 with CH7. The A/DIN1 and A/DIN2 pinscanbeassignedpositiveornegativepolarity. With the single-ended multiplexer configuration, CH0 through CH7 can be assigned to the MUXOUT1 pin. The COM pin is always assigned to the MUXOUT2 pin. A/DIN1 is assigned as the positive input; A/DIN2 is assigned asthenegativeinput.(SeeFigure64). The Multiplexer assignment tables for these ADCs (Table 2,Table 3, andTable 4) summarize the aforementioned functionsforthedifferentversionsofADCs. 34 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 2.1BiasingforVariousMultiplexerConfigurations Figure 65 is an example of device connections for single-ended operation. The sign bit is always low. The digital outputrangeis0000000000000to0111111111111.OneLSBisequalto1mV(4.1V/4096LSBs). ANALOG INPUT CH0 VA+ 0.01 uF 0.1 uF 10 uF VOLTAGE RANGE CH2 0V TO 4.096V CH4 12-BITS ASSIGNED or UNSIGNED (+) INPUT CH6 VD+ 0.01 uF 0.1 uF 10 uF +5.0V ADC1203Y 1k ASSIGNED (-) INPUT VREF+ 0.01 uF 0.1 uF 10 uF +4.096V COM VREF- LM4040-4.1 AGND DGND ANALOG INPUT VOLTAGE GROUND REFERENCE Figure65. Single-EndedBiasing For pseudo-differential signed operation, the circuit of Figure 66 shows a signal AC coupled to the ADC. This gives a digital output range of −4096 to +4095. With a 2.5V reference, 1 LSB is equal to 610 µV. Although the ADC is not production tested with a 2.5V reference, when V + and V + are +5.0V, linearity error typically will not A D change more than 0.1 LSB (see the curves in the Typical Electrical Characteristics Section). With the ADC set to an acquisition time of 10 clock periods, the input biasing resistor needs to be 600Ω or less. Notice though that the input coupling capacitor needs to be made fairly large to bring down the high pass corner. Increasing the acquisition time to 34 clock periods (with a 5 MHz CCLK frequency) would allow the 600Ω to increase to 6k, which with a 1 µF coupling capacitor would set the high pass corner at 26 Hz. Increasing R, to 6k would allow R 2 tobe2k. ANALOG INPUT CH0 VA+ 0.01 uF 0.1 uF 10 uF VOLTAGE RANGE CH1 0V to 5V ASSIGNED CH2 12-BITS SIGNED (+) INPUT to CH8 VD+ 0.01 uF 0.1 uF 10 uF +5.0V 600: R1 ADC1203Y R2 430: (DEPENDS UPON ACQUISITION TIME) ASSIGNED (-) INPUT COM VREF+ 0.01 uF 0.1 uF 10 uF +2.5V LM4040-2.5 VREF- AGND DGND ANALOG INPUT VOLTAGE GROUND REFERENCE Figure66. Pseudo-DifferentialBiasingwiththeSignalSourceACCoupledDirectlyintotheADC An alternative method for biasing pseudo-differential operation is to use the +2.5V from the LM4040 to bias any amplifier circuits driving the ADC as shown in Figure 67. The value of the resistor pull-up biasing the LM4040-2.5 willdependuponthecurrentrequiredbytheopampbiasingcircuitry. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com In the circuit of Figure 67, some voltage range is lost since the amplifier will not be able to swing to +5V and GND with a single +5V supply. Using an adjustable version of the LM4041 to set the full scale voltage at exactly 2.048V and a lower grade LM4040D-2.5 to bias up everything to 2.5V as shown in Figure 68will allow the use of alltheADC'sdigitaloutputrangeof−4096to+4095whileleavingplentyofheadroomfortheamplifier. FullydifferentialoperationisshowninFigure69.OneLSBforthiscaseisequalto(4.1V/4096)=1mV. ANALOG INPUT VOLTAGE RANGE 0V to 5V CH0 VA+ 0.01 uF 0.1 uF 10 uF - CH2 ANALOG CH4 INPUT + ASSIGNED or VOLTAGE (+) INPUT CH6 VD+ 0.01 uF 0.1 uF 10 uF +5.0V 1M ADC1203Y 1k ASSIGNED (-) INPUT VREF+ 0.01 uF 0.1 uF 10 uF +2.5V COM LM4040-2.5 VREF- AGND DGND ANALOG INPUT VOLTAGE GROUND REFERENCE Figure67. AlternativePseudo-DifferentialBiasing ANALOG INPUT VOLTAGE RANGE 2.5V +/- 2.048V 12-BITS SIGNED CH0 VA+ 0.01 uF 0.1 uF 10 uF - CH2 ANALOG CH4 INPUT + ASSIGNED or VOLTAGE +5.0V (+) INPUT CH6 VD+ 0.01 uF 0.1 uF 10 uF +5.0V 1M ADC1203Y 2k 1k ASSIGNED (-) INPUT VREF+ 0.01 uF 0.1 uF 10 uF +2.048V COM LM4040-2.5 VREF- AGND DGND LM4041-ADJ ANALOG INPUT VOLTAGE GROUND REFERENCE Figure68. Pseudo-DifferentialBiasingwithouttheLossofDigitalOutputRange 36 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 CH0 VA+ 0.01 uF 0.1 uF 10 uF ANALOG INPUT CH2 VOLTAGE RANGE CH4 0.45V to 4.55V ASSIGNED or (+) INPUT CH6 VD+ 0.01 uF 0.1 uF 10 uF +5.0V FULLY DIFFERENTIAL 12-BIT PLUS SIGN ADC1203Y 1k CH1 +4.1V VOALNTAALGOEG R IANNPGUET CCHH35 VREF+ 0.01 uF 0.1 uF 10 uF 0.45V to 4.55V ASSIGNED or LM4040-4.1 (-) INPUT CH7 VREF- AGND DGND ANALOG INPUT VOLTAGE GROUND REFERENCE Figure69. FullyDifferentialBiasing 3.0 REFERENCE VOLTAGE The difference in the voltages applied to the V + and V − defines the analog input span (the difference REF REF between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground) over which 4095 positive and 4096 negative codes exist. The voltage sources driving V + and V − must have very low output impedance and noise. The circuit in Figure 70 is an example of a REF REF verystablereferenceappropriateforusewiththedevice. *Tantalum Figure70. LowDriftExtremely StableReferenceCircuit The ADC12030/2/4/8 can be used in either ratiometric or absolute reference applications. In ratiometric systems, the analog input voltage is proportional to the voltage used for the ADC's reference voltage. When this voltage is the system power supply, the V + pin is connected to V + and V − is connected to ground. This technique REF A REF relaxes the system reference stability requirements because the analog input voltage and the ADC reference voltage move together. This maintains the same output code for given input conditions. For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and temperature stable voltage source can be connected to the reference inputs. Typically, the reference voltage magnitude will require an initial adjustmenttonullreferencevoltageinducedfull-scaleerrors. Belowarerecommendedreferencesalongwithsomekeyspecifications. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com PartNumber OutputVoltageTolerance TemperatureCoefficient LM4041CI-Adj ±0.5% ±100ppm/°C LM4040AI-4.1 ±0.1% ±100ppm/°C LM4120AI-4.1 ±0.2% ±50ppm/°C LM4121AI-4.1 ±0.2% ±50ppm/°C LM4050AI-4.1 ±0.1% ±50ppm/°C LM4030AI-4.1 ±0.05% ±10ppm/°C LM4140AC-4.1 ±0.1% ±3.0ppm/°C CircuitofFigure70 Adjustable ±2ppm/°C The reference voltage inputs are not fully differential. The ADC12030/2/4/8 will not generate correct conversions or comparisons if V + is taken below V −. Correct conversions result when V + and V − differ by 1V or REF REF REF REF more and remain at all times between ground and V +. The V common mode range, (V + + V −)/2, is A REF REF REF restricted to (0.1 × V +) to (0.6 × V +). Therefore, with V + = 5V the center of the reference ladder should not go A A A below0.5Vorabove3.0V.Figure71isagraphicrepresentationofthevoltagerestrictionsonV +andV −. REF REF Figure71. V OperatingRange REF 4.0 ANALOG INPUT VOLTAGE RANGE The ADC12030/2/4/8's fully differential ADC generate a two's complement output that is found by using the equationsshownbelow: for(12-bit)resolutiontheOutputCode= (1) 38 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 for(8-bit)resolutiontheOutputCode= (2) Round off to the nearest integer value between −4096 to 4095 for 12-bit resolution and between −256 to 255 for 8-bitresolutioniftheresultoftheaboveequationisnotawholenumber. Examplesareshowninthetablebelow: V + V − V + V − DigitalOutputCode REF REF IN IN +2.5V +1V +1.5V 0V 0,1111,1111,1111 +4.096V 0V +3V 0V 0,1011,1011,1000 +4.096V 0V +2.499V +2.500V 1,1111,1111,1111 +4.096V 0V 0V +4.096V 1,0000,0000,0000 5.0 INPUT CURRENT Atthestartoftheacquisitionwindow(t )achargingcurrentflowsintooroutoftheanaloginputpins(A/DIN1and A A/DIN2) depending upon the input voltage polarity. The analog input pins are CH0–CH7 and COM when A/DIN1 is tied to MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value of this input current will depend upon the actual input voltage applied, the source impedance and the internal multiplexer switch on resistance. With MUXOUT1 tied to A/DIN1 and MUXOUT2 tied to A/DIN2 the internal multiplexer switch on resistance is typically 1.6kΩ.TheA/DIN1andA/DIN2muxonresistanceistypically750Ω. 6.0 INPUT SOURCE RESISTANCE For low impedance voltage sources (<600Ω), the input charging current will decay before the end of the S/H's acquisition time of 2 µs (10 CCLK periods with f = 5 MHz), to a value that will not introduce any conversion C errors. For high source impedances, the S/H's acquisition time can be increased to 18 or 34 CCLK periods. For less ADC resolution and/or slower CCLK frequencies the S/H's acquisition time may be decreased to 6 CCLK periods. To determine the number of clock periods (N ) required for the acquisition time with a specific source c impedanceforthevariousresolutionsthefollowingequationscanbeused: 12Bit+Sign N =[R +2.3]×f ×0.824 C S C 8Bit+Sign N =[R +2.3]×f ×0.57 C S C where • f istheconversionclock(CCLK)frequencyinMHz C • R istheexternalsourceresistanceinkΩ (3) S As an example, operating with a resolution of 12 Bits+sign, a 5 MHz clock frequency and maximum acquisition time of 34 conversion clock periods the ADC's analog inputs can handle a source impedance as high as 6 kΩ. The acquisition time may also be extended to compensate for the settling or response time of external circuitry connectedbetweentheMUXOUTandA/DINpins. AnacquisitionstartsatafallingedgeofSCLKandendsatarisingedgeofCCLK(seetimingdiagrams).IfSCLK and CCLK are asynchronous, one extra CCLK clock period may be inserted into the programmed acquisition time for synchronization. Therefore, with asynchronous SCLK and CCLKs the acquisition time will change from conversiontoconversion. 7.0 INPUT BYPASS CAPACITANCE External capacitors (0.01 µF–0.1 µF) can be connected between the analog input pins, CH0–CH7, and analog ground to filter any noise caused by inductive pickup associated with long input leads. These capacitors will not degradetheconversionaccuracy. 8.0 NOISE The leads to each of the analog multiplexer input pins should be kept as short as possible. This will minimize input noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce theeffectsofthenoisesources. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com 9.0 POWER SUPPLIES Noise spikes on the V + and V + supply lines can cause conversion errors; the comparator will respond to the A D noise. The ADC is especially sensitive to any power supply spikes that occur during the Auto Zero or linearity correction. The minimum power supply bypassing capacitors recommended are low inductance tantalum capacitors of 10 µF or greater paralleled with 0.1 µF monolithic ceramic capacitors. More or different bypassing maybenecessarydependingupontheoverallsystemrequirements.Separatebypasscapacitorsshouldbeused fortheV +andV +suppliesandplacedascloseaspossibletothesepins. A D 10.0 GROUNDING The ADC12030/2/4/8's performance can be maximized through proper grounding techniques. These include the useofseparateanaloganddigitalareasoftheboardwithanaloganddigitalcomponentsandtraceslocatedonly in their respective areas. Bypass capacitors of 0.01 µF and 0.1 µF surface mount capacitors and a 10 µF are recommended at each of the power supply pins for best performance. These capacitors should be located as closetothebypassedpinaspractical,especiallythesmallervaluecapacitors. 11.0 CLOCK SIGNAL LINE ISOLATION The ADC12030/2/4/8's performance is optimized by routing the analog input/output and reference signal conductors as far as possible from the conductors that carry the clock signals to the CCLK and SCLK pins. Maintaining a separation of at least 7 to 10 times the height of the clock trace above its reference plane is recommended. 12.0 THE CALIBRATION CYCLE A calibration cycle needs to be started after the power supplies, reference, and clock have been given enough time to stabilize after initial turn-on. During the calibration cycle, correction values are determined for the offset voltage of the sampled data comparator and any linearity and gain errors. These values are stored in internal RAM and used during an analog-to-digital conversion to bring the overall full-scale, offset, and linearity errors down to the specified limits. Full-scale error typically changes ±0.4 LSB over temperature and linearity error changes even less; therefore it should be necessary to go through the calibration cycle only once after power up if the Power Supply Voltage and the ambient temperature do not change significantly (see the curves in Typical PerformanceCharacteristics). 13.0 THE Auto Zero CYCLE To correct for any change in the zero (offset) error of the ADC, the Auto Zero cycle can be used. It may be necessary to do an Auto Zero cycle whenever the ambient temperature or the power supply voltage change significantly.(Seethecurves,Figure18andFigure20,inTypicalPerformanceCharacteristics.) 14.0 DYNAMIC PERFORMANCE Many applications require the converter to digitize AC signals, but the standard DC integral and differential nonlinearity specifications will not accurately predict the ADC's performance with AC input signals. The important specifications for AC applications reflect the converter's ability to digitize AC signals without significant spectral errors and without adding noise to the digitized signal. Dynamic characteristics such as signal-to-noise (S/N), signal-to-noise + distortion ratio (S/(N + D)), effective bits, full power bandwidth, aperture time and aperture jitter arequantitativemeasuresoftheADC'scapability. An ADC's AC performance can be measured using Fast Fourier Transform (FFT) methods. A sinusoidal waveformisappliedtotheADC'sinput,andthetransformisthenperformedonthedigitizedwaveform.S/(N+D) and S/N are calculated from the resulting FFT data, and a spectral plot may also be obtained. Typical values for S/N are shown in Converter Electrical Characteristics, and spectral plots of S/(N + D) are included in Typical PerformanceCharacteristics. The ADC's noise and distortion levels will change with the frequency of the input signal, with more distortion and noiseoccurringathighersignalfrequencies.ThiscanbeseenintheS/(N+D)versusfrequencycurves. Effective number of bits can also be useful in describing the ADC's noise and distortion performance. An ideal ADC will have some amount of quantization noise, determined by its resolution, and no distortion, which will yield anoptimumS/(N+D)ratiogivenbythefollowingequation: S/(N+D)=(6.02×n+1.76)dB 40 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 where • "n"istheADC'sresolutioninbits (4) TheeffectivebitsofanactualADCisfoundtobe: n(effective)=ENOB=(S/(N+D)-1.76/6.02 (5) As an example, this device with a differential signed 5V, 1 kHz sine wave input signal will typically have a S/(N + D)of77dB,whichisequivalentto12.5effectivebits. 15.0 AN RS232 SERIAL INTERFACE Shown on the following page is a schematic for an RS232 interface to any IBM and compatible PCs. The DTR, RTS, and CTS RS232 signal lines are buffered via level translators and connected to the ADC12038's DI, SCLK, andDOpins,respectively.TheDflipflopdrivestheCScontrolline. CH0 VD+ +5V 1/6 74HC04 1/4 DS14C89 CH1 DOR RTS CH2 CCLK 5 MHz 1/4 DS14C89 CH3 SCLK DTR CH4 DI CH5 DO CTS 1/4 DS14C88 CH6 CS ABC RS-232 CH7 CONV Interface COM EOC D Q MUXOUT1 PD CLK A/DIN1 AGND MUXOUT2 VREF+ +4.096V 7474 A/DIN2 VREF- DGND VA+ +5V Note:V +,V +,andV +ontheADC12038eachhave0.01µFand0.1µFchipcaps,and10µFtantalumcaps.All A D REF logicdevicesarebypassedwith0.1µFcaps. Figure72. SchematicforanRS232InterfacetoanyIBMandCompatiblePCs TheassignmentoftheRS-232portisshownbelow B7 B6 B5 B4 B3 B2 B1 B0 InputAddress 3FE X X X CTS X X X X COM1 OutputAddress 3FC X X X 0 X X RTS DTR A sample program, written in Microsoft QuickBasic, is shown on the next page. The program prompts for data mode select instruction to be sent to the ADC. This can be found from the Mode Programming table shown earlier. The data should be entered in “1”s and “0”s as shown in the table with DI0 first. Next, the program prompts for the number of SCLK cycles required for the programmed mode select instruction. For instance, to send all “0”s to the ADC, selects CH0 as the +input, CH1 as the −input, 12-bit conversion, and 13-bit MSB first data output format (if the sign bit was not turned off by a previous instruction). This would require 13 SCLK periodssincetheoutputdataformatis13bits. Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com TheADCpowersupwithNoAutoCal,NoAutoZero,10CCLKAcquisitionTime,12-bitconversion,dataoutwith sign, power up, 12- or 13-bit MSB first, and user mode. Auto Cal, Auto Zero, Power Up and Power Down instructionsdonotchangethesedefaultsettings.Thefollowingpowerupsequenceshouldbefollowed: 1. Runtheprogram 2. PriortorespondingtothepromptapplythepowertotheADC12038 3. Respondtotheprogramprompts It is recommended that the first instruction issued to the ADC12038 be Auto Cal (see Section 1.1 Interface Concepts). Code Listing:'variables DOL=Data Out word length, DI=Data string for ADC DI input, ' DO=ADC result string 'SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) 'set RTS HIGH OUT &H3FC, (&HFE AND INP(&H3FC)) 'set DTR LOW OUT &H3FC, (&HFD AND INP(&H3FC)) 'set RTS LOW OUT &H3FC, (&HEF AND INP(&H3FC)) 'set B4 low 10 LINE INPUT “DI data for ADC12038 (see Mode Table on data sheet)”; DI$ INPUT “ADC12038 output word length (8,9,12,13,16 or 17)”; DOL 20 'SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) 'set RTS HIGH OUT &H3FC, (&HFE AND INP(&H3FC)) 'set DTR LOW OUT &H3FC, (&HFD AND INP(&H3FC)) 'set RTS LOW 'SET CS# LOW OUT &H3FC, (&H2 OR INP (&H3FC)) 'set RTS HIGH OUT &H3FC, (&H1 OR INP(&H3FC)) 'set DTR HIGH OUT &H3FC, (&HFD AND INP(&H3FC)) 'set RTS LOW DO$= “ ” 'reset DO variable OUT &H3FC, (&H1 OR INP(&H3FC)) 'SET DTR HIGH OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low FOR N=1 TO 8 Temp$=MID$(DI$,N,1) IF Temp$=“0” THEN OUT &H3FC,(&H1 OR INP(&H3FC)) ELSE OUT &H3FC, (&HFE AND INP(&H3FC)) END IF 'out DI OUT &H3FC, (&H2 OR INP(&H3FC)) 'SCLK high IF (INP(&H3FE) AND 16)=16 THEN DO$=DO$+“0” ELSE DO$=DO$+“1” END IF 'input DO OUT &H3FC, (&H1 OR INP(&H3FC)) 'SET DTR HIGH OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low NEXT N IF DOL>8 THEN FOR N=9 TO DOL OUT &H3FC, (&H1 OR INP(&H3FC)) 'SET DTR HIGH OUT &H3FC, (&HFD AND INP(&H3FC)) 'SCLK low OUT &H3FC, (&H2 OR INP(&H3FC)) 'SCLK high IF (INP(&H3FE) AND &H10)=&H10 THEN DO$=DO$+“0” ELSE DO$=DO$+“1” END IF NEXT N END IF OUT &H3FC, (&HFA AND INP(&H3FC)) 'SCLK low and DI high FOR N=1 TO 500 NEXT N PRINT DO$ INPUT “Enter “C” to convert else “RETURN” to alter DI data”; s$ 42 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 www.ti.com SNAS080K–JULY1999–REVISEDMARCH2013 IF s$=“C” OR s$=“c” THEN GOTO 20 ELSE GOTO 10 END IF END Copyright©1999–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

ADC12030, ADC12032, ADC12034 ADC12038, ADC12H030, ADC12H032 ADC12H034, ADC12H038 SNAS080K–JULY1999–REVISEDMARCH2013 www.ti.com REVISION HISTORY ChangesfromRevisionJ(March2013)toRevisionK Page • ChangedlayoutofNationalDataSheettoTIformat.......................................................................................................... 42 44 SubmitDocumentationFeedback Copyright©1999–2013,TexasInstrumentsIncorporated ProductFolderLinks:ADC12030ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032ADC12H034 ADC12H038

PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ADC12030CIWM/NOPB OBSOLETE SOIC DW 16 TBD Call TI Call TI -40 to 85 ADC12030 CIWM ADC12030CIWMX/NOPB OBSOLETE SOIC DW 16 TBD Call TI Call TI -40 to 85 ADC12030 CIWM ADC12038CIWM NRND SOIC DW 28 26 TBD Call TI Call TI -40 to 85 ADC12038 CIWM ADC12038CIWM/NOPB ACTIVE SOIC DW 28 26 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 ADC12038 & no Sb/Br) CIWM ADC12038CIWMX/NOPB ACTIVE SOIC DW 28 1000 Green (RoHS CU SN Level-3-260C-168 HR -40 to 85 ADC12038 & no Sb/Br) CIWM ADC12H034CIMSA/NOPB OBSOLETE SSOP DB 24 TBD Call TI Call TI ADC12H034 CIMSA ADC12H034CIMSAX/NOPB OBSOLETE SSOP DB 24 TBD Call TI Call TI ADC12H034 CIMSA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2017 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ADC12030CIWMX/NOPB SOIC DW 16 1000 330.0 16.4 10.9 10.7 3.2 12.0 16.0 Q1 ADC12038CIWMX/NOPB SOIC DW 28 1000 330.0 24.4 10.8 18.4 3.2 12.0 24.0 Q1 ADC12H034CIMSAX/NOP SSOP DB 24 2000 330.0 16.4 8.6 8.9 2.5 12.0 16.0 Q1 B PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ADC12030CIWMX/NOPB SOIC DW 16 1000 367.0 367.0 38.0 ADC12038CIWMX/NOPB SOIC DW 28 1000 367.0 367.0 45.0 ADC12H034CIMSAX/NOP SSOP DB 24 2000 367.0 367.0 38.0 B PackMaterials-Page2

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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BuyersandotherswhoaredevelopingsystemsthatincorporateTIproducts(collectively,“Designers”)understandandagreethatDesigners remainresponsibleforusingtheirindependentanalysis,evaluationandjudgmentindesigningtheirapplicationsandthatDesignershave fullandexclusiveresponsibilitytoassurethesafetyofDesigners'applicationsandcomplianceoftheirapplications(andofallTIproducts usedinorforDesigners’applications)withallapplicableregulations,lawsandotherapplicablerequirements.Designerrepresentsthat,with respecttotheirapplications,Designerhasallthenecessaryexpertisetocreateandimplementsafeguardsthat(1)anticipatedangerous consequencesoffailures,(2)monitorfailuresandtheirconsequences,and(3)lessenthelikelihoodoffailuresthatmightcauseharmand takeappropriateactions.DesigneragreesthatpriortousingordistributinganyapplicationsthatincludeTIproducts,Designerwill thoroughlytestsuchapplicationsandthefunctionalityofsuchTIproductsasusedinsuchapplications. TI’sprovisionoftechnical,applicationorotherdesignadvice,qualitycharacterization,reliabilitydataorotherservicesorinformation, including,butnotlimitedto,referencedesignsandmaterialsrelatingtoevaluationmodules,(collectively,“TIResources”)areintendedto assistdesignerswhoaredevelopingapplicationsthatincorporateTIproducts;bydownloading,accessingorusingTIResourcesinany way,Designer(individuallyor,ifDesignerisactingonbehalfofacompany,Designer’scompany)agreestouseanyparticularTIResource solelyforthispurposeandsubjecttothetermsofthisNotice. TI’sprovisionofTIResourcesdoesnotexpandorotherwisealterTI’sapplicablepublishedwarrantiesorwarrantydisclaimersforTI products,andnoadditionalobligationsorliabilitiesarisefromTIprovidingsuchTIResources.TIreservestherighttomakecorrections, enhancements,improvementsandotherchangestoitsTIResources.TIhasnotconductedanytestingotherthanthatspecifically describedinthepublisheddocumentationforaparticularTIResource. Designerisauthorizedtouse,copyandmodifyanyindividualTIResourceonlyinconnectionwiththedevelopmentofapplicationsthat includetheTIproduct(s)identifiedinsuchTIResource.NOOTHERLICENSE,EXPRESSORIMPLIED,BYESTOPPELOROTHERWISE TOANYOTHERTIINTELLECTUALPROPERTYRIGHT,ANDNOLICENSETOANYTECHNOLOGYORINTELLECTUALPROPERTY RIGHTOFTIORANYTHIRDPARTYISGRANTEDHEREIN,includingbutnotlimitedtoanypatentright,copyright,maskworkright,or otherintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservicesareused.Information regardingorreferencingthird-partyproductsorservicesdoesnotconstitutealicensetousesuchproductsorservices,orawarrantyor endorsementthereof.UseofTIResourcesmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthe thirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI. TIRESOURCESAREPROVIDED“ASIS”ANDWITHALLFAULTS.TIDISCLAIMSALLOTHERWARRANTIESOR REPRESENTATIONS,EXPRESSORIMPLIED,REGARDINGRESOURCESORUSETHEREOF,INCLUDINGBUTNOTLIMITEDTO ACCURACYORCOMPLETENESS,TITLE,ANYEPIDEMICFAILUREWARRANTYANDANYIMPLIEDWARRANTIESOF MERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENTOFANYTHIRDPARTYINTELLECTUAL PROPERTYRIGHTS.TISHALLNOTBELIABLEFORANDSHALLNOTDEFENDORINDEMNIFYDESIGNERAGAINSTANYCLAIM, INCLUDINGBUTNOTLIMITEDTOANYINFRINGEMENTCLAIMTHATRELATESTOORISBASEDONANYCOMBINATIONOF PRODUCTSEVENIFDESCRIBEDINTIRESOURCESOROTHERWISE.INNOEVENTSHALLTIBELIABLEFORANYACTUAL, DIRECT,SPECIAL,COLLATERAL,INDIRECT,PUNITIVE,INCIDENTAL,CONSEQUENTIALOREXEMPLARYDAMAGESIN CONNECTIONWITHORARISINGOUTOFTIRESOURCESORUSETHEREOF,ANDREGARDLESSOFWHETHERTIHASBEEN ADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES. UnlessTIhasexplicitlydesignatedanindividualproductasmeetingtherequirementsofaparticularindustrystandard(e.g.,ISO/TS16949 andISO26262),TIisnotresponsibleforanyfailuretomeetsuchindustrystandardrequirements. WhereTIspecificallypromotesproductsasfacilitatingfunctionalsafetyorascompliantwithindustryfunctionalsafetystandards,such productsareintendedtohelpenablecustomerstodesignandcreatetheirownapplicationsthatmeetapplicablefunctionalsafetystandards andrequirements.Usingproductsinanapplicationdoesnotbyitselfestablishanysafetyfeaturesintheapplication.Designersmust ensurecompliancewithsafety-relatedrequirementsandstandardsapplicabletotheirapplications.DesignermaynotuseanyTIproductsin life-criticalmedicalequipmentunlessauthorizedofficersofthepartieshaveexecutedaspecialcontractspecificallygoverningsuchuse. Life-criticalmedicalequipmentismedicalequipmentwherefailureofsuchequipmentwouldcauseseriousbodilyinjuryordeath(e.g.,life support,pacemakers,defibrillators,heartpumps,neurostimulators,andimplantables).Suchequipmentincludes,withoutlimitation,all medicaldevicesidentifiedbytheU.S.FoodandDrugAdministrationasClassIIIdevicesandequivalentclassificationsoutsidetheU.S. TImayexpresslydesignatecertainproductsascompletingaparticularqualification(e.g.,Q100,MilitaryGrade,orEnhancedProduct). Designersagreethatithasthenecessaryexpertisetoselecttheproductwiththeappropriatequalificationdesignationfortheirapplications andthatproperproductselectionisatDesigners’ownrisk.Designersaresolelyresponsibleforcompliancewithalllegalandregulatory requirementsinconnectionwithsuchselection. DesignerwillfullyindemnifyTIanditsrepresentativesagainstanydamages,costs,losses,and/orliabilitiesarisingoutofDesigner’snon- compliancewiththetermsandprovisionsofthisNotice. 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