Single-Supply, Differential, 18-Bit ADC Driver Data Sheet ADA4941-1 FEATURES FUNCTIONAL BLOCK DIAGRAM Single-ended-to-differential converter Excellent linearity FB 1 8 IN Distortion −110 dBc at 100 kHz for VO, dm = 2 V p-p Low noise: 10.2 nV/√Hz, output-referred, G = 2 REF 2 7 DIS Extremely low power: 2.2 mA (3 V supply) High input impedance: 24 MΩ V+ 3 6 V– User-adjustable gain HFaigsth s septteleindg: 3ti1m MeH: 3z0, 0− 3n sd Bto b 0a.n00d5w%id ftohr ( Ga 2= V + 2st)e p OUT+ 4 5 OUT– 05704-001 Figure 1. Low offset: 0.8 mV maximum, output-referred, G = 2 Rail-to-rail output Disable feature Wide supply voltage range: 2.7 V to 12 V Available in space-saving, 3 mm × 3 mm LFCSP APPLICATIONS Single-supply data acquisition systems Instrumentation Process control Battery-power systems Medical instrumentation GENERAL DESCRIPTION bipolar (XFCB) process, which enables the amplifier to achieve The ADA4941-1 is a low power, low noise differential driver for 18-bit performance on low supply currents. analog-to-digital converters (ADCs) up to 18 bits in systems that are sensitive to power. The ADA4941-1 is configured in an The ADA4941-1 is available in a small 8-lead LFCSP as well as a easy-to-use, single-ended-to-differential configuration and standard 8-lead SOIC and is rated to work over the extended requires no external components for a gain of 2 configuration. industrial temperature range, −40°C to +125°C. A resistive feedback network can be added to achieve gains greater than 2. The ADA4941-1 provides essential benefits, such as low –60 –65 distortion and high SNR that are required for driving high –70 resolution ADCs. –75 –80 VO = 6V p-p With a wide input voltage range (0 V to 3.9 V on a single 5 V c) –85 supply), rail-to-rail output, high input impedance, and a user- N (dB ––9905 adjustable gain, the ADA4941-1 is designed to drive single-supply TIO–100 ADCs with differential inputs found in a variety of low power OR–105 ST–110 applications, including battery-operated devices and single- DI–115 VO = 2V p-p supply data acquisition systems. –120 HD3 HD2 –125 The ADA4941-1 is ideal for driving the 16-bit and 18-bit –130 PulSAR® ADCs, such as the AD7687, AD7690, and AD7691. –135 HD2 HD3 –140 The ADA4941-1 is manufactured on Analog Devices, Inc., 0.1 1 FREQUE1N0CY (kHz) 100 1000 05704-045 proprietary, second-generation, eXtra fast complementary Figure 2. Distortion vs. Frequency at Various Output Amplitudes Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADA4941-1 Data Sheet TABLE OF CONTENTS Features........................................................................................... 1 DC Error Calculations ............................................................ 16 Applications ................................................................................... 1 Output Voltage Noise .............................................................. 17 Functional Block Diagram ............................................................ 1 Frequency Response vs. Closed-Loop Gain .......................... 19 General Description ...................................................................... 1 Applications Information............................................................ 20 Revision History ............................................................................ 2 Overview .................................................................................. 20 Specifications ................................................................................. 3 Using the REF Pin.................................................................... 20 Absolute Maximum Ratings ......................................................... 6 Internal Feedback Network Power Dissipation ..................... 20 Thermal Resistance ................................................................... 6 Disable Feature......................................................................... 20 Maximum Power Dissipation ................................................... 6 Adding a 3-Pole, Sallen-Key Filter.......................................... 21 ESD Caution............................................................................... 6 Driving the AD7687 ADC ...................................................... 22 Pin Configuration and Function Descriptions............................ 7 Gain of −2 Configuration........................................................ 22 Typical Performance Characteristics............................................ 8 Outline Dimensions .................................................................... 23 Theory of Operation.................................................................... 15 Ordering Guide........................................................................ 23 Basic Operation ....................................................................... 15 REVISION HISTORY 5/16—Rev. C to Rev. D 8/10—Rev. A to Rev. B Change CP-8-2 to CP-8-13 ........................................ Throughout Added Caption to Figure 1.............................................................1 Changes to Figure 4 ........................................................................7 Added Exposed Pad Notation to Figure 4 and Table 6 ................7 Added Figure 5; Renumbered Sequentially ..................................7 Added Exposed Pad Notation to Outline Dimensions ..............23 Updated Outline Dimensions ......................................................23 Changes to Ordering Guide .........................................................23 Changes to Ordering Guide .........................................................23 3/09—Rev. 0 to Rev. A 8/11—Rev. B to Rev. C Change to Gain Error Drift Parameter, Table 1............................3 Change to Gain Error Drift Unit, Table 1 .....................................3 Change to Gain Error Drift Parameter, Table 2............................4 Change to Gain Error Drift Unit, Table 2 .....................................4 Change to Gain Error Drift Parameter, Table 3............................5 Change to Gain Error Drift Unit, Table 3 .....................................5 Updated Outline Dimensions ......................................................23 4/06—Revision 0: Initial Version Rev. D | Page 2 of 23

Data Sheet ADA4941-1 SPECIFICATIONS T = 25°C, V = 3 V, OUT+c onnected to FB (G = 2), R = 1 kΩ, REF = 1.5 V, unless otherwise noted. A S L, dm Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.1 V p-p 21 30 MHz O V = 2.0 V p-p 4.6 6.5 MHz O Overdrive Recovery Time +Recover/−recovery 320/650 ns Slew Rate V = 2 V step 22 V/µs O Settling Time 0.005% V = 2 V p-p step 300 ns O NOISE/DISTORTION PERFORMANCE Harmonic Distortion f = 40 kHz, V = 2 V p-p, HD2/HD3 −116/−112 dBc C O f = 100 kHz, V = 2 V p-p, HD2/HD3 −101/−98 dBc C O f = 1 MHz, V = 2 V p-p, HD2/HD3 −75/−71 dBc C O RTO Voltage Noise f = 100 kHz 10.2 nV/√Hz Input Current Noise f = 100 kHz 1.6 pA/√Hz DC PERFORMANCE Differential Output Offset Voltage 0.2 0.8 mV Differential Input Offset Voltage Drift 1.0 µV/°C Single-Ended Input Offset Voltage Amp A1 or Amp A2 0.1 0.4 mV Single-Ended Input Offset Voltage Drift 0.3 µV/°C Input Bias Current IN and REF 3 4.5 µA Input Offset Current IN and REF 0.1 µA Gain (+OUT − −OUT)/(IN − REF) 1.98 2.00 2.01 V/V Gain Error −1 +1 % Gain Error Drift 1 5 ppm/°C INPUT CHARACTERISTICS Input Resistance IN and REF 24 MΩ Input Capacitance IN and REF 1.4 pF Input Common-Mode Voltage Range 0.2 1.9 V Common-Mode Rejection Ratio (CMRR) CMRR = V /V , VREF = VIN, V = 0.2 V to 1.9 V, G = 4 81 105 dB OS, dm CM CM OUTPUT CHARACTERISTICS Output Voltage Swing Each single-ended output, G = 4 ±2.90 ±2.95 V Output Current 25 mA Capacitive Load Drive 20% overshoot, V , dm = 200 mV p-p 20 pF O POWER SUPPLY Operating Range 2.7 12 V Quiescent Current 2.2 2.4 mA Quiescent Current—Disable 10 16 µA Power Supply Rejection Ratio (PSRR) +PSRR PSRR = V /ΔV, G = 4 86 100 dB OS, dm S −PSRR 86 110 dB DISABLE DIS Input Voltage Disabled, DIS = high ≥1.5 V Enabled, DIS = low ≤1.0 V DIS Input Current Disabled, DIS = high 5.5 8 µA Enabled, DIS = low 4 6 µA Turn-On Time 0.7 µs Turn-Off Time 30 µs Rev. D | Page 3 of 23

ADA4941-1 Data Sheet T = 25°C, V = 5 V, OUT+c onnected to FB (G = 2), R = 1 kΩ, REF = 2.5 V, unless otherwise noted. A S L, dm Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.1 V p-p 22 31 MHz O V = 2.0 V p-p 4.9 7 MHz O Overdrive Recovery Time +Recover/−recovery 200/600 ns Slew Rate V = 2 V step 24.5 V/µs O Settling Time 0.005% V = 6 V p-p step 610 ns O NOISE/DISTORTION PERFORMANCE Harmonic Distortion f = 40 kHz, V = 2 V p-p, HD2/HD3 −118/−119 dBc C O f = 100 kHz, V = 2 V p-p, HD2/HD3 −110/−112 dBc C O f = 1 MHz, V = 2 V p-p, HD2/HD3 −83/−73 dBc C O RTO Voltage Noise f = 100 kHz 10.2 nV/√Hz Input Current Noise f = 100 kHz 1.6 pA/√Hz DC PERFORMANCE Differential Output Offset Voltage 0.2 0.8 mV Differential Input Offset Voltage Drift 1.0 µV/°C Single-Ended Input Offset Voltage Amp A1 or Amp A2 0.1 0.4 mV Single-Ended Input Offset Voltage Drift 0.3 µV/°C Input Bias Current IN and REF 3 4.5 µA Input Offset Current IN and REF 0.1 µA Gain (+OUT − −OUT)/(IN − REF) 1.98 2 2.01 V/V Gain Error −1 +1 % Gain Error Drift 1 5 ppm/°C INPUT CHARACTERISTICS Input Resistance IN and REF 24 MΩ Input Capacitance IN and REF 1.4 pF Input Common-Mode Voltage Range 0.2 3.9 V Common-Mode Rejection Ratio (CMRR) CMRR = V /V , VREF = VIN, V = 0.2 V to 3.9 V, G = 4 84 106 dB OS, dm CM CM OUTPUT CHARACTERISTICS Output Voltage Swing Each single-ended output, G = 4 ±4.85 ±4.93 V Output Current 25 mA Capacitive Load Drive 20% overshoot, V , dm = 200 mV p-p 20 pF O POWER SUPPLY Operating Range 2.7 12 V Quiescent Current 2.3 2.6 mA Quiescent Current—Disable 12 20 µA Power Supply Rejection Ratio (PSRR) +PSRR PSRR = V /ΔV, G = 4 87 100 dB OS, dm S −PSRR 87 110 dB DISABLE DIS Input Voltage Disabled, DIS = high ≥1.5 V Enabled, DIS = low ≤1.0 V DIS Input Current Disabled, DIS = high 5.5 8 µA Enabled, DIS = low 4 6 µA Turn-On Time 0.7 µs Turn-Off Time 30 µs Rev. D | Page 4 of 23

Data Sheet ADA4941-1 T = 25°C, V = ±5 V, OUT+ connected to FB (G = 2), R = 1 kΩ, REF = 0 V, unless otherwise noted. A S L, dm Table 3. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.1 V p-p 23 32 MHz O V = 2.0 V p-p 5.2 7.5 MHz O Overdrive Recovery Time +Recover/−recovery 200/650 ns Slew Rate V = 2 V step 26 V/µs O Settling Time 0.005% V = 12 V p-p step 980 ns O NOISE/DISTORTION PERFORMANCE Harmonic Distortion f = 40 kHz, V = 2 V p-p, HD2/HD3 −118/−119 dBc C O f = 100 kHz, V = 2 V p-p, HD2/HD3 −109/−112 dBc C O f = 1 MHz, V = 2 V p-p, HD2/HD3 −84/−75 dBc C O RTO Voltage Noise f = 100 kHz 10.2 nV/√Hz Input Current Noise f = 100 kHz 1.6 pA/√Hz DC PERFORMANCE Differential Output Offset Voltage 0.2 0.8 mV Differential Input Offset Voltage Drift 1.0 µV/°C Single-Ended Input Offset Voltage Amp A1 or Amp A2 0.1 0.4 mV Single-Ended Input Offset Voltage Drift 0.3 µV/°C Input Bias Current IN and REF 3 4.5 µA Input Offset Current IN and REF 0.1 µA Gain (+OUT − −OUT)/(IN − REF) 1.98 2 2.01 V/V Gain Error −1 +1 % Gain Error Drift 1 5 ppm/°C INPUT CHARACTERISTICS Input Resistance IN and REF 24 MΩ Input Capacitance IN and REF 1.4 pF Input Common-Mode Voltage Range −4.8 +3.9 V Common-Mode Rejection Ratio (CMRR) CMRR = VOS, dm/VCM, VREF = VIN, 85 105 dB V = −4.8 V to +3.9 V, G = 4 CM OUTPUT CHARACTERISTICS Output Voltage Swing Each single-ended output, G = 4 V − 0.25 V ± 0.14 V S S Output Current 25 mA Capacitive Load Drive 20% overshoot, V , dm = 200 mV p-p 20 pF O POWER SUPPLY Operating Range 2.7 12 V Quiescent Current 2.5 2.7 mA Quiescent Current—Disable 15 26 µA Power Supply Rejection Ratio (PSRR) +PSRR PSRR = V /ΔV, G = 4 87 100 dB OS, dm S −PSRR 87 110 dB DISABLE DIS Input Voltage Disabled, DIS = high ≥ −3 V Enabled, DIS = low ≤ −4 V DIS Input Current Disabled, DIS = high 7 10 µA Enabled, DIS = low 4 6 µA Turn-On Time 0.7 µs Turn-Off Time 30 µs Rev. D | Page 5 of 23

ADA4941-1 Data Sheet ABSOLUTE MAXIMUM RATINGS quiescent current (I). The power dissipated due to the load S Table 4. drive depends upon the particular application. For each output, Parameter Rating the power due to load drive is calculated by multiplying the load Supply Voltage 12 V current by the associated voltage drop across the device. The Power Dissipation See Figure 3 power dissipated due to all of the loads is equal to the sum of Storage Temperature Range −65°C to +125°C the power dissipation due to each individual load. RMS voltages Operating Temperature Range −40°C to +85°C and currents must be used in these calculations. Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads Stresses at or above those listed under Absolute Maximum from metal traces, through holes, ground, and power planes Ratings may cause permanent damage to the product. This is a reduces the θ . The exposed paddle on the underside of the stress rating only; functional operation of the product at these JA package must be soldered to a pad on the PCB surface that is or any other conditions above those indicated in the operational thermally connected to a copper plane to achieve the specified θ . section of this specification is not implied. Operation beyond JA the maximum operating conditions for extended periods may Figure 3 shows the maximum safe power dissipation in the affect product reliability. packages vs. the ambient temperature for the 8-lead SOIC (126°C/W) and for the 8-lead LFCSP (83°C/W) on a JEDEC THERMAL RESISTANCE standard 4-layer board. The LFCSP must have its underside θ is specified for the worst-case conditions, that is, θ is JA JA paddle soldered to a pad that is thermally connected to a PCB specified for a device soldered in the circuit board with its plane. θ values are approximations. JA exposed paddle soldered to a pad (if applicable) on the PCB 2.5 surface that is thermally connected to a copper plane, with zero airflow. W) N ( 2.0 O Table 5. Thermal Resistance TI A Package Type θJA θJC Unit SSIP 1.5 LFCSP 8-Lead SOIC on 4-Layer Board 126 28 °C/W DI R 8-Lead LFCSP with EP on 4-Layer Board 83 19 °C/W WE O 1.0 P MAXIMUM POWER DISSIPATION M SOIC U M The maximum safe power dissipation in the ADA4941-1 AXI 0.5 M package is limited by the associated rise in junction temperature (T) on the die. At approximately 150°C, which is the glass J 0 tteramnpsiotiroanri ltye mexpceeeradtiunrge ,t hthise t pelmasptiecr cahtuarneg leims iitts c parno cphearntigees. t Ehvee n –40 –20 0AMBIE20NT TEM40PERAT6U0RE (°C8)0 100 120 05704-002 Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4941-1. Exceeding a ESD CAUTION junction temperature of 150°C for an extended period can result in changes in the silicon devices potentially causing failure. The power dissipated in the package (P ) is the sum of the D quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V) times the S Rev. D | Page 6 of 23

Data Sheet ADA4941-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADA4941-1 FB 1 8 IN REF 2 7 DIS TOP VIEW V+ 3 (Not to Scale) 6 V– OUT+ 4 5 OUT– NOTES 1 . TITTHH IEAS T ET XIYSPP TOICHSAEELRDLM PYAA SLDOL YILS DC NEOORNTED DEU LTCEOTC IGVTERR.OICUANLDL YO CRO AN PNOEWCTEERD P TLOA NTEH EO DNE TVHICE EP.CB 05704-102 Figure 4. 8-Lead LFCSP Pin Configuration ADA4941-1 FB 1 8 IN REF 2 7 DIS TOP VIEW OUVT++ 34 (Not to Scale) 65 VO–UT– 05704-101 Figure 5. 8-Lead SOIC Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 FB Feedback Input. 2 REF Reference Input. 3 V+ Positive Power Supply. 4 OUT+ Noninverting Output. 5 OUT− Inverting Output. 6 V− Negative Power Supply. 7 DIS Disable. 8 IN Input. EPAD (LFCSP Only) Exposed Paddle. The exposed pad is not electrically connected to the device. It is typically soldered to ground or a power plane on the PCB that is thermally conductive. Rev. D | Page 7 of 23

ADA4941-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, V = 5 V, R = 1 kΩ, REF = 2.5 V, DIS = low, OUT+ directly connected to FB (G = 2), T = 25°C. S L, dm A 2 2 1 VO, dm = 0.1V p-p 1 B) 0 B) 0 AIN (d ––12 AIN (d ––12 VVSO ,= d m+3 =V 2V p-p G –3 G –3 P –4 P –4 O O O –5 O –5 L L D- –6 D- –6 LOSE ––78 LOSE ––78 VVSO ,= dm±5 =V 12V p-p LIZED C ––1–1091 LIZED C ––1–1091 VO, dmV =S 6=V + p5V-p MA –12 MA –12 R –13 VS = +5V R –13 O O N –14 N –14 –15 VS = +3V VS =±5V –15 –16 –16 1 10FREQUENCY (MHz1)00 1000 05704-004 0.1 1FREQUENCY (MHz)10 100 05704-007 Figure 6. Small Signal Frequency Response for Various Power Supplies Figure 9. Large Signal Frequency Response for Various Power Supplies 2 2 1 VO, dm = 0.1V p-p 1 VO, dm = 6V p-p B) 0 B) 0 AIN (d ––12 AIN (d ––12 G –3 G –3 P –4 P –4 O O O –5 O –5 L L D- –6 D- –6 SE –7 SE –7 LO –8 LO –8 D C –9 D C –9 E –10 E –10 LIZ –11 +85°C LIZ –11 +85°C MA –12 MA –12 OR –13 +25°C OR –13 –40°C +25°C N –14 –40°C N –14 –15 –15 –16 –16 1 10FREQUENCY (MHz1)00 1000 05704-005 0.1 1FREQUENCY (MHz)10 100 05704-008 Figure 7. Small Signal Frequency Response at Various Temperatures Figure 10. Large Signal Frequency Response at Various Temperatures 2 2 1 VO, dm = 0.1V p-p 1 VO, dm = 6V p-p B) 0 B) 0 OP GAIN (d ––––1234 OP GAIN (d ––––1234 RL, dRmL ,= d m1k =Ω 5kΩ RL, dm = 500Ω O O –5 L –5 L D CLOSED- ––––6789 D CLOSED- ––––6789 E E –10 LIZ –10 LIZ –11 RMA ––1121 RL, dm = 1kΩ RMA ––1123 O O N ––1134 RL, dm = 500Ω RL, dm = 5kΩ N ––1145 –15 –16 1 10FREQUENCY (MHz1)00 1000 05704-006 0.1 FREQUEN1CY (MHz) 10 05704-009 Figure 8. Small Signal Frequency Response for Various Resistive Loads Figure 11. Large Signal Frequency Response for Various Resistive Loads Rev. D | Page 8 of 23

Data Sheet ADA4941-1 2 2 1 VO, dm = 0.1V p-p 1 G = +4 VO, dm = 2V p-p B) 0 B) 0 AIN (d ––12 AIN (d ––12 G = –2 G = +2 G –3 G –3 OP –4 OP –4 G = +10 O –5 O –5 D-L –6 D-L –6 SE –7 SE –7 LO –8 LO –8 D C –9 G = +2 D C –9 E –10 E –10 LIZ –11 LIZ –11 MA –12 G = +10 MA –12 OR –13 G = +4 G = –2 OR –13 N –14 N –14 –15 –15 –16 –16 1 FREQUE1N0CY (MHz) 100 05704-010 1 10FREQUENCY (MHz1)00 1000 05704-013 Figure 12. Small Signal Frequency Response for Various Gains Figure 15. Large Signal Frequency Response for Various Gains 2 2 1 VO, dm = 0.1V p-p 1 B) 0 0 AIN (d ––12 ––12 G –3 B) –3 LOOP ––45 AIN (d ––45 VO, dm = 2V p-p VO, dm = 0.1V p-p SED- ––67 ED G ––67 D CLO ––89 CL = 20pF MALIZ ––89 VO, dm = 6V p-p E –10 R –10 Z O LI –11 N –11 MA –12 –12 R –13 CL = 0pF –13 O N –14 –14 –15 –15 –16 –16 1 10FREQUENCY (MHz1)00 1000 05704-011 0.1 1 FREQUE1N0CY (MHz) 100 1000 05704-014 Figure 13. Small Signal Frequency Response for Various Capacitive Loads Figure 16. Frequency Response for Various Output Amplitudes 2 –70 1 VREF = 0.05V p-p VO, dm= 2V p-p AIN (dB) ––120 –80 VREF = MIDSUPPLY OOP G –––345 VS =±5V dBc) –90 LOSED-L –––678 ORTION (––110100 HD3 D C –9 ST E –10 DI LIZ –11 –120 MA –12 VS = +3V RL = 2kΩ R –13 NO –14 VS = +5V –130 HD2 RL = 1kΩ –15 HD2 RL =500Ω –16 –140 1 FREQUE1N0CY (MHz) 1000 05704-012 0.1 1 FREQUE1N0CY (kHz) 100 1000 05704-015 Figure 14. REF Input Small Signal Frequency Response for Various Supplies Figure 17. Distortion vs. Frequency for Various Loads Rev. D | Page 9 of 23

ADA4941-1 Data Sheet –65 –65 f = 10kHz DIFFERENTIAL G = –2 f = 10kHz –75 –75 VS = +3V VS = +5V VS = ±5V –85 –85 c) c) dB dB –95 ON ( –95 ON ( VS = +3V VS = +5V VS = ±5V TI TI–105 R R O–105 O HD3 ST HD3 ST–115 HD3 HD3 DI DI –115 HD3 –125 HD2 –125 HD2 –135 HD2 HD3 HD2 –135 –145 0 2 4 O6UTPUT8 AMP1L0ITUD1E2 (V p1-p4) 16 18 20 05704-016 0 2 4 O6UTPUT8 AMP1L0ITUD1E2 (V p1-p4) 16 18 20 05704-019 Figure 18. Distortion vs. Output Amplitude for Various Supplies (G = +2) Figure 21. Distortion vs. Output Amplitude for Various Supplies (G = −2) –60 –70 –65 VO, dm= 2V p-p VO, dm= 2V p-p VREF = MIDSUPPLY VREF = MIDSUPPLY –70 –80 –75 –80 –90 c) –85 c) dB –90 dB N ( –95 N (–100 O O TI–100 TI OR–105 OR–110 HD2 ST–110 HD2 ST DI–115 DI HD3 –120 HD2 –120 –125 HD2 VS = +3V HD3 G = –2 –130 HD3 VS = +5V –130 G = +2 –135 VS =±5V HD3 HD3 G =+4 –140 –140 0.1 1 FREQUE1N0CY (kHz) 100 1000 05704-017 0.1 1 FREQUE1N0CY (kHz) 100 1000 05704-020 Figure 19. Distortion vs. Frequency for Various Supplies Figure 22. Distortion vs. Frequency for Various Gains –60 0.12 –65 CL =0pF VOUT=200mV p-p –70 0.08 –75 –80 VO = 6V p-p N (dBc) –––899505 TAGE (V) 0.04 CL = 20pF O L DISTORTI––––111100110505 VO = 2V p-p OUTPUT VO–0.040 –120 HD3 HD2 –125 –0.08 –130 ––1134500.1 HD2 1 HDF3REQUE1N0CY (kHz) 100 1000 05704-045 –0.12 50ns/DIV 05704-022 Figure 20. Distortion vs. Frequency at Various Output Amplitudes Figure 23. Small Signal Transient Response for Various Capacitive Loads Rev. D | Page 10 of 23

Data Sheet ADA4941-1 0.12 8 VS =+3V VOUT=200mV p-p VS = ±5V 6 VO, dm=12V p-p 0.08 V) VS =+5V OR VS = ±5V V) 4 VVSO ,= d m±2=.56VV p-p GE ( 0.04 GE ( 2 A A T T OL 0 OL 0 VS = ±1.5V V V VO, dm=2V p-p T T U U P P –2 UT–0.04 UT O O –4 –0.08 –6 –0.12 50ns/DIV 05704-018 –8 200ns/DIV 05704-021 Figure 24. Small Signal Transient Response for Various Supplies Figure 27. Large Signal Transient Response for Various Supplies 8 2.4 9 1.2 VO, dm 6 1.8 8 0.9 VS =±5V VS =+5V 4 VO, dm=12V p-p 1.2 % 7 VO, dm=6V p-p 0.6 % 5 5 0 0 0 0 E (V) 2 ERROR = 2 × VIN – VO, dm 0.6 V = 0. E (V) 6 ERROR = 2 × VIN – VO, dm 0.3 V = 0. LITUD 0 0 V) 1 DI LITUD 5 0 V) 1 DI P m P m AM –2 –0.6 R ( AM 4 VO, dm –0.3 R ( O O –4 2 × VIN –1.2 ERR 3 2 × VIN –0.6 ERR –6 –1.8 2 –0.9 –8 1µs/DIV –2.4 05704-023 1 1µs/DIV –1.2 05704-026 Figure 25. Settling Time (0.005%), VS = ±5 V Figure 28. Settling Time (0.005%), VS = +5 V 12 8 INPUT × 2 10 6 INPUT × 2 8 OUTPUT 6 4 V) V) GE ( 4 GE ( 2 OUTPUT A 2 A T T L L O 0 O 0 V V UT –2 UT P P –2 UT –4 UT O O –6 –4 –8 –6 ––1120 1µs/DIV 05704-024 –8 1µs/DIV 05704-027 Figure 26. Input Overdrive Recovery, VS = ±5 V Figure 29. Input Overdrive Recovery, VS = +5 V Rev. D | Page 11 of 23

ADA4941-1 Data Sheet 0 0.18 –10 ±5V SUPPLIES, POSITIVE RAIL 0.16 –20 E G AV) –30 LTL (0.14 PSRR (dB) –––––4567800000 +PSRR –PSRR TPUT SATURATION VOWITH RESPECT TO RAI000...110208 +±55VV SSUUPPPPLLIIEESS,, NNEEGGAATTIIVVEE RR+A5AVIILL SUPPLIES, POSITIVE RAIL U –90 O 0.06 +3V SUPPLIES, POSITIVE RAIL –100 +3V SUPPLIES, NEGATIVE RAIL –110 0.04 0.001 0.01 0.1FREQUEN1CY (MHz)10 100 1000 05704-028 –40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 05704-031 Figure 30. Power Supply Rejection Ratio vs. Frequency Figure 33. Output Saturation Voltage vs. Temperature 3.5 2.5 VPD = VS– ICC@ VS =±5V A) 3.0 2.0 ICC@ VS =+3V m URRENT ( 2.5 VS =±5V VS =+5V ENT (mA) 1.5 ICC@ VS =+5V C R UPPLY 2.0 LY CUR 1.0 WER S VS =+3V SUPP 0.5 PO 1.5 0 1.0 –0.5 –40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 05704-029 0.6 DIS0A.8BLE INP1U.0T VOLT1.A2GE WI1T.H4 RESP1E.C6T TO V1S.–8 (V) 2.0 05704-032 Figure 31. Power Supply Current vs. Temperature Figure 34. Power Supply Current vs. Disable Voltage 150 140 VOS1 MEAN = –8µV µV) 125 120 STD. DEV = 47µV SET ( VOS_A2 =10V 100 M E VAONS 2= 11µV F OF 100 VOS_A2 =5V STD. DEV = 20µV L OUTPUT 75 VOS_A2 =3V REQUENCY 8600 NO. OF UNITS = 611 A F NTI 50 RE VOS_A1 10V 40 E F DIF 25 VOS_A1 =3V VOS_A1 =5V 20 0 0 –40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 05704-030 –200–180–160–140–120–100–80O–60FF–40SET–20 V0OL20TA40GE 60(µV80) 100120140160180200 05704-033 Figure 32. Differential Output Offset Voltage vs. Temperature Figure 35. Differential Output Offset Distribution Rev. D | Page 12 of 23

Data Sheet ADA4941-1 Hz) 100 28 V/√ 26 OISE (n √Hz) 2242 N A/ 20 LTAGE OISE (p 1186 O N T V 10 NT 14 U E 12 P R UT UR 10 O C L T 8 A U NTI NP 6 RE I 4 E F 2 F DI 1 0 1 10 100 1FkREQU1E0NkCY (1H0z0)k 1M 10M 100M 05704-034 1 10 100FREQUE1NkCY (Hz)10k 100k 1M 05704-037 Figure 36. Differential Output Voltage Noise vs. Frequency Figure 39. Input Current Noise vs. Frequency 2.65 3.5 2.60 VS =±5V µA) VS =+5V µA) 3.0 T ( 2.55 T ( N N E E R R R VS =+3V R CU 2.50 CU 2.5 S S A A BI BI UT 2.45 UT VS = +3V VS = +5V VS =±5V P P N N 2.0 I I 2.40 2.35 1.5 –40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 05704-035 –0.500.51.I0N1P.5U2T.0 V2O.5L3T.0A3G.5E4 .W04IT.5H5 .R0E5.S5P6.E0C6T.5 7T.O0 7V.S5–8 .(0V8).59.09.510.005704-038 Figure 37. Input Bias Current vs. Temperature for Various Supplies Figure 40. Input Bias Current vs. Input Voltage 3.3 4.0 VREF = VIN A) A) 3.2 T (µ URRENT (µ 3.1 REFERENCE IBIAS =10V S CURREN 3.5 C A ENCE BIAS 32..09 REFERENCE IBIAS =5V CE INPUT BI 3.0 VS = +3V VS = +5V VS =±5V R N REFE 2.8 REFERENCE IBIAS =3V FERE 2.5 E R 2.7 2.0 –40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 05704-036 0 0R.5E1F.0E1R.E5N2.C0E2 .I5N3P.0U3T. 5V4O.0L4T.A55G.E0 5W.5I6T.H0 6R.5E7S.P0E7C.5T8 .T0O8. 5VS9–.0 (9V.)510.005704-039 Figure 38. REF Input Bias Current vs. Temperature Figure 41. REF Input Bias Current vs. REF Input Voltage Rev. D | Page 13 of 23

ADA4941-1 Data Sheet 10 14 G = 4 VS =±5V RF =1kΩ ENT (µA) 8 VS =±5V DRILS = =∞ HIGH NT (µA) 1120 R E CUR 6 URR 8 PLY VS =+5V UT C D SUP 4 VS =+3V E INP 6 BLE ABL 4 A S S 2 DI DI 2 0 0 –40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 05704-040 0 D1ISABL2E INPU3T VOL4TAGE5 WITH6 RESP7ECT TO8 VS– (9V) 10 05704-043 Figure 42. Disable Supply Current vs. Temperature for Various Supplies Figure 45. Disable Input Current vs. Disable Input Voltage VO, dm VO, dm V V DI DI V/ V/ m m 0 0 0 0 5 5 VPD VPD 40µs/DIV 05704-041 40µs/DIV 05704-044 Figure 43. Disable Assert Time Figure 46. Disable Deassert Time –40 100 VIN = 50mV p-p –50 10 –60 VON B) Ω) 1 TION (d –70 ANCE ( 0.1 A D L –80 E O P S M I I 0.01 VOP –90 0.001 –100 –110 0.0001 0.1 1 FREQUE1N0CY (MHz) 100 1000 05704-042 0.001 0.01 FR0E.1QUENCY (M1Hz) 10 100 05704-025 Figure 44. Disabled Input-to-Output Isolation vs. Frequency Figure 47. Single-Ended Output Impedance vs. Frequency Rev. D | Page 14 of 23

Data Sheet ADA4941-1 THEORY OF OPERATION V ,dm The ADA4941-1 is a low power, single-ended input, differential O output amplifier optimized for driving high resolution ADCs.  R  R  (3) VOPVON2(VIN)1 F 2VG F 2(VREF) Figure 48 illustrates how the ADA4941-1 is typically connected.      RG  RG  The amplifier is composed of an uncommitted amplifier, A1, driving a precision inverter, A2. The negative input of A1 is VOPVON V ,cm VREF (4) brought out to Pin 1 (FB), allowing for user-programmable O  2  gain. The inverting op amp, A2, provides accurate inversion of the output of A1, VOP, producing the output signal VON. When RF = 0 and RG is removed, Equation 3 simplifies to the following: RF OUT+ 4 V , dm = 2(VIN) − 2(VREF) (5) + O VOP 1kΩ – 1kΩ OUT+ 4 + 1 FB VOP RG 8 IN A1 1kΩ OUT– 5 3 +5V 1kΩ – RF||RG 2 REF500Ω A2 VO+–N 4.99kΩ 18 FINB A1VS+ 1kΩ OUT– 5 VS– REF A2 + VG VIN VREF 05704-052 825Ω 6–5V 2 500Ω VO–N The voltFaiggeu raep 4p8l. iBeads itco C othnen eRctEioFn sp (iPno wapepr Seuaprps laiess tNhoet Sohuotwpnu)t VIN 05704-053 Figure 49. Dual Supply, G = 2.4, Single-Ended-to-Differential Amplifier common-mode voltage. Note that the voltage applied to the REF pin does not affect the voltage at the OUT+ pin. Because of Figure 49 shows an example of a dual-supply connection. In this this, a differential offset can exist between the outputs, while the example, VG and VREF are set to 0 V, and the external R and F desired output common-mode voltage is present. For example, R network provides a noninverting gain of 1.2 in A1. This G when VOP = 3.5 V and VON = 1.5 V, the output common- example takes full advantage of the rail-to-rail output stage. mode voltage is equal to 2.5 V, just as it is when both outputs The gain equation is are at 2.5 V. In the first case, the differential voltage (or offset) is VOP − VON = 2.4(VIN) (6) 2.0 V, and in the latter case, the differential voltage is 0 V. When calculating output voltages, both differential and common-mode The in-series, 825 Ω resistor combined with Pin 8 compensates voltages must be considered at the same time to avoid undesired for the voltage error generated by the input offset current of A1. differential offsets. The linear output range of both A1 and A2 extends to within 200 mV of each supply rail, which allows a peak-to-peak BASIC OPERATION differential output voltage of 19.2 V on ±5 V supplies. In Figure 48, R and R form the external gain-setting network. G F OUT+ 4 VG and VREF are externally applied voltages. V , cm is defined O + as the output common-mode voltage and V , dm is defined as VOP O 3 1kΩ – the differential-mode output voltage. The following equations +5V can be derived from Figure 48: 1 FB VS+ 1kΩ A1 8 IN OUT– 5 VOPVIN1 RRGF VGRRGF  (1) VIN 6 VS–2 REF500Ω A2 VO+–N  R  R  +2.5V VONVIN1 RGF VGRGF 2(VREF) (2) 05704-054 Figure 50. Single +5V Supply, G=2 Single-Ended-to-Differential Amplifier Figure 50 shows a single 5 V supply connection with A1 used as a unity gain follower. The 2.5 V at the REF pin sets the output common-mode voltage to 2.5 V. The transfer function is then VOP − VON = 2(VIN) − 5 V (7) Rev. D | Page 15 of 23

ADA4941-1 Data Sheet In this case, the linear output voltage is limited by A1. On the When using data from the Specifications tables, it is often more low end, the output of A1 starts to saturate and show degraded expedient to use input offset current in place of the individual linearity when VOP approaches 200 mV. On the high end, the input bias currents when calculating errors. Input offset current input of A1 becomes saturated and exhibits degraded linearity is defined as the magnitude of the difference between the two when VIN moves beyond 4 V (within 1 V of VCC). This limits input bias currents. Using this definition, each input bias the linear differential output voltage in the circuit shown in current can be expressed in terms of the average of the two Figure 50 to about 7.6 V p-p. input bias currents, I , and the input offset current, I , as B OS 1.02kΩ OUT+ 4 IBP, N = IB ± IOS/2. DC errors are minimized when RS = RF || RG. In + this case, Equation 9 is reduced to VOP 3 1kΩ – +5V VOP_error1RF V _A1(I )R (R R ||R ) 665Ω 18 FINB A1VS+ 1kΩ OUT– 5  RG  OS OS F S F G 6 VS–2 REF500Ω A2 VO+–N Equation 10 expresses the dc voltage error present at the VON 402Ω output. VIN +2.5V 05704-055 V(IOBP_NA_2e)r(rRorS_ =R −E(FV +O 5P0_0e)r]r o+r )1 0+0 20[(VIBONS__AA22) − (10) Figure 51. 5 V Supply, G = 5, Single-Ended-to-Differential Amplifier The internal 500 Ω resistor is provided on-chip to minimize dc errors due to the input offset current in A2. The minimum Figure 51 shows a single 5 V supply connection for G = 5. The error is achieved when R_REF = 0 Ω. In this case, Equation 10 R and R network sets the gain of A1 to 2.5, and the 2.5 V at S F G is reduced to the REF input provides a centered 2.5 V output common-mode voltage. The transfer function is then VON_error = −(VOP_error) + 2[V _A2] + (I )1000 (R_REF = 0 Ω) VOP − VON = 5(VIN) − 5 V (8) OS OS S The differential output voltage error V _error, dm, is the The output range limits of A1 and A2 limit the differential O difference between VOP_error and VON_error: output voltage of the circuit shown in Figure 51 to approximately 8.4 V p-p. VO_error, dm = VOP_error − VON_error (11) DC ERROR CALCULATIONS The output offset voltage of each amplifier in the ADA4941-1 RF OUT+ 4 also includes the effects of finite common-mode rejection ratio + (CMRR), power supply rejection ratio (PSRR), and dc open- VOP 1kΩ – loop gain (AVOL). IBN–A1 1 FB IBN1–kAΩ2 V V _nom ΔVCM  ΔVS ΔVOUT (12) RG RS–IN VIOBSP––AA181 IN RAS1–REF2 REF 500Ω VOS–A2 A2 OUT–VO+–N5 where: OS OS CMRR PSRR AVOL IBP–A2 V _nom is the nominal output offset voltage without including OS 05704-056 Δth ein edfifceacttess o tfh Ce MchRaRng, eP SinR cRo, nadnidti AonVsO Lf.r om nominal. Figure 52. DC Error Sources V is the input common-mode voltage (for A1, the voltage at CM IN, and for A2, the voltage at REF). Figure 52 shows the major contributions to the dc output V is the power supply voltage. voltage error. For each output, the total error voltage can be S VOUT is either op amp output. calculated using familiar op amp concepts. Equation 9 expresses the dc voltage error present at the VOP output. VOP_error 1RRGF VOS_A1(IBP_A1)(RS_IN)(IBP_A1)RF (9) Rev. D | Page 16 of 23

Data Sheet ADA4941-1 Table 7, Table 8, and Table 9 show typical error budgets for the Figure 53 shows the major contributors to the ADA4941-1 circuits shown in Figure 49, Figure 50, and Figure 51. differential output voltage noise. The differential output noise mean-square voltage equals the sum of twice the noise mean- R = 1.0 kΩ, R = 4.99 kΩ, R_IN = 825 Ω, R_REF = 0 Ω F G S S square voltage contributions from the noninverting channel (A1), plus the noise mean-square voltage terms associated with Table 7. Output Voltage Error Budget for G = 2.4 Amplifier the inverting channel (A2). Shown in Figure 49 2 Error Typical V ,dm_n  O Source Value VOP_error VON_error V _dm_error O 2 VOS_A1 0.1 mV +0.12 mV −0.12 mV +0.24 mV 21 RF (vn_A1) 2   IBP_A1 3 μA +2.48 mV −2.48 mV −4.96 mV  RG  IVBON_S_AA12 30 .1μ Am V −0 2m.4V8 mV ++02..24 8m mVV ++40..926 m mVV 1 RRGF (ip_A1RS)22in_A1RF2 (13) Total V _error, dm = 0.44 mV 2 O  2  R  2 4kTRF 2 4kTRG RGF 2 R = 0 Ω, R = ∞, R_IN = 0 Ω, R_REF = 0 Ω F G S S 2 1 RF  4kTR  VON_n2 Table 8. Output Voltage Error Budget for Amplifier Shown  RG S in Figure 50 Error Typical where VON_n2 is calculated as Source Value VOP_error VON_error VO_dm_error 2  2 VON_n 4 vn_A2  V _A1 0.1 mV +0.1 mV −0.1 mV +0.2 mV OS IBP_A1 3 μA +2.48 mV −2.48 mV −4.96 mV 4(ip_A2)(500R _REF)2  1000(in_A2)2 (14) S I _A1 3 μA −2.48 mV +2.48 mV +4.96 mV BN 8 kT(1000)16kT(500)16kT(R _REF) V _A2 0.1 mV 0 mV +0.2 mV +0.2 mV S OS where: Total VO_error, dm = 0.4 mV vn_A1 and vn_A2 are the input voltage noises of A1 and A2, each equal to 2.1 nV/√Hz. R = 1.02 kΩ, R = 665 Ω, R_IN = 402 Ω, R_REF = 0 Ω in_A1, in_A2, ip_A1, and ip_A2 are amplifier input current F G S S noise terms, each equal to 1 pA/√Hz. Table 9. Output Voltage Error Budget for G = 5 Amplifier R, R, and R are the external source, feedback, and gain S F G Shown in Figure 51 resistors, respectively. Error Typical kT is Boltzmann’s constant times absolute temperature, equal to Source Value VOP_error VON_error VO_dm_error 4.2 x 10-21 W-s at room temperature. VOS_A1 0.1 mV +0.25 mV −0.25 mV +0.5 mV RS_REF is any source resistance at the REF pin. I _A1 3 μA +1.21 mV −1.21 mV −2.4 mV BP When A1 is used as a unity gain follower, the output voltage I _A1 3 μA −1.21 mV +1.21 mV +2.4 mV BN noise spectral density is at its minimum, 10 nV/√Hz. Higher V _A2 0.1 mV 0 mV +0.2 mV +0.2 mV OS voltage gains have higher output voltage noise. Total V _error, dm = 0.7 mV O Table 10, Table 11, and Table 12 show the noise contributions OUTPUT VOLTAGE NOISE and output voltage noise for the circuits in Figure 49, Figure 50, √4kTRF RF OUT+ 4 and Figure 51. + VOP √4kT (1kΩ) – in–A1 in–A2 1kΩ 1 FB √4kT (1kΩ) 1kΩ RG 8 IN A1 OUT– 5 REF A2 + RS vinp––AA11 RS–REF2 √4kT (500Ω) 500Ω vn–A2 VO–N ip–A2 √4kTRG √4kTRS √4kT (RS–REF) 05704-057 Figure 53. Noise Sources Rev. D | Page 17 of 23

ADA4941-1 Data Sheet Table 10. Output Voltage Noise, G = 2.4 Differential Amplifier Shown in Figure 49 Noise Source Typical Value VOP Contribution (nV√Hz) VON Contribution (nV√Hz) V , dm Contribution (nV√Hz) O vn_A1 2.1 nV/√Hz 2.5 2.5 5 ip_A1 1 pA/√Hz 1 1 2 in_A1 1 pA/√Hz 1 1 2 √4 kTR 4 nV/√Hz 4 4 8 F √4 kTR 9 nV/√Hz 1.8 1.8 3.6 G √4 kTR 3.6 nV/√Hz 4.4 4.4 8.8 S vn_inverter 9.2 nV/√Hz 0 9.2 9.2 √R_REF 0 0 0 0 S ip_A2 × R_REF 0 0 0 0 S Totals 6.8 11.4 16.5 R = 1.0 kΩ, R = 4.99 kΩ, R = 825 Ω, R_REF = 0 Ω. F G S S vn_inverter = noise contributions from A2 and its associated internal 1 kΩ feedback resistors and 500 Ω offset current balancing resistor. Table 11. Output Voltage Noise, G = 2 Differential Amplifier Shown in Figure 50 Noise Source Typical Value VOP Contribution (nV√Hz) VON Contribution (nV√Hz) V , dm Contribution (nV√Hz) O vn_A1 2.1 nV/√Hz 2.1 2.1 4.2 ip_A1 0 0 0 0 in_A1 0 0 0 0 √4 kTR 0 0 0 0 F √4 kTR 0 0 0 0 G √4 kTR 0 0 0 0 S vn_inverter 9.2 nV/√Hz 0 9.2 9.2 √R_REF 0 0 0 0 S ip_A2 × R_REF 0 0 0 0 S Totals 2.1 9.4 10 R = 0 Ω, R = ∞, R = 0 Ω, R_REF = 0 Ω. F G S S Table 12. Output Voltage Noise, G = 5 Differential Amplifier Shown in Figure 51 Noise Source Typical Value VOP Contribution (nV√Hz) VON Contribution (nV√Hz) V , dm Contribution (nV√Hz) O vn_A1 2.1 nV/√Hz 5.25 5.25 10.5 ip_A1 1 pA/√Hz 1 1 2 in_A1 1 pA/√Hz 1 1 2 √4 kTR 4 nV/√Hz 4 4 8 F √4 kTR 3.26 nV/√Hz 4.9 4.9 9.8 G √4 kTR 2.54 nV/√Hz 6.54 6.54 13.1 S vn_inverter 9.2 nV/√Hz 0 9.2 9.2 √R_REF 0 0 0 0 S ip_A2 × R_REF 0 0 0 0 S Totals 10.7 14.1 23.1 R = 1.02 kΩ, R = 665 Ω, R = 402 Ω, R_REF = 0 Ω. F G S S Rev. D | Page 18 of 23

Data Sheet ADA4941-1 FREQUENCY RESPONSE VS. CLOSED-LOOP GAIN The frequency response of A1 depends on the external feedback network as indicated by Equation 15. The overall differential The operational amplifiers used in the ADA4941-1 are voltage output voltage is therefore feedback with an open-loop frequency response that can be approximated with the integrator response, as shown in Figure 54.     100  1  V , dm = VOP − VON = VOP + VOP × (18) O  f  1  25MHz   80 B)   AIN (d 60  R   1  OOP G VO, dm VIN1RGF 1RF RG f  EN-L 40   RG  50MHz (19) P O   20 fcr =50MHz    1  1  f   1  00.001 0.01 FR0E.1QUENCY (M1Hz) 10 100 05704-062 Multiply2in5gM thHez terms and neglecting negligible terms leads to Figure 54. ADA4941-1 Op Amp Open-Loop Gain vs. Frequency the following approximation: For each amplifier, the frequency response can be approximated  R  by the following equations: V ,dmVIN1 F  O  RG         R   1    (20) VO_A1VIN1RGF 1RFRGRG fcfr  (15) 1RFRGRG50M2fHz125MfHz (Noninverting Response) There are two poles in this transfer function, and the lower frequency pole limits the bandwidth of the differential     amplifier. If VOP is shorted to IN− (A1 is a unity gain follower), R   1  the 25 MHz closed-loop bandwidth of the inverting channel VO_A2VIN RGF 1RF RG f  (16) lnimoisites gtahien os,v tehrea lbl abnadnwdwiditdht his. Wlimhietned A b1y i tsh oep celroasteindg-l owoitph higher   RG  fcr  bandwidth of A1, which is inversely proportional to the noise (Inverting Response) gain (1 + R/R ). For instance, if the external feedback network F G provides a noise gain of 10, the bandwidth drops to 5 MHz. f is the gain-bandwidth frequency of the amplifier (where the CR open-loop gain shown in Figure 54 equals 1). fCR for both amplifiers is about 50 MHz. The inverting amplifier A2 has a fixed feedback network. The transfer function is approximately          1   1  V _A2VIN VOP (17) O  2 f   f  1  1   50MHz   25MHz Rev. D | Page 19 of 23

ADA4941-1 Data Sheet APPLICATIONS INFORMATION OVERVIEW The best use of the REF pin can be further illustrated by The ADA4941-1 is an adjustable-gain, single-ended-to-differential considering a single-supply case with a 10 V power supply and an input signal that varies between 2 V and 7 V. This is a case voltage amplifier, optimized for driving high resolution ADCs. where the midswing level of the input signal is not at midsupply Single-ended-to-differential gain is controlled by one feedback but is at 4.5 V. Setting the REF input at 4.5 V and neglecting network, comprised of two external resistors: R and R . F G offsets, Equation 21 and Equation 22 are used to calculate the USING THE REF PIN results. When the input signal is at its midpoint of 4.5 V, OUT+ The REF pin sets the output base line in the inverting path and is at 4.5 V, as is VON. This can be considered as a base line state is used as a reference for the input signal. In most applications, where the differential output voltage is 0. When the input increases the REF pin is set to the input signal midswing level, which in to 7 V, VOP tracks the input to 7 V, and VON decreases to 2 V. many cases is also midsupply. For bipolar signals and dual power This can be viewed as a positive peak signal where the differential supplies, REF is generally set to ground. In single-supply output voltage equals 5 V. When the input signal decreases to applications, setting REF to the input signal midswing level 2 V, VOP again tracks to 2 V, and VON increases to 7 V. This provides optimal output dynamic range performance with can be viewed as a negative peak signal where the differential minimum differential offset. Note that the REF input only output voltage equals −5 V. The resulting differential output affects the inverting signal path or VON. voltage is 10 V p-p. Most applications require a differential output signal with the The previous discussion reveals how the single-ended-to- same dc common-mode level on each output. It is possible for differential gain of 2 is achieved. the signal measured across VOP and VON to have a common- INTERNAL FEEDBACK NETWORK POWER mode voltage that is of the desired level but not common to DISSIPATION both outputs. This type of signal is generally avoided because While traditional op amps do not have on-chip feedback it does not allow for optimal use of the output dynamic range of elements, the ADA4941-1 contains two on-chip, 1 kΩ resistors the amplifier. that comprise an internal feedback loop. The power dissipated Defining VIN as the voltage applied to the input pin, the in these resistors must be included in the overall power dissipation equations that govern the two signal paths are given in calculations for the device. Under certain circumstances, the Equation 21 and Equation 22. power dissipated in these resistors could be comparable to the quiescent dissipation of the device. For example, on ±5 V supplies VOP = VIN (21) with the REF pin tied to ground and OUT− at +4 VDC, each VON = −VIN + 2 (REF) (22) 1 kΩ resistor carries 4 mA and dissipates 16 mW for a total of When the REF voltage is set to the midswing level of the input 32 mW. This is comparable to the quiescent power and must signal, the two output signals fall directly on top of each other therefore be included in the overall device power dissipation calculations. For ac signals, rms analysis is required. with minimal offset. Setting the REF voltage elsewhere results in an offset between the two outputs. DISABLE FEATURE The ADA4941-1 includes a disable feature that can be asserted to minimize power consumption in a device that is not needed at a particular time. When asserted, the disable feature does not place the device output in a high impedance or tristate condition. The disable feature is active high. See the Specifications tables for the high and low level voltage specifications. Rev. D | Page 20 of 23

Data Sheet ADA4941-1 ADDING A 3-POLE, SALLEN-KEY FILTER Figure 55 illustrates a 3-pole, Sallen-Key, low-pass filter with a −3 dB cutoff frequency of 100 kHz. The 1.69 kΩ resistor is The noninverting amplifier in the ADA4941-1 can be used as included to minimize dc errors due to the input offset current the buffer amplifier of a Sallen-Key filter. A 3-pole, low-pass in A1. The passive RC filters on the outputs are generally filter can be designed to limit the signal bandwidth in front of required by the ADC converter that is being driven. The an ADC. The input signal first passes through the noninverting frequency response of the filter is shown in Figure 56. stage where it is filtered. The filtered signal is then passed through the inverting stage to obtain the complementary output. OUT+ 4 33Ω 2.7nF 3 +5V 1kΩ + VO, dm 10nF 1.69kΩ 1 FB VS+ 1kΩ 0.1µF – 562Ω 562Ω 562Ω 8 IN A1 OUT– 5 33Ω VS– REF A2 6 2 500Ω 2.7nF 3.9nF 560pF –5V 0.1µF VIN 05704-058 Figure 55. Sallen-Key, Low-Pass Filter with 100 kHz Cutoff Frequency 0 VO, dm = 3V p-p –10 –20 –30 dB) –40 N ( VI –50 /m d O, –60 V –70 –80 –90 –100 10 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M05704-059 Figure 56. Frequency Response of the Circuit Shown in Figure 55 Rev. D | Page 21 of 23

ADA4941-1 Data Sheet DRIVING THE AD7687 ADC GAIN OF −2 CONFIGURATION The ADA4941-1 is an excellent driver for high resolution The ADA4941-1 can be operated in a configuration referred to ADCs, such as the AD7687, as shown in Figure 57. The Sallen- as gain of −2. Clearly, a gain of −2 can be achieved by simply Key, low-pass filter shown in Figure 55 is included in this swapping the outputs of a gain of +2 circuit, but the example but is not required. The circuit shown in Figure 57 configuration described here is different. The configuration is accepts single-ended input signals that swing between 0 V and 3 V. referred to as having negative gain to emphasize that the input amplifier, A1, is operated as an inverting amplifier instead of in The ADR443 provides a stable, low noise, 3 V reference that is its usual noninverting mode. As implied in its name, the voltage buffered by one of the AD8032 amplifiers and applied to the gain from VIN to V , dm is −2 V/V. See Figure 58 for the gain O AD7687 REF input, providing a differential input full-scale level of −2 configuration on ±5 V supplies. of 6 V. The reference voltage is also divided by two and buffered to supply the midsupply REF level of 1.5 V for the ADA4941-1. The gain of −2 configuration is most useful in applications that have wide input swings because the input common-mode voltages are held at constant levels. The signal size is therefore constrained by the output swing limits. The gain of −2 has a low input resistance that is equal to R . G +5V 0.1µF OUT+ 4 33Ω 2 3 1kΩ 2.7nF 3 IN+ VDD 10nF 1.69kΩ 1 FB VS+ 1kΩ 0.1µF AD7687 562Ω 562Ω 562Ω 8 IN A1 OUT– 5 33Ω 4 IN– GND REF ADA4941-1 A2 VS– 5 1 6 2 REF 500Ω 2.7nF VIN 3.9nF 560pF –5V 0.1µF 0V TO 3V +5V 10µF ADR443 0.1µF 8 2 6 3 +5V VIN VOUT 1 10µF 0.1µF GND 0.1µF 2 1/2 10µF 1kΩ 4 4 AD8032 5 7 1kΩ 6 AD18/0232 05704-060 Figure 57. ADA4941-1 Driving the AD7687 ADC RF 1kΩ OUT+ 4 3 1kΩ + RG +5V VO–, dm 1kΩ 1 FB VS+ 1kΩ A1 VIN 8 IN OUT– 5 500Ω VS– REF A2 6–5V 2 500Ω 05704-061 Figure 58. Gain of −2 Configuration Rev. D | Page 22 of 23

Data Sheet ADA4941-1 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27B(0S.C0500) 1.75(0.0688) 00..5205((00..00109969)) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 59. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 1.84 3.10 1.74 3.00SQ 2.90 1.64 0.50BSC 5 8 PIN1INDEX EXPOSED 1.55 AREA PAD 1.45 0.50 1.35 0.40 0.30 4 1 PIN1 TOPVIEW BOTTOMVIEW INDICATOR (R0.15) 0.80 FORPROPERCONNECTIONOF 0.75 0.05MAX TTHHEEPEIXNPCOOSNEDFIGPAUDR,ARTEIOFNERANTOD 0.70 0.02NOM FUNCTIONDESCRIPTIONS COPLANARITY SECTIONOFTHISDATASHEET. SEATING 0.30 0.08 PLANE 0.25 0.203REF 0.C2O0MPLIANTTOJEDECSTANDARDSMO-229-WEED 12-07-2010-A Figure 60. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters ORDERING GUIDE Package Ordering Model1 Temperature Range Package Description Option Quantity Branding ADA4941-1YRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 98 ADA4941-1YRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2,500 ADA4941-1YRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1,000 ADA4941-1YCPZ-R2 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 250 H0C ADA4941-1YCPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 5,000 H0C ADA4941-1YCPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 1,500 H0C ADA4941-1YCP-EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05704-0-5/16(D) Rev. D | Page 23 of 23

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADA4941-1YRZ ADA4941-1YCPZ-R7 ADA4941-1YCPZ-RL ADA4941-1YRZ-R7 ADA4941-1YRZ-RL ADA4941- 1YCP-EBZ ADA4941-1YCPZ-R2