Low Power, 1 nV/√Hz, G ≥ 10 Stable, Rail- to-Rail Output Amplifier Data Sheet ADA4895-1/ADA4895-2 FEATURES FUNCTIONAL BLOCK DIAGRAMS Low wideband noise NC 1 8 DISABLE 1 nV/√Hz –IN 2 7 +VS 1.6 pA/√Hz +IN 3 6 OUT Low 1/f noise: 2 nV/√Hz at 10 Hz –VS 4 ADA4895-1 5 NC LLooww dpioswtoerrt:i 3o nm (ASF pDeRr )a: m−9p6li fdiBerc at 100 kHz, VOUT = 2 V p-p NC=NCOONCNOENCNTE TCOT.TDHOISNPOINT. 10186-102 Figure 1. ADA4895-1 Single Amplifier (8-Lead SOIC) Low input offset voltage: 350 µV maximum High speed OUT1 1 10 +VS 236 MHz, −3 dB bandwidth (G = +10) –IN1 2 9 OUT2 943 V/µs slew rate +IN1 3 8 –IN2 Ra2il2-t nos-r saeilt toluintgp utitm e to 0.1% DISABL–VE1S 45 ADA4895-2 76 +DIINS2ABLE2 10186-001 Wide supply range: 3 V to 10 V Figure 2. ADA4895-2 Dual Amplifier (10-Lead MSOP) Disable feature 5 30 APPLICATIONS Low noise preamplifier Hz)4 24 Hz) Ultrasound amplifiers V/√ A/√ n p PLL loop filters E ( E ( High performance analog-to-digital converter (ADC) drivers NOIS3 18 NOIS E T Digital-to-analog converter (DAC) buffers G N A E LT2 12 RR O U V C GENERAL DESCRIPTION PUT VOLTAGE PUT N1 6 N The ADA4895-1 (single) and ADA4895-2 (dual) are high speed I I CURRENT voltage feedback amplifiers that are gain ≥ 10 stable with low ianmppulti nfioeirs. eW, riatihl- tao 1-r/af inl oouistep uotf, 2a nndV a/ √qHuize sacte 1n0t cHuzr raenndt oaf s3p murAio upse-r 01 10 100FREQUE1NkCY (Hz)10k 100k 1M0 10186-002 free dynamic range (SFDR) of −72 dBc at 2 MHz, the ADA4895-1/ Figure 3. Input Voltage and Current Noise vs. Frequency ADA4895-2 are an ideal solution in a variety of applications, Table 1. Other Low Noise Amplifiers1 including ultrasound, low noise preamplifiers, and drivers of ven at 100 kHz Bandwidth Supply high performance ADCs. The Analog Devices, Inc., proprietary Part Number(s) (nV/√Hz) (MHz) Voltage (V) next generation SiGe bipolar process and innovative architecture AD8021 2.1 490 5 to 24 enables the high performance of these amplifiers. AD8045 3 1000 3.3 to 12 The ADA4895-1/ADA4895-2 have a small signal bandwidth of AD8099 0.95 510 5 to 12 236 MHz at a gain of +10 with a slew rate of 943 V/µs, and settle ADA4841-1/ADA4841-2 2.1 80 2.7 to 12 to 0.1% in 22 ns. The wide supply voltage range (3 V to 10 V) ADA4896-2 1 230 3 to 10 of the ADA4895-1/ADA4895-2 make these amplifiers ideal ADA4897-1/ADA4897-2 1 230 3 to 10 candidates for systems that require large dynamic range, high ADA4898-1/ADA4898-2 0.9 65 10 to 32 gain, precision, and high speed. ADA4899-1 1 600 5 to 12 The ADA4895-1 is available in 8-lead SOIC and 6-lead SOT-23 1 See www.analog.com for the latest selection of low noise amplifiers. packages, and the ADA4895-2 is available in a 10-lead MSOP COMPANION PRODUCTS package. All packages operate over the extended industrial ADCs: AD7944 (14-bit), AD7985 (16-bit), AD7986 (18-bit) temperature range of −40°C to +125°C. Additional companion products on the ADA4895-1/ADA4895-2 product page Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADA4895-1/ADA4895-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Amplifier Description ................................................................ 16 General Description ......................................................................... 1 Input Protection ......................................................................... 16 Functional Block Diagrams ............................................................. 1 Disable Operation ...................................................................... 16 Companion Products ....................................................................... 1 DC Errors .................................................................................... 17 Revision History ............................................................................... 2 Bias Current Cancellation ......................................................... 17 Specifications ..................................................................................... 3 Noise Considerations ................................................................. 18 ±5 V (or +10 V) Supply ............................................................... 3 Applications Information .............................................................. 19 ±2.5 V (or +5 V) Supply .............................................................. 4 Using the ADA4895-1/ADA4895-2 at a Gain < +10 .............. 19 ±1.5 V (or +3 V) Supply .............................................................. 5 High Gain Bandwidth Application .......................................... 20 Absolute Maximum Ratings ............................................................ 7 Feedback Capacitor Application .............................................. 20 Thermal Resistance ...................................................................... 7 Wideband Photomultiplier Preamplifier ................................ 21 Maximum Power Dissipation ..................................................... 7 Layout Considerations ............................................................... 22 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 23 Pin Configurations and Function Descriptions ........................... 8 Ordering Guide .......................................................................... 24 Typical Performance Characteristics ........................................... 10 REVISION HISTORY 4/15—Rev. A to Rev. B Changes to Amplifier Description Section ................................. 16 Changes to Ordering Guide .......................................................... 24 12/12—Rev. 0 to Rev. A Added ADA4895-1 ............................................................. Universal Changes to Features Section, General Description Section, and Table 1 ............................................................................................................. 1 Added Figure 1; Renumbered Sequentially .................................. 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 4 Changes to Table 4 ............................................................................ 5 Changes to Figure 4 .......................................................................... 7 Added Figure 5, Table 7, Figure 6, and Table 8 ............................. 8 Added Figure 14 and Figure 17..................................................... 11 Changes to Figure 24 ...................................................................... 12 Added Figure 26 and Figure 29..................................................... 13 Changes to Amplifier Description Section ................................. 16 Changes to Noise Considerations Section .................................. 18 Added Feedback Capacitor Applications Section and Figure 54 .......................................................................................... 20 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 24 9/12—Revision 0: Initial Version Rev. B | Page 2 of 24

Data Sheet ADA4895-1/ADA4895-2 SPECIFICATIONS ±5 V (OR +10 V) SUPPLY T = 25°C, G = +10, R = 249 Ω, R = 1 kΩ to midsupply, unless otherwise noted. A F L Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.2 V p-p 236 MHz OUT V = 2 V p-p 146 MHz OUT V = 0.2 V p-p, G = +20, R = 1 kΩ 115 MHz OUT F Bandwidth for 0.1 dB Flatness V = 2 V p-p, R = 100 Ω 8.9 MHz OUT L Slew Rate V = 6 V step 943 V/µs OUT Settling Time to 0.1% V = 2 V step 22 ns OUT NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) f = 100 kHz, V = 2 V p-p −96 dBc C OUT f = 1 MHz, V = 2 V p-p −78 dBc C OUT f = 2 MHz, V = 2 V p-p −72 dBc C OUT f = 5 MHz, V = 2 V p-p −64 dBc C OUT Input Voltage Noise f = 10 Hz, G = +25.9 2 nV/√Hz f = 100 kHz, G = +25.9 1 nV/√Hz Input Current Noise f = 10 Hz, R = 10 kΩ, R = 1.1 kΩ, R = 1 kΩ 14 pA/√Hz F G S f = 100 kHz, R = 10 kΩ, R = 1.1 kΩ, R = 1 kΩ 1.6 pA/√Hz F G S 0.1 Hz to 10 Hz Noise G = +101, R = 1 kΩ, R = 10 Ω 99 nV p-p F G DC PERFORMANCE Input Offset Voltage −350 +53 +350 µV Input Offset Voltage Drift 0.15 µV/°C Input Bias Current −16 −11 −6 µA Input Bias Current Drift 1.2 nA/°C Input Bias Offset Current −0.6 −0.02 +0.6 µA Open-Loop Gain V = −4 V to +4 V 100 110 dB OUT INPUT CHARACTERISTICS Input Resistance Common mode/differential mode 10 M/10 k Ω Input Capacitance Common mode/differential mode 3/11 pF Input Common-Mode Voltage Range −4.9 to +4.1 V Common-Mode Rejection V = −2 V to +2 V −100 −109 dB CM OUTPUT CHARACTERISTICS Output Overdrive Recovery Time V = −0.55 V to +0.55 V 80 ns IN Positive Output Voltage Swing R = 1 kΩ 4.85 4.96 V L R = 100 Ω 4.5 4.77 V L Negative Output Voltage Swing R = 1 kΩ −4.85 −4.97 V L R = 100 Ω −4.5 −4.85 V L Linear Output Current SFDR = −45 dBc 80 mA rms Short-Circuit Current Sinking/sourcing 116/111 mA Capacitive Load Drive 30% overshoot 6 pF POWER SUPPLY Operating Range 3 to 10 V Quiescent Current per Amplifier 2.8 3 3.2 mA DISABLEx = −5 V 0.1 mA Positive Power Supply Rejection +V = 4 V to 6 V, −V = −5 V −98 −136 dB S S Negative Power Supply Rejection +V = 5 V, −V = −4 V to −6 V −98 −135 dB S S Rev. B | Page 3 of 24

ADA4895-1/ADA4895-2 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit DISABLEx PIN DISABLEx Voltage Device enabled >+VS − 0.5 V Device disabled <+V − 2 V S Input Current per Amplifier Device Enabled DISABLEx = +5 V −1.1 µA Device Disabled DISABLEx = −5 V −40 µA Switching Speed Device Enabled 0.25 µs Device Disabled 6 µs ±2.5 V (OR +5 V) SUPPLY T = 25°C, G = +10, R = 249 Ω, R = 1 kΩ to midsupply, unless otherwise noted. A F L Table 3. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.2 V p-p 216 MHz OUT V = 2 V p-p 131 MHz OUT V = 0.2 V p-p, G = +20, R = 1 kΩ 113 MHz OUT F Bandwidth for 0.1 dB Flatness V = 2 V p-p, R = 100 Ω 7.9 MHz OUT L Slew Rate V = 3 V step 706 V/µs OUT Settling Time to 0.1% V = 2 V step 21 ns OUT NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) f = 100 kHz, V = 2 V p-p −94 dBc C OUT f = 1 MHz, V = 2 V p-p −75 dBc C OUT f = 2 MHz, V = 2 V p-p −69 dBc C OUT f = 5 MHz, V = 2 V p-p −61 dBc C OUT Input Voltage Noise f = 10 Hz, G = +25.9 1.8 nV/√Hz f = 100 kHz, G = +25.9 1 nV/√Hz Input Current Noise f = 10 Hz, R = 10 kΩ, R = 1.1 kΩ, R = 1 kΩ 14 pA/√Hz F G S f = 100 kHz, R = 10 kΩ, R = 1.1 kΩ, R = 1 kΩ 1.7 pA/√Hz F G S 0.1 Hz to 10 Hz Noise G = +101, R = 1 kΩ, R = 10 Ω 99 nV p-p F G DC PERFORMANCE Input Offset Voltage −350 +53 +350 µV Input Offset Voltage Drift 0.15 µV/°C Input Bias Current −16 −11 −6 µA Input Bias Current Drift 1.2 nA/°C Input Bias Offset Current −0.6 −0.02 +0.6 µA Open-Loop Gain V = −2 V to +2 V 97 108 dB OUT INPUT CHARACTERISTICS Input Resistance Common mode/differential mode 10 M/10 k Ω Input Capacitance Common mode/differential mode 3/11 pF Input Common-Mode Voltage Range −2.4 to +1.6 V Common-Mode Rejection V = −1.5 V to +1.5 V −98 −110 dB CM OUTPUT CHARACTERISTICS Output Overdrive Recovery Time V = −0.275 V to +0.275 V 90 ns IN Positive Output Voltage Swing R = 1 kΩ 2.35 2.48 V L R = 100 Ω 2.3 2.38 V L Negative Output Voltage Swing R = 1 kΩ −2.35 −2.48 V L R = 100 Ω −2.3 −2.38 V L Linear Output Current SFDR = −45 dBc 64 mA rms Short-Circuit Current Sinking/sourcing 111/98 mA Capacitive Load Drive 30% overshoot 6 pF Rev. B | Page 4 of 24

Data Sheet ADA4895-1/ADA4895-2 Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Range 3 to 10 V Quiescent Current per Amplifier 2.6 2.8 3 mA DISABLEx = −2.5 V 0.05 mA Positive Power Supply Rejection +V = 2 V to 3 V, −V = −2.5 V −98 −137 dB S S Negative Power Supply Rejection +V = 2.5 V, −V = −3 V to −2 V −98 −141 dB S S DISABLEx PIN DISABLEx Voltage Device enabled >+VS − 0.5 V Device disabled <+V − 2 V S Input Current per Amplifier Device Enabled DISABLEx = +2.5 V −1.1 µA Device Disabled DISABLEx = −2.5 V −20 µA Switching Speed Device Enabled 0.25 µs Device Disabled 6 µs ±1.5 V (OR +3 V) SUPPLY T = 25°C, G = +10, R = 249 Ω, R = 1 kΩ to midsupply, unless otherwise noted. A F L Table 4. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.2 V p-p 205 MHz OUT V = 1 V p-p 131 MHz OUT V = 0.2 V p-p, G = +20, R = 1 kΩ 111 MHz OUT F Bandwidth for 0.1 dB Flatness V = 2 V p-p, R = 100 Ω 7.5 MHz OUT L Slew Rate V = 1 V step 384 V/µs OUT Settling Time to 0.1% V = 2 V step 20 ns OUT NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) f = 100 kHz, V = 2 V p-p −92 dBc C OUT f = 1 MHz, V = 2 V p-p −73 dBc C OUT f = 2 MHz, V = 2 V p-p −67 dBc C OUT f = 5 MHz, V = 2 V p-p −59 dBc C OUT Input Voltage Noise f = 10 Hz, G = +25.9 1.9 nV/√Hz f = 100 kHz, G = +25.9 1 nV/√Hz Input Current Noise f = 10 Hz, R = 10 kΩ, R = 1.1 kΩ, R = 1 kΩ 14 pA/√Hz F G S f = 100 kHz, R = 10 kΩ, R = 1.1 kΩ, R = 1 kΩ 1.7 pA/√Hz F G S 0.1 Hz to 10 Hz Noise G = +101, R = 1 kΩ, R = 10 Ω 99 nV p-p F G DC PERFORMANCE Input Offset Voltage −350 +55 +350 µV Input Offset Voltage Drift 0.15 µV/°C Input Bias Current −16 −11 −6 µA Input Bias Current Drift 1.2 nA/°C Input Bias Offset Current −0.6 −0.02 +0.6 µA Open-Loop Gain V = −1 V to +1 V 95 106 dB OUT INPUT CHARACTERISTICS Input Resistance Common mode/differential mode 10 M/10 k Ω Input Capacitance Common mode/differential mode 3/11 pF Input Common-Mode Voltage Range −1.4 to +0.6 V Common-Mode Rejection V = −0.4 V to +0.4 V −93 −110 dB CM Rev. B | Page 5 of 24

ADA4895-1/ADA4895-2 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Overdrive Recovery Time V = −0.165 V to +0.165 V 80 ns IN Positive Output Voltage Swing R = 1 kΩ 1.35 1.48 V L R = 100 Ω 1.3 1.43 V L Negative Output Voltage Swing R = 1 kΩ −1.35 −1.49 V L R = 100 Ω −1.3 −1.45 V L Linear Output Current SFDR = −45 dBc 46 mA rms Short-Circuit Current Sinking/sourcing 99/83 mA Capacitive Load Drive 30% overshoot 6 pF POWER SUPPLY Operating Range 3 to 10 V Quiescent Current per Amplifier 2.5 2.7 2.9 mA DISABLEx = −1.5 V 0.03 mA Positive Power Supply Rejection +V = 1.2 V to 2.2 V, −V = −1.5 V −98 −133 dB S S Negative Power Supply Rejection +V = 1.5 V, −V = −2.2 V to −1.2 V −98 −146 dB S S DISABLEx PIN DISABLEx Voltage Device enabled >+VS − 0.5 V Device disabled <+V − 2 V S Input Current per Amplifier Device Enabled DISABLEx = +1.5 V −1.2 µA Device Disabled DISABLEx = −1.5 V −10 µA Switching Speed Device Enabled 0.25 µs Device Disabled 6 µs Rev. B | Page 6 of 24

Data Sheet ADA4895-1/ADA4895-2 ABSOLUTE MAXIMUM RATINGS P = Quiescent Power + (Total Drive Power − Load Power) D Table 5. The quiescent power dissipation is the voltage between the supply Parameter Rating pins (±V) multiplied by the quiescent current (I). Supply Voltage 11 V S S Power Dissipation See Figure 4 ( ) V V  V 2 Common-Mode Input Voltage −VS − 0.7 V to +VS + 0.7 V PD = VS ×IS +  2S × ROUT  − ORUT L L Differential Input Voltage ±0.7 V Consider rms output voltages. If R is referenced to −V, as in Storage Temperature Range −65°C to +125°C L S single-supply operation, the total drive power is V × I . In Operating Temperature Range −40°C to +125°C S OUT single-supply operation with R referenced to −V, the worst Lead Temperature (Soldering 10 sec) 300°C L S case is V = V/2. Junction Temperature 150°C OUT S If the rms signal levels are indeterminate, consider the worst case, Stresses at or above those listed under Absolute Maximum when V = V/4 with R referenced to midsupply. OUT S L Ratings may cause permanent damage to the product. This is a ( ) stress rating only; functional operation of the product at these ( ) V /4 2 P = V ×I + S or any other conditions above those indicated in the operational D S S R L section of this specification is not implied. Operation beyond Airflow increases heat dissipation, effectively reducing θ . Also, JA the maximum operating conditions for extended periods may more metal directly in contact with the package leads reduces θ . JA affect product reliability. Figure 4 shows the maximum safe power dissipation in the package THERMAL RESISTANCE vs. the ambient temperature on a JEDEC standard, 4-layer board. θJA is specified for the worst-case conditions, that is, θJA is specified θJA values are approximations. for a device soldered in a circuit board for surface-mount 1.6 packages. Table 6 lists the θ for the ADA4895-1/ADA4895-2. JA 1.4 W) Table 6. Thermal Resistance N ( O 1.2 ADA4895-1 (SOIC) Package Type θJA Unit ATI 8-Lead Single SOIC 133 °C/W SIP 1.0 ADA4895-1 (SOT-23) S 6-Lead Single SOT-23 150 °C/W DI R 0.8 10-Lead Dual MSOP 210 °C/W WE O P 0.6 M MAXIMUM POWER DISSIPATION U XIM 0.4 ADA4895-2 (MSOP) The maximum safe power dissipation for the ADA4895-1/ A M 0.2 ADA4895-2 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the 0 gElvaesns ttreamnspitoioranr tielym epxecreaetudrine,g t hthe ips rtoepmerpteiersa toufr teh lei mpliats ctiacn c hchanagneg.e –40–30–20–10 0AM10BIE20NT3 T0EM40PE5R0AT6U0R7E0 (°C80) 90100110120 10186-003 the stresses that the package exerts on the die, permanently Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board shifting the parametric performance of the ADA4895-1/ ESD CAUTION ADA4895-2. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. The power dissipated in the package (P ) is the sum of the D quiescent power dissipation and the power dissipated in the die due to the ADA4895-1/ADA4895-2 drive at the output. Rev. B | Page 7 of 24

ADA4895-1/ADA4895-2 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 8 DISABLE –IN 2 7 +VS +IN 3 6 OUT –VS 4 ADA4895-1 5 NC NC=NCOONCNOENCNTE TCOT.TDHOISNPOINT. 10186-105 Figure 5. 8-Lead SOIC Pin Configuration for the ADA4895-1 Table 7. 8-Lead SOIC Pin Function Descriptions for the ADA4895-1 Pin No. Mnemonic Description 1, 5 NC No Connect. Do not connect to these pins. 2 −IN Inverting Input. 3 +IN Noninverting Input. 4 −V Negative Supply. S 6 OUT Output. 7 +V Positive Supply. S 8 DISABLE Disable. OUT 1 6 +VS –VS 2 5 DISABLE +IN 3 ADA4895-1 4 –IN 10186-106 Figure 6. 6-Lead SOT-23 Pin Configuration for the ADA4895-1 Table 8. 6-Lead SOT-23Pin Function Descriptions for the ADA4895-1 Pin No. Mnemonic Description 1 OUT Output 2 −V Negative Supply S 3 +IN Noninverting Input 4 −IN Inverting Input 5 DISABLE Disable 6 +V Positive Supply S Rev. B | Page 8 of 24

Data Sheet ADA4895-1/ADA4895-2 OUT1 1 10 +VS –IN1 2 9 OUT2 +IN1 3 8 –IN2 DISABL–VE1S 45 ADA4895-2 76 +DIINS2ABLE2 10186-004 Figure 7. 10-Lead MSOP Pin Configuration for the ADA4895-2 Table 9. 10-Lead MSOP Pin Function Descriptions for the ADA4895-2 Pin Number Mnemonic Description 1 OUT1 Output 1 2 −IN1 Inverting Input 1 3 +IN1 Noninverting Input 1 4 −V Negative Supply S 5 DISABLE1 Disable 1 6 DISABLE2 Disable 2 7 +IN2 Noninverting Input 2 8 −IN2 Inverting Input 2 9 OUT2 Output 2 10 +V Positive Supply S Rev. B | Page 9 of 24

ADA4895-1/ADA4895-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = ±2.5 V, G = +10, R = 249 Ω, R = 1 kΩ to midsupply, unless otherwise noted. A S F L 3 2 N (dB) 2 VS = ±2.5V VSV S= =± 1±.55.V0V N (dB) 1 VS = ±2.5V VS = ±1.5V AI 1 AI P G P G 0 O O O 0 O D-L D-L –1 SE –1 SE VS = ±5.0V O O L L –2 C C D –2 D E E ALIZ –3 ALIZ –3 M M R R NO –4 NO –4 VOUT = 200mV p-p VOUT = 2V p-p –50.1 1 FREQUE1N0CY (MHz) 100 1000 10186-006 –50.1 1 FREQUE1N0CY (MHz) 100 1000 10186-010 Figure 8. Small Signal Frequency Response vs. Supply Voltage Figure 11. Large Signal Frequency Response vs. Supply Voltage 8 3 G = –10 G = +10 B) 6 B) 2 d d AIN ( 4 AIN ( 1 G G OP 2 G = +10 OP G = –10 O O 0 L L D- 0 G = –20 D- SE SE –1 LO –2 LO C C D D –2 E –4 E G =–20 Z Z ALI ALI –3 M –6 M R R O O N –8 RF = 1kΩ N –4 RF = 1kΩ VOUT = 200mV p-p VOUT = 2V p-p –100.1 1 FREQUE1N0CY (MHz) 100 1000 10186-005 –50.1 1 FREQUE1N0CY (MHz) 100 1000 10186-009 Figure 9. Small Signal Frequency Response vs. Gain Figure 12. Large Signal Frequency Response vs. Gain 4 3 B) 3 –40°C B) 2 VOUT = 100mV p-p VOUT = 400mV p-p d d GAIN ( 2 +125°C +25°C GAIN ( 1 OP 1 OP O O 0 L L D- 0 D- E E S S –1 LO –1 LO VOUT = 2V p-p C C D D –2 E –2 E Z Z RMALI –3 RMALI –3 VOUT = 1V p-p O O N –4 N –4 VOUT = 200mV p-p –50.1 1 FREQUE1N0CY (MHz) 100 1000 10186-007 –50.1 1 FREQUE1N0CY (MHz) 100 1000 10186-008 Figure 10. Small Signal Frequency Response vs. Temperature Figure 13. Frequency Response for Various Output Voltages Rev. B | Page 10 of 24

Data Sheet ADA4895-1/ADA4895-2 4 4 ADA4895-2, MSOP B) ADA4895-1, SOT-23 B) ADA4895-2, MSOP d 2 d 2 N ( N ( ADA4895-1, SOT-23 AI AI OP G 0 ADA4895-1, SOIC OP G 0 ADA4895-1, SOIC O O D-L –2 D-L –2 E E S S O O CL –4 CL –4 D D E E LIZ –6 LIZ –6 A A M M R R O –8 O –8 N N VOUT = 200mV p-p VOUT = 2V p-p –100.1 1 FREQUE1N0CY (MHz) 100 1000 10186-138 –100.1 1 FREQUE1N0CY (MHz) 100 1000 10186-141 Figure 14. Small Signal Frequency Response vs. Package Figure 17. Large Signal Frequency Response vs. Package 6 120 0 CL = 6pF 110 –20 B) 4 AIN (d 2 CL = 3pF 10900 GAIN ––6400 G OSED-LOOP –20 CL = 0pF AIN (dB) 678000 PHASE –––11820000 E (Degrees) CL G 50 –140 AS ED –4 40 –160 PH Z ALI –6 30 –180 M OR 20 –200 N –8 10 –220 –100.1VOUT = 200mV 1p-p FREQUE1N0CY (MHz) 100 1000 10186-011 01k 10k 100kFREQ1UMENCY(H1z0)M 100M 1G –240 10186-017 Figure 15. Small Signal Frequency Response vs. Capacitive Load Figure 18. Open-Loop Gain and Phase vs. Frequency –40 –40 VOUT = 2V p-p VOUT = 2V p-p –50 –50 HD2, RL = 100Ω –60 –60 HD2 HD2, RL = 1kΩ dBc) –70 dBc) –70 VSV S= =±2 ±.55VV N ( N ( –80 VS = ±1.5V O O TI –80 TI STOR –90 HD3, RL = 1kΩ STOR –90 HD3 DI HD3, RL = 100Ω DI–100 –100 –110 VS = ±5V VS = ±2.5V –110 –120 VS = ±1.5V –1200.1 FREQUEN1CY (MHz) 10 10186-012 –1300.1 FREQUEN1CY (MHz) 10 10186-016 Figure 16. Harmonic Distortion vs. Frequency for Various Loads Figure 19. Harmonic Distortion vs. Frequency for Various Supplies Rev. B | Page 11 of 24

ADA4895-1/ADA4895-2 Data Sheet –20 –20 VOUT = 2V p-p VS = ±5.0V G = +20 RG = 27.4Ω –40 8V p-p –40 4V p-p RL =100Ω HD2 N (dBc) –60 RL =1kΩ N (dBc) –60 HD2 2V p-p O O TI TI –80 HD3 R R O O T –80 T 8V p-p S S DI HD3 DI–100 4V p-p –100 RL =100Ω –120 2V p-p RL =1kΩ –1200.1 FREQUEN1CY (MHz) 10 10186-013 –1400.1 FREQUEN1CY (MHz) 10 10186-015 Figure 20. Harmonic Distortion vs. Frequency, G = +20 Figure 23. Harmonic Distortion vs. Frequency for Various Output Voltages OLTAGE NOISE (nV/√Hz) 3456 GRVRSFG = === + ±2125405V9Ω.9Ω RRENT NOISE (pA/√Hz) 10100 RRRFGS === 1110k.1kΩkΩΩ UT V 2 T CU P U N P I 1 IN 01 10 100 1FkREQU1E0NkCY (H10z0)k 1M 10M 100M 10186-018 11 10 100FREQUE1NkCY (Hz)10k 100k 1M 10186-019 Figure 21. Input Voltage Noise vs. Frequency Figure 24. Input Current Noise vs. Frequency 00..1250 VVVSSS === ±±±125...550VVV VOUT = 200mV p-p 00..1250 CCCLLL === 530..p63FppFF VOUT = 200mV p-p 0.10 0.10 OUTPUT VOLTAGE (V)–00..00550 OUTPUT VOLTAGE (V)–00..00550 –0.10 –0.10 –0.15 –0.15 –0.20 TIME (5ns/DIV) 10186-021 –0.20 TIME (5ns/DIV) 10186-023 Figure 22. Small Signal Transient Response for Various Supplies Figure 25. Small Signal Transient Response for Various Capacitive Loads Rev. B | Page 12 of 24

Data Sheet ADA4895-1/ADA4895-2 0.20 1.5 ADA4895-2, MSOP VOUT = 200mV p-p ADA4895-2, MSOP 0.15 ADA4895-1, SOIC 1.0 0.10 ADA4895-1, SOIC V) V) GE ( 0.05 GE ( 0.5 A A LT LT VO 0 VO 0 T T U U TP–0.05 TP U U–0.5 O O –0.10 –1.0 –0.15 –0.20 TIME (5nsA/DDIAV4)895-1, SOT-23 10186-139 –1.5 VOUT = 2V p-p TIME (5ns/DIV) ADA4895-1, SOT-23 10186-142 Figure 26. Small Signal Transient Response vs. Package Figure 29. Large Signal Transient Response vs. Package 10 1.5 ASTVAENRDAAGRED = D1E5V4nIAVT/°IOCN = 184nV/°C G = +10 G = +20 VOUT = 2V p-p 9 –40°C TO +125°C 1.0 8 OF SAMPLES 567 VOLTAGE (V) 0.50 R T BE 4 PU NUM 3 OUT–0.5 2 –1.0 1 0 –0.4 –0.3 –0.2 –0.1 V0DRIF0T.1(µV/0°C.2) 0.3 0.4 0.5 0.6 10186-020 –1.5 TIME (5ns/DIV) 10186-024 Figure 27. Input Offset Voltage Drift Distribution Figure 30. Large Signal Transient Response for Various Gains 3 0.2 VOUT 90ns RECOVERY TIME VOUT = 2V STEP V) 2 PUT VOLTAGE ( 01 10 × VIN G TIME (%) 0.10 ERROR D OUT TTLIN AN –1 SE T U –0.1 P N I –2 –3 TIME (100ns/DIV) 10186-026 –0.2 TIME (10ns/DIV) 10186-029 Figure 28. Output Overdrive Recovery Time Figure 31. Settling Time to 0.1% Rev. B | Page 13 of 24

ADA4895-1/ADA4895-2 Data Sheet 0 0 –10 –20 –20 –30 –40 –50 –40 –60 R (dB) ––8700 –VS = –2.5V ± 1V p-p R (dB) –60 R R S –90 M P C –100 +VS = 2.5V ± 1V p-p –80 –110 –120 –130 –100 –140 –150 –1600.001 0.01 FR0E.1QUENCY (M1Hz) 10 100 10186-031 –1200.001 0.01 FR0E.1QUENCY (M1Hz) 10 100 10186-030 Figure 32. PSRR vs. Frequency Figure 35. CMRR vs. Frequency 800 160 VOUT = 3V p-p 140 POSITIVE SLOPE 750 120 E (V/µs) 700 RISE TIME (ns) 100 NEGATIVE SLOPE RAT RY 80 LEW 650 FALL COVE 60 S E R 40 600 20 550–40 –20 0 T2E0MPER4A0TURE6(0˚C) 80 100 120 10186-028 00 100 200OVE3R0L0OAD 4D0U0RATI5O0N0 (ns)600 700 800 10186-027 Figure 33. Slew Rate vs. Temperature Figure 36. Output Overload Recovery Time vs. Overload Duration 3.2 –10.8 VS = ±5.0V 3.1 VS = ±5.0V –11.0 A) 3.0 µA) NT (m ENT (–11.2 VS = ±2.5V E 2.9 R R R Y CUR 2.8 VS = ±2.5V AS CU–11.4 VS = ±1.5V SUPPL 2.7 PUT BI–11.6 N VS = ±1.5V I 2.6 –11.8 2.5–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10186-034 –12.0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10186-035 Figure 34. Supply Current vs. Temperature for Various Supplies Figure 37. Input Bias Current vs. Temperature for Various Supplies Rev. B | Page 14 of 24

Data Sheet ADA4895-1/ADA4895-2 0.05 0 –20 0.04 VS = ±5.0V VS = ±2.5V B) –40 V)0.03 K (d m L V (OS SSTA –60 0.02 O R VS = ±1.5V C –80 0.01 –100 0–40 –25 –10 5 T2E0MPE35RATU5R0E (°6C5) 80 95 110 125 10186-033 –1200.01 0.1 FREQUEN1CY (MHz) 10 100 10186-036 Figure 38. Input Offset Voltage vs. Temperature for Various Supplies Figure 41. Crosstalk, OUT1 to OUT2 1M 0 100k –20 DISABLED –40 Ω) 10k NCE ( 1k dB) –60 DA N ( –80 E O TPUT IMP 10100 ISOLATI––112000 U O 1 –140 ENABLED 0.1 –160 0.010.01 0.1 FRE1QUENCY (M10Hz) 100 1000 10186-032 –1800.01 0.1 FREQUEN1CY (MHz) 10 100 10186-039 Figure 39. Output Impedance vs. Frequency Figure 42. Forward Isolation vs. Frequency 3.0 3.0 DISABLE 2.5 DISABLE 2.5 2.0 2.0 V) V) –40°C GE ( 1.5 GE ( 1.5 +25°C +125°C A OUTPUT A VOLT 1.0 –40°C VOLT 1.0 +25°C 0.5 0.5 +125°C 0 0 –0.5 TIME (1µs/DIV) 10186-038 –0.5 OUTPUTTIME (40ns/DIV) 10186-037 Figure 40. Output Turn-Off Time vs. Temperature Figure 43. Output Turn-On Time vs. Temperature Rev. B | Page 15 of 24

ADA4895-1/ADA4895-2 Data Sheet THEORY OF OPERATION AMPLIFIER DESCRIPTION At differential voltages above approximately 0.7 V, the diode clamps begin to conduct. Too much current can cause damage The ADA4895-1/ADA4895-2 amplifiers have an input noise of due to excessive heating. If large differential voltages must be 1 nV/√Hz and consume 3 mA per amplifier from supply voltages sustained across the input terminals, it is recommended that the of 3 V to 10 V. Using the Analog Devices XFCB3 process, the current through the input clamps be limited to less than 10 mA. ADA4895-1/ADA4895-2 have a gain bandwidth product in Series input resistors that are sized appropriately for the expected excess of 1.5 GHz and are gain ≥ 10 stable, with an input differential overvoltage provide the needed protection. structure that results in an extremely low input 1/f noise for a relatively high speed amplifier. The ESD clamps begin to conduct at input voltages that are more than 0.7 V above the positive supply or more than 0.7 V below The rail-to-rail output stage is designed to drive the heavy feedback the negative supply. If an overvoltage condition is expected, it is load required to achieve an overall low output referred noise. recommended that the fault current be limited to less than 10 mA. The low input noise and high bandwidth of the ADA4895-1/ ADA4895-2 are achieved with minimal power penalty. For this DISABLE OPERATION reason, the maximum offset voltage of 350 µV and voltage drift Figure 45 shows the ADA4895-1/ADA4895-2 power-down of 0.15 µV/°C make the ADA4895-1/ADA4895-2 an excellent circuitry. If the DISABLEx pin is left unconnected, the base of the choice, even when the low noise performance of the amplifier is input PNP transistor is pulled high through the internal pull-up not needed. resistor to the positive supply and the device is turned on. Pulling For any gain greater than 10, the closed-loop frequency response the DISABLEx pin more than 2 V below the positive supply turns of a basic noninverting configuration can be approximated by the device off, reducing the supply current to approximately R 50 µA for a 5 V voltage supply. Closed-Loop −3 dB Frequency = (GBP) × G (R +R ) +VS F G For inverting gain configurations, the source impedance must be IBIAS considered when sizing R to maintain the minimum stable gain. ESD G For gains lower than 10, see the Using the ADA4895-1/ADA4895-2 DISABLEx ESD at a Gain < +10 section, or use the ADA4897-1/ADA4897-2, which TO is a unity-gain stable amplifier with 230 MHz bandwidth. AMPLIFIER BIAS INPUT PROTECTION The ADA4895-1/ADA4895-2 are fully protected from ESD events achnadr gceadn- dweivthicset amndo dheul mevaenn tbs oodf y1 mkVo dweilt hE SnDo meveeanstusr oefd 2 p.5e rkfoVr manadn ce –VS 10186-041 Figure 45. DISABLEx Circuit degradation. The precision input is protected with an ESD network between the power supplies and diode clamps across the input The DISABLEx pin is protected by ESD clamps, as shown in device pair, as shown in Figure 44. Figure 45. Voltages beyond the power supplies cause these diodes +VS to conduct. For protection of the DISABLEx pins, the voltage to these pins should not exceed 0.7 V beyond the supply voltage, or BIAS the input current should be restricted to less than 10 mA with a ESD ESD series resistor. +IN –IN ESD ESD –VS TO THE REST OF THE AMPLIFIER 10186-040 Figure 44. Input Stage and Protection Diodes Rev. B | Page 16 of 24

Data Sheet ADA4895-1/ADA4895-2 DC ERRORS The output error due to the input currents can be estimated as follows: Figure 46 shows a typical connection diagram and the major dc error sources.  R   R  V =(R ||R )×1+ F ×I −R ×1+ F ×I (5) RF OUTERROR F G  R  B− S  R  B+ G G –VIN+ RG +VOS– BIAS CURRENT CANCELLATION IB– +VOUT– To cancel the output voltage error due to unmatched bias currents –VIP+ RS at the inputs, Resistors RBP and RBN can be used (see Figure 47). IB+ 10186-042 RG RF Figure 46. Typical Connection Diagram and DC Error Sources The ideal transfer function (all error sources set to 0 and infinite dc gain) can be expressed as follows: RBN VOUT = 1+ RRF ×VIP −RRF ×VIN (1) RS RBP 10186-043 G G Figure 47. Using RBP and RBN to Cancel Bias Current Error This equation reduces to the familiar forms for noninverting To compensate for the unmatched bias currents at the two inputs, and inverting op amp gain expressions, as follows: set Resistors R and R as shown in Table 10. BP BN For noninverting gain (V = 0 V), IN Table 10. Setting R and R to Cancel Bias Current Error BP BN VOUT = 1+ RRGF  ×VIP (2) VGareluatee or Tf hRaF|n|R RGS VRFa||lRuGe − o Rf SR BP (Ω) 0V alue of RBN (Ω) Less Than R 0 R − R||R For inverting gain (V = 0 V), S S F G IP −R  VOUT = R F  ×VIN (3) G The total output voltage error is the sum of the errors due to the amplifier offset voltage and input currents. The output error due to the offset voltage can be estimated as follows: V = (4) OUTERROR  V V −V V   R  VOFFSETNOM + CMCMRR + PPSRPRNOM + OAUT ×1+RF  G where: V is the offset voltage at the specified supply voltage, OFFSETNOM which is measured with the input and output at midsupply. V is the common-mode voltage. CM CMRR is the common-mode rejection ratio. V is the power supply voltage. P VPNOM is the specified power supply voltage. PSRR is the power supply rejection ratio. A is the dc open-loop gain. Rev. B | Page 17 of 24

ADA4895-1/ADA4895-2 Data Sheet NOISE CONSIDERATIONS Source resistance noise, amplifier voltage noise (ven), and the Figure 48 illustrates the primary noise contributors for the voltage noise from the amplifier current noise (iep × RS) are all typical gain configurations. The total rms output noise is subject to the noise gain term (1 + RF/RG). Note that with a the root mean square of all the contributions. 1 nV/√Hz input voltage noise and a 1.7 pA/√Hz input current noise, the noise contributions of the amplifier are relatively RF vn _ RF = 4kT × RF small for source resistances from approximately 50 Ω to 700 Ω. vn _ RG = 4kT × RG RG ven Figure 49 shows the total RTI noise due to the amplifier vs. the ien + vout_en – source resistance. In addition, the value of the feedback resistors vn _ RS = 4kT × RS RS iep 10186-044 artoeffsteaicsltt nso orthsi sebe ne l oomiwsae. i. nItt aisin reedco bmemtweenedne 2d5 t0h aΩt t ahne dv a1l ukeΩ o ft oth kee feepe dtbhaec k Figure 48. Noise Sources in Typical Gain Configurations 500 The output noise spectral density can be calculated as follows: vout_en = (6) 4kTRF+1+RRGF 2[4kTRS+iep2RS2+ven2]+RRGF 24kTRG +ien2RF2 nV/√Hz) 50 RAEMSPISLTIFOIERR N AONISDE E ( S OI where: N 5 SOURCE k is Boltzmann’s constant. RESISTANCE NOISE T is the absolute temperature (degrees Kelvin). RF and RG are the feedback network resistances, as shown in AMPLIFIER NOISE iFReiSpg i usa rntehd 4e i 8es.no urrecper erseesnistt athnec ea,m asp slihfioewr nin ipnu Ft icguurrree n4t8 .n oise spectral 0.550 S5O0U0RCE RESISTANCE5 (kΩ) 50k 10186-045 Figure 49. RTI Noise vs. Source Resistance density (pA/√Hz). ven is the amplifier input voltage noise spectral density (nV/√Hz). Rev. B | Page 18 of 24

Data Sheet ADA4895-1/ADA4895-2 APPLICATIONS INFORMATION USING THE ADA4895-1/ADA4895-2 AT A Figure 51 shows the small and large signal frequency response of GAIN < +10 the circuit shown in Figure 50 into a 50 Ω analyzer (G = +5 V/V or 14 dB). As shown in Figure 51, the circuit is very stable, and The ADA4895-1/ADA4895-2 are minimum gain 10 stable when the peaking is a little over 2 dB. This configuration is scalable to used in normal gain configurations. However, the ADA4895-1/ accommodate any gain from +5 to +10, as shown in Table 11. ADA4895-2 can be configured to work at lower gains down to a 17 gain of +5. Figure 50 shows how to add a simple RC circuit (R1 = VOUT = 30mV p-p 49.9 Ω and C1 = 60 pF) to allow the ADA4895-1/ADA4895-2 to VOUT = 250mV p-p 14 operate at a gain of +5. VIN RT 5R0OΩ VOUT AIN (dB) 11 VOUT = 2V p-p 50Ω 50RΩ1 20R0FΩ C15L0pF OOP G 8 60CpF1 5R0ΩG 10186-046 CLOSED-L 5 Figure 50. Configuring the ADA4895-1/ADA4895-2 for a Gain of +5 Stable 2 This circuit has a gain of +9 at high frequency and a gain of +5 at VS = ±5V f(r1e/q2uπeRn1cCie1s) .l oWwietrh t ah anno itshee g raeisno onfa napcpe rforexqimueanteclyy o+f9 5 a3t MhiHghz –10.1G = +5 1 FREQUE1N0CY (MHz) 100 1000 10186-047 frequency, the total output noise increases unless an antialiasing Figure 51. Frequency Response for G = +5 filter is used to block the high frequency content. Table 11. Component Values Used with the ADA4895-1/ADA4895-2 for Gain < +10 Gain R (Ω) R1 (Ω) C1 (pF) R (Ω) R (Ω) R (Ω) C (pF) T G F O L +5 49.9 49.9 60 49.9 200 49.9 150 +6 49.9 66.5 45 40.2 200 49.9 150 +7 49.9 110 27 37.4 226 49.9 150 +8 49.9 205 15 32.4 226 49.9 120 +9 49.9 Not applicable Not applicable 30.9 249 49.9 100 Rev. B | Page 19 of 24

ADA4895-1/ADA4895-2 Data Sheet HIGH GAIN BANDWIDTH APPLICATION FEEDBACK CAPACITOR APPLICATION The circuit in Figure 52 shows cascaded dual amplifier stages For applications where frequency response flatness is necessary, using the ADA4895-1/ADA4895-2. Each stage has a gain of +10 or a larger feedback resistor value is desired, a small feedback (20 dB), making the output 100 times (40 dB) the input. The total capacitor in parallel with the feedback resistor can be used to gain bandwidth product is approximately 9 GHz with the device reduce peaking and increase flatness. operating on 6 mA of quiescent current (3 mA per amplifier). Figure 54 shows the small signal frequency response with and VIN 24R91Ω without a feedback capacitor. 50RΩT 22R6FΩ 5CpF1 22R6FΩ R1kLΩ VOUT N (dB) 36 VVRGASODL = UA== T+ 4±1 18=2k09 .Ω2550-V10 mSVO IpC-p RRFF = = 4 14k9ΩΩ 25.R5ΩG 2CpFF 25.R5ΩG 2CpFF 10186-048 OOP GAI 0 RF = 499Ω, CF = 1pF Figure 52. Cascaded Amplifier Stages for High Gain Applications (G = +100) D-L –3 RF = 1kΩ, CF = 0.5pF E S O Figure 53 shows the large signal frequency response for two cases. L –6 C The first case is with installed feedback capacitors (C = 2 pF), and D F E Z the second case is without these capacitors. Removing the 2 pF LI –9 A M feedback capacitors from this circuit increases the bandwidth, R O –12 but adds about 0.5 dB of peaking. N 344604 NO CF Figure–1 5541. Small Signal Freq1u0eFnRcEyQ RUeEsNpCoYn (sMeH Wz1)it0h0 and Without a 1F0e0e0dba10186-153c k 32 CF = 2pF Capacitor 28 B) d 24 N ( AI 20 G 16 12 8 4 VOUT = 2V p-p G = +100 00.1 1 FREQUE1N0CY (MHz) 100 1000 10186-049 Figure 53. Large Signal Frequency Response, G = +100, VS = ±5 V To better balance the second stage and remove the current offset contribution, an R1C1 circuit can be sized to correct for any mis-match between the source impedance and the feedback network impedance on the input amplifier. (In the example shown in Figure 52, R1 = 249 Ω and C1 = 5 pF.) The offset of each amplifier is within the same statistical range. As configured, the offset of the output amplifier is not statistically significant to the overall offset of the system. Figure 53 was captured using a ±5 V supply; however, this circuit also operates with supplies from ±1.5 V to ±5 V as long as the input and output headroom values are not violated. Rev. B | Page 20 of 24

Data Sheet ADA4895-1/ADA4895-2 WIDEBAND PHOTOMULTIPLIER PREAMPLIFIER R and the total capacitance produce a pole in the loop trans- F mission of the amplifier that can result in peaking and instability. A decompensated amplifier can provide significantly greater Adding C creates a zero in the loop transmission that compensates speed in transimpedance applications than a unity-gain stable F for the pole effect and reduces the signal bandwidth. It can be amplifier. The speed increases by the square root of the ratio of shown that the signal bandwidth resulting in a 45° phase margin the bandwidth of the two amplifiers; that is, a 1 GHz GBP amplifier (f ) is defined as follows: is 10 times faster than a 10 MHz amplifier in the same trans- (45) impedance application if all other parameters are kept constant. GBP f  Additionally, the input voltage noise normally dominates the 45 2πR C F S total output rms noise because it is multiplied by the capacitive noise gain network. where:   GBP is the gain bandwidth product. C C C C S M F D R is the feedback resistance. F C F CS is the total capacitance at the amplifier summing junction In the case of the ADA4895-1/ADA4895-2, the input noise is (amplifier + photomultiplier + board parasitics). low, but the capacitive noise gain network must be kept greater The value of C that produces f is F (45) than 10 for stability reasons. C One disadvantage of using the ADA4895-1/ADA4895-2 in C  S F 2πR GBP transimpedance applications is that the input current and input F current noise can create large offsets and output voltage noise The frequency response in this case shows approximately 2 dB when coupled with an excessively high feedback resistance. Despite of peaking and 15% overshoot. Doubling C and reducing the F these two issues, the ADA4895-1/ADA4895-2 noise and gain bandwidth by half results in a flat frequency response with bandwidth can provide a significant increase in performance approximately 5% transient overshoot. within certain transimpedance ranges. The output noise over frequency for the preamplifier is shown Figure 55 shows an I/V converter with an electrical model of a in Figure 56. photomultiplier. CF 1 RF f1 =2πRF(CS + CM + CF + CD) 1 f2 =2πRFCF – CM nV/ Hz) f3 = (CS + CM G+ BCPF + CD)/CF IPHOTO CS RSH + CD CM VOUT NOISE( VB GE RF NOISE A T L O CF+CS RF 10186-050 V f f2 ven (CS + CM + CF + CD)/CF f3 Figure 55. Wideband Photomultiplier Preamplifier 1 The basic transfer function is ven NOISE DUETOAMPLIFIER V  IPHOTO  RF FREQUENCY (Hz) 10186-051 OUT 1sC R Figure 56. Photomultiplier Voltage Noise Contributions F F where IPHOTO is the output current of the photomultiplier, and Table 12. RMS Noise Contributions of Photomultiplier the parallel combination of RF and CF sets the signal bandwidth. Preamplifier The stable bandwidth attainable with this preamplifier is a function Contributor Expression of RF, the gain bandwidth product of the amplifier, and the total RF 4kTR f 1.57 F 2 capacitance at the summing junction of the amplifier, including C S   Amplifier ven C C C C and the amplifier input capacitance. ven S M F D  f  1.57 C 3 F Amplifier ien ien RF f21.57 Rev. B | Page 21 of 24

ADA4895-1/ADA4895-2 Data Sheet LAYOUT CONSIDERATIONS Paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided with low ac impedance To ensure optimal performance, careful and deliberate attention across a wide band of frequencies. This is important for minimizing must be paid to the board layout, signal routing, power supply the coupling of noise into the amplifier—especially when the bypassing, and grounding. amplifier PSRR begins to roll off—because the bypass capacitors Ground Plane can help lessen the degradation in PSRR performance. It is important to avoid ground in the areas under and around the Place the smallest value capacitor on the same side of the board input and output of the ADA4895-1/ADA4895-2. Stray capacitance as the amplifier and as close as possible to the amplifier power created between the ground plane and the input and output pads of supply pins. Connect the ground end of the capacitor directly to a device is detrimental to high speed amplifier performance. Stray the ground plane. capacitance at the inverting input, along with the amplifier input It is recommended that a 0.1 µF ceramic capacitor with a 0508 case capacitance, lowers the phase margin and can cause instability. size be used. The 0508 case size offers low series inductance and Stray capacitance at the output creates a pole in the feedback excellent high frequency performance. Place a 10 µF electrolytic loop, which can reduce phase margin and can cause the circuit capacitor in parallel with the 0.1 µF capacitor. Depending on the to become unstable. circuit parameters, some enhancement to performance can be Power Supply Bypassing realized by adding additional capacitors. Each circuit is different Power supply bypassing is a critical aspect in the performance and should be analyzed individually for optimal performance. of the ADA4895-1/ADA4895-2. A parallel connection of capacitors from each power supply pin to ground works best. Smaller value capacitor electrolytics offer better high frequency response, whereas larger value capacitor electrolytics offer better low frequency performance. Rev. B | Page 22 of 24

Data Sheet ADA4895-1/ADA4895-2 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 57. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 01..2407((00..00515007)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA R(CINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 58. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. B | Page 23 of 24

ADA4895-1/ADA4895-2 Data Sheet 3.00 2.90 2.80 1.70 6 5 4 3.00 1.60 2.80 1.50 2.60 1 2 3 PIN1 INDICATOR 0.95BSC 1.90 BSC 1.30 1.15 0.90 1.45MAX 0.20MAX 0.95MIN 0.08MIN 0.55 0.15MAX 10° 0.45 0.05MIN 0.50MAX SPELAATNIENG 4° B0S.6C0 0.35 0.30MIN 0° COMPLIANTTOJEDECSTANDARDSMO-178-AB 12-16-2008-A Figure 59. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters ORDERING GUIDE Ordering Model1 Temperature Range Package Description Package Option Quantity Branding ADA4895-1ARZ −40°C to +125°C 8-Lead SOIC_N R-8 98 ADA4895-1ARZ-R7 −40°C to +125°C 8-Lead SOIC_N R-8 1,000 ADA4895-1ARZ-RL −40°C to +125°C 8-Lead SOIC_N R-8 2,500 ADA4895-1ARJZ-R2 −40°C to +125°C 6-Lead SOT-23 RJ-6 250 H3D ADA4895-1ARJZ-R7 −40°C to +125°C 6-Lead SOT-23 RJ-6 3,000 H3D ADA4895-1AR-EBZ Evaluation Board for the 8-Lead SOIC_N ADA4895-1ARJ-EBZ Evaluation Board for the 6-Lead SOT-23 ADA4895-2ARMZ −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 50 H35 ADA4895-2ARMZ-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 1,000 H35 ADA4895-2ARMZ-RL −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 3,000 H35 ADA4895-2ARM-EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10186-0-4/15(B) Rev. B | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADA4895-1ARJZ-R7 ADA4895-1ARJZ-RL ADA4895-1ARZ ADA4895-1ARZ-R7 ADA4895-1ARZ-RL ADA4895- 2ARMZ ADA4895-2ARMZ-R7 ADA4895-2ARMZ-RL ADA4895-1ARJZ-R2