Low Noise, Precision, Rail-to-Rail Output, JFET Single/Dual/Quad Op Amps Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 FEATURES PIN CONFIGURATION Low offset voltage OUT A 1 8 V+ B grade: 0.4 mV maximum (ADA4610-1/ADA4610-2 only) –IN A 2 ADA4610-2 7 OUT B TOP VIEW LoABw ggorrfaafsddeeet:: v41o µmltVaV/g °mCe amdxraiimfxti ummu m (ADA4610-1/ADA4610-2 only) +INV A– 34 (Not to Scale) 65 –+IINN BB 09646-002 Figure 1. ADA4610-2 8-Lead SOIC (R Suffix); for Additional Packages and A grade: 8 µV/°C maximum (SOIC, MSOP, LFCSP packages) Models, See the Pin Configurations and Function Descriptions Section Low input bias current: 5 pA typical Dual-supply operation: ±5 V to ±15 V Low voltage noise: 0.45 µV p-p at 0.1 Hz to 10 Hz Voltage noise density: 7.30 nV/√Hz at f = 1 kHz Low THD + N: 0.00025% No phase reversal Rail-to-rail output Unity-gain stable Long-term offset voltage drift (10,000 hours): 5 µV typical Temperature hysteresis: 8 µV typical APPLICATIONS Instrumentation Medical instruments Multipole filters Precision current measurement Photodiode amplifiers Sensors Audio GENERAL DESCRIPTION The ADA4610-1/ADA4610-2/ADA4610-4 are precision junction performance filters. Low input bias currents, low offset, and low field effect transistor (JFET) amplifiers that feature low input noise noise result in a wide dynamic range for photodiode amplifier voltage, current noise, offset voltage, input bias current, and rail-to- circuits. Low noise and distortion, high output current, and rail output. The ADA4610-1 is a single amplifier, the ADA4610-2 is excellent speed make the ADA4610-1/ADA4610-2/ADA4610-4 a dual amplifier, and the ADA4610-4 is a quad amplifier. great choices for audio applications. The combination of low offset, noise, and very low input bias The ADA4610-1/ADA4610-2/ADA4610-4 are specified over current makes these amplifiers especially suitable for high the −40°C to +125°C extended industrial temperature range. impedance sensor amplification and precise current measurements The ADA4610-1 is available in an 8-lead SOIC package and in a using shunts. With excellent dc precision, low noise, and fast 5-lead SOT-23 package. The ADA4610-2 is available in 8-lead settling time, the ADA4610-1/ADA4610-2/ADA4610-4 provide SOIC, 8-lead MSOP, and 8-lead LFCSP packages. The ADA4610-4 superior accuracy in medical instruments, electronic measurement, is available in a 14-lead SOIC package and in a 16-lead LFCSP. and automated test equipment. Unlike many competitive amplifiers, the ADA4610-1/ADA4610-2/ADA4610-4 maintain Table 1. Related Precision JFET Operational Amplifiers fast settling performance with substantial capacitive loads. Unlike Single Dual Quad many older JFET amplifiers, the ADA4610-1/ADA4610-2/ AD8510 AD8512 AD8513 ADA4610-4 do not suffer from output phase reversal when input AD8610 AD8620 Not applicable voltages exceed the maximum common-mode voltage range. AD820 AD822 AD824 ADA4627-1/ADA4637-1 Not applicable Not applicable The fast slew rate and great stability with capacitive loads make Not applicable ADA4001-2 Not applicable the ADA4610-1/ADA4610-2/ADA4610-4 ideal for high Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Comparative Voltage and Variable Voltage Graphs ............... 17 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 20 Pin Configuration ............................................................................. 1 Applications Information .............................................................. 21 General Description ......................................................................... 1 Input Overvoltage Protection ................................................... 21 Revision History ............................................................................... 3 Peak Detector .............................................................................. 21 Specifications ..................................................................................... 4 Current to Voltage (I to V) Conversion Applications ........... 21 Electrical Characteristics ............................................................. 5 Comparator Operation .............................................................. 22 Absolute Maximum Ratings ............................................................ 7 Long-Term Drift ......................................................................... 23 Thermal Resistance ...................................................................... 7 Temperature Hysteresis ............................................................. 23 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 24 Pin Configurations and Function Descriptions ........................... 8 Ordering Guide .......................................................................... 27 Typical Performance Characteristics ........................................... 11 Rev. H | Page 2 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 REVISION HISTORY 5/2017—Rev. G to Rev. H 11/2014—Rev. C to Rev. D Changed CP-8-21 to CP-8-11 ...................................... Throughout Change to Figure 56 ........................................................................ 19 Changes to Features Section ............................................................ 1 Changes to Figure 15 Caption, Figure 16 Caption, Figure 18 5/2014—Rev. B to Rev. C Caption, and Figure 19 Caption .................................................... 12 Added ADA4610-4 and 14-Lead SOIC ........................... Universal Changed Functional Description Section to Theory of Added Voltage Noise Density to Features Section, Figure 3, and Operation Section ........................................................................... 20 Table 1; Renumbered Sequentially .................................................. 1 Added Long-Term Drift Section, Temperature Hysteresis Section, Changes to Table 2 ............................................................................ 3 Figure 61, Figure 62, and Figure 63; Renumbered Sequentially ..... 23 Changes to Table 3 ............................................................................ 4 Updated Outline Dimensions ........................................................ 24 Changes to Table 4 ............................................................................ 6 Changes to Ordering Guide ........................................................... 27 Added Pin Configurations and Function Descriptions Section, Figure 4 to Figure 6, Table 6, and Table 7 ....................... 7 5/2016—Rev. F to Rev. G Changes to Typical Performance Characteristics Section ........... 8 Changed CP-8-20 to CP-8-21 ...................................... Throughout Added Functional Description Section ........................................ 17 Changes to Figure 23 Caption and Figure 26 Caption ............... 13 Added Input Overvoltage Protection Section, Peak Detector Updated Outline Dimensions ........................................................ 24 Section, I to V Conversion Applications Section, and Changes to Ordering Guide ........................................................... 25 Photodiode Circuits Section .......................................................... 18 Change to Figure 56 ........................................................................ 18 1/2016—Rev. E to Rev. F Added Figure 62, Outline Dimensions ........................................ 20 Added 5-Lead SOT-23 ....................................................... Universal Changes to Ordering Guide ........................................................... 20 Changed CP-8-9 to CP-8-20 ........................................ Throughout Change to Features Section .............................................................. 1 8/2012—Rev. A to Rev. B Added Figure 3 and Table 7; Renumbered Sequentially .............. 8 Changes to Figure 9 .......................................................................... 8 Updated Outline Dimensions ........................................................ 23 Changes to Ordering Guide ........................................................... 25 5/2012—Rev. 0 to Rev. A Changes to Data Sheet Title and General Description Section .. 1 4/2015—Rev. D to Rev. E Changed Input Impedance Parameter, Differential to Input Added ADA4610-1 ............................................................ Universal Capacitance Parameter, and Differential Parameter, Table 1 ...... 3 Added 16-Lead LFCSP_WQ ............................................. Universal Added Input Resistance in Table 1.................................................. 3 Deleted Figure 1 and Figure 3; Renumbered Sequentially .......... 1 Changed Input Impedance, Differential Parameter to Input Changes to Features Section ............................................................ 1 Capacitance, Differential Parameter, Table 2 ................................ 4 Changes to Table 2 ............................................................................ 4 Added Input Resistance Parameter, Table 2 .................................. 4 Changes to Table 3 ............................................................................. 5 Added Figure 9, Figure 10, and Figure 14; Renumbered Added Figure 2 and Table 6; Renumbered Sequentially .............. 7 Sequentially ........................................................................................ 8 Added Figure 4 .................................................................................. 8 Added Figure 15 ................................................................................ 9 Added Figure 7 .................................................................................. 9 Updated Outline Dimensions........................................................ 16 Changes to Table 8 ............................................................................ 9 Changes to Ordering Guide ........................................................... 17 Changes to Figure 10 Caption and Figure 13 Caption ............... 10 Changes to Figure 14 Caption, Figure 15, Figure 17 Caption, 12/2011—Revision 0: Initial Version and Figure 18 ...................................................................................1 1 Changes to Figure 22 and Figure 25 ............................................. 12 Changes to Figure 26 to Figure 31 ................................................ 13 Changes to Figure 32 and Figure 35 ............................................. 14 Changes to Figure 38 and Figure 40 ............................................. 15 Changes to Figure 42 to Figure 46 ................................................ 16 Changes to Figure 48, Figure 50, and Figure 53 .......................... 17 Changes to Figure 54 and Figure 55 ............................................. 18 Changes to Figure 57 and Figure 58 ............................................. 20 Updated Outline Dimensions ........................................................ 22 Added Figure 64 .............................................................................. 23 Changes to Ordering Guide ........................................................... 24 Rev. H | Page 3 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet SPECIFICATIONS V = ±5 V, V = 0 V, T = 25°C, unless otherwise noted. SY CM A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS B Grade (ADA4610-1/ADA4610-2) 0.2 0.4 mV −40°C < T < +125°C 0.8 mV A A Grade 0.4 1 mV −40°C < T < +125°C 1.8 mV A Offset Voltage Drift ΔV /ΔT OS B Grade (ADA4610-1/ADA4610-2)1 0.5 4 µV/°C A Grade1 (SOIC, MSOP, LFCSP) 1 8 µV/°C A Grade1 (SOT-23) 1 12 µV/°C Input Bias Current I 5 25 pA B −40°C < T < +125°C 1.5 nA A Input Offset Current I 2 20 pA OS −40°C < T < +125°C 0.25 nA A Input Voltage Range −2.5 +2.5 V Common-Mode Rejection Ratio CMRR V = −2.5 V to +2.5 V 94 110 dB CM −40°C < T < +125°C 86 dB A Large Signal Voltage Gain A R = 2 kΩ, V = −3.5 V to +3.5 V VO L OUT ADA4610-2 98 100 dB −40°C < T < +125°C 86 dB A ADA4610-1/ADA4610-4 96 98 dB −40°C < T < +125°C 84 dB A Input Capacitance V = 0 V CM Differential 3.1 pF Common-Mode 4.8 pF Input Resistance V = 0 V >1013 Ω CM OUTPUT CHARACTERISTICS Output Voltage High V R = 2 kΩ 4.85 4.90 V OH L −40°C < T < +125°C 4.60 V A R = 600 Ω 4.60 4.89 V L −40°C < T < +125°C 4.05 V A Output Voltage Low V R = 2 kΩ −4.95 −4.90 V OL L −40°C < T < +125°C −4.75 V A R = 600 Ω −4.90 −4.80 V L −40°C < T < +125°C −4.40 V A Short-Circuit Current I ±63 mA SC POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V SY ADA4610-2 106 125 dB −40°C < T < +125°C 103 dB A ADA4610-1/ADA4610-4 104 117 dB −40°C < T < +125°C 100 dB A Supply Current per Amplifier I I = 0 mA 1.50 1.70 mA SY OUT −40°C < T < +125°C 1.85 mA A Rev. H | Page 4 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 Parameter Symbol Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Slew Rate ±SR R = 2 kΩ, A = 1 L V Rising 151 21 V/µs Falling 151 46 V/µs Gain Bandwidth Product GBP V = 5 mV p-p, R = 2 kΩ, A = 100 15.4 MHz IN L V Unity-Gain Crossover UGC V = 5 mV p-p, R = 2 kΩ, A = 1 9.3 MHz IN L V Phase Margin φ 61 Degrees M −3 dB Closed-Loop Bandwidth −3 dB A = 1, V = 5 mV p-p 10.6 MHz V IN Total Harmonic Distortion + Noise THD + N 1 kHz, A = 1, R = 2 kΩ, V = 1 V rms 0.00025 % V L IN NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.45 µV p-p n Voltage Noise Density e f = 10 Hz 14 nV/√Hz n f = 100 Hz 8.20 nV/√Hz f = 1 kHz 7.30 nV/√Hz f = 10 kHz 7.30 nV/√Hz 1 Guaranteed by design and characterization. ELECTRICAL CHARACTERISTICS V = ±15 V, V = 0 V, T = 25°C, unless otherwise noted. SY CM A Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS B Grade (ADA4610-1/ADA4610-2) 0.2 0.4 mV −40°C < T < +125°C 0.8 mV A A Grade 0.4 1 mV −40°C < T < +125°C 1.8 mV A Offset Voltage Drift ΔV /ΔT OS B Grade (ADA4610-1/ADA4610-2)1 0.5 4 µV/°C A Grade1 (SOIC, MSOP, LFCSP) 1 8 µV/°C A Grade1 (SOT-23) 1 12 µV/°C Input Bias Current I 5 25 pA B −40°C < T < +125°C 1.50 nA A Input Offset Current I 2 20 pA OS −40°C < T < +125°C 0.25 nA A Input Voltage Range −12.5 +12.5 V Common-Mode Rejection Ratio CMRR V = −12.5 V to +12.5 V 100 115 dB CM −40°C < T < +125°C 96 dB A Large Signal Voltage Gain A R = 2 kΩ, V = ±13.5 V VO L OUT ADA4610-2 104 107 dB −40°C < T < +125°C 91 dB A ADA4610-1/ADA4610-4 102 104 dB −40°C < T < +125°C 86 dB A Input Capacitance V = 0 V CM Differential 3.1 pF Common-Mode 4.8 pF Input Resistance V = 0 V >1013 Ω CM Rev. H | Page 5 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage High V R = 2 kΩ 14.80 14.90 V OH L −40°C < T < +125°C 14.65 V A R = 600 Ω 14.25 14.47 V L −40°C < T < +125°C 13.35 V A Output Voltage Low V R = 2 kΩ −14.90 −14.85 V OL L −40°C < T < +125°C −14.75 V A R = 600 Ω −14.68 −14.60 V L −40°C < T < +125°C −14.30 V A Short-Circuit Current I ±79 mA SC POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V SY ADA4610-2 106 125 dB −40°C < T < +125°C 103 dB A ADA4610-1/ADA4610-4 104 117 dB −40°C < T < +125°C 100 dB A Supply Current per Amplifier I I = 0 mA 1.60 1.85 mA SY OUT −40°C < T < +125°C 2.0 mA A DYNAMIC PERFORMANCE Slew Rate ±SR R = 2 kΩ, A = +1 L V Rising 171 25 V/µs Falling 171 61 V/µs Gain Bandwidth Product GBP V = 5 mV p-p, R = 2 kΩ, A = 100 16.3 MHz IN L V Unity-Gain Crossover UGC V = 5 mV p-p, R = 2 kΩ, A = 1 9.3 MHz IN L V Phase Margin φ 66 Degrees M −3 dB Closed-Loop Bandwidth −3 dB A = 1, V = 5 mV p-p 9.5 MHz V IN Total Harmonic Distortion + Noise THD + N 1 kHz, A = 1, R = 2 kΩ, V = 5 V rms 0.00025 % V L IN NOISE PERFORMANCE Peak-to-Peak Voltage Noise e p-p 0.1 Hz to 10 Hz bandwidth 0.45 µV p-p n Voltage Noise Density e f = 10 Hz 14 nV/√Hz n f = 100 Hz 8.50 nV/√Hz f = 1 kHz 7.30 nV/√Hz f = 10 kHz 7.30 nV/√Hz 1 Guaranteed by design and characterization. Rev. H | Page 6 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating Table 5. Thermal Resistance Supply Voltage ±18 V Package Type θ 1 θ Unit JA JC Input Voltage ±V S 5-Lead SOT-23 219.4 155.6 °C/W Input Current1 ±10 mA 8-Lead SOIC 120 43 °C/W Storage Temperature Range −65°C to +150°C 8-Lead LFCSP 57 12 °C/W Operating Temperature Range −40°C to +125°C 8-Lead MSOP 142 45 °C/W Junction Temperature Range −65°C to +150°C 14-Lead SOIC 115 36 °C/W Lead Temperature (Soldering, 10 sec) 300°C 16-Lead LFCSP 65 3.2 °C/W Electrostatic Discharge (ESD) Human Body Model (HBM)2 2500 V 1 θJA is specified for worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for surface-mount packages. Field Induced Charge Device Model (FICDM)3 1250 V 1 The input pins have clamp diodes connected to the power supply pins. Limit the input current to 10 mA or less whenever input signals exceed the power ESD CAUTION supply rail by 0.3 V. 2 ESDA/JEDEC JS-001-2011 applicable standard. 3 JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. H | Page 7 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NIC 1 8 NIC –IN 2 ADA4610-1 7 V+ +IN 3 TOP VIEW 6 OUT (Not to Scale) V– 4 5 NIC N1.O NTIECS = NOT INTERNALLY CONNECTED. 09646-101 Figure 2. ADA4610-1 Pin Configuration, 8-Lead SOIC (R Suffix) Table 6. ADA4610-1 Pin Function Descriptions, 8-Lead SOIC Pin No. Mnemonic Description 1, 5, 8 NIC Not Internally Connected. 2 −IN Inverting Input. 3 +IN Noninverting Input. 4 V− Negative Supply Voltage. 6 OUT Output. 7 V+ Positive Supply Voltage. OUT 1 5 V+ ADA4610-1 V– 2 TOP VIEW (Not to Scale) +IN 3 4 –IN 09646-100 Figure 3. ADA4610-1 Pin Configuration, 5-Lead SOT-23 (RJ Suffix) Table 7. ADA4610-1 Pin Function Descriptions, 5-Lead SOT-23 Pin No. Mnemonic Description 1 OUT Output. 2 V− Negative Supply Voltage. 3 +IN Noninverting Input. 4 −IN Inverting Input. 5 V+ Positive Supply Voltage. Rev. H | Page 8 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 OUT A 1 8 V+ ADA4610-2 –IN A 2 7 OUT B TOP VIEW +INV A– 34 (Not to Scale) 65 –+IINN BB 09646-104 Figure 4. ADA4610-2 Pin Configuration, 8-Lead SOIC (R Suffix) OUT A 1 8 V+ –IN A 2 ADA4610-2 7 OUT B TOP VIEW +IN A 3 (Not to Scale) 6 –IN B V– 4 5 +IN B 09646-102 Figure 5. ADA4610-2 Pin Configuration, 8-Lead MSOP (RM Suffix) OUT A 1 8 V+ –IN A 2 ADA4610-2 7 OUT B +IN A 3 TOP VIEW 6 –IN B (Not to Scale) V– 4 5 +IN B N1 . O TCTHOEENS NEEXCPOTESDEDTOPA VD– .MUST BE 09646-105 Figure 6. ADA4610-2 Pin Configuration, 8-Lead LFCSP (CP Suffix) Table 8. ADA4610-2 Pin Function Descriptions, 8-Lead SOIC, 8-Lead MSOP, and 8-Lead LFCSP Pin No. Mnemonic Description 1 OUT A Output Channel A. 2 −IN A Inverting Input Channel A. 3 +IN A Noninverting Input Channel A. 4 V− Negative Supply Voltage. 5 +IN B Noninverting Input Channel B. 6 −IN B Inverting Input Channel B. 7 OUT B Output Channel B. 8 V+ Positive Supply Voltage. EPAD Exposed Pad for the 8-Lead LFCSP (CP Suffix). The exposed pad must be connected to V−. Rev. H | Page 9 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet A D CIN TUO T UO CIN 6 5 4 3 1 1 1 1 –IN A 1 12 –IN D +IN A 2 ADA4610-4 11 +IN D OUT A 1 14 OUT D V+ 3 VTIOEWP 10 V– –IN A 2 13 –IN D +IN B 4 9 +IN C +IN A 3 ADA4610-4 12 +IN D V+ 4 TOP VIEW 11 V– 5 6 7 8 +IN B 5 (Not to Scale) 10 +IN C BN B T C T C N O–UINT BB 67 98 –OIUNT C C 09646-106 N12..OTNHTICEE S =E XNPOOTS IENDT EPRAND–IA MLLUUOYS TC UOOBEN NI–CEOCNTNEEDC.TED TO V–. 09646-107 Figure 7. ADA4610-4 Pin Configuration, 14-Lead SOIC (R Suffix) Figure 8. ADA4610-4 Pin Configuration, 16-Lead LFCSP (CP Suffix) Table 9. ADA4610-4 Pin Function Descriptions, 14-Lead SOIC and 16-Lead LFCSP Pin No. 14-Lead SOIC 16-Lead LFCSP Mnemonic Description 1 15 OUT A Output Channel A. 2 1 −IN A Inverting Input Channel A. 3 2 +IN A Noninverting Input Channel A. 4 3 V+ Positive Supply Voltage. 5 4 +IN B Noninverting Input Channel B. 6 5 −IN B Inverting Input Channel B. 7 6 OUT B Output Channel B. 8 7 OUT C Output Channel C. 9 8 −IN C Inverting Input Channel C. 10 9 +IN C Noninverting Input Channel C. 11 10 V− Negative Supply Voltage. 12 11 +IN D Noninverting Input Channel D. 13 12 −IN D Inverting Input Channel D. 14 14 OUT D Output Channel D. Not applicable 13, 16 NIC Not Internally Connected. Not applicable EPAD Exposed Pad. The exposed pad must be connected to V−. Rev. H | Page 10 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A 400 400 SOIC SOIC 350 350 300 300 S S L L E E N N N250 N250 A A H H C C F 200 F 200 O O R R BE150 BE150 M M U U N100 N100 50 50 –01000–800 –600 –400O–F2F0S0ET 0VOL2T0A0GE4 0(µ0V)600 800 1000 120009646-003 –01000–800 –600 –400O–F2F0S0ET 0VOL2T0A0GE4 0(µ0V)600 800 1000 120009646-006 Figure 9. Input Offset Voltage Distribution, VSY = ±5 V Figure 12. Input Offset Voltage Distribution, VSY = ±15 V 350 350 SOIC SOIC 300 300 LS250 LS250 E E N N N N HA200 HA200 C C F F O O R 150 R 150 E E B B M M NU100 NU100 50 50 0 00.51.01.52.02.53.03.54.0TC4.5VO5.0S (5.5µV/6.0°C)6.57.07.58.08.59.09.510.010.5 09646-004 0 00.51.01.52.02.53.03.54.0TC4.5VO5.0S (5.5µV/6.0°C)6.57.07.58.08.59.09.510.010.5 09646-007 Figure 10. Input Offset Voltage Drift (TCVOS) Distribution, VSY = ±5 V Figure 13. TCVOS Distribution, VSY = ±15 V 1500 1500 1000 1000 V) V) E (µ E (u G 500 G 500 A A OLT OLT V V T 0 T 0 E E S S F F F F O O T –500 T –500 U U INP MMEEAANN + 3σ INP MMEEAANN + 3σ –1000 MEAN – 3σ –1000 MEAN – 3σ –1500–5 –4 –3 –2 –1 VCM0 (V) 1 2 3 4 5 09646-005 –1500–15 –10 –5 VCM0 (V) 5 10 15 09646-008 Figure 11. Input Offset Voltage vs. Common-Mode Input Voltage (VCM), Figure 14. Input Offset Voltage vs. Input Common-Mode Voltage (VCM), VSY = ±5 V, RL = ∞ VSY = ±15 V, RL = ∞ Rev. H | Page 11 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet 50 50 40 40 30 30 A) A) T (p 20 T (p 20 N N RE 10 RE 10 R R U U C 0 C 0 S S A A BI–10 BI –10 MEAN T MEAN T MEAN + 3σ PU–20 MEAN + 3σ PU –20 MEAN – 3σ N MEAN – 3σ N I I –30 –30 –40 –40 –50–5 –4 –3 –2 –1 VCM0 (V) 1 2 3 4 5 09646-055 –50–15 –10 –5 VCM0 (V) 5 10 15 09646-057 Figure 15. Input Bias Current vs. Common-Mode Input Voltage (VCM), Figure 18. Input Bias Current vs. Common-Mode Input Voltage (VCM), Mean and Three Standard Deviations, VSY = ±5 V, RL = ∞ Mean and Three Standard Deviations, VSY = ±15 V, RL = ∞ 100k 100k SOIC SOIC 10k 10k A) A) NT (p 1k +125°C NT (p 1k E E RR 100 RR +125°C CU CU 100 AS 10 AS BI +25°C BI UT UT 10 NP 1 NP +25°C I –40°C I 1 0.1 –40°C 0.01–5 –4 –3 –2 –1 VCM0(V) 1 2 3 4 5 09646-056 0.1–15 –10 –5 VCM0(V) 5 10 15 09646-058 Figure 16. Input Bias Current vs. Common-Mode Input Voltage (VCM), Figure 19. Input Bias Current vs. Common-Mode Input Voltage (VCM), Three Temperatures, VSY = ±5 V, RL = ∞ Three Temperatures, VSY = ±15 V, RL = ∞ 100 100 A) A) p p NT ( 10 NT ( 10 E E R R R R U U C C S S A A BI BI UT 1 UT 1 P P N N I I 0.1–50 –25 0 TEMP25ERATUR5E0 (°C) 75 100 12509646-009 0.1–50 –25 0 TEMP25ERATUR5E0 (°C) 75 100 12509646-012 Figure 17. Input Bias Current vs. Temperature, VSY = ±5 V Figure 20. Input Bias Current vs. Temperature, VSY = ±15 V Rev. H | Page 12 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 1 1 (V+ – V) (V)OUT0.1 (V+ – V) (V)OUT0.1 0.010.1 1IOUT SOURCE (mA)10 100 09646-011 00..00110.1 1IOUT SOURCE (mA)10 100 09646-014 Figure 21. Dropout Voltage (V+ − VOUT) vs. IOUT Source, VSY = ±5 V Figure 24. Dropout Voltage (V+ − VOUT) vs. IOUT Source, VSY = ±15 V 10 10 V–) (V) 1 V–) (V) 1 UT – UT – O O V V ( ( 0.1 0.1 0.010.1 1 IOUT SINK (mA) 10 100 09646-015 0.001.01 0.1 IOUT SIN1K (mA) 10 10009646-018 Figure 22. Dropout Voltage (VOUT − V−) vs. IOUT Sink, VSY = ±5 V Figure 25. Dropout Voltage (VOUT − V−) vs. IOUT Sink, VSY = ±15 V 120 270 120 270 100 GAIN 225 100 GAIN 225 80 180 80 180 GAIN (dB) 642000 PHASE 1943055 HASE (Degrees) GAIN (dB) 642000 PHASE 1943055 HASE (Degrees) P P 0 0 0 0 –20 –45 –20 –45 –4010 100 1k FR1E0QkUENC1Y0 0(Hkz) 1M 10M 100–M90 09646-016 –4010 100 1k FR1E0QkUENC1Y0 0(Hkz) 1M 10M 100–M90 09646-019 Figure 23. Open-Loop Gain and Phase Margin vs. Frequency, Figure 26. Open-Loop Gain and Phase Margin vs. Frequency, VSY = ±5 V, RL = 2 kΩ, VIN = 5 mV VSY = ±15 V, RL = 2 kΩ, VIN = 5 mV Rev. H | Page 13 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet 60 60 AV = +100 AV = +100 40 40 AV = +10 AV = +10 B) 20 B) 20 d d N ( N ( AI AV = +1 AI AV = +1 G 0 G 0 –20 –20 –401k 10k F1R00EkQUENCY 1(HMz) 10M 100M09646-017 –401k 10k F1R00EkQUENCY 1(HMz) 10M 100M09646-020 Figure 27. Closed-Loop Gain vs. Frequency, VSY = ±5 V Figure 30. Closed-Loop Gain vs. Frequency, VSY = ±15 V 1k 1k 100 100 10 10 (Ω)UT AV = +100 (Ω)UT AV = +100 O O Z Z 1 1 AV = +10 AV = +10 0.1 0.1 AV = +1 AV = +1 0.01100 1k 10kFREQU1E0N0kCY (Hz)1M 10M 100M09646-021 0.01100 1k 10kFREQU1E0N0kCY (Hz)1M 10M 100M09646-024 Figure 28. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V Figure 31. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V 120 120 100 100 80 80 PSRR– PSRR– B) 60 B) 60 d d R ( R ( R R PS 40 PS 40 PSRR+ PSRR+ 20 20 0 0 –20100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M09646-022 –20100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 09646-025 Figure 29. PSRR vs. Frequency, VSY = ±5 V Figure 32. PSRR vs. Frequency, VSY = ±15 V Rev. H | Page 14 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 140 140 120 120 100 100 dB) 80 dB) 80 R ( R ( R R M 60 M 60 C C 40 40 20 20 0100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M09646-023 0100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M09646-026 Figure 33. CMRR vs. Frequency, VSY = ±5 V Figure 36. CMRR vs. Frequency, VSY = ±15 V 3 12 2 8 V) V) E ( 1 E ( 4 G G A A T T L L O 0 O 0 V V T T U U P P UT–1 UT –4 O O –2 –8 –30 1 2 3 4TIME5 (µs)6 7 8 9 1009646-027 –120 1 2 3 4TIME5 (µs)6 7 8 9 1009646-030 Figure 34. Large Signal Transient Response, VSY = ±5 V, AV = 1, Figure 37. Large Signal Transient Response, VSY = ±15 V, AV = 1, RL = 2 kΩ, CL = 100 pF RL = 2 kΩ, CL = 100 pF 75 75 50 50 E (mV) 25 E (mV) 25 G G A A OLT 0 OLT 0 V V UT UT UTP–25 UTP–25 O O –50 –50 –750 1 2 3 4TIME5 (µs)6 7 8 9 1009646-028 –750 1 2 3 4TIME5 (µs)6 7 8 9 1009646-031 Figure 35. Small Signal Transient Response, VSY = ±5 V, AV = 1, Figure 38. Small Signal Transient Response, VSY = ±15 V, AV = 1, RL = 2 kΩ, CL = 100 pF RL = 2 kΩ, CL = 100 pF Rev. H | Page 15 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet 100 100 Hz) Hz) V/ V/ n n Y ( Y ( T T SI SI N N E E E D 10 E D 10 S S OI OI N N E E G G A A T T L L O O V V 11 10 F1R0E0QUENCY (1Hkz) 10k 100k 09646-033 11 10 FR1E0Q0UENCY (Hz1)k 10k 09646-036 Figure 39. Voltage Noise Density vs. Frequency, VSY = ±5 V Figure 41. Voltage Noise Density vs. Frequency, VSY = ±15 V 50 50 40 40 OS+ %) %) OS+ T (30 T ( 30 O O O O H H S S R OS– R E20 E 20 V V O O OS– 10 10 00.01 LOAD0 C.1APACITANCE (nF) 1 09646-034 00.01 LOAD0 C.1APACITANCE (nF) 1 09646-037 Figure 40. Overshoot vs. Load Capacitance, VSY = ±5 V, AV = 1, Figure 42. Overshoot vs. Load Capacitance, VSY = ±15 V, AV = 1, RL = 2 kΩ, VIN = 100 mV p-p RL = 2 kΩ, VIN = 100 mV p-p Rev. H | Page 16 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPHS 10 10 VSY = ±5V VSY = ±15V RL = 2kΩ RL = 2kΩ 1 8fI0Nk =H z1 kFHILzTER 1 f8I0Nk =H z1 kFHILzTER 0.1 0.1 %) %) N ( N ( + 0.01 + 0.01 D D H H T T 0.001 0.001 0.0001 0.0001 0.000010.01 AM0P.1LITUDE (V rms) 1 09646-205 0.000001.001 0.01 AMPLITU0D.1E (V rms) 1 10 09646-040 Figure 43. THD + N vs. Amplitude, VSY = ±5 V Figure 46. THD + N vs. Amplitude, VSY = ±15 V 1 VVSINY == 1±.55VV rms 1 VVSINY == 5±V1 5rmVs 0.1 0.1 HD + N (%) 0.01 D + N (%) 0.01 T 0.001 500kHz BAND-PASS FILTER H T 0.001 500kHz BAND-PASS FILTER 0.0001 80kHz BAND-PASS FILTER 0.0001 80kHz BAND-PASS FILTER 0.0000110 100 FREQUE1kNCY (Hz) 10k 100k 09646-204 0.0000110 100 FREQUE1kNCY (Hz) 10k 100k09646-141 Figure 44. THD + N vs. Frequency, VSY = ±5 V Figure 47. THD + N vs. Frequency, VSY = ±15 V –40 16 12 –60 dB) 8 N ( –80 O TI V) 4 RA E ( PA–100 AG 0 E T S L EL VO –4 N–120 N A H –8 C –140 OUTPUT –12 INPUT –160100 1kFREQUENCY (Hz)10k 100k 09646-039 –160 0.1 0.2 0.3 0.4TIM0E. 5(ms)0.6 0.7 0.8 0.9 1.009646-042 Figure 45. Channel Separation vs. Frequency Figure 48. No Phase Reversal, VSY = ±15 V, AV = +1, RL = 2 kΩ, CL = 100 pF Rev. H | Page 17 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet 400 2.0 1.9 1.8 300 1.7 +125°C 1.6 200 A)1.5 +85°C m1.4 LTAGE (nV) 1000 AMPLIFIER (01111.....90123 +–2450°°CC O R0.8 V–100 PE0.7 Y0.6 S –200 I0.5 0.4 0.3 –300 0.2 0.1 –4000 1 2 3 T4IME (S5econd6s) 7 8 9 10 09646-043 00 5 10 15VSY (V)20 25 30 35 09646-047 Figure 49. Voltage Noise, 0.1 Hz to 10 Hz Figure 52. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) at Various Temperatures 12 12 10 10 8 8 SIZE (V) 6 0.1% SIZE (V) 6 0.1% 0.01% EP EP ST 0.01% ST 4 4 2 2 00 0.2 0.4 SETT0.L6ING TIM0.E8 (µs) 1.0 1.2 1.409646-044 00 0.2 0.4 SETT0.L6ING TIM0.E8 (µs) 1.0 1.2 1.409646-045 Figure 50. Positive Step Settling Time Figure 53. Negative Step Settling Time 18 4 16 VOUT VOUT = 7.3 × VIN 2 VOUT = 7.3 × VIN 14 0 12 –2 VIN 10 –4 V (V)OUT 68 V (V)OUT––86 4 –10 2 –12 VIN 0 –14 VOUT –2 –16 –4–0.5 0 0.5 1.T0IME (µ1s.)5 2.0 2.5 3.0 09646-200 –18–0.5 0 0.5 1.T0IME (µ1s.)5 2.0 2.5 3.0 09646-201 Figure 51. Positive Overload Recovery Figure 54. Negative Overload Recovery Rev. H | Page 18 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 3 15 2 VVRACISVLLNY === == 21+ k0±±1Ω052pVVF 10 VIN VVRACSIVLLNY === == 21+ ±k0±11Ω010 5VpVF INPUT 1 5 V) V) E ( E ( VOUT G G A 0 A 0 T T L L VO OUTPUT VO –1 –5 –2 –10 ––30.2 0 0.2 0.4 0.6TIM0E.8 (µs)1.0 1.2 1.4 1.6 1.8 09646-203 –1–52.0 –1.5 –1.0 TIM–0E.5 (µs) 0 0.5 1.0 09646-202 Figure 55. Positive and Negative Slew Rate (VSY = ±5 V, AV = 1, RL = 2 kΩ) Figure 56. Positive and Negative Slew Rate (VSY = ±15 V, AV = 1, RL = 2 kΩ) Rev. H | Page 19 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet THEORY OF OPERATION The ADA4610-1/ADA4610-2/ADA4610-4 are manufactured The ADA4610-1/ADA4610-2 B grades achieve less than 0.4 mV using the Analog Devices, Inc., iPolar® process, a 36 V dielectrically of offset and 4 µV/°C of offset drift; these characteristics are isolated (DI) process with P-channel JFET technology. The usually associated with very high precision bipolar input amplifiers. unique architecture of the ADA4610-1/ADA4610-2/ADA4610-4 The gate current of a typical JFET doubles every 10°C, resulting makes it possible to combine high precision and high speed in a similar increase in input bias current over temperature. The characteristics into a high voltage, low power op amp. A simplified low power consumption characteristic of the ADA4610-1/ schematic for the ADA4610-1/ADA4610-2/ADA4610-4 is ADA4610-2/ADA4610-4 minimizes the die temperature, which shown in Figure 57. The JFET input stage architecture offers warrants low input bias currents even at elevated ambient tem- advantages of low input bias current, high bandwidth, high peratures, making the amplifiers ideal for applications that require gain, low noise, and no phase reversal when the applied input low leakage specifications without active cooling. Ensure proper signal exceeds the common-mode voltage range. The output printed circuit board (PCB) layout to minimize leakage currents stage is rail-to-rail with high drive characteristics and low between PCB traces. Improper layout and board handling can dropout voltage for both sinking and sourcing currents. generate leakage currents exceeding the bias currents of the operational amplifier. The ADA4610-1/ADA4610-2/ADA4610-4 are unconditionally stable for all gain configurations, even with capacitive loads well The ADA4610-1/ADA4610-2/ADA4610-4 are fully specified with in excess of 1 nF. The devices have internal protective circuitry supply voltages from ±5 V to ±15 V over the extended industrial that allows voltages as high as 0.3 V beyond the supplies to be temperature range of −40°C to +125°C. The ADA4610-1 is applied at the input of either terminal without causing damage (for available in an 8-lead SOIC. The ADA4610-2 is available in an higher input voltages, refer to the Input Overvoltage Protection 8-lead MSOP, an 8-lead SOIC, and an 8-lead LFCSP. The section). ADA4610-4 is available in a 14-lead SOIC and a 16-lead LFCSP. All these packages are surface-mount type. V+ D31 R6 R7 C3 Q30 Q29 R16 Q8 Q9 Q28 RC4 C2 + – 1+ Q12 Q18 C4 DE5 A1 Q14 Q15 A2 DE1 R10 R11 Q1 Q5 Q4 Q23 Q13 Q16 Q17 VOUT DE3 R2 R3 VIN+ J1 J2 R5 DE6 VIN– DE4 C1 Q7 Q6 DE2 Q27 R15 I2 I3 Q24 Q25 I4 D26 V– 09646-054 Figure 57. Simplified Schematic Rev. H | Page 20 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 APPLICATIONS INFORMATION INPUT OVERVOLTAGE PROTECTION The ADA4610-1/ADA4610-2/ADA4610-4, shown in Figure 58, are ideal for building a peak detector because U2A requires dc The ADA4610-1/ADA4610-2/ADA4610-4 have internal protective precision and high output current during fast peaks, and U2B circuitry that allows voltages as high as 0.3 V beyond the supplies requires low input bias current (I) to minimize capacitance to be applied at the input of either terminal without causing B discharge between peaks. A low leakage and low dielectric damage. For higher input voltages, a series resistor is necessary absorption capacitor, such as polystyrene or polypropylene, is to limit the input current. Determine the resistor value by required for C3. Reversing the diode directions causes the V −V IN S ≤10mA circuit to detect negative peaks. R S CURRENT TO VOLTAGE (I TO V) CONVERSION where: APPLICATIONS VIN is the input voltage. Photodiode Circuits V is the voltage of either V+ or V−. S Common applications for I to V conversion include photodiode R is the series resistor. S circuits where the amplifier converts a current emitted by a diode With a very low bias current of <1.5 nA up to 125°C, higher placed at the negative input terminal into an output voltage. resistor values can be used in series with the inputs. A 5 kΩ The low input bias current, wide bandwidth, and low noise of resistor protects the inputs from voltages as high as 25 V the ADA4610-1/ADA4610-2/ADA4610-4 make them excellent beyond the supplies and adds less than 10 µV to the offset. choices for various photodiode applications, including fax PEAK DETECTOR machines, fiber optic controls, motion sensors, and barcode The function of a peak detector is to capture the peak value of a readers. signal and produce an output equal to it. By taking advantage of The circuit shown in Figure 59 uses a silicon diode with zero the dc precision and super low input bias current of the JFET input bias voltage. This setup is a photovoltaic mode, which uses amplifiers, such as the ADA4610-1/ADA4610-2/ADA4610-4, a many large photodiodes. This configuration limits the overall highly accurate peak detector can be built, as shown in Figure 58. noise and is suitable for instrumentation applications. VCCADA4610-1/ +PEAK CF 8 ADA4610-2 ADA4610-1/ 3 ADA4610-4 8 ADA4610-2 RF + 2 U2A 1 5 U2BADA4610-4 4 D3 D4 6 7 VEE –VIN 5C0p4F 1N4148 1N4148 C1µ3F 4 VEE 2 4 R7 1/2 D2 10kΩ ADA4610-1/ 1N448 ADA4610-2 1 Figu1rRek6 Ω58. Positive Peak Detector 09646-149 RD CT 3 ADA46810-4 09646-154 VCC In this application, Diode D3 and Diode D4 act as unidirectional Figure 59. Equivalent Preamplifier Photodiode Circuit current switches that open up when the output is kept constant (in hold mode). To detect a positive peak, U2A drives C3 through D3 A larger signal bandwidth can be attained at the expense of and D4 until C3 is charged to a voltage equal to the input peak additional output noise. The total input capacitance (CT) consists of value. Feedback from the output of the U2B + peak through R6 the sum of the diode capacitance (typically 30 pF to 40 pF) and limits the output voltage of U2A. After detecting the peak, the the amplifier input capacitance (<10 pF), which includes external output of U2A swings low but is clamped by D2. Diode D3 parasitic capacitance. CT creates a zero in the frequency response reverses bias and the common node of D3, D4, and R7 is held to a that can lead to an unstable system. To ensure stability and voltage equal to + peak by R7. The voltage across D4 is 0 V; optimize the bandwidth of the signal, place a capacitor in the therefore, its leakage is small. The bias current of U2B is also small. feedback loop of the circuit shown in Figure 59. The capacitor With almost no leakage, C3 has a long hold time. creates a pole and yields a bandwidth with a corner frequency of 1/(2π(RC)) F F where: R is the feedback resistor. F C is the feedback capacitor. F Rev. H | Page 21 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet Determine the R value by the following ratio: COMPARATOR OPERATION F V/ID Although op amps are quite different from comparators, occasionally an unused section of a dual or a quad op amp can where: be used as a comparator; however, this is not recommended for V is the desired output voltage of the op amp. rail-to-rail output op amps. For rail-to-rail output op amps, the I is the diode current. D output stage is generally a ratioed current mirror with bipolar or For example, if I is 100 µA and a 10 V output voltage is needed, D MOSFET transistors. With the device operating in open-loop R must be 100 kΩ. The resistance of the photodiode (R ) is a F D mode, the second stage increases the current drive to the ratioed junction resistance (see Figure 59). mirror to close the loop. However, the second stage cannot close A typical value for RD is 1000 MΩ. Because RD >> RF, the circuit the loop, which results in an increase in supply current. With behavior is not impacted by the effect of the junction resistance. the ADA4610-1/ADA4610-2/ADA4610-4 op amps configured The maximum signal bandwidth (fMAX) is as comparators, the supply current can be significantly higher (see Figure 60 for the supply current vs. the supply voltage for the ft f = ADA4610-4). Configuring an unused section as a voltage follower MAX 2πR C F T with the noninverting input connected to a voltage within the where ft is the unity-gain frequency of the op amp. input voltage range is recommended. The ADA4610-1/ADA4610-2/ ADA4610-4 have a unique output stage design that reduces the Calculate C by F excess supply current but does not entirely eliminate this effect C when the op amp is operating in open-loop mode. C = T F 2πR ft 9 F COMPARATOR, VOUT = HIGH 8 where ft is the unity-gain frequency of the op amp, and achieves a COMPARATOR, VOUT = LOW phase margin, φM, of approximately 45°. mA)7 Increase the CF value to obtain a higher phase margin. Setting ELS (6 CF to twice the previous value yields approximately φM = 65° and a ANN5 FOLLOWER maximal flat frequency response, but it reduces the maximum CH L 4 signal bandwidth by 50%. L A Using the previous parameters with a CF ≈ 7 pF, the signal FORY3 bandwidth is approximately 250 kHz. IS2 1 00 5 10 15 VS2Y0 (V) 25 30 35 40 09646-053 Figure 60. Supply Current (ISY) vs. Supply Voltage (VSY) for the ADA4610-4 Only Rev. H | Page 22 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 LONG-TERM DRIFT TEMPERATURE HYSTERESIS The stability of a precision signal path over its lifetime or In addition to stability over time as described in the Long-Term between calibration procedures is dependent on the long-term Drift section, it is useful to know the temperature hysteresis, stability of the analog components in the path, such as op amps, that is, the stability vs. cycling of temperature. Hysteresis is an references, and data converters. To help system designers important parameter because it tells the system designer how predict the long-term drift of circuits that use the ADA4610-1/ closely the signal returns to its starting amplitude after the ADA4610-2/ADA4610-4, Analog Devices measured the offset ambient temperature changes and subsequent return to room voltage of multiple units for 10,000 hours (more than 13 months) temperature. Figure 62 shows the change in input offset voltage using a high precision measurement system, including an as the temperature cycles three times from room temperature to ultrastable oil bath. To replicate real-world system performance, 125°C to −40°C and back to room temperature. The dotted line the devices under test (DUTs) were soldered onto an FR4 PCB is an initial preconditioning cycle to eliminate the original using a standard reflow profile (as defined in the JEDEC J-STD- temperature-induced offset shift from exposure to production 020D standard), as opposed to testing them in sockets. This solder reflow temperatures. In the three full cycles, the offset manner of testing is important because expansion and hysteresis is typically only 8 µV, or 1% of its 800 µV maximum contraction of the PCB can apply stress to the integrated circuit offset voltage over the full operating temperature range. The (IC) package and contribute to shifts in the offset voltage. histogram in Figure 63 shows that the hysteresis is larger when the device is cycled through only a half cycle, from room The ADA4610-1/ADA4610-2/ADA4610-4 have extremely low temperature to 125°C and back to room temperature. long-term drift, as shown in Figure 61. The red, blue, and green traces show sample units. Note that the ADA4610-1/ 150 PRECONDITION ADA4610-2/ADA4610-4 (B-grade) have a mean drift over VSY = 10V CYCLE 1 CYCLE 2 10,000 hours of approximately 5 µV, or less than 2% of their µV) 100 CYCLE 3 E ( maximum specified offset voltage of 400 µV at room G A temperature. LT 50 O V 60 T MEAN FSE 0 MEAN PLUS ONE STANDARD DEVIATION F O V) 40 MEAN MINUS ONE STANDARD DEVIATION N E (µ GE I –50 G N TA 20 HA OL C–100 V T E 0 E IN OFFS –20 –150–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 09646-062 G Figure 62. Change in Offset Voltage over Three Full Temperature Cycles N CHA –40 SSSAAAMMMPPPLLLEEE 123 2V7S YU =N I1T0SV 5405 V27S YU =N I1T0SV × 3 CYCLES HFUALLLF CCYYCCLLEE TA = 25°C 40 HALF CYCLE = +26°C, +125°C, +26°C 35 FULL CYCLE = +26°C, +125°C, +26°C,–40°C, +26°C –60 0 0 0 0 0 0 0 0 0 0 0 30 00 00 00 00 00 00 00 00 00 00 25 Figure 61. Me1asure2d Lon3g-Term4TI MDEr i(f5Ht oouf rtsh6)e ADA746108-1/AD9A46110,0-209646-061/ F DEVICES21105005 ADA4610-4 Offset Voltage over 10,000 Hours ER O5405 MB40 U35 N30 25 20 15 10 5 –080 –64 –4O8FFS–E3T2 VOL–T1A6GE 0HYST1E6RES3IS2 (µV4)8 64 80 09646-063 Figure 63. Histogram Showing the Temperature Hysteresis of the Offset Voltage over Three Full Cycles and over Three Half Cycles Rev. H | Page 23 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 01..4207((00..00155070)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 64. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 65. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. H | Page 24 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 3.00 2.90 2.80 1.70 5 4 3.00 1.60 2.80 1.50 2.60 1 2 3 0.95BSC 1.90 BSC 1.30 1.15 0.90 1.45MAX 0.20MAX 0.95MIN 0.08MIN 0.55 0.15MAX 10° 0.45 0.05MIN 0.50MAX SPELAATNIENG 5° B0S.6C0 0.35 0.35MIN 0° COMPLIANTTOJEDECSTANDARDSMO-178-AA 11-01-2010-A Figure 66. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters DETAIL A (JEDEC 95) 2.44 3.10 2.34 3.00 SQ 2.24 2.90 0.50 BSC 5 8 PIN 1 INDEX 1.70 AREA EXPPAODSED 1.60 0.50 1.50 0.40 4 11 0.30 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR AREA OPTIONS (SEE DETAIL A) 0.80 0.75 SIDE VIEW 0.05 MAX FTOHER EPXRPOOPSEERD C POANDN, ERCETFIEORN TOOF 0.70 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS SEATING 0.30 0.08 SECTION OF THIS DATA SHEET PKG-005136 PLANE CO00..M2250PLIANTTOJEDEC S0.T2A0N3 DRAERFDS MO-229-W3030D-4 02-10-2017-C Figure 67. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-11) Dimensions shown in millimeters Rev. H | Page 25 of 27

ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINEOFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 68. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) DETAIL A (JEDEC 95) 4.10 0.35 4.00 SQ 0.30 PIN 1 3.90 0.25 INDICATOR PIN 1 0.65 13 16 1 I(NSDEEIC DAETTAOIRL AAR)EA OPTIONS BSC 12 2.25 EXPOSED 2.10 SQ PAD 1.95 9 4 0.70 8 5 0.25 MIN TOP VIEW 0.60 BOTTOM VIEW 0.50 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO 0.70 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.203 REF PKG-004025/5112 COMPLIANTTOJEDEC STANDARDS MO-220-WGGC. 04-15-2016-A Figure 69. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-16-23) Dimensions shown in millimeters Rev. H | Page 26 of 27

Data Sheet ADA4610-1/ADA4610-2/ADA4610-4 ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding ADA4610-1ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-1ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-1ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-1BRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-1BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-1BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-1ARJZ-R2 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A37 ADA4610-1ARJZ-R7 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A37 ADA4610-1ARJZ-RL −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A37 ADA4610-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2U ADA4610-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2U ADA4610-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U ADA4610-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U ADA4610-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U ADA4610-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-2BRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-2BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-2BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4610-4ARZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADA4610-4ARZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADA4610-4ARZ-RL −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADA4610-4ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23 ADA4610-4ACPZ-RL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23 1 Z = RoHS Compliant Part. ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09646-0-5/17(H) Rev. H | Page 27 of 27

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADA4610-2ARMZ ADA4610-2ARZ ADA4610-2BRZ ADA4610-2ACPZ-R7 ADA4610-2ACPZ-RL ADA4610-2ARMZ- R7 ADA4610-2ARMZ-RL ADA4610-2ARZ-R7 ADA4610-2ARZ-RL ADA4610-2BRZ-R7 ADA4610-2BRZ-RL ADA4610-4ARZ ADA4610-4ARZ-R7 ADA4610-4ARZ-RL ADA4610-1ARZ ADA4610-1BRZ ADA4610-1BRZ-RL ADA4610-1ARZ-RL ADA4610-1BRZ-R7 ADA4610-1ARZ-R7 ADA4610-4ACPZ-R7 ADA4610-4ACPZ-RL ADA4610- 1ARJZ-R2 ADA4610-1ARJZ-R7 ADA4610-1ARJZ-RL