Precision, Ultralow Noise, RRIO, Zero-Drift Op Amp Data Sheet ADA4528-1/ADA4528-2 FEATURES PIN CONNECTION DIAGRAMS Low offset voltage: 2.5 µV maximum NIC 1 8 NIC Low offset voltage drift: 0.015 μV/°C maximum –IN 2 ADA4528-1 7 V+ TOP VIEW Low noise +IN 3 (Not to Scale) 6 OUT 5.6 nV/√Hz at f = 1 kHz, A = +100 V– 4 5 NIC V Op9e7n n-lVo opp-p g aatin f := 1 03.01 d HBz mtoi n1i0m Huzm, A V = +100 N1.O NTIECS = NO INTERNAL CONNECTION. 09437-001 CMRR: 135 dB minimum Figure 1. ADA4528-1 Pin Configuration, 8-Lead MSOP PSRR: 130 dB minimum Unity-gain crossover: 4 MHz NIC 1 8 NIC Gain bandwidth product: 3 MHz at AV = +100 –IN 2 ADA4528-1 7 V+ −3 dB closed-loop bandwidth: 6.2 MHz +IN 3 TOP VIEW 6 OUT (Not to Scale) Single-supply operation: 2.2 V to 5.5 V V– 4 5 NIC Dual-supply operation: ±1.1 V to ±2.75 V Rail-to-rail input and output Unity-gain stable N12..O VNCT–IOEC NOS =NR NE LCOET AI NTVTHEEE IR TEN UXAPNLOC COSOENNDNN EPECACTDTE ITDOO.N. 09437-102 APPLICATIONS Figure 2. ADA4528-1 Pin Configuration, 8-Lead LFCSP Thermocouple/thermopile For ADA4528-2 pin connections and for more information about Load cell and bridge transducers the pin connections for these products, see the Pin Configurations Precision instrumentation and Function Descriptions section. Electronic scales 100 Medical instrumentation VSY = 5V Handheld test equipment AV = 1 Hz) VCM = VSY/2 GENERAL DESCRIPTION V/√ n Y ( The ADA4528-1/ADA4528-2 are ultralow noise, zero-drift T SI N operational amplifiers featuring rail-to-rail input and output E swing. With an offset voltage of 2.5 μV, offset voltage drift of SE D 10 OI 0.015 μV/°C, and typical noise of 97 nV p-p (0.1 Hz to 10 Hz, N E G AV = +100), the ADA4528-1/ADA4528-2 are well suited for TA L applications in which error sources cannot be tolerated. VO The ADA4528-1/ADA4528-2 have a wide operating supply range 1 ocaf t2io.2n Vs, wtoh 5i.c5h V m, haikgeh i tg iadinea, la fnodr eaxpcpellilceantito CnMs tRhaRt arenqdu PirSeR pRre scpiseicoifni - 1 10 100 FRE1QkUENCY10 (kHz) 100k 1M 10M 09437-063 amplification of low level signals, such as position and pressure Figure 3. Voltage Noise Density vs. Frequency sensors, strain gages, and medical instrumentation. Table 1. Analog Devices, Inc., Zero-Drift Op Amp Portfolio1 The ADA4528-1/ADA4528-2 are specified over the extended Low 16 V 30 V industrial temperature range (−40°C to +125°C). The ADA4528-1 Ultralow Micropower Power Operating Operating Type Noise (<20 µA) (<1 mA) Voltage Voltage and ADA4528-2 are available in 8-lead MSOP and 8-lead LFCSP Single ADA4528-1 ADA4051-1 AD8628 AD8638 ADA4638-1 packages. AD8538 For more information about the ADA4528-1/ADA4528-2, Dual ADA4528-2 ADA4051-2 AD8629 AD8639 see the AN-1114 Application Note, Lowest Noise Zero-Drift AD8539 Amplifier Has 5.6 nV/√Hz Voltage Noise Density. Quad AD8630 1 See www.analog.com for the latest selection of zero-drift operational amplifiers. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADA4528-1/ADA4528-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................7 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................9 General Description ......................................................................... 1 Applications Information .............................................................. 19 Pin Connection Diagrams ............................................................... 1 Input Protection ......................................................................... 19 Revision History ............................................................................... 2 Rail-to-Rail Input and Output .................................................. 19 Specifications ..................................................................................... 3 Noise Considerations ................................................................. 19 Electrical Characteristics—2.5 V Operation ............................. 3 Comparator Operation .............................................................. 21 Electrical Characteristics—5 V Operation ................................ 4 Printed Circuit Board Layout ................................................... 22 Absolute Maximum Ratings ............................................................ 6 Outline Dimensions ....................................................................... 23 Thermal Resistance ...................................................................... 6 Ordering Guide .......................................................................... 24 ESD Caution .................................................................................. 6 REVISION HISTORY 8/2017—Rev. E to Rev. F Added Pin Connection Diagrams Section and Figure 3; Deleted CP-8-19 .................................................................. Universal Renumbered Sequentially ................................................................ 1 Updated Outline Dimensions ....................................................... 24 Changes to Table 2 ............................................................................. 3 Changes to Ordering Guide .......................................................... 25 Changes to Table 3 ............................................................................. 5 Change to Endnote 1 of Table 4 and Thermal Resistance 6/2017—Rev. D to Rev. E Section .................................................................................................7 Deleted CP-8-12 .................................................................. Universal Added Pin Configurations and Function Descriptions Section, Added CP-8-19 ................................................................... Universal Figure 4, Figure 5, and Table 6 ......................................................... 8 Updated Outline Dimensions ....................................................... 24 Added Figure 6 and Table 7 ............................................................. 9 Changes to Ordering Guide .......................................................... 25 Changes to Input Protection Section ........................................... 19 Changes to Source Resistance Section and 5/2013—Rev. C to Rev. D Caption of Figure 63 ...................................................................... 20 Added 8-Lead LFCSP Package (CP-8-11) ....................... Universal Changes to Residual Voltage Ripple Section and Changes to Table 5 ............................................................................ 7 Caption of Figure 64 ...................................................................... 21 Added Figure 7, Renumbered Sequentially .................................. 8 Changes to Ordering Guide .......................................................... 22 Added Figure 62 and Figure 63 .................................................... 19 Changes to Comparator Operation Section, Figure 68, 9/2011—Rev. 0 to Rev. A Figure 69, Figure 70, and Figure 71 .............................................. 21 Added 8-Lead LFCSP_WD Package ................................ Universal Changes to Figure 72 ...................................................................... 22 Changes to General Description Section ...................................... 1 Added Figure 76 .............................................................................. 24 Added Figure 2; Renumbered Sequentially ................................... 1 Changes to Offset Voltage, Offset Voltage Drift, Power Supply 9/2012—Rev. B to Rev. C Rejection Ratio, and Settling Time to 0.1% Parameters, Table 2 ... 3 Changes to Features Section............................................................ 1 Changes to Thermal Resistance Section and Table 5 ................... 5 Added Comparator Operation Section ....................................... 21 Changes to Figure 41 and Figure 44............................................. 12 Added Figure 65 to Figure 69; Renumbered Sequentially ........ 21 Changes to Figure 45 and Figure 48............................................. 13 Updated Outline Dimensions ....................................................... 18 7/2012—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 18 Added ADA4528-2 ............................................................. Universal Changes to Features Section, Figure 1, Figure 2, and Table 1 .... 1 1/2011—Revision 0: Initial Version Rev. F | Page 2 of 24

Data Sheet ADA4528-1/ADA4528-2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—2.5 V OPERATION V = 2.5 V, V = V /2, T = 25°C, unless otherwise specified. SY CM SY A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V V = 0 V to 2.5 V 0.3 2.5 μV OS CM −40°C ≤ T ≤ +125°C, MSOP package 4 μV A −40°C ≤ T ≤ +125°C, LFCSP package 4.3 μV A Offset Voltage Drift ΔV /ΔT −40°C ≤ T ≤ +125°C, MSOP package 0.002 0.015 μV/°C OS A −40°C ≤ T ≤ +125°C, LFCSP package 0.018 μV/°C A Input Bias Current I 220 400 pA B −40°C ≤ T ≤ +125°C 600 pA A Input Offset Current I 440 800 pA OS −40°C ≤ T ≤ +125°C 1 nA A Input Voltage Range 0 2.5 V Common-Mode Rejection Ratio CMRR V = 0 V to 2.5 V 135 158 dB CM −40°C ≤ T ≤ +125°C 116 dB A Open-Loop Gain A R = 10 kΩ, V = 0.1 V to 2.4 V 130 140 dB VO L O −40°C ≤ T ≤ +125°C 126 dB A ADA4528-1 RL = 2 kΩ, VO = 0.1 V to 2.4 V 125 132 dB −40°C ≤ T ≤ +125°C 121 dB A ADA4528-2 RL = 2 kΩ, VO = 0.1 V to 2.4 V 122 132 dB −40°C ≤ T ≤ +125°C 119 dB A Input Resistance Differential Mode R 225 kΩ INDM Common Mode R 1 GΩ INCM Input Capacitance Differential Mode C 15 pF INDM Common Mode C 30 pF INCM OUTPUT CHARACTERISTICS Output Voltage High V R = 10 kΩ to V 2.49 2.495 V OH L CM −40°C ≤ T ≤ +125°C 2.485 V A R = 2 kΩ to V 2.46 2.48 V L CM −40°C ≤ T ≤ +125°C 2.44 V A Output Voltage Low V R = 10 kΩ to V 5 10 mV OL L CM −40°C ≤ T ≤ +125°C 15 mV A R = 2 kΩ to V 20 40 mV L CM −40°C ≤ T ≤ +125°C 60 mV A Short-Circuit Current I ±30 mA SC Closed-Loop Output Impedance Z f = 1 kHz, A = +10 0.1 Ω OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.2 V to 5.5 V 130 150 dB SY −40°C ≤ T ≤ +125°C 127 dB A Supply Current per Amplifier I I = 0 mA 1.4 1.7 mA SY O −40°C ≤ T ≤ +125°C 2.1 mA A DYNAMIC PERFORMANCE Slew Rate SR R = 10 kΩ, C = 100 pF, A = +1 0.45 V/μs L L V Settling Time to 0.1% t V = 1.5 V step, R = 10 kΩ, C = 100 pF, A = −1 7 µs S IN L L V Unity-Gain Crossover UGC V = 10 mV p-p, R = 10 kΩ, C = 100 pF, A = +1 4 MHz IN L L V Phase Margin Φ V = 10 mV p-p, R = 10 kΩ, C = 100 pF, A = +1 57 Degrees M IN L L V Gain Bandwidth Product GBP V = 10 mV p-p, R = 10 kΩ, C = 100 pF, A = +100 3 MHz IN L L V Rev. F | Page 3 of 24

ADA4528-1/ADA4528-2 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit −3 dB Closed-Loop Bandwidth f V = 10 mV p-p, R = 10 kΩ, C = 100 pF, A = +1 6.2 MHz −3dB IN L L V Overload Recovery Time R = 10 kΩ, C = 100 pF, A = −10 50 μs L L V NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz, A = +100 97 nV p-p n V Voltage Noise Density e f = 1 kHz, A = +100 5.6 nV/√Hz n V f = 1 kHz, A = +100, V = 2.0 V 5.5 nV/√Hz V CM Current Noise i p-p f = 0.1 Hz to 10 Hz, A = +100 10 pA p-p n V Current Noise Density i f = 1 kHz, A = +100 0.7 pA/√Hz n V ELECTRICAL CHARACTERISTICS—5 V OPERATION V = 5 V, V = V /2, T = 25°C, unless otherwise specified. SY CM SY A Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V V = 0 V to 5 V 0.3 2.5 μV OS CM −40°C ≤ T ≤ +125°C 4 μV A Offset Voltage Drift ΔV /ΔT −40°C ≤ T ≤ +125°C 0.002 0.015 μV/°C OS A Input Bias Current I B ADA4528-1 90 200 pA −40°C ≤ T ≤ +125°C 300 pA A ADA4528-2 125 250 pA −40°C ≤ T ≤ +125°C 350 pA A Input Offset Current I OS ADA4528-1 180 400 pA −40°C ≤ T ≤ +125°C 500 pA A ADA4528-2 250 500 pA −40°C ≤ T ≤ +125°C 600 pA A Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V = 0 V to 5 V 137 160 dB CM −40°C ≤ T ≤ +125°C 122 dB A Open-Loop Gain A R = 10 kΩ, V = 0.1 V to 4.9 V 127 139 dB VO L O −40°C ≤ T ≤ +125°C 125 dB A R = 2 kΩ, V = 0.1 V to 4.9 V 121 131 dB L O −40°C ≤ T ≤ +125°C 120 dB A Input Resistance Differential Mode R 190 kΩ INDM Common Mode R 1 GΩ INCM Input Capacitance Differential Mode C 16.5 pF INDM Common Mode C 33 pF INCM OUTPUT CHARACTERISTICS Output Voltage High V R = 10 kΩ to V 4.99 4.995 V OH L CM −40°C ≤ T ≤ +125°C 4.98 V A R = 2 kΩ to V 4.96 4.98 V L CM −40°C ≤ T ≤ +125°C 4.94 V A Output Voltage Low V R = 10 kΩ to V 5 10 mV OL L CM −40°C ≤ T ≤ +125°C 20 mV A R = 2 kΩ to V 20 40 mV L CM −40°C ≤ T ≤ +125°C 60 mV A Short-Circuit Current I ±40 mA SC Closed-Loop Output Impedance Z f = 1 kHz, A = +10 0.1 Ω OUT V Rev. F | Page 4 of 24

Data Sheet ADA4528-1/ADA4528-2 Parameter Symbol Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.2 V to 5.5 V 130 150 dB SY −40°C ≤ T ≤ +125°C 127 dB A Supply Current per Amplifier I I = 0 mA 1.5 1.8 mA SY O −40°C ≤ T ≤ +125°C 2.2 mA A DYNAMIC PERFORMANCE Slew Rate SR R = 10 kΩ, C = 100 pF, A = +1 0.5 V/μs L L V Settling Time to 0.1% t V = 4 V step, R = 10 kΩ, C = 100 pF, A = −1 10 µs S IN L L V Unity-Gain Crossover UGC V = 10 mV p-p, R = 10 kΩ, C = 100 pF, A = +1 4 MHz IN L L V Phase Margin Φ V = 10 mV p-p, R = 10 kΩ, C = 100 pF, A = +1 57 Degrees M IN L L V Gain Bandwidth Product GBP V = 10 mV p-p, R = 10 kΩ, C = 100 pF, A = +100 3.4 MHz IN L L V −3 dB Closed-Loop Bandwidth f V = 10 mV p-p, R = 10 kΩ, C = 100 pF, A = +1 6.5 MHz −3dB IN L L V Overload Recovery Time R = 10 kΩ, C = 100 pF, A = −10 50 μs L L V NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz, A = +100 99 nV p-p n V Voltage Noise Density e f = 1 kHz, A = +100 5.9 nV/√Hz n V f = 1 kHz, A = +100, V = 4.5 V 5.3 nV/√Hz V CM Current Noise i p-p f = 0.1 Hz to 10 Hz, A = +100 10 pA p-p n V Current Noise Density i f = 1 kHz, A = +100 0.5 pA/√Hz n V Rev. F | Page 5 of 24

ADA4528-1/ADA4528-2 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA Supply Voltage 6 V soldered in a circuit board for surface-mount packages using a Input Voltage ±VSY ± 0.3 V 4-layer JEDEC board. The exposed pad of the LFCSP package is Input Current1 ±10 mA soldered to the board. Differential Input Voltage ±V SY Output Short-Circuit Duration to GND Indefinite Table 5. Thermal Resistance Storage Temperature Range −65°C to +150°C Package Type θJA θJC Unit Operating Temperature Range −40°C to +125°C 8-Lead MSOP (RM-8) 142 45 °C/W Junction Temperature Range −65°C to +150°C 8-Lead LFCSP (CP-8-11) 83.5 48.51 °C/W Lead Temperature (Soldering, 60 sec) 300°C 1 θJC is measured on the top surface of the package. 1 The input pins have clamp diodes to the power supply pins. Limit the input ESD CAUTION current to 10 mA or less whenever input signals exceed the power supply rail by 0.3 V. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. F | Page 6 of 24

Data Sheet ADA4528-1/ADA4528-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NIC 1 8 NIC NIC 1 ADA4528-1 8 NIC –IN 2 ADA4528-1 7 V+ –IN 2 7 V+ +IN 3 (NToOt Pto V SIEcWale) 6 OUT +IN 3 (NToOt Pto V SIEcWale) 6 OUT V– 4 5 NIC V– 4 5 NIC N1.O NTIECS = NO INTERNAL CONNECTION. 09437-001 N12..O VNCT–IOEC NOS =NR NE LCOET AI NTVTHEEE IR TEN UXAPNLOC COSOENNDNN EPECACTDTE ITDOO.N. 09437-102 Figure 4. ADA4528-1 Pin Configuration, 8-Lead MSOP Figure 5. ADA4528-1 Pin Configuration, 8-Lead LFCSP Table 6. ADA4528-1 Pin Function Descriptions Pin No. Mnemonic Description 1, 5, 8 NIC No Internal Connection. 2 −IN Inverting Input. 3 +IN Noninverting Input. 4 V− Negative Supply Voltage. 6 OUT Output. 7 V+ Positive Supply Voltage. EPAD Exposed Pad (LFCSP Only). Connect the exposed pad to V− or leave it unconnected. Rev. F | Page 7 of 24

ADA4528-1/ADA4528-2 Data Sheet OUT A 1 8 V+ OUT A 1 8 V+ –IN A 2 ADA4528-2 7 OUT B ADA4528-2 –IN A 2 7 OUT B +IN A 3 TOP VIEW 6 –IN B TOP VIEW (Not to Scale) +INV A– 34 (Not to Scale) 65 –+IINN BB 09437-103 V– 4 5 +IN B N1 . O CVTO–E NOSNRE LCETA VTHE EIT E UXNPCOOSNEDNEPCATDETDO. 09437-107 Figure 6. ADA4528-2 Pin Configuration, 8-Lead MSOP Figure 7. ADA4528-2 Pin Configuration, 8-Lead LFCSP Table 7. ADA4528-2 Pin Function Descriptions Pin No. Mnemonic Description 1 OUT A Output, Channel A. 2 −IN A Inverting Input, Channel A. 3 +IN A Noninverting Input, Channel A. 4 V− Negative Supply Voltage. 5 +IN B Noninverting Input, Channel B. 6 −IN B Inverting Input, Channel B. 7 OUT B Output, Channel B. 8 V+ Positive Supply Voltage. EPAD Connect the exposed pad to V- or leave it unconnected. Rev. F | Page 8 of 24

Data Sheet ADA4528-1/ADA4528-2 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A 100 100 90 VSY = 2.5V 90 VSY = 5V VCM = VSY/2 VCM = VSY/2 80 80 S S ER 70 ER 70 FI FI PLI 60 PLI 60 M M A A F 50 F 50 O O ER 40 ER 40 B B M M U 30 U 30 N N 20 20 10 10 –01.0 –0.8 –0.6 –0.4 –0.2VOS0 (µV)0.2 0.4 0.6 0.8 1.0 09437-002 –01.0 –0.8 –0.6 –0.4 –0.2VOS0 (µV)0.2 0.4 0.6 0.8 1.0 09437-005 Figure 8. Input Offset Voltage Distribution Figure 11. Input Offset Voltage Distribution 60 60 VSY = 2.5V VSY = 5V 50 VCM = VSY/2 50 VCM = VSY/2 S S R R E E FI 40 FI 40 LI LI P P M M A A F 30 F 30 O O R R E E MB 20 MB 20 U U N N 10 10 0 09437-003 0 09437-006 0 3 6 9 12 15 0 3 6 9 12 15 TCVOS (nV/°C) TCVOS (nV/°C) Figure 9. Input Offset Voltage Drift Distribution Figure 12. Input Offset Voltage Drift Distribution 1.0 1.0 VSY = 2.5V VSY = 5V 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 V) V) µ µ (S 0 (S 0 O O V V –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.00 0.5 1.0VCM (V) 1.5 2.0 2.5 09437-004 –1.00 1 2 VCM (V) 3 4 5 09437-007 Figure 10. Input Offset Voltage vs. Common-Mode Voltage Figure 13. Input Offset Voltage vs. Common-Mode Voltage Rev. F | Page 9 of 24

ADA4528-1/ADA4528-2 Data Sheet 400 400 VSY = 2.5V VSY = 5V 300 VCM = VSY/2 300 VCM = VSY/2 200 IB+ 200 100 100 IB+ A) A) I (pB 0 I (pB 0 IB– –100 –100 IB– –200 –200 –300 –300 –400–50 –25 0 TEMP25ERATUR5E0 (°C) 75 100 125 09437-008 –400–50 –25 0 TEMP25ERATUR5E0 (°C) 75 100 125 09437-110 Figure 14. Input Bias Current vs. Temperature Figure 17. Input Bias Current vs. Temperature 600 600 400 +85°C 400 +85°C –40°C 200 200 –40°C +25°C (pA)B 0 +125°C (pA)B 0 +25°C I I –200 +125°C –200 –400 –400 –600 VSY = 2.5V VSY = 5V –6000 0.5 1.0VCM (V) 1.5 2.0 2.5 09437-009 –8000 1 2 VCM (V) 3 4 5 09437-012 Figure 15. Input Bias Current vs. Common-Mode Voltage Figure 18. Input Bias Current vs. Common-Mode Voltage 10 10 L (V) VSY = 2.5V L (V) VS = 5V AI AI R 1 R 1 Y Y L L P P P P U U O S 100m O S 100m T T ) L –40°C ) L –40°C VO +25°C VO +25°C GE ( 10m ++8152°5C°C GE ( 10m ++8152°5C°C A A T T L L O O T V 1m T V 1m U U P P T T U U O O 0.1m0.001 0.01 LOAD0 .C1URRENT (m1A) 10 100 09437-014 0.1m0.001 0.01 LOAD0 .C1URRENT (m1A) 10 100 09437-017 Figure 16. Output Voltage (VOL) to Supply Rail vs. Load Current Figure 19. Output Voltage (VOL) to Supply Rail vs. Load Current Rev. F | Page 10 of 24

Data Sheet ADA4528-1/ADA4528-2 10 10 L (V) VSY = 2.5V L (V) VSY = 5V AI AI R 1 R 1 Y Y L L P P P P U U TO S 100m TO S 100m +–2450°°CC E (V) OH 10m ++–284550°°°CCC E (V) OH 10m ++81525°C°C G G A +125°C A T T L L O O T V 1m T V 1m U U P P T T U U O O 0.1m0.001 0.01 LOAD0 .C1URRENT (m1A) 10 100 09437-010 0.1m0.001 0.01 LOAD0 .C1URRENT (m1A) 10 100 09437-013 Figure 20. Output Voltage (VOH) to Supply Rail vs. Load Current Figure 23. Output Voltage (VOH) to Supply Rail vs. Load Current 25 45 Y RAIL (mV) 20 VSY = 2.5V RL = 2kΩ Y RAIL (mV) 3450 VSY = 5V RL = 2kΩ L L P P UP UP 30 TO S 15 TO S 25 )OL ) OL V V 20 E ( 10 E ( G G A A 15 OUTPUT VOLT 5 RL = 10kΩ OUTPUT VOLT 105 RL = 10kΩ –050 –25 0 TEMP25ERATUR5E0 (°C) 75 100 125 09437-016 0–50 –25 0 TEMP25ERATUR5E0 (°C) 75 100 125 09437-019 Figure 21. Output Voltage (VOL) to Supply Rail vs. Temperature Figure 24. Output Voltage (VOL) to Supply Rail vs. Temperature 25 25 V) V) L (m VSY = 2.5V RL = 2kΩ L (m VSY = 5V RL = 2kΩ AI AI R 20 R 20 Y Y L L P P P P U U O S 15 O S 15 T T )H )H O O V V E ( 10 E ( 10 G G A A T T OL RL = 10kΩ OL RL = 10kΩ V V T 5 T 5 U U P P T T U U O O –050 –25 0 TEMP25ERATUR5E0 (°C) 75 100 125 09437-015 –050 –25 0 TEMP25ERATUR5E0 (°C) 75 100 125 1709437-1 Figure 22. Output Voltage (VOH) to Supply Rail vs. Temperature Figure 25. Output Voltage (VOH) to Supply Rail vs. Temperature Rev. F | Page 11 of 24

ADA4528-1/ADA4528-2 Data Sheet 2.00 2.0 +125°C 1.75 +85°C 1.8 A)1.50 A) m +25°C m R (1.25 R ( VSY= 5.0V E E 1.6 FI –40°C FI LI LI P1.00 P M M A A ER0.75 ER 1.4 VSY= 2.5V P P Y Y S S I0.50 I 1.2 0.25 00 0.5 1.0 1.5 2.0 2V.5SY (3V.)0 3.5 4.0 4.5 5.0 5.5 09437-021 1.0–50 –25 0 TEMP25ERATUR5E0 (°C) 75 100 125 09437-024 Figure 26. Supply Current vs. Supply Voltage Figure 29. Supply Current vs. Temperature 120 135 120 135 PHASE PHASE 90 90 90 90 B) B) N (d es) N (d es) P GAI 60 45 Degre P GAI 60 45 Degre N-LOO 30 GAIN 0 HASE ( N-LOO 30 GAIN 0 HASE ( E P E P P P O O VSY = 2.5V VSY = 5V 0 RL = 10kΩ –45 0 RL = 10kΩ –45 CL = 100pF CL = 100pF –301k 10k FREQU1E0N0kCY (Hz) 1M 10M–90 09437-022 –301k 10k FREQU1E0N0kCY (Hz) 1M 10M–90 09437-025 Figure 27. Open-Loop Gain and Phase vs. Frequency Figure 30. Open-Loop Gain and Phase vs. Frequency 60 60 VSY = 2.5V VSY = 5V 50 50 AV = 100 AV = 100 B) 40 B) 40 d d N ( N ( AI 30 AI 30 G G P AV = 10 P AV = 10 O O O 20 O 20 L L D- D- SE 10 SE 10 LO AV = 1 LO AV = 1 C C 0 0 –10 –10 –2010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 09437-026 –2010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 09437-029 Figure 28. Closed-Loop Gain vs. Frequency Figure 31. Closed-Loop Gain vs. Frequency Rev. F | Page 12 of 24

Data Sheet ADA4528-1/ADA4528-2 160 140 VSY = 2.5V 140 120 VSY = 5V VCM = VSY/2 120 100 100 CMRR (dB) 80 CMRR (dB) 6800 60 40 40 20 VCM = VSY/2 20 VCM = 1.1V 0100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 09437-126 0100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 09437-031 Figure 32. CMRR vs. Frequency Figure 35. CMRR vs. Frequency 120 120 VSY = 2.5V VSY = 5V 100 100 80 80 dB) 60 dB) 60 R ( PSRR+ R ( PSRR+ R R PS 40 PS 40 PSRR– PSRR– 20 20 0 0 –20100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 09437-032 –20100 1k F1R0EkQUENCY1 0(H0zk) 1M 10M 09437-035 Figure 33. PSRR vs. Frequency Figure 36. PSRR vs. Frequency 1k 1k VSY = 2.5V VSY = 5V 100 100 10 10 (Ω)UT 1 AV = 100 AV = 10 (Ω)UT 1 AV = 100 AV = 10 O O Z AV = 1 Z AV = 1 0.1 0.1 0.01 0.01 0.001 0.001 100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 09437-027 100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 09437-030 Figure 34. Closed-Loop Output Impedance vs. Frequency Figure 37. Closed-Loop Output Impedance vs. Frequency Rev. F | Page 13 of 24

ADA4528-1/ADA4528-2 Data Sheet VOLTAGE (0.5V/DIV) VVSINY == 2±V1 .p2-5pV VOLTAGE (1V/DIV) VVSINY == 4±V2 .p5-Vp AV = 1 AV = 1 RL = 10kΩ RL = 10kΩ CL = 100pF CL = 100pF TIME (20µs/DIV) 09437-034 TIME (20µs/DIV) 09437-037 Figure 38. Large Signal Transient Response Figure 41. Large Signal Transient Response V) V) DI DI V/ V/ m m 0 0 GE (5 VVISNY == 1±010.m25VV p-p GE (5 VOLTA ARCVLL === 11100k0ΩpF VOLTA VVASIVNY = == 1 1±020.m5VV p-p RL = 10kΩ CL = 100pF TIME (1µs/DIV) 09437-038 TIME (1µs/DIV) 09437-041 Figure 39. Small Signal Transient Response Figure 42. Small Signal Transient Response 16 16 VSY = 2.5V VSY = 5V 14 VAIVN == 1100mV p-p 14 VAIVN == 1100mV p-p RL = 10kΩ RL = 10kΩ 12 12 %) OS+ %) T (10 T (10 OS+ O O O O SH 8 OS– SH 8 R R E E V 6 V 6 O O 4 4 OS– 2 2 0 0 1 LO10AD CAPACITANCE 1(p0F0) 1000 09437-033 1 LO10AD CAPACITANCE 1(p0F0) 1000 09437-036 Figure 40. Small Signal Overshoot vs. Load Capacitance Figure 43. Small Signal Overshoot vs. Load Capacitance Rev. F | Page 14 of 24

Data Sheet ADA4528-1/ADA4528-2 V) 0.5 V) 0.5 E ( E ( G G A INPUT A INPUT LT 0 LT 0 O O V V T T U U–0.5 INP–0.5 OUTPUT VAVRCSIVLLNY === == 11– 100±18k0107Ωp..25F5mVV 2 E (V) INP VAVRCSIVLLNY === == 11– 300±17k0205Ωp.m5FVV 23 E (V) G G 1 A A LT 1 LT O O V OUTPUT V 0 PUT 0 PUT T T U U TIME (10µs/DIV) –1 O09437-040 TIME (10µs/DIV) –1 O09437-043 Figure 44. Positive Overload Recovery Figure 47. Positive Overload Recovery V) 0.5 V) 0.5 E ( E ( G G LTA 0 INPUT LTA 0 INPUT O O V V T T U U INP–0.5 VASVY = = – ±110.25V INP–0.5 1 VRCILLN === 111008k07Ωp.5FmV 1 V) OUTPUT 0 GE (V) OUTPUT E ( TA 0 TAG VSY = ±2.5V –1 VOL –1 UT VOL AVRIVLN === 1–3017k05ΩmV –2 UTPUT TP CL = 100pF O U TIME (10µs/DIV) –2 O09437-039 TIME (10µs/DIV) –3 09437-042 Figure 45. Negative Overload Recovery Figure 48. Negative Overload Recovery INPUT INPUT VSY = 2.5V VSY = 5V RL = 10kΩ RL = 10kΩ DIV) CDUL T= A10V0 =p F–1 DIV) CDUL T= A10V0 =p F–1 V/ V/ 1 2 GE ( +7.5mV GE ( +20mV A A T OUTPUT T OUTPUT OL 0 OL 0 V ERROR BAND V ERROR BAND POST GAIN = 5 –7.5mV POST GAIN = 5 –20mV 09437-044 09437-047 TIME (10µs/DIV) TIME (10µs/DIV) Figure 46. Positive Settling Time to 0.1% Figure 49. Positive Settling Time to 0.1% Rev. F | Page 15 of 24

ADA4528-1/ADA4528-2 Data Sheet VSY = 2.5V VSY = 5V RL = 10kΩ RL = 10kΩ CL = 100pF CL = 100pF DUT AV = –1 DUT AV = –1 INPUT V) V) INPUT DI DI V/ V/ AGE (1 +7.5mV AGE (2 ERROR BAND +20mV OLT OUTPUT 0 OLT POST GAIN = 5 OUTPUT 0 V ERROR BAND V POST GAIN = 5 –7.5mV –20mV TIME (10µs/DIV) 09437-045 TIME (10µs/DIV) 09437-048 Figure 50. Negative Settling Time to 0.1% Figure 53. Negative Settling Time to 0.1% 100 100 VSY = 2.5V VSY = 5V √Hz) AVCVM = =1 0V0SY/2 √Hz) AVCVM = =1 0V0SY/2 V/ V/ n n Y ( Y ( T T SI SI N N E E E D 10 E D 10 S S OI OI N N E E G G A A T T L L O O V V 11 10 FREQ1U00ENCY (Hz) 1k 10k 09437-046 11 10 FREQ1U00ENCY (Hz) 1k 10k 09437-049 Figure 51. Voltage Noise Density vs. Frequency Figure 54. Voltage Noise Density vs. Frequency 10 10 VSY = 2.5V VSY = 5V Hz) VACVM = =1 0V0SY/2 Hz) VACVM = =1 0V0SY/2 √ √ A/ A/ p p Y ( Y ( T T SI SI N N E E E D 1 E D 1 S S OI OI N N T T N N E E R R R R U U C C 0.11 10 F1R0E0QUENCY (1Hkz) 10k 100k 09437-150 0.11 10 F1R0E0QUENCY (1Hkz) 10k 100k 09437-153 Figure 52. Current Noise Density vs. Frequency Figure 55. Current Noise Density vs. Frequency Rev. F | Page 16 of 24

Data Sheet ADA4528-1/ADA4528-2 VSY = 2.5V VSY = 5V AV = 100 AV = 100 VCM = VSY/2 VCM = VSY/2 V) V) DI DI V/ V/ n n 0 0 2 2 E ( E ( G G A A T T L L O O V V T T U U P P N N I I TIME (1s/DIV) 09437-050 TIME (1s/DIV) 09437-053 Figure 56. 0.1 Hz to 10 Hz Noise Figure 59. 0.1 Hz to 10 Hz Noise 10 10 1 1 %) %) N ( N ( + 0.1 + 0.1 D D H H T T 0.01 VASVY = = 1 2.5V 0.01 fVA =SV Y 1= k= 1H 5zV fR =L 1=k 1H0zkΩ RL = 10kΩ 0.0001.001 0.01 AMPLITU0D.1E (V p-p) 1 10 09437-152 0.0001.001 0.01 AMPLITU0D.1E (V p-p) 1 10 09437-155 Figure 57. THD + N vs. Amplitude Figure 60. THD + N vs. Amplitude 1 1 VSY = 2.5V VSY = 5V AV = 1 AV = 1 RL = 10kΩ RL = 10kΩ 80kHz LOW-PASS FILTER 80kHz LOW-PASS FILTER VIN = 2V p-p VIN = 2V p-p 0.1 0.1 %) %) N ( N ( + + D D H H T T 0.01 0.01 0.00110 100 FREQUE1NkCY (Hz) 10k 100k 09437-056 0.00110 100 FREQUE1NkCY (Hz) 10k 100k 09437-057 Figure 58. THD + N vs. Frequency Figure 61. THD + N vs. Frequency Rev. F | Page 17 of 24

ADA4528-1/ADA4528-2 Data Sheet 0 0 VSY=2.5V VSY=5V –20 RL=2kΩ –20 RL=2kΩ B) AV= –100 B) AV= –100 d d N ( –40 N ( –40 O O ERATI –60 VVIINN==01.V5Vp-pp-p ERATI –60 VVIINN==12VVpp--pp EP VIN=1.2Vp-p EP VIN=2.4Vp-p L S –80 L S –80 E E N N N N A–100 A–100 H H C C –120 –120 –140100 1kFREQUENCY (Hz)10k 100k 09437-262 –140100 1kFREQUENCY (Hz)10k 100k 09437-263 Figure 62. Channel Separation vs. Frequency Figure 63.Channel Separation vs. Frequency Rev. F | Page 18 of 24

Data Sheet ADA4528-1/ADA4528-2 APPLICATIONS INFORMATION The ADA4528-1/ADA4528-2 are precision, ultralow noise, RAIL-TO-RAIL INPUT AND OUTPUT zero-drift operational amplifiers that feature a patented chop- The ADA4528-1/ADA4528-2 feature rail-to-rail input and ping technique. This chopping technique offers ultralow input output with a supply voltage from 2.2 V to 5.5 V. Figure 64 offset voltage of 0.3 µV typical and input offset voltage drift of shows the input and output waveforms of the ADA4528- 0.002 µV/°C typical. 1/ADA4528-2 configured as a unity-gain buffer with a supply Offset voltage errors due to common-mode voltage swings voltage of ±2.5 V and a resistive load of 10 kΩ. With an input and power supply variations are also corrected by the chopping voltage of ±2.5 V, the ADA4528-1/ADA4528-2 allow the output technique, resulting in a typical CMRR figure of 158 dB and a to swing very close to both rails. Additionally, the devices do PSRR figure of 150 dB at 2.5 V supply voltage. The ADA4528-1/ not exhibit phase reversal. ADA4528-2 have low broadband noise of 5.6 nV/√Hz (at f = 3 1 kHz, A = +100, and V = 2.5 V) with no 1/f noise component. V SY These features are ideal for amplification of low level signals in 2 VIN VOUT dc or subhertz high precision applications. 1 For more information about the chopper architecture of the V) E ( ADA4528-1/ADA4528-2, see the AN-1114 Application Note, G A 0 T Lowest Noise Zero-Drift Amplifier Has 5.6 nV/√Hz Voltage L O V Noise Density. –1 INPUT PROTECTION VSY = ±2.5V –2 AV = 1 The ADA4528-1/ADA4528-2 have internal ESD protection diodes RL = 10kΩ tdhioatd aerse p croontencetc ttehde bineptwute etrna tnhseis itnoprsu tisn a tnhde eeavcehn ts uopf pellyec rtariol.s Ttahtiecs e –3 TIME (200µs/DIV) 09437-059 Figure 64. Rail-to-Rail Input and Output discharge and are reverse biased during normal operation. This protection scheme allows voltages as high as approximately 300 mV NOISE CONSIDERATIONS beyond the rails to be applied at the input of either terminal For more information about the noise characteristics of the without causing permanent damage (see Table 4 in the Absolute ADA4528-1/ADA4528-2, see the AN-1114 Application Note, Maximum Ratings section). Lowest Noise Zero-Drift Amplifier Has 5.6 nV/√Hz Voltage Noise When either input exceeds one of the supply rails by more than Density. 300 mV, the ESD diodes become forward biased and large amounts 1/f Noise of current begin to flow through them. Without current limiting, 1/f noise, also known as pink noise or flicker noise, is inherent this excessive fault current causes permanent damage to the device. in semiconductor devices and increases as frequency decreases. If the inputs are subjected to overvoltage conditions, insert a At low frequency, 1/f noise is a major noise contributor and resistor in series with each input to limit the input current to 10 mA causes a significant output voltage offset when amplified by the maximum. However, consider the resistor thermal noise effect noise gain of the circuit. However, the ADA4528-1/ADA4528-2 on the entire circuit. eliminate the 1/f noise internally, thus making these devices an For example, at a 5 V supply voltage, the broadband voltage noise excellent choice for dc or subhertz high precision applications. of the ADA4528-1/ADA4528-2 is approximately 6 nV/√Hz (at The 0.1 Hz to 10 Hz amplifier voltage noise is only 97 nV p-p unity gain). A 1 kΩ resistor has thermal noise of 4 nV/√Hz. Adding (AV = +100) at a supply voltage of 2.5 V. a 1 kΩ resistor at the noninverting input pin increases the total The low frequency 1/f noise, which appears as a slow varying noise by 30% root sum square (rss). offset to the ADA4528-1/ADA4528-2, is greatly reduced by the chopping technique. This reduction in 1/f noise allows the ADA4528-1/ADA4528-2 to have much lower noise at dc and low frequency compared to standard low noise amplifiers that are susceptible to 1/f noise. Figure 51 and Figure 54 show the voltage noise density of the amplifier with no 1/f noise. Rev. F | Page 19 of 24

ADA4528-1/ADA4528-2 Data Sheet Source Resistance Voltage Noise Density with Different Gain Configurations With 5.6 nV/√Hz of broadband noise at 1 kHz (V = 2.5 V Figure 65 shows the voltage noise density vs. closed-loop gain of a SY and A = +100), the ADA4528-1/ADA4528-2 are among the zero-drift amplifier from a leading competitor. The voltage noise V lowest noise zero-drift amplifiers currently available in the density of the amplifier increases from 11 nV/√Hz to 21 nV/√Hz industry. Therefore, it is important to carefully select the input as the closed-loop gain decreases from 1000 to 1. source resistance to maintain a total low noise. 24 VSY = 5V The total input referred broadband noise (en total) from any f = 100Hz amplifier is primarily a function of three types of noise: input Hz)20 COMPETITOR A √ V/ voltage noise, input current noise, and thermal (Johnson) noise n Y (16 from the external resistors. SIT N E These uncorrelated noise sources can be summed up in a root D12 E S sum squared (rss) manner using the following equation: OI N E 8 e total = [e2 + 4 kTR + (i × R)2]1/2 G n n S n S A T L where: VO 4 ken i iss t thhee B inopltuztm vaonltna’sg ec onnositsaen ot f( t1h.3e8 a ×m p10li−f2i3e rJ /(KV)/. √Hz). 0 09437-061 1 10 100 1000 T is the temperature in Kelvin (K). CLOSED-LOOP GAIN (V/V) RS is the total input source resistance (Ω). Figure 65. Competitor A: Voltage Noise Density vs. Closed-Loop Gain i is the input current noise of the amplifier (A/√Hz). n Figure 66 shows the voltage noise density vs. frequency of the The total equivalent rms noise over a specific bandwidth is ADA4528-1/ADA4528-2 for three different gain configurations. expressed as The ADA4528-1/ADA4528-2 offer a constant input voltage e = e total × √BW noise density of 6 nV/√Hz to 7 nV/√Hz, regardless of the gain n,rms n configuration. where BW is the bandwidth in hertz. 100 This analysis is valid for broadband noise calculation. If the VSY = 5V VCM = VSY/2 bandwidth of concern includes the chopping frequency, more Hz) √ complicated calculations must be made to include the effect of V/ n the noise energy spectrum at the chopping frequency (see the Y ( T SI Residual Voltage Ripple section). N E With a low source resistance of RS < 1 kΩ, the voltage noise OISE D 10 of the amplifier dominates. As source resistance increases, the N E G thermal noise of RS dominates. As the source resistance increases LTA AV = 1 further, where RS > 100 kΩ, the current noise becomes the main VO AAVV == 11000 contributor to the total input noise. A good selection table for low noise op amps can be found in the AN-940 Application Note, Low 1 Noise Amplifier Selection Guide for Optimal Noise Performance. 1 10 FREQU1E0N0CY (Hz) 1k 10k 09437-062 Figure 66. Voltage Noise Density vs. Frequency with Different Gain Configurations Rev. F | Page 20 of 24

Data Sheet ADA4528-1/ADA4528-2 Residual Voltage Ripple 3.5 Although autocorrection feedback (ACFB) suppresses the chop- 3.0 ping related voltage ripple, higher noise spectrum exists at the mA) chopping frequency and its harmonics due to the remaining ripple. R ( 2.5 E FI Figure 67 shows the voltage noise density of the ADA4528-1/ PLI 2.0 M ADA4528-2 configured in unity gain. A noise energy spectrum A L of 50 nV/√Hz can be seen at the chopping frequency of 200 kHz. UA 1.5 D This noise energy spectrum is significant when the op amp has a R PE 1.0 closed-loop frequency that is higher than the chopping frequency. Y S I 100 0.5 VSY = 5V AV = 1 Y (nV/√Hz) VCM = VSY/2 00 0.5 1.0 1.5 2.0 VS2Y.5 (V) 3.0 3.5 4.0 4.5 5.0 09437-066 T Figure 69. Supply Current vs. Supply Voltage (Voltage Follower) SI N E E D 10 Figure 70 and Figure 71 show the ADA4528-2 configured as OIS comparators, with 1kΩ resistors in series with the input pins. N E Figure 72 shows the supply currents for both configurations. G TA Supply currents increase slightly to 3.2 mA per dual amplifier at L O V 5 V of supplies. +VSY 1 1 10 100 FRE1QkUENCY10 (kHz) 100k 1M 10M 09437-063 1kΩ A1 ISY+ Figure 67. Voltage Noise Density vs. Frequency To further suppress the noise at the chopping frequency, it is recommended that a post filter be placed at the output of the ADA4528-2 VOUT 1/2 amplifier. For more information about residual voltage ripple, see the AN-1114 Application Note, Lowest Noise Zero-Drift Amplifier Has 5.6 nV/√Hz Voltage Noise Density. 1kΩ A2 ISY– COMPARATOR OPERATION Figure 68 shows the ADA4528-2 configured as a voltage –VSY 09437-067 follower with an input voltage that is always kept at midpoint Figure 70. Comparator A of the power supplies. The same configuration is applied to the +VSY unused channel. A1 and A2 indicate the placement of ammeters to measure supply current. As shown in Figure 69, as expected, in normal operating condition, ISY+ = ISY− = 3 mA for the dual A1 ISY+ ADA4528-2 at 5 V of supplies. 1kΩ +VSY ADA4528-2 VOUT 1/2 A1 ISY+ 1kΩ A2 ISY– 1kΩ ADA14/5228-2 VOUT –VSY 09437-068 Figure 71. Comparator B 1kΩ A2 ISY– –VSY 09437-065 Figure 68. Voltage Follower Rev. F | Page 21 of 24

ADA4528-1/ADA4528-2 Data Sheet 3.5 dissimilar metals and is a function of the temperature of the junction. The most common metallic junctions on a circuit 3.0 A) board are solder-to-board trace and solder-to-component lead. m ER ( 2.5 Figure 73 shows a cross section of a surface-mount component FI PLI 2.0 soldered to a PCB. A variation in temperature across the board M A (where TA1 ≠ TA2) causes a mismatch in the Seebeck voltages at L UA 1.5 the solder joints, thereby resulting in thermal voltage errors D R that degrade the ultralow offset voltage performance of the PE 1.0 Y ADA4528-1/ADA4528-2. S I 0.5 COMPONENT LEAD 00 0.5 1.0 1.5 2.0 VS2Y. 5 (V)3.0 3.5 4.0 4.5 5.0 09437-069 VTS1VS+C1 + SUCROFMACPEO-NMEONUTNT +VS+C2VTSS2OLDER Figure 72. Supply Current vs. Supply Voltage (Comparator A and Comparator B) PC BOARD For more details on op amps as comparators, refer to the TA1 TA2 AN-849 Application Note, Using Op Amps as Comparators. CTORPAPCEER IVFT ST1A 1+ ≠V TSCA12 ,≠ T VHTESN2 + VSC2 09437-154 PRINTED CIRCUIT BOARD LAYOUT Figure 73. Mismatch in Seebeck Voltages Causes Seebeck Voltage Error The ADA4528-1/ADA4528-2 are high precision devices with To minimize these thermocouple effects, orient resistors so that ultralow offset voltage and noise. Therefore, care must be taken heat sources warm both ends equally. Where possible, the input in the design of the printed circuit board (PCB) layout to achieve signal paths must contain matching numbers and types of com- the optimum performance of the ADA4528-1/ADA4528-2 at ponents to match the number and type of thermocouple junctions. board level. For example, dummy components, such as zero value resistors, can To avoid leakage currents, keep the surface of the board clean be used to match the thermoelectric error source (real resistors and free of moisture. Coating the board surface creates a barrier in the opposite input path). Place matching components in close to moisture accumulation and reduces parasitic resistance on proximity and orient them in the same manner to ensure equal the board. Seebeck voltages, thus canceling thermal errors. Additionally, use To minimize power supply disturbances caused by output current leads of equal length to keep thermal conduction in equilibrium. variation, properly bypass the power supplies and keep the supply Keep heat sources on the PCB as far away from the amplifier traces short. Connect bypass capacitors as close as possible to the input circuitry as practical. device supply pins. It is highly recommended that a ground plane be used. A ground Stray capacitances are a concern at the outputs and the inputs of plane helps to distribute heat throughout the board, maintains a the amplifier. It is recommended that signal traces be kept at a constant temperature across the board, and reduces EMI noise distance of at least 5 mm from supply lines to minimize coupling. pickup. A potential source of offset error is the Seebeck voltage on the circuit board. The Seebeck voltage occurs at the junction of two Rev. F | Page 22 of 24

Data Sheet ADA4528-1/ADA4528-2 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0.T25OJEDECSTA0°NDARDS0M.0O9-187-AA 0.40 10-07-2009-B Figure 74. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters DETAIL A (JEDEC 95) 2.44 3.10 2.34 3.00 SQ 2.24 2.90 0.50 BSC 5 8 PIN 1 INDEX 1.70 AREA EXPPAODSED 1.60 0.50 1.50 0.40 4 11 0.30 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR AREA OPTIONS (SEE DETAIL A) 0.80 0.75 SIDE VIEW 0.05 MAX FTOHER EPXRPOOPSEERD C POANDN, ERCETFIEORN TOOF 0.70 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS SEATING 0.30 0.08 SECTION OF THIS DATA SHEET PKG-005136 PLANE CO00..M2250PLIANTTOJEDEC S0.T2A0N3 DRAERFDS MO-229-W3030D-4 02-10-2017-C Figure 75. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-11) Dimensions shown in millimeters Rev. F | Page 23 of 24

ADA4528-1/ADA4528-2 Data Sheet ORDERING GUIDE Model1 Temperature Range Package Description Package Option Branding ADA4528-1ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2R ADA4528-1ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2R ADA4528-1ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2R ADA4528-1ACPZ-R2 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2R ADA4528-1ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2R ADA4528-1ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2R ADA4528-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A32 ADA4528-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A32 ADA4528-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A32 ADA4528-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A32 ADA4528-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A32 1 Z = RoHS Compliant Part. ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09437-0-8/17(F) Rev. F | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADA4528-1ARMZ ADA4528-1ARMZ-R7 ADA4528-2ARMZ ADA4528-2ARMZ-R7 ADA4528-1ACPZ-R7 ADA4528- 1ACPZ-RL ADA4528-1ARMZ-RL ADA4528-2ACPZ-R7 ADA4528-2ACPZ-RL ADA4528-2ARMZ-RL ADA4528- 1ACPZ-R2 ADA4528-2TCPZ-EP