IF Digitizing Subsystem AD9874* FEATURES GENERAL DESCRIPTION 10 MHz to 300 MHz Input Frequency The AD9874 is a general-purpose IF subsystem that digitizes a 7.2 kHz to 270 kHz Output Signal Bandwidth low level 10 MHz to 300 MHz IF input with a signal bandwidth 8.1 dB SSB NF ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874 0 dBm IIP3 consists of a low noise amplifier, a mixer, a band-pass sigma-delta AGC Free Range up to –34 dBm analog-to-digital converter, and a decimation filter with program- 12 dB Continuous AGC Range mable decimation factor. An automatic gain control (AGC) circuit 16 dB Front End Attenuator gives the AD9874 12 dB of continuous gain adjustment. Auxil- Baseband I/Q 16-Bit (or 24-Bit) Serial Digital Output iary blocks include both clock and LO synthesizers. LO and Sampling Clock Synthesizers The AD9874’s high dynamic range and inherent antialiasing Programmable Decimation Factor, Output Format, provided by the band-pass sigma-delta converter allow the AGC, and Synthesizer Settings AD9874 to cope with blocking signals up to 95 dB stronger 370 (cid:1) Input Impedance than the desired signal. This attribute can often reduce the cost of 2.7 V to 3.6 V Supply Voltage a radio by reducing its IF filtering requirements. Also, it enables Low Current Consumption: 20 mA multimode radios of varying channel bandwidths, allowing the 48-Lead LQFP Package (1.4 mm Thick) IF filter to be specified for the largest channel bandwidth. APPLICATIONS The SPI port programs numerous parameters of the AD9874, Multimode Narrow-Band Radio Products thus allowing the device to be optimized for any given application. Analog/Digital UHF/VHF FDMA Receivers Programmable parameters include synthesizer divide ratios, AGC TETRA, APCO25, GSM/EDGE attenuation and attack/decay time, received signal strength level, Portable and Mobile Radio Products decimation factor, output data format, 16dB attenuator, and the Base Station Applications selected bias currents. The bias currents of the LNA and mixer SATCOM Terminals can be further reduced at the expense of degraded performance for battery-powered applications. FUNCTIONAL BLOCK DIAGRAM MXOP MXON IF2P IF2N GCP GCN DAC AGC AD9874 –16dB IFIN LNA (cid:2)-(cid:3) ADC DECIMATION FORMATTING/SSI DOUTA FILTER DOUTB FS CLKOUT FREF CONTROL LOGIC LO CLK SYN VOLTAGE SYN REFERENCE SPI IOUTL LOP LON IOUTC CLKP CLKN VREFP VCM VREFN PC PD PE SYNCB LO VCO AND LOOP FILTER LOOP FILTER *Protected by U.S. Patent No. 5,969,657; REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

AD9874 TABLE OF CONTENTS AD9874—SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5 PIN CONFIGURATION/DESCRIPTION . . . . . . . . . . . . . 6 DEFINITION OF SPECIFICATIONS/ TEST METHODS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 8 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . 13 SYNCHRONOUS SERIAL INTERFACE (SSI) . . . . . . . . 16 Synchronization Using SYNCB . . . . . . . . . . . . . . . . . . . . 18 Interfacing to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 POWER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LO SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Fast Acquire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CLOCK SYNTHESIZER . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IF LNA/MIXER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BAND-PASS SIGMA DELTA ((cid:1)-(cid:2)) ADC . . . . . . . . . . . . 24 DECIMATION FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VARIABLE GAIN AMPLIFIER WITH AGC . . . . . . . . . . 28 Variable Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . 29 System NF vs. VGA Control . . . . . . . . . . . . . . . . . . . . . . 31 APPLICATION CONSIDERATIONS . . . . . . . . . . . . . . . 32 Frequency Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Spurious Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 EXTERNAL PASSIVE COMPONENT REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Superheterodyne Receiver . . . . . . . . . . . . . . . . . . . . . . . . 34 Synchronization of Multiple AD9874s . . . . . . . . . . . . . . . 36 Split Path Rx Architecture . . . . . . . . . . . . . . . . . . . . . . . . 37 Hung Mixer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 LAYOUT EXAMPLE EVALUATION BOARD AND SOFTWARE . . . . . . . . . 38 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 39 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 –2– REV. A

AD9874–SPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f = 18 MSPS, f = 109.65 MHz, f = 107.4 MHz, f = 16.8 MHz, unless otherwise noted.)1 CLK IF LO REF Parameter Temp Test Level Min Typ Max Unit SYSTEM DYNAMIC PERFORMANCE2 SSB Noise Figure @ Min VGA Attenuation3, 4 Full IV 8.1 9.5 dB @ Max VGA Attenuation3, 4 Full IV 13 dB Dynamic Range with AGC Enabled3, 4 Full IV 91 95 dB IF Input Clip Point @ Max VGA Attenuation3 Full IV –20 –19 dBm @ Min VGA Attenuation3 Full IV –32 –31 dBm Input Third Order Intercept (IIP3) Full IV –5 0 dBm Gain Variation over Temperature Full IV 0.7 2 dB LNA + MIXER Maximum RF and LO Frequency Range Full IV 300 500 MHz LNA Input Impedance 25oC V 370//1.4 (cid:1)//pF Mixer LO Input Resistance 25oC V 1 k(cid:1) LO SYNTHESIZER LO Input Frequency Full IV 7.75 300 MHz LO Input Amplitude Full IV 0.3 2.0 V p-p FREF Frequency (for Sinusoidal Input ONLY) Full IV 8 25 MHz FREF Input Amplitude Full IV 0.3 3 V p-p FREF Slew Rate Full IV 7.5 V/(cid:2)s Minimum Charge Pump Current @ 5 V5 Full VI 0.48 0.67 0.78 mA Maximum Charge Pump Current @ 5 V5 Full VI 3.87 5.3 6.2 mA Charge Pump Output Compliance6 Full VI 0.4 VDDP – 0.4 V Synthesizer Resolution Full IV 6.25 kHz CLOCK SYNTHESIZER CLK Input Frequency Full IV 13 26 MHz CLK Input Amplitude Full IV 0.3 VDDC V p-p Minimum Charge Pump Output Current5 Full VI 0.48 0.67 0.78 mA Maximum Charge Pump Output Current5 Full VI 3.87 5.3 6.2 mA Charge Pump Output Compliance6 Full VI 0.4 VDDQ – 0.4 V Synthesizer Resolution Full IV 2.2 kHz SIGMA-DELTA ADC Resolution Full IV 16 24 Bits Clock Frequency (f ) Full IV 13 26 MHz CLK Center Frequency Full V f /8 MHz CLK Pass-Band Gain Variation Full IV 1.0 dB Alias Attenuation Full IV 80 dB GAIN CONTROL Programmable Gain Step Full V 16 dB AGC Gain Range (Continuous) Full V 12 dB GCP Output Resistance Full IV 50 72.5 95 k(cid:1) OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) Full VI 2.7 3.0 3.6 V Digital Supply Voltage (VDDD, VDDC, VDDL) Full VI 2.7 3.0 3.6 V Interface Supply Voltage7 (VDDH) Full VI 1.8 3.6 V Charge Pump Supply Voltage (VDDP, VDDQ) Full VI 2.7 5.0 5.5 V Total Current High Performance Setting8 Full VI 20 26.5 mA Low Power Mode8 Full VI 17 22 mA Standby Full VI 0.01 0.1 mA OPERATING TEMPERATURE RANGE –40 +85 °C NOTES 1Standard operating mode: LNA/Mixer @ high bias setting, VGA @ Min ATTEN setting, synthesizers in normal (not fast acquire) mode, f = 18 MHz, decimation CLK factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. 2This includes 0.9 dB loss of matching network. 3AGC with DVGA enabled. 4Measured in 10 kHz bandwidth. 5Programmable in 0.67 mA steps. 6Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2). 7VDDH must be less than VDDD + 0.5 V. 8Clock VCO off, add additional 0.7 mA with VGA @ Max ATTEN setting. Specifications subject to change without notice. REV. A –3–

AD9874 DIGITAL SPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f = 18 MSPS, f = 109.65 MHz, f = 107.4 MHz, f = 16.8 MHz, unless otherwise noted.)1 CLK IF LO REF Parameter Temp Test Level Min Typ Max Unit DECIMATOR Decimation Factor2 Full IV 48 960 Pass-Band Width Full V 50% f CLKOUT Pass-Band Gain Variation Full IV 1.2 dB Alias Attenuation Full IV 88 dB SPI-READ OPERATION (See Figure 1a) PC Clock Frequency Full IV 10 MHz PC Clock Period (t ) Full IV 100 ns CLK PC Clock HI (t ) Full IV 45 ns HI PC Clock LOW (t ) Full IV 45 ns LOW PC to PD Setup Time (t ) Full IV 2 ns DS PC to PD Hold Time (t ) Full IV 2 ns DH PE to PC Setup Time (t ) Full IV 5 ns S PC to PE Hold Time (t ) Full IV 5 ns H SPI-WRITE OPERATION3 (See Figure 1b) PC Clock Frequency Full IV 10 MHz PC Clock Period (t ) Full IV 100 ns CLK PC Clock HI (t ) Full IV 45 ns HI PC Clock LOW (t ) Full IV 45 ns LOW PC to PD Setup Time (t ) Full IV 2 ns DS PC to PD Hold Time (t ) Full IV 2 ns DH PC to PD (or DOUBT) Data Valid Time (t ) Full IV 3 ns DV PE to PD Output Valid to Hi-Z (t ) Full IV 8 ns EZ SSI3 (see Figure 2b) CLKOUT Frequency Full IV 0.867 26 MHz CLKOUT Period (t ) Full IV 38.4 1153 ns CLK CLKOUT Duty Cycle (t t ) Full IV 33 50 67 ns HI, LOW CLKOUT to FS Valid Time (t ) Full IV –1 +1 ns V CLKOUT to DOUT Data Valid Time (t ) Full IV –1 +1 ns DV CMOS LOGIC INPUTS4 Logic “1” Voltage (V ) Full IV VDDH – 0.2 V IH Logic “0” Voltage (V ) Full IV 0.5 V IL Logic “1” Current (V ) Full IV 10 µA IH Logic “0” Current (V ) Full IV 10 µA IL Input Capacitance Full IV 3 pF CMOS LOGIC OUTPUTS3, 4, 5 Logic “1” Voltage (V ) Full IV VDDH – 0.2 V IH Logic “0” Voltage (V ) Full IV 0.2 V IL NOTES 1Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f = 18 MHz, decimation factor = 300, 10 pF load on SSI output pins: CLK VDDx = 3.0 V. 2Programmable in steps of 48 or 60. 3CMOS output mode with C = 10 pF and Drive Strength = 7. LOAD 4Absolute Max and Min input/output levels are VDDH +0.3 V and –0.3 V. 5I = 1 mA; specification is also dependent on Drive Strength setting. OL Specifications subject to change without notice. –4– REV. A

AD9874 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Unit VDDF, VDDA, VDDC, VDDD, VDDH, GNDF, GNDA, GNDC, GNDD, GNDH, –0.3 +4.0 V VDDL, VDDI GNDL, GNDI, GNDS VDDF, VDDA, VDDC, VDDD, VDDH, VDDR, VDDA, VDDC, VDDD, VDDH, –4.0 +4.0 V VDDL, VDDI VDDL, VDDI VDDP, VDDQ GNDP, GNDQ –0.3 +6.0 V GNDF, GNDA, GNDC, GNDD, GNDH, GNDF, GNDA, GNDC, GNDD, GNDH, –0.3 +0.3 V GNDL, GNDI, GNDQ, GNDP, GNDS GNDL, GNDI, GNDQ, GNDP, GNDS MXOP, MXON, LOP, LON, IFIN, GNDI –0.3 VDDI + 0.3 V CXIF, CXVL, CXVM PC, PD, PE, CLKOUT, DOUTA, GNDH –0.3 VDDH + 0.3 V DOUTB, FS, SYNCB IF2N, IF2P, GCP, GCN GNDF –0.3 VDDF + 0.3 V VREFP, VREFN, RREF GNDA –0.3 VDDA + 0.3 V IOUTC GNDQ –0.3 VDDQ + 0.3 V IOUTL GNDP –0.3 VDDP + 0.3 V CLKP, CLKN GNDC –0.3 VDDC + 0.3 V FREF GNDL –0.3 VDDL + 0.3 V Junction Temperature 150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) 300 °C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS EXPLANATION OF TEST LEVELS TEST LEVEL Thermal Resistance I. 100% production tested. 48-Lead LQFP (cid:5) = 76.2°C/W II. 100% production tested at 25°C and sample tested at JA specified temperatures. AC testing done on sample basis. (cid:5) = 17°C/W JC III. Sample tested only. IV. Parameter is guaranteed by design and/or characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25°C; min and max guaranteed by design and characterization for industrial temperature range. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9874ABST –40°C to +85°C 48-Lead Thin Plastic Quad Flatpack (LQFP) ST-48 AD9874EB Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9874 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –5–

AD9874 PIN CONFIGURATION VDDI IFIN CXIF GNDI CXVL LOP LON CXVM VDDL VDDP IOUTL GNDP 48 47 46 45 44 43 42 41 40 39 38 37 MXOP 1 36 GNDL PIN 1 MXON 2 IDENTIFIER 35 FREF GNDF 3 34 GNDS IF2N 4 33 SYNCB IF2P 5 32 GNDH AD9874 VDDF 6 31 FS TOP VIEW GCP 7 (Not to Scale) 30 DOUTB GCN 8 29 DOUTA VDDA 9 28 CLKOUT GNDA10 27 VDDH VREFP11 26 VDDD VREFN12 25 PE 13 14 15 16 17 18 19 20 21 22 23 24 F QCQC CPNSD CD E DTDD DKKDD PP R DUND NLLNN R VOGV GCCGG I PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description Pin Mnemonic Description 1 MXOP Mixer Output, Positive. 27 VDDH Positive Power Supply for Digital Interface. 2 MXON Mixer Output, Negative. 28 CLKOUT Clock Output for SSI Port. 3 GNDF Ground for Front End of ADC. 29 DOUTA Data Output for SSI Port. 4 IF2N Second IF Input (to ADC), Negative. 30 DOUTB Data Output for SSI Port (Inverted) or SPI Port. 5 IF2P Second IF Input (to ADC), Positive. 31 FS Frame Sync for SSI Port. 6 VDDF Positive Power Supply for Front End of ADC. 32 GNDH Ground for Digital Interface. 7 GCP Filter Capacitor for ADC Full-Scale Control. 33 SYNCB Resets SSI and Decimator Counters; 8 GCN Full-Scale Control Ground. Active Low. 9 VDDA Positive Power Supply for ADC Back End. 34 GNDS Substrate Ground. 10 GNDA Ground for ADC Back End. 35 FREF Reference Frequency Input for Both 11 VREFP Voltage Reference, Positive. Synthesizers. 12 VREFN Voltage Reference, Negative. 36 GNDL Ground for LO Synthesizer. 13 RREF Reference Resistor: Requires 100 kΩ to 37 GNDP Ground for LO Synthesizer Charge Pump. GNDA. 38 IOUTL LO Synthesizer Charge Pump Output 14 VDDQ Positive Power Supply for Clock Synthesizer. Current Charge Pump. 15 IOUTC Clock Synthesizer Charge Pump Output 39 VDDP Positive Power Supply for LO Synthesizer Current. Charge Pump. 16 GNDQ Ground for Clock Synthesizer Charge 40 VDDL Positive Power Supply for LO Synthesizer. Pump. 41 CXVM External Filter Capacitor; DC Output of 17 VDDC Positive Power Supply for Clock Synthesizer. LNA. 42 LON LO Input to Mixer and LO Synthesizer, 18 GNDC Ground for Clock Synthesizer. Negative. 19 CLKP Sampling Clock Input/Clock VCO Tank, 43 LOP LO Input to Mixer and LO Synthesizer, Positive. Positive. 20 CLKN Sampling Clock Input/Clock VCO Tank, 44 CXVL External Bypass Capacitor for LNA Power Negative. Supply. 21 GNDS Substrate Ground. 45 GNDI Ground for Mixer and LNA. 22 GNDD Ground for Digital Functions. 46 CXIF External Capacitor for Mixer V-I Con- 23 PC Clock Input for SPI Port. verter Bias. 24 PD Data I/O for SPI Port. 47 IFIN First IF Input (to LNA). 25 PE Enable Input for SPI Port. 48 VDDI Positive Power Supply for LNA and Mixer. 26 VDDD Positive Power Supply for Internal Digital Function. –6– REV. A

AD9874 DEFINITION OF SPECIFICATIONS/TEST METHODS Dynamic Range (DR) Dynamic range is the measure of a small target input signal Single-Sideband Noise Figure (SSB NF) (P ) in the presence of a large unwanted interferer signal Noise figure (NF) is defined as the degradation in SNR perfor- TARGET (P ). Typically, the large signal will cause some unwanted mance (in dB) of an IF input signal after it passes through a INTER characteristic of the component or system to degrade, thus component or system. It can be expressed with the equation making it unable to detect the smaller target signal correctly. In NoiseFigure=10×log(SNR SNR ) the case of the AD9874, it is often a degradation in noise figure IN OUT at increased VGA attenuation settings that limits its dynamic The term SSB is applicable for heterodyne systems containing a range (refer to TPCs 15a, 15b, and 15c). mixer. It indicates that the desired signal spectrum resides on only one side of the LO frequency (i.e., single sideband); thus a The test method for the AD9874 is as follows. The small target “noiseless” mixer has a noise figure of 3 dB. signal (an unmodulated carrier) is input at the center of the IF frequency, and its power level (P ) is adjusted to achieve an The AD9874’s SSB noise figure is determined by the equation TARGET SNR of 6 dB. The power of the signal is then increased by { ( )} TARGET SSBNF =P − 10×log BW −174dBm Hz−SNR 3 dB prior to injecting the interferer signal. The offset frequency IN of the interferer signal is selected so that aliases produced by where P is the input power of an unmodulated carrier, BW is the decimation filter’s response as well as phase noise from the LO IN the noise measurement bandwidth, –174 dBm/Hz is the thermal (due to reciprocal mixing) do not fall back within the measurement noise floor at 293 K, and SNR is the measured signal-to-noise bandwidth. For this reason, an offset of 110 kHz was selected. ratio in dB of the AD9874. The interferer signal (also an unmodulated carrier) is then Note that P is set to –85 dBm to minimize any degradation in injected into the input and its power level is increased to the IN measured SNR due to phase noise from the RF and LO signal point (PINTER) where the target signal SNR is reduced to 6dB. generators. The IF frequency, CLK frequency, and decimation The dynamic range is determined with the equation: factors are selected to minimize any spurious components DR=P –P +SNR INTER TARGET TARGET falling within the measurement bandwidth. Note also that a Note that the AD9874’s AGC is enabled for this test. bandwidth of 10 kHz is used for the data sheet specification. Refer to Figures 22a and 22b for an indication of how NF varies IF Input Clip Point with BW. Also, refer to the TPCs to see how NF is affected by The IF input clip point is defined as 2 dB below the input power different operating conditions. All references to noise figures level (P ), resulting in the clipping of the AD9874’s ADC. IN within this data sheet imply single-sideband noise figure. Unlike other linear components that typically exhibit a soft compression (characterized by its 1 dB compression point), an Input Third Order Intercept (IIP3) IIP3 is a figure of merit used to determine a component’s or ADC exhibits a hard compression once its input signal exceeds system’s susceptibility to intermodulation distortion (IMD) its rated maximum input signal range. In the case of the AD9874, from its third order nonlinearities. Two unmodulated carriers at which contains a (cid:1)-(cid:2) ADC, hard compression should be avoided a specified frequency relationship (f and f ) are injected into a because it causes severe SNR degradation. 1 2 nonlinear system exhibiting third order nonlinearities producing IMD components at 2f – f and 2f – f . IIP3 graphically repre- 1 2 2 1 sents the extrapolated intersection of the carrier’s input power with the third order IMD component when plotted in dB. The difference in power (D in dBc) between the two carriers and the resulting third order IMD components can be determined from the equation D=2×(IIP3–P ) IN REV. A –7–

AD9874–Typical Performance Characteristics (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f = 18 MSPS, f = 109.56 MHz, f = 107.4 MHz, CLK IF LO T = 25(cid:4)C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 A 9.5 9.5 100 9.0 9.0 80 +85(cid:4)C +85(cid:4)C % –40(cid:4)C +25(cid:4)C +85(cid:4)C 8.5 8.5 E – 60 +25(cid:4)C G B 8.0 B 8.0 A d d CENT 40 NF – 7.5 NF – 7.5 +25(cid:4)C R –40(cid:4)C E P 7.0 7.0 20 –40(cid:4)C 6.5 6.5 0 6.0 6.0 7.2 7.5 7.8 8.1 8.4 8.7 9.0 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 NOISE FIGURE – dB VDDx – V VDDx – V TPC 1a.CDF of SSB Noise Figure TPC 1b.SSB Noise Figure vs. Supply TPC 1c.SSB Noise Figure vs. Supply (VDDx = 3.0 V, High Bias2) (High Bias2) (Low Bias3) 1.5 0 100 1.0 +85(cid:4)C –2 80 0.5 % –40(cid:4)C +25(cid:4)C +85(cid:4)C 0 E – 60 m–0.5 +25(cid:4)C m –4 +85(cid:4)C PERCENTAG 40 IIP3 – dB–––112...050 –40(cid:4)C IIP3 – dB ––86 +25(cid:4)C 20 –2.5 –40(cid:4)C –10 –3.0 0 –3.5 –12 –3 –2 –1 0 1 2 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 IIP3 – dBm VDDx – V VDDx – V TPC 2a.CDF of IIP3 (VDDx = 3.0 V, TPC 2b.IIP3 vs. Supply (High Bias2) TPC 2c.IIP3 vs. Supply (Low Bias3) High Bias2) 98 98 100 97 97 80 –40(cid:4)C +25(cid:4)C % E – 60 –40(cid:4)C 96 96 –40(cid:4)C G B B A d d CENT 40 DR – 95 +85(cid:4)C DR – 95 PER 94 +25(cid:4)C 94 +85(cid:4)C 20 +85(cid:4)C 93 93 +25(cid:4)C 0 92 92 92 93 94 95 96 97 98 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 DYNAMIC RANGE – dB VDDx – V VDDx – V TPC 3a.CDF of Dynamic Range TPC 3b.Dynamic Range vs. Supply TPC 3c.Dynamic Range vs. Supply (VDDx = 3.0 V, High Bias2) (High Bias2) (Low Bias3) 1Data taken with Toko FSLM series 10 µH inductors. 2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01. 3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01. –8– REV. A

AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f = 18 MSPS, f = 109.56 MHz, f = 107.4 MHz, CLK IF LO T = 25(cid:1)C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 A –17.5 –17.5 100 –18.0 –18.0 80 m m B B AGE – % 60 –40(cid:1)C +25(cid:1)C +85(cid:1)C OINT – d–18.5 +85(cid:1)C OINT – d–18.5 +85(cid:1)C CENT 40 LIP P–19.0 +25(cid:1)C LIP P–19.0 +25(cid:1)C R C C PE PUT –19.5 –40(cid:1)C PUT –19.5 –40(cid:1)C 20 IN IN –20.0 –20.0 0 –20.5 –20.5 –19.4 –19.2 –19.0 –18.8 –18.6 –18.4 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 IFIN CLIP POINT – dBm VDDx – V VDDx – V TPC 4a.CDF of Maximum VGA TPC 4b.Maximum VGA Attenuation TPC 4c.Maximum VGA Attenuation Attenuation Clip Point (VDDx = 3.0 V, Clip Point vs. Supply (High Bias2) Clip Point vs. Supply (Low Bias3) High Bias2) –29.5 –29.5 100 80 m–30.0 m–30.0 B B PERCENTAGE – % 6400 –40(cid:1)C +25(cid:1)C +85(cid:1)C PUT CLIP POINT – d––3301..50 ++8255(cid:1)(cid:1)CC PUT CLIP POINT – d––3301..50 ++8255(cid:1)(cid:1)CC 20 IN–31.5 –40(cid:1)C IN–31.5 0 –40(cid:1)C –32.0 –32.0 –31.6 –31.4 –31.2 –31.0 –30.8 –30.6 –30.4 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 IFIN CLIP POINT – dBm VDDx – V VDDx – V TPC 5a.CDF of Minimum VGA TPC 5b.Minimium VGA Attenuation TPC 5c.Minimium VGA Attenuation Attenuation Clip Point (VDDx = 3.0V, Clip Point vs. Supply (High Bias2) Clip Point vs. Supply (Low Bias3) High Bias2) 16 18 100 ANALOG ANALOG 14 (IDDA, IDDF, AND IDDI) 16 (IDDA, IDDF, AND IDDI) 80 mA12 mA14 AGE – % 60 –40(cid:1)C +25(cid:1)C +85(cid:1)C RENT – 10 RENT – 1120 PERCENT 4200 SUPPLY CUR 648 (IDDD, IDDDIGCI,T AANLD IDDL) SUPPLY CUR 486 (IDDD, IDDDIGCI,T AANLD IDDL) DIGITAL INTERFACE 2 (IDDH) 2 DIGITAL INTERFACE (IDDH) 0 0 0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 13 15 17 19 21 23 25 2.7 3.0 3.3 3.6 SUPPLY CURRENT – mA fCLK – MHz VDDx – V TPC 6a.CDF of Supply Current TPC 6b.Supply Current vs. f TPC 6c.Supply Current vs. Supply CLK (VDDx = 3.0 V, High Bias2) (VDDx = 3.0 V, High Bias2) (High Bias2) 1Data taken with Toko FSLM series 10 µH inductors. 2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01. 3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01. REV. A –9–

AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f = 18 MSPS, f = 109.56 MHz, f = 107.4 MHz, CLK IF LO T = 25(cid:1)C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 A 0.1 9.0 0 –12 HIGH BIAS 0 8.8 –10 –15 –0.1 8.6 Bc GAIN VARIATION – dB–––––00000.....26345 LOW BIASHIGH BIAS NOISE FIGURE – dBc 787878......448062 NNIMFFD--HL-LIOGOWHW BB BIIAAIASSS –––––2463500000MD w/ IFIN = –36 dBm – d dBm–––––3222104178 LOW BIAS I –0.7 7.2 IMD-HIGH BIAS –70 –33 –0.8 7.0 –80 –36 –20 –17 –14 –11 –8 –5 –20 –15 –10 –5 0 5 –36 –30 –24 –18 –12 –6 0 LO DRIVE – dBm LO DRIVE – dBm IFIN – dBm TPC 7a.Normalized Gain Variation TPC 7b.Noise Figure and IMD TPC 7c.Gain Compression vs. IFIN vs. LO Drive (VDDx = 3.0 V) vs. LO Drive (VDDx = 3.0 V) with 16 dB LNA Attenuator Enabled 0 0 0 NBW = 3.66kHz ADC GOES INTO ADC DOES NOT GO INTO –20 –2.8dBFS OUTPUT MAfCXL KV G= A18 AMTHTEzN –2 HARD COM3P.6RVESSION –2 HARD COMPRE3.S6SVION DEC–BY–120 3.3V 3.3V –40 –4 –4 dBFS––6800 dBFS ––86 2.73V.0V dBFS ––86 2.7V3.0V –100 –10 –10 –120 –12 –12 –140 –14 –14 –80 –60 –40 –20 0 20 40 60 80 –30 –28 –26 –24 –22 –20 –18 –16 –30 –28 –26 –24 –22 –20 –18 –16 –14 FREQUENCY – kHz IFIN – dBm IFIN – dBm TPC 8a.Complex FFT of Baseband TPC 8b.Gain Compression vs. IFIN TPC 8c. Gain Compression vs. IFIN I/Q for Single-Tone (High Bias) (High Bias2) (Low Bias3) 0 –70 –15 –55 –15 NBW = 3.66kHz –20 –18.2dBFS OUTPUT MAfCXL KV G= A18 AMTHTEzN –76 PIN –18 –61 PIN –18 DEC–BY–120 –82 –21 –67 –21 2.7V 2.7V –40 –88 –24 –73 –24 dBFS––6800 IMD = 74dBc IMD – dBc–––11900406 3.3V3.0V –––332037PIN – dBFS IMD – dBc–––789951 3.3V3.0V –––332037PIN – dBFS –100 –112 –36 –97 –36 3.6V 3.6V –118 –39 –103 –39 –120 –124 –42 –109 –42 –140 –130 –45 –115 –45 –80 –60 –40 –20 0 20 40 60 80 –51 –48 –45 –42 –39 –36 –33 –30 –51 –48 –45 –42 –39 –36 –33 –30 FREQUENCY – kHz IFIN – dBm IFIN – dBm TPC 9a.Complex FFT of Baseband TPC 9b.IMD vs. IFIN (High Bias2) TPC 9c.IMD vs. IFIN (Low Bias3) I/Q for Dual Tone IMD (High Bias with Each IFIN Tone @ –35 dBm) 1Data taken with Toko FSLM series 10 µH inductors. 2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01. 3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01. –10– REV. A

AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f = 18 MSPS, f = 109.56 MHz, f = 107.4 MHz, CLK IF LO T = 25(cid:1)C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 A 10.0 10.0 10.0 16-BIT DATA w/ DVGA 16-BIT ENABLED 9.5 I/Q DATA 16-BIT 9.5 9.5 I/Q DATA 16-BIT – dB EwN/A DBVLGEAD – dB DATA 16-BIT DATA – dB 1D6A-BTAIT 2D4A-BTAIT E 9.0 E 9.0 w/ DVGA E 9.0 UR UR ENABLED UR G G G FI FI FI E 8.5 E 8.5 E 8.5 S S S OI OI OI N N N 8.0 8.0 8.0 24-BIT 24-BIT I/Q DATA DATA 7.5 7.5 7.5 10 100 1000 10 100 1000 10 100 1000 CHANNEL BANDWIDTH – kHz CHANNEL BANDWIDTH – kHz CHANNEL BANDWIDTH – kHz TPC 10a.Noise Figure vs. BW (Mini- TPC 10b.Noise Figure vs. BW (Mini- TPC 10c.Noise Figure vs. BW (Mini- mum Attenuation, f = 13 MSPS) mum Attenuation, f = 18 MSPS) mum Attenuation, f = 26 MSPS) CLK CLK CLK 11.5 14 14 11.0 13 13 BW = 135.42kHz (K = 1, M = 1) 10.5 BW = 27.08kHz BW = 75kHz B (K = 0, M = 3) B12 (K = 0, M = 1) B12 BW = 90.28kHz RE – d109..50 B(WK == 01,2 M.0 4=k 8H)z RE – d11 (BKW = =0 , 5M0 k=H 2z) RE – d11 (K = 1, M = 2) U U U G G G E FI 9.0 BW = 6.78kHz E FI10 BW = 15kHz E FI10 OIS 8.5 (K = 0, M = 15) OIS (K = 0, M = 9) OIS B(WK == 12,7 M.0 8=k 9H)z N N 9 N 9 8.0 8 8 7.5 7.0 7 7 0 3 6 9 12 0 3 6 9 12 0 3 6 9 12 VGA ATTENUATION – dB VGA ATTENUATION – dB VGA ATTENUATION – dB TPC 11a.Noise Figure vs. VGA TPC 11b.Noise Figure vs. VGA TPC 11c.Noise Figure vs. VGA Attenuation (f = 13 MSPS) Attenuation (f = 18 MSPS) Attenuation (f = 26 MSPS) CLK CLK CLK –30 –5 –30 –5 –30 –5 –40 –10 –40 –10 –40 –10 –50 –50 –50 PIN –15 PIN –15 PIN –15 –60 –60 –60 IMD – dBc–––789000 LOW HBIIGAHS BIAS –––322005POUT – dBFS IMD – dBc–––789000 LOW BHIIAGSH BIAS –––322005PIN – dBFS IMD – dBc–––789000 LOW BHIIAGSH BIAS –––322005PIN – dBFS –100 –100 –100 –35 –35 –35 –110 –110 –110 –120 –40 –120 –40 –120 –40 –130 –45 –130 –45 –130 –45 –45 –42 –39 –36 –33 –30 –27 –24 –45 –42 –39 –36 –33 –30 –27 –24 –45 –42 –39 –36 –33 –30 –27 –24 IFIN – dBm IFIN – dBm IFIN – dBm TPC 12a.IMD vs. IFIN (fCLK = 13 MSPS) TPC 12b. IMD vs. IFIN (fCLK = 18 MSPS) TPC 12c.IMD vs. IFIN (fCLK = 26 MSPS) 1Data taken with Toko FSLM series 10 µH inductors. 2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01. 3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01. REV. A –11–

AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f = 18 MSPS, f = 109.56 MHz, f = 107.4 MHz, CLK IF LO T = 25(cid:4)C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 A 13 13 4 16-BIT w/DVGA 16-BIT w/DVGA 12 12 2 HIGH BIAS B11 B11 0 d d – – RE 10 RE 10 Bm –2 GU 24-BIT GU – d SE FI 9 SE FI 9 24-BIT IIP3 –4 OI OI N 8 N 8 –6 LOW BIAS 7 7 –8 6 6 –10 0 50 100150200250300350400450500 0 50 100150200250300350400450500 0 50 100150200250300350400450500 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz TPC 13a.Noise Figure vs. Frequency TPC 13b. Noise Figure vs. Frequency TPC 13c.Input IP3 vs. Frequency (Minimum Attenuation, f = 18 MSPS, (Minimum Attenuation, f = 18 MSPS, (f = 18 MSPS) CLK CLK CLK BW = 10 kHz, High Bias) BW = 10 kHz, Low Bias) 13 13 2 16-BIT w/DVGA HIGH BIAS 12 12 0 B11 B11 – d 16-BIT w/DVGA – d –2 RE 10 RE 10 Bm U U d SE FIG 9 SE FIG 9 IIP3 – –4 OI OI –6 N 8 N 8 LOW BIAS 24-BIT 24-BIT –8 7 7 6 6 –10 0 50 100150200250300350400450500 0 50 100150200250300350400450500 0 50 100150200250300350400450500 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz TPC 14a.Noise Figure vs. Frequency TPC 14b. Noise Figure vs. Frequency TPC 14c.Input IP3 vs. Frequency (Minimum Attenuation, f = 26 MSPS, (Minimum Attenuation, f = 26 MSPS, (f = 26 MSPS) CLK CLK CLK BW = 24 kHz, High Bias) BW = 24 kHz, Low Bias) 20.0 128 16 256 16 128 AGC AGC ATTN 18.5 112 15 224 15 AGC ATTN 17.0 96 E 14 192E 14 96 E c U c U c U B L B L B L d A d A d A FIGURE – 1154..50 8604 GC ATTN V FIGURE – 1132 116208GC ATTN V FIGURE – 1132 NOISE FIGURE 64 GC ATTN V OISE 12.5 NOISE FIGURE 48 AN A OISE 11 NOISE FIGURE 96 AN A OISE 11 AN A N11.0 32 ME N10 64 ME N10 32 ME 9.5 16 9 32 9 8.0 0 8 0 8 0 –55–50–45–40–35–30–25–20–15–10 –5 –50 –45 –40 –35 –30 –25 –20 –15 –10 –65 –55 –45 –35 –25 –15 –5 INTERFERER LEVEL – dBm INTERFERER LEVEL – dBm INTERFERER LEVEL – dBm TPC 15a.Noise Figure vs. Interferer TPC 15b.Noise Figure vs. Interferer TPC 15c.Noise Figure vs. Interferer Level (16-Bit Data, BW = 12.5 kHz, Level (16-Bit Data with DVGA, BW = Level (24-Bit Data, BW = 12.5 kHz, AGCR = 1, f = f + 110 kHz) 12.5 kHz, AGCR = 1, f = AGCR = 1, f = f + 110 kHz) INTERFERER IF INTERFERER INTERFERER IF f + 110 kHz) IF 1Data taken with Toko FSLM series 10 µH inductors. 2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01. 3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01. –12– REV. A

AD9874 SERIAL PERIPHERAL INTERFACE (SPI) The serial peripheral interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed below as well as to read back their contents. TableI provides a list of the registers that may be programmed through the SPI port. Addresses and default values are given in hexadecimal form. Table I. SPI Address Map Address Bit (Hex) Breakdown Width Default Value Name Description POWER CONTROL REGISTERS 0x00 (7:0) 8 0xFF STBY Standby Control Bits (REF, LO, CKO, CK, GC, LNAMX, Unused, and ADC). 0x01 (7:6) 2 0 LNAB LNA Bias Current (0 = 0.5 mA, 1 = 1 mA, 2 = 2 mA, 3 = 3 mA). (5:4) 2 0 MIXB Mixer Bias Current (0 = 0.5 mA, 1 = 1.5 mA, 2 = 2.7 mA, 3 = 4 mA). (3:2) 2 0 CKOB CK Oscillator Bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.40 mA, 3 = 0.65 mA). (1:0) 2 0 ADCB Do not use. 0x02 (7:0) 8 0x00 TEST Factory Test Mode. Do not use. AGC 0x03 (7) 1 0 ATTEN Apply 16 dB attenuation in the front end. (6:0) 7 0x00 AGCG(14:8) AGC Attenuation Setting (7 MSB of a 15-Bit Unsigned Word). 0x04 (7:0) 8 0x00 AGCG(7:0) AGC Attenuation Setting (8 LSB of a 15-Bit Unsigned Word). Default corresponds to maximum gain. 0x05 (7:4) 4 0 AGCA AGC Attack Bandwidth Setting. Default yields 50 Hz raw loop bandwidth. (3:0) 4 0 AGCD AGC Decay Time Setting. Default is decay time = attack time. 0x06 (7) 1 0 AGCV Enable digital VGA to increase AGC range by 12 dB. (6:4) 3 0 AGCO AGC Overload Update Setting. Default is slowest update. (3) 1 0 AGCF Fast AGC (Minimizes resistance seen between GCP and GCN). (2:0) 3 0 AGCR AGC Enable/Reference Level (Disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB below Clip). DECIMATION FACTOR 0x07 (7:5) 3 Unused (4) 1 0 K Decimation Factor = 60 (cid:6) (M + 1), if K = 0; 48 (cid:6) (M + 1), if K = 1. (3:0) 4 4 M Default is Decimate-by-300. LO SYNTHESIZER 0x08 (5:0) 6 0x00 LOR(13:8) Reference Frequency Divisor (6 MSB of a 14-Bit Word). 0x09 (7:0) 8 0x38 LOR(7:0) Reference Frequency Divisor (8 LSB of a 14-Bit Word). Default (56) yields 300 kHz from f = 16.8 MHz. REF 0x0A (7:5) 3 0x5 LOA “A” Counter (Prescaler Control Counter). (4:0) 5 0x00 LOB(12:8) “B” Counter MSB (5 MSB of a 13-Bit Word). Default LOA and LOB values yield 300 kHz from 73.35 MHz to 2.25 MHz. 0x0B (7:0) 8 0x1D LOB(7:0) “B” Counter LSB (8 LSB of a 13-Bit Word). 0x0C (6) 1 0 LOF Enable fast acquire. (5) 1 0 LOINV Invert charge pump (0 = source current to increase VCO frequency). (4:2) 3 0 LOI Charge Pump Current in Normal Operation. I = (LOI + 1) (cid:6) 0.625 mA. PUMP (1:0) 2 3 LOTM Manual Control of LO Charge Pump (0 = Off, 1 = Up, 2 = Down, 3 = Normal). 0x0D (5:0) 4 0x0 LOFA(13:8) LO Fast Acquire Time Unit (6 MSB of a 14-Bit Word). 0x0E (7:0) 8 0x04 LOFA(7:0) LO Fast Acquire Time Unit (8 LSB of a 14-Bit Word). REV. A –13–

AD9874 Table I. SPI Address Map (continued) Address Bit (Hex) Breakdown Width Default Value Name Description CLOCK SYNTHESIZER 0x10 (5:0) 6 00 CKR(13:8) Reference Frequency Divisor (6 MSB of a 14-Bit Word). 0x11 (7:0) 8 0x38 CKR(7:0) Reference Frequency Divisor (8 LSB of a 14-Bit Word). Default yields 300 kHz from f =16.8 MHz; Min = 3, Max = 16383. REF 0x12 (4:0) 5 0x00 CKN(12:8) Synthesized Frequency Divisor (5 MSB of a 13-Bit Word). 0x13 (7:0) 8 0x3C CKN(7:0) Synthesized Frequency Divisor (8 LSB of a 13-Bit Word). Default yields 300 kHz from f = 18 MHz; Min = 3, Max = 8191. CLK 0x14 (6) 1 0 CKF Enable fast acquire. (5) 1 0 CKINV Invert charge pump (0 = source current to increase VCO frequency). (4:2) 3 0 CKI Charge Pump Current in Normal Operation. I = (CKI + 1) (cid:6) 0.625 mA. PUMP (1:0) 2 3 CKTM Manual Control of CLK Charge Pump (0 = Off, 1 = Up, 2 = Down, 3 = Normal). 0x15 (5:0) 6 0x0 CKFA(13:8) CK Fast Acquire Time Unit (6 MSB of a 14-Bit Word). 0x16 (7:0) 8 0x04 CKFA(7:0) CK Fast Acquire Time Unit (8 LSB of a 14-Bit Word). SSI CONTROL 0x18 (7:0) 8 0x12 SSICRA SSI Control Register A. See TableIII. (Default is FS and CLKOUT three-stated.) 0x19 (7:0) 8 0x07 SSICRB SSI Control Register B. See TableIII. (16-bit data, maximum drive strength.) 0x1A (3:0) 4 1 SSIORD Output Rate Divisor. f = f /SSIORD. CLKOUT CLK ADC TUNING 0x1C (1) 1 0 TUNE_LC Perform tuning on the LC portion of the ADC (cleared when done). (0) 1 0 TUNE_RC Perform tuning on the RC portion of the ADC (cleared when done). 0x1D (2:0) 3 0 CAPL1(2:0) Coarse Capacitance Setting for LC Tank (LSB is 25 pF, Differential). 0x1E (5:0) 6 0x00 CAPL0(5:0) Fine Capacitance Setting for LC Tank (LSB is 0.4 pF, Differential). 0x1F (7:0) 8 0x00 CAPR Capacitance Setting for RC Resonator (64 LSB of Fixed Capacitance). TEST REGISTERS AND SPI PORT READ ENABLE 0x37– (7:0) 8 0x00 TEST Factory Test Mode. Do not use. 0x39 0x3A (7:4, 2:0) 7 0x0 TEST Factory Test Mode. Do not use. (3) 1 0 SPIREN Enable read from SPI port. 0x3B (7:4, 2:0) 7 0x0 TEST Factory Test Mode. Do not use. (3) 1 0 TRI Three-state DOUTB. 0x3C– (7:0) 1 0x00 TEST Factory Test Mode. Do not use. 0x3E 0x3F (7:0) 8 Subject to ID Revision ID (Read-Only); A write of 0x99 to this register is equivalent to Change a power-on reset. –14– REV. A

AD9874 SERIAL PORT INTERFACE (SPI) shifted into the data pin (PD) on the rising edge of the next The serial port of the AD9874 has 3-wire or 4-wire SPI capability, eight clock cycles. PE stays low during the operation and goes allowing read/write access to all registers that configure the high at the end of the transfer. If PE rises before the eightclock device’s internal parameters. The default 3-wire serial commu- cycles have passed, the operation is aborted. nication port consists of a clock (PC), peripheral enable (PE), and If PE stays low for an additional eight clock cycles, the destina- bidirectional data (PD) signal. The inputs to PC, PE, and PD tion address is incremented and another eight bits of data are contain a Schmitt trigger with a nominal hysteresis of 0.4V shifted in. Again, should PE rise early, the current byte is centered about the digital interface supply (i.e., VDDH/2). ignored. By using this implicit addressing mode, the entire A 4-wire SPI interface can be enabled by setting the MSB of the chip can be configured with a single write operation. Regis- SSICRB register (Reg. 0x19, Bit 7), resulting in the output data ters identified as being subject to frequent updates, namely also appearing on the DOUTB pin. Note that since the default those associated with power control and AGC operation, have power-up state sets DOUTB low, bus contention is possible for been assigned adjacent addresses to minimize the time required systems sharing the SPI output line. To avoid any bus contention, to update them. Note that multibyte registers are big-endian the DOUTB pin can be three-stated by setting the fourth control (the most significant byte has the lower address) and are updated bit in the three-state bit (Reg 0x3B, Bit 3). This bit can then be when a write to the least significant byte occurs. toggled to gain access to the shared SPI output line. Figure 1b illustrates the timing for a read operation to the SPI An 8-bit instruction header must accompany each read and port. Although the AD9874 does not require read access for write SPI operation. Only the write operation supports an auto- proper operation, it is often useful in the product development increment mode, allowing the entire chip to be configured in a phase or for system authentication. Note that the readback single write operation. The instruction header is shown in enable bit (Register 0x3A, Bit 3) must be set for a read opera- Table II. It includes a read/not-write indicator bit, six address tion with a 3-wire SPI interface. After the peripheral enable bits, and a don’t care bit. The data bits immediately follow the (PE) signal goes low, data (PD) pertaining to the instruction instruction header for both read and write operations. Note that header is read on the rising edges of the clock (PC). A read the address and data are always given MSB first. operation occurs if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data Table II. Instruction Header Information bits pertaining to the specified register are shifted out of the MSB LSB data pin (PD) on the falling edges of the next eight clock cycles. I7 I6 I5 I4 I3 I2 I1 I0 If the 4-wire SPI interface is enabled, the eight data bits will also appear on the DOUTB pin with the same timing relation- R/W A5 A4 A3 A2 A1 A0 X ship as those appearing at PD. After the last data bit is shifted Figure 1a illustrates the timing requirements for a write opera- out, the user should return PE high, causing PD to become tion to the SPI port. After the peripheral enable (PE) signal goes three-stated and return to its normal status as an input pin. low, data (PD) pertaining to the instruction header is read on Since the auto increment mode is not supported for read opera- the rising edges of the clock (PC). To initiate a write operation, tions, an instruction header is required for each register read the read/not-write bit is set low. After the instruction header is operation and PE must return high before initiating the next read, the eight data bits pertaining to the specified register are read operation. tS tCLK tH PE t t HI LOW PC t DS t PD R/WDH A5 A4 A0 DCOANR’ET D7 D6 D1 D0 Figure 1a.SPI Write Operation Timing PE tS tCLK tHI tLOW PC t tDV tEZ DS t DH PD R/W A5 A1 A0 DCOANR’ET D7 D6 D1 D0 DOUTB DON’T DON’T DON’T DON’T DON’T D7 D6 D1 D0 DON’T CARE CARE CARE CARE CARE CARE Figure 1b.SPI Read Operation Timing REV. A –15–

AD9874 SYNCHRONOUS SERIAL INTERFACE (SSI) The two optional bytes follow the I and Q data as a 16-bit The AD9874 provides a high degree of programmability of its word provided that the AAGC bit of SSICRA is not set. If SSI output data format, control signals, and timing parameters the AAGC bit is set, the two bytes follow the I and Q data in to accommodate various digital interfaces. In a 3-wire digital an alternating fashion. In this alternate AGC data mode, the interface, the AD9874 provides a frame sync signal (FS), a LSB of the byte containing the AGC attenuation is a 0, while clock output (CLKOUT), and a serial data stream (DOUTA) the LSB of the byte containing reset and RSSI information is signal to the host device. In a 2-wire interface, the frame sync always a 1. information is embedded into the data stream, thus only In a 2-wire interface, the embedded frame sync bit (EFS) within CLKOUT and DOUTA output signals are provided to the the SSICRA register is set to 1. In this mode, the framing infor- host device. The SSI control registers are SSICRA, SSICRB, mation is embedded in the data stream, with each eight bits of and SSIORD. Table III shows the different bit fields associated data surrounded by a start bit (low) and a stop bit (high), and with these registers. each frame ends with at least 10 high bits. FS remains either The primary output of the AD9874 is the converted I and Q low or three-stated (default), depending on the state of the demodulated signal available from the SSI port as a serial bit SFST bit. Other control bits can be used to invert the frame stream contained within a frame. The output frame rate is equal sync (SFSI), to delay the frame sync pulse by one clock to the modulator clock frequency (f ) divided by the digital period (SLFS), to invert the clock (SCKI), or to three-state the CLK filter’s decimation factor that is programmed in the Decimator clock (SCKT). Note that if EFS is set, SLFS is a don’t care. Register (0x07). The bit stream consists of an I word followed by a Q word, where each word is either 24 bits or 16 bits long Table III. SSI Control Registers and is given MSB first in twos complement form. Two optional Name Width Default Description bytes may also be included within the SSI frame following the Qword. One byte contains the AGC attenuation and the other besyttiem caotne toafi ntsh eb orethce aiv ceodu snigt noaf lm amodpuliltautodre r(erseelat teivvee nttos faunlld s acnale SSICRA (ADDR = 0x18) AGCAGCFSFSTFSILFSCKTCKI AEESSSSS of the AD9874’s ADC). Figure 2 illustrates the structure of the SSI data frames in a number of SSI modes. AAGC 1 0 Alternate AGC Data Bytes. EAGC 1 0 Embed AGC data. 24-Bit I AND Q, EAGC = 0, AAGC = X: 48 DATA BITS EFS 1 0 Embed frame sync. SFST 1 1 Three-state frame sync. I (24:0) Q (24:0) SFSI 1 0 Invert frame sync. SLFS 1 0 Late Frame Sync (1 = Late, 0 = Early). 24-Bit I AND Q, EAGC = 1, AAGC = 0:64 DATA BITS SCKT 1 1 Three-state CLKOUT. SCKI 1 0 Invert CLKOUT. I (24:0) Q (24:0) ATTN (7:0) SSI(5:0) I 210 RESET COUNT SSICRB (ADDR = 0x19) P W___ S SSS 16-Bit I AND Q, EAGC = 0, AAGC = X:32 DATA BITS _ DDDD 4 I (15:0) Q (15:0) 4_SPI 1 0 Enable 4-Wire SPI Interface for SPI Read operation via DOUTB. 16-Bit I AND Q, EAGC = 1, AAGC = 0:48 DATA BITS DW 1 0 I/Q Data-Word Width (0 = 16 bit, 1 bit–24 bit). I (15:0) Q (15:0) ATTN (7:0) SSI(5:0) Automatically 16-bit when the AGCV = 1. DS 3 7 FS, CLKOUT, and DOUT Drive 16-Bit I AND Q, EAGC = 1, AAGC = 1:40 DATA BITS Strength. I (15:0) Q (15:0) ATTN (7:1)0 3210 I (15:0) Q (15:0) SSI(5:1)1 SSIORD (ADDR = 0x1A) V_V_V_V_ DIDIDIDI RESET COUNT Figure 2.SSI Frame Structure DIV 4 1 Output Bit Rate Divisor fCLKOUT = fCLK/SSIORD. The two optional bytes are output if the EAGC bit of SSICRA is set. The first byte contains the 8-bit attenuation setting (0 = The SSIORD register controls the output bit rate (f ) of no attenuation, 255 = 24 dB of attenuation), while the second CLKOUT the serial bit stream. f can be set to equal the modulator byte contains a 2-bit reset field and 6-bit received signal CLKOUT clock frequency (f ) or an integer fraction of it. Itis equal to strength field. The reset field contains the number of modula- CLK f divided by the contents of the SSIORD register. Note that tor reset events since the last report, saturating at 3. The received CLK f should be chosen such that it does not introduce harm- signal strength (RSSI) field is a linear estimate of the signal CLKOUT ful spurs within the pass band of the target signal. Users must strength at the output of the first decimation stage; 60 corre- verify that the output bit rate is sufficient to accommodate the sponds to a full-scale signal. required number of bits per frame for a selected word size and decimation factor. Idle (high) bits are used to fill out each frame. –16– REV. A

AD9874 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 ATTN7 ATTEN6 RSSI0 SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC = 0 CLKOUT FS HI-Z START START START DOUT BIT I15 I8 STOP BIT I7 I0 STOP BIT Q15 BIT BIT SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0 IDLE (HIGH) BITS SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 0, EAGC = 0: AS ABOVE, BUT FS IS LOW Figure 3a.SSI Timing for Several SSICRA Settings with 16-Bit I/Q Data Table IV. An example helps illustrate how the maximum SSIORD setting Number of Bits per Frame for Different SSICR Settings is determined. Suppose a user selects a decimation factor of 600 (Register 0x07, K = 0, M = 9) and prefers a 3-wire interface Number of Bits with a dedicated frame sync (EFS = 0) containing 24-bit data DW EAGC EFS AAGC per Frame (DW = 1) with nonalternating embedded AGC data included 0 (16-bit) 0 0 NA 32 (EAGC = 1, AAGC = 0). Referring to TableIV, each frame 0 1 NA 49* will consist of 64 data bits. Using Equation 1, the maximum SSIORD setting is 9 (= TRUNC(600/64)). Thus, the user 1 0 0 48 can select any SSIORD setting between 1 and 9. 1 0 1 40 Figure 3a illustrates the output timing of the SSI port for several 1 1 0 69* SSI control register settings with 16-bit I/Q data, while Figure3b 1 1 1 59* shows the associated timing parameters. Note that the same timing 1 (24-bit) 0 0 NA 48 relationship holds for 24-bit I/Q data, with the exception that I 0 1 NA 69* and Qword lengths now become 24 bits. In the default mode of 1 0 0 64 the operation, data is shifted out on rising edges of CLKOUT 1 0 1 56 after a pulse equal to a clock period is output from the Frame Sync (FS) pin. As described above, the output data consists of a 1 1 0 89* 16- or 24-bit I sample followed by a 16- or 24-bit Q sample, 1 1 1 79* plus two optional bytes containing AGC and status information. *The number of bits per frame with embedded frame sync (EFS = 1) assume at tCLK least 10 idle bits are desired. t t HI LOW The maximum SSIORD setting can be determined by the equation CLKOUT SSIORD≤TRUNC{(Dec.Factor)/ tV (1) (#ofBitsperFrame)} FS t where TRUNC is the truncated integer value. DV DOUT I15 I14 Table IV lists the number of bits within a frame for 16-bit and Figure 3b. Timing Parameters for SSI Timing* 24-bit output data formats for all of the different SSICR set- *Timing parameters also apply to inverted CLKOUT or FS modes, with t tings. The decimation factor is determined by the contents of DV relative to the falling edge of the CLK and/or FS. Register 0x07. REV. A –17–

AD9874 The AD9874 also provides the means for controlling the Table V. Typical Rise/Fall Times ((cid:7)25%) with switching characteristics of the digital output signals via the a 10 pF Capacitive Load for Each DS Setting DS (drive strength) field of the SSICRB. This feature is useful DS Typ (ns) in limiting switching transients and noise from the digital out- put that may ultimately couple back into the analog signal path, 0 13.5 potentially degrading the AD9874’s sensitivity performance. 1 7.2 Figures 3c and 3d show how the NF can vary as a function of 2 5.0 the SSI setting for an IF frequency of 109.65 MHz. The follow- 3 3.7 ing two observations can be made from these figures: 4 3.2 • The NF becomes more sensitive to the SSI output drive 5 2.8 strength level at higher signal bandwidth settings. 6 2.3 7 2.0 • The NF is dependent on the number of bits within an SSI frame, becoming more sensitive to the SSI output drive Synchronization Using SYNCB strength level as the number of bits is increased. As a result, Many applications require the ability to synchronize one or more one should select the lowest possible SSI drive strength set- AD9874 in a way that causes the output data to be precisely ting that still meets the SSI timing requirements. aligned to an external asynchronous signal. For example, receiver applications employing diversity often require synchronization of 10.0 multiple AD9874 digital outputs. Satellite communication appli- 9.8 cations using TDMA methods may require synchronization 9.6 between payload bursts to compensate for reference frequency 16-BIT I/O DATA drift and Doppler effects. 9.4 B RE – d 9.2 SthYaNt cCleBa rcsa tnh eb ec luoscekd c foourn ttheirss pinu rbpootshe .t hIte i sd eacni macattiivoen- lfoiwlte sri gannadl GU 9.0 the SSI port. The counters in the clock synthesizers are not FI E 8.8 24-BIT I/O DATA reset because it is presumed that the CLK signals of multiple S NOI 8.6 chips would be connected. SYNCB also resets the modulator, resulting in a large-scale impulse that must propagate through 8.4 the AD9874’s digital filter and SSI data formatting circuitry 8.2 16-BIT I/O DATA before recovering valid output data. At a result, data samples w/DVGA ENABLED 8.0 unaffected by this SYNCB induced impulse can be recovered 1 2 3 4 5 6 7 12 output data samples after SYNCB goes high (independent of SSI OUTPUT DRIVE STRENGTH SETTING the decimation factor). Figure 3c. NF vs. SSI Output Drive Strength Figure 4a shows the timing relationship between SYNCB and (VDDx = 3.0 V, f = 18 MSPS, BW = 10 kHz) CLK the SSI port’s CLKOUT and FS signals. SYNCB is an asyn- 14 chronous active-low signal that must remain low for at least half an input clock period (i.e., 1/(2 (cid:6) f )). CLKOUT remains CLK 13 high while FS remains low upon SYNCB going low. CLKOUT 24-BIT I/O DATA will become active within one to two output clock periods upon 12 SYNCB returning high. FS will reappear several output cycles B RE – d 11 w1/D6V-BGIAT EI/ON ADBALTAED lSaSteIrO, RdeDp esnedttiinngg .o Nn othtee tdhigatit afol rf ialtneyr’ sd edceicmimataitoionn f afcatcotor ra anndd the U SE FIG 10 16-BIT I/O DATA SprSoIpOeRr Dsy nsecthtrinong,i ztahtiiso nd,e ltahye iFs Sfi xseigdn aanlsd o rfe tpheea tmabulleti.p Tleo A vDer9if8y74 NOI 9 devices should be monitored. SYNCB 8 CLKOUT 7 1 2 3 4 5 6 7 FS SSI OUTPUT DRIVE STRENGTH SETTING Figure 4a.SYNCB Timing Figure 3d. NF vs. SSI Output Drive Strength Interfacing to DSPs (VDDx = 3.0 V, f = 18 MSPS, BW = 75 kHz) CLK The AD9874 connects directly to an Analog Devices programmable Table V lists the typical output rise/fall times as a function of digital signal processor (DSP). Figure 4b illustrates an example DS for a 10pF load. Rise/fall times for other capacitor loads with the Blackfin® series of ADSP-2153x processors. The Blackfin can be determined by multiplying the typical values presented DSP series is a family of 16-bit products optimized for telecommu- in TableV by a scaling factor equal to the desired capacitive nications applications with its dynamic power management feature, load divided by 10 pF. making it well suited for portable radio products. The code compatible family members share the fundamental core attributes of high performance, low power consumption, and the ease-of-use advantages of a microcontroller instruction set. –18– REV. A

AD9874 The AD9874 also allows control over the bias current in the LNA, AD9874 ADSP-2153x mixer, and clock oscillator. The effects on current consumption PC SCK SPI PE SEL and system performance are described in the section dealing SPI-PORT PD MOSI with the affected block. DOUTB MISO SSI CLKOUFST RRSFSCLK SERIAL LO SYNTHESIZER DOUTA DR PORT The LO Synthesizer shown in Figure 5 is a fully programmable PLL capable of 6.25kHz resolution at input frequencies up to Figure 4b. Example of AD9874 and ADSP-2153x Interface 300MHz and reference clocks of up to 25MHz. It consists of a As shown in Figure 4b, AD9874’s synchronous serial interface low noise digital phase-frequency detector (PFD), a variable (SSI) links the receive data stream to the DSP’s Serial Port output current charge pump (CP), a 14-bit reference divider, (SPORT). For AD9874 setup and register programming, the programmable A and B counters, and a dual-modulus 8/9 pres- device connects directly to ADSP-2153x’s SPI port. Dedicated caler. The A (3-bit) and B (13-bit) counters, in conjunction select lines (SEL) allow the ADSP-2153x to program and read with the dual 8/9 modulus prescaler, implement an N divider back registers of multiple devices using only one SPI port. The with N = 8 (cid:1) B + A. In addition, the 14-bit reference counter DSP driver code pertaining to this interface is available on the (R Counter) allows selectable input reference frequencies, fREF, AD9874 web page (http://www.analog.com/Analog_Root/ at the PFD input. A complete PLL (phase-locked loop) can be static/techSupport/designTools/evaluationBoards/ implemented if the synthesizer is used with an external loop ad9874blackfinInterfacing.html). filter and VCO (voltage controlled oscillator). The A, B, and R counters can be programmed via the following POWER CONTROL registers: LOA, LOB, and LOR. The charge pump output cur- To allow power consumption to be minimized, the AD9874 rent is programmable via the LOI register from 0.625mA to possesses numerous SPI programmable power-down and bias 5.0mA using the equation control bits. The AD9874 powers up with all of its functional blocks placed into a standby state (i.e., STBY register default is I PUMP =(LOI+1)×0.625mA (2) 0xFF). Each major block may then be powered up by writing An on-chip fast acquire function (enabled by the LOF bit) a0 to the appropriate bit of the STBY register. This scheme automatically increases the output current for faster settling provides the greatest flexibility for configuring the IC to a spe- during channel changes. The synthesizer may also be disabled cific application as well as for tailoring the IC’s power-down and using the LO standby bit located in the STBY register. wake-up characteristics. Table VI summarizes the function of each of the STBY bits. Note that when all the blocks are in TO EXTERNAL standby, the master reference circuit is also put into standby, f LOOP and thus the current is reduced by a further 0.4 mA. fREF BURFEFFER (cid:2)R REF FDREPETHQEAUCSETENO/CRY CHPUAMRGPE FILTER Table VI. Standby Control Bits LOR fLO FAST Current ACQUIRE LOA, LOB STBY Reduction Wake-Up Bit Effect (mA)1 Time (ms) f 7:REF Voltage reference OFF; 0.6 <0.1 (C COUAN, TBERS (cid:2)8/9 BULFOFER FVLRCOOOM REF all biasing shut down. = 4.7 nF) 6:LO LO synthesizer OFF, 1.2 Note 2 Figure 5.LO Synthesizer IOUTL three-state. The LO (and CLK) synthesizer works in the following manner. 5:CKO Clock Oscillator OFF. 1.1 Note 2 The externally supplied reference frequency, f , is buffered REF 4:CK Clock synthesizer OFF, 1.3 Note 2 and divided by the value held in the R counter. The internal IOUTC three-state. Clock fREF is then compared to a divided version of the VCO fre- buffer OFF if ADC is OFF. quency, fLO. The phase/frequency detector provides UP and DOWN pulses whose widths vary, depending upon the differ- 3:GC Gain control DAC OFF. 0.2 Depends ence in phase and frequency of the detector’s input signals. The GCP and GCN three-state. on C GC UP/DOWN pulses control the charge pump, making current 2:LNAMX LNA and Mixer OFF. CXVM, 8.2 <2.2 available to charge the external low-pass loop filter when there is CXVL, and CXIF three-state. a discrepancy between the inputs of the PFD. The output of the 1:Unused low-pass filter feeds an external VCO whose output frequency, f , is driven such that its divided down version, f , matches 0:ADC ADC OFF; Clock Buffer OFF 9.2 <0.1 LO LO that of f , thus closing the feedback loop. if CLK synthesizer OFF; VCM REF three-state; Clock to the digital The synthesized frequency is related to the reference frequency filter halted; Digital outputs and the LO register contents as follows: static. f =(8×LOB+LOA)/LOR× f (3) LO REF NOTES 1When all blocks are in standby, the master reference circuit is also put into Note that the minimum allowable value in the LOB register is 3 standby, and thus the current is further reduced by 0.4 mA. and its value must always be greater than that loaded into LOA. 2Wake-up time is dependent on programming and/or external components. REV. A –19–

AD9874 An example may help illustrate how the values of LOA, LOB, Fast Acquire Mode and LOR can be selected. Consider an application employing The fast acquire circuit attempts to boost the output current a 13 MHz crystal oscillator (i.e., f = 13 MHz) with the when the phase difference between the divided-down LO REF requirement that f = 100 kHz and f = 143 MHz (i.e., (i.e., f ) and the divided-down reference frequency (i.e., f ) REF LO LO REF high side injection with f = 140.75 MHz and f = 18 MSPS). exceeds the threshold determined by the LOFA register. The IF CLK LOR is selected to be 130 such that f = 100 kHz. The LOFA register specifies a divisor for the f signal that deter- REF REF N-divider factor is 1430, which can be realized by selecting mines the period (T) of this divided-down clock. This period LOB = 178 and LOA = 6. defines the time interval used in the fast acquire algorithm to control the charge pump current. The stability, phase noise, spur performance, and transient response of the AD9874’s LO (and CLK) synthesizers are Assume for the moment that the nominal charge pump current determined by the external loop filter, the VCO, the N-divide is at its lowest setting (i.e., LOI = 0) and denote this minimum factor, and the reference frequency, FREF. A good overview current by I . When the output pulse from the phase compara- 0 of the theory and practical implementation of PLL synthesiz- tor exceeds T, the output current for the next pulse is 2I . 0 ers (featured as a three-part series in Analog Dialogue) can When the pulse is wider than 2T, the output current for the be found at: next pulse is 3I , and so forth, up to eight times the minimum 0 • www.analog.com/library/analogDialogue/archives/33-03/ output current. If the nominal charge pump current is more than the minimum value (i.e., LOI > 0), the preceding rule is phase/index.html only applied if it results in an increase in the instantaneous • www.analog.com/library/analogDialogue/archives/33-05/ charge pump current. If the charge pump current is set to its phase_locked/index.html lowest value (LOI = 0) and the fast acquire circuit is enabled, • www.analog.com/library/analogDialogue/archives/33-07/ the instantaneous charge pump current will never fall below 2I 0 phase3/index.html when the pulsewidth is less than T. Thus, the charge pump current when fast acquire is enabled is given by: Also, a free software copy of the Analog Devices ADIsimPLL, aPLL synthesizer simulation tool, is available at www.analog.com. I =I ×{1+max(1,LOI,Pulsewidth T)} (4) PUMP−FA 0 Note that the ADF4112 model can be used as a close approxima- The recommended setting for LOFA is LOR/16. Choosing a tion to the AD9874’s LO synthesizer when using this software tool. larger value for LOFA will increase T. Thus, for a given phase difference between the LO input and the f input, the instan- REF taneous charge pump current will be less than that available for LOP 84k(cid:1) LO a LOFA value of LOR/16. Similarly, a smaller value for LOFA BUFFER ~VDDL/2 will decrease T, making more current available for the same LON phase difference. In other words, a smaller value of LOFA will FREF enable the synthesizer to settle faster in response to a frequency TO MIXER LO PORT hop than will a large LOFA value. Care must be taken to choose 500(cid:1) 500(cid:1) a value for LOFA that is large enough (values greater than 4 1.75V recommended) to prevent the loop from oscillating back and BIAS forth in response to a frequency hop. NOTES 1. ESD DIODE STRUCTURES OMITTED FOR CLARITY. Table VII. SPI Registers Associated with LO Synthesizer 2. FREF STBY SWITCHES SHOWN WITH LO SYNTHESIZER ON. Address Bit Default Figure 6.Equivalent Input of LO and REF Buffers (Hex) Breakdown Width Value Name Figure 6 shows the equivalent input structures of the synthesiz- ers’ LO and REF buffers (excluding the ESD structures). 0x00 (7:0) 1 0xFF STBY The LO input is fed to the LO synthesizer’s buffer as well as 0x08 (5:0) 6 0x00 LOR(13:8) the AD9874’s mixer’s LO port. Both inputs are self-biasing and thus tolerate ac-coupled inputs. The LO input can be 0x09 (7:0) 8 0x38 LOR(7:0) driven with a single-ended or differential signal. Single-ended 0x0A (7:5) 3 0x5 LOA dc-coupled inputs should ensure sufficient signal swing above (4:0) 5 0x00 LOB(12:8) and below the common-mode bias of the LO and REF buffers (i.e., 1.75 V and VDDL/2). Note that the f input is slew rate 0x0B (7:0) 8 0x1D LOB(7:0) REF dependent and must be driven with input signals exceeding 0x0C (6) 1 0 LOF 7.5 V/(cid:1)s to ensure proper synthesizer operation. If this con- (5) 1 0 LOINV dition can not be met, an external logic gate can be inserted (4:2) 3 0 LOI prior to the fREF input to “square-up” the signal thus allowing a (1:0) 2 0 LOTM f input frequency approching dc. REF 0x0D (3:0) 4 0x0 LOFA(13:8) 0x0E (7:0) 8 0x04 LOFA(7:0) –20– REV. A

AD9874 CLOCK SYNTHESIZER is approximately determined by L and the series equivalent OSC The clock synthesizer is a fully programmable integer-N PLL capacitance of C and C . As a result, L , C , and OSC VAR OSC OSC capable of 2.2kHz resolution at clock input frequencies up to C should be selected to provide a sufficient tuning range to VAR 18MHz and reference frequencies up to 25MHz. It is similar ensure proper locking of the clock synthesizer. to the LO synthesizer described in Figure 5 with the following The bias, I , of the negative-resistance core has four pro- exceptions: BIAS grammable settings. Lower equivalent Q of the LC tank circuit • It does not include an 8/9 prescaler nor an A counter. may require a higher bias setting of the negative-resistance core to ensure proper oscillation. R should be selected so the • It includes a negative-resistance core that, when used in conjunc- BIAS common-mode voltage at CLKP and CLKN is approximately tion with an external LC tank and varactor, serves as the VCO. 1.6 V. The synthesizer may be disabled via the CK standby bit The 14-bit reference counter and 13-bit N-divider counter can to allow the user to employ an external synthesizer and/or VCO be programmed via registers CKR and CKN. The clock in place of those resident on the IC. Note that if an external frequency, fCLK, is related to the reference frequency by the CLK source or VCO is used, the clock oscillator must be dis- equation abled via the CKO standby bit. ( ) fCLK = CKN CKR × fREF (5) The phase noise performance of the clock synthesizer is depen- The charge pump current is programmable via the CKI register dent on several factors, including the CLK oscillator IBIAS from 0.625mA to 5.0mA using the equation: setting, charge pump setting, loop filter component values, and ( ) internal f setting. Figures 7b and 7c show how the measured I = CKI +1 ×0.625mA (6) REF PUMP phase noise attributed to the clock synthesizer varies (relative to The fast acquire subcircuit of the charge pump is controlled by an external fCLK) as a function of the IBIAS setting and charge the CKFA register in the same manner as the LO synthesizer is pump setting for a –31 dBm IFIN signal at 73.35 MHz with an controlled by the LOFA register. An on-chip lock detect func- external LO signal at 71.1 MHz. Figure 7b shows that the opti- tion (enabled by the CKF bit) automatically increases the mum phase noise is achieved with the highest IBIAS (CKO) output current for faster settling during channel changes. The setting, while Figure 7c shows that the higher charge pump synthesizer may also be disabled using the CK standby bit values provide the optimum performance for the given loop located in the STBY register. filter configuration. The AD9874 clock synthesizer and oscilla- tor were set up to provide an f of 18 MHz from an external CLK VDDC = 3.0 V fREF of 16.8 MHz. The following external component values were selected for the synthesizer: R = 390 Ω, R = 2 kΩ, LOOP F D FILTER RBIAS C = 0.68 µF, C = 0.1 µF, C = 91pF, L = 1.2µH, and RD COSC LOSC CZ = ToshibaP 1SV228 VarOacSCtor. OSC VAR RF CP 0.1(cid:6)F CVAR 0 CZ –10 –20 –30 IOUTC AD9874 CLKP CLKN –40 –50 Hz –60 VCM = VDDC – RBIAS (cid:7) IBIAS > 1.6V Bc/ –70 fOSC > 1/{2(cid:8) (cid:7) (LOSC (cid:7)(CVARACTOR//COSC))1/2} d –80 CKO = 2 –90 CKO = 0 CKO = 3 CLK OSC. BIAS IBIAS = 0.15 mA, 0.25 mA, –100 CKO = 1 2 0.40 mA, OR 0.65 mA –110 EXT CLK –120 –130 Figure 7a.External Loop Filter, Varactor, and LC –140 Tank Are Required to Realize a Complete Clock –25 –20 –15 –10 –5 0 5 10 15 20 25 Synthesizer FREQUENCY OFFSET – kHz The AD9874 clock synthesizer circuitry includes a negative- Figure 7b. CLK Phase Noise vs. I Setting (CKO) BIAS resistance core so that only an external LC tank circuit with a (IF = 73.35 MHz, IF = 71.1 MHz, IFIN = –31 dBm, varactor is needed to realize a voltage controlled clock oscillator f = 18 MHz, f = 16.8 MHz) (CLK SYN Settings: CLK REF (VCO). Figure 7a shows the external components required to CKI = 7, CLR = 56, and CLN = 60 with f = 300 kHz) REF complete the clock synthesizer along with the equivalent input circuitry of the CLK input. The resonant frequency of the VCO REV. A –21–

AD9874 0 2.7V TO 3.6V –10 50(cid:1) –20 –30 –40 L L –50 C Hz –60 Bc/ –70 VDDI MXOP MXON d –80 CP = 0 –90 CP = 2 CP = 4 –100 CP = 6 –110 EXT CLK –120 –130 –140 RBIAS CXVL –25 –20 –15 –10 –5 0 5 10 15 20 25 LO INPUT = FREQUENCY OFFSET – kHz 0.3V p-p TO RGAIN 1.0V p-p Figure 7c. CLK Phase Noise vs. Charge Pump Setting Bias MULTI-TANH CXIF (IF = 73.35 MHz, IF = 71.1 MHz, –31 dBm, fCLK = 18 MHz, RF V–I STAGE f = 16.8 MHz) (CLK SYN Settings: CKO Bias = 3, CKR = 56, REF and CKN = 60 with f = 300 kHz) CXVM REF IFIN Table VIII. SPI Registers Associated with CLK Synthesizer DC SERVO LOOP Address Bit Default (Hex) Breakdown Width Value Name Figure 8.Simplified Schematic of AD9874’s LNA/Mixer 0x00 (7:0) 8 0xFF STBY 600 0x01 (3:2) 2 0 CKOB LNA BIAS = 0 0x10 (5:0) 6 00 CKR(13:8) 550 LNA BIAS = 1 0x11 (7:0) 8 0x38 CKR(7:0) LNA BIAS = 2 (cid:1) 500 0x12 (4:0) 5 0x00 CKN(12:8) – E C 0x13 (7:0) 8 0x3C CKN(7:0) AN 450 T S LNA BIAS = 3 0x14 (6) 1 0 CKF SI (5) 1 0 CKINV RE 400 (4:2) 3 0 CKI (1:0) 1 0 CKTM 350 0x15 (3:0) 4 0x0 CKFA(13:8) 300 0 50 100 150 200 250 300 350 0x16 (7:0) 8 0x04 CKFA(7:0) FREQUENCY – MHz Figure 9a.The Shunt Input Resistance vs. the IF LNA/MIXER Frequency of the AD9874’s IF1 Input The AD9874 contains a single-ended LNA followed by a Gil- bert-type active mixer, shown in Figure 8 with the required 2.5 external components. The LNA uses negative shunt feedback to set its input impedance at the IFIN pin, thus making it depen- 2.0 LNA BIAS = 3 dent on the LNA bias setting and input frequency. It can be LNA BIAS = 2 modeled as approximately 370Ω//1.4 pF (620%) for the higher F p bias settings below 100 MHz. Figures 9a and 9b show the E – 1.5 LNA BIAS = 1 equivalent input impedance versus frequency characteristics of C N A the AD9874 with all the LNA bias settings. The increase in shunt T resistance versus frequency can be attributed to the reduction in PACI 1.0 A LNA BIAS = 0 bandwidth, thus the amount of negative feedback of the LNA. C Note that the input signal into IFIN should be ac-coupled via a 0.5 10 nF capacitor since the LNA input is self-biasing. 0 0 50 100 150 200 250 300 350 FREQUENCY – MHz Figure 9b.The Shunt Capacitance vs. the Frequency of the AD9874’s IF1 Input –22– REV. A

AD9874 The mixer’s differential LO port is driven by the LO buffer 0 stage shown in Figure 6, which can be driven single-ended or fIN = 109.65MHz differential. Since it is self-biasing, the LO signal level can be –20 PIN m ac-coupled and range from 0.3 V p-p to 1.0 V p-p with negligible B d effect on performance. The mixer’s open-collector outputs, R – –40 MXOP and MXON, drive an external resonant tank consisting WE of a differential LCnetwork tuned to the IF of the band-pass PO –60 (cid:3)-(cid:4) ADC (i.e., f = f /8). The two inductors provide a ED TOKO INDUCTOR dc bias path for tIhFe2 _mADixCer coCrLeK via a series resistor of 50 Ω, which ERR –80 PIMD = 2.64 (cid:4) PIN + 4.6 F is included to dampen the common-mode response. The mixer’s RE output must be ac-coupled to the input of the band-pass (cid:3)-(cid:4) ADC, UT –100 P IF2P, and IF2N via two 100 pF capacitors to ensure proper tuning IN–120 COILCRAFT of the LC center frequency. PIMD = 2.92 (cid:4) PIN + 6.9 The external differential LC tank forms the resonant element –140 –54 –48 –42 –36 –30 –24 –18 for the first resonator of the band-pass (cid:3)-(cid:4) modulator, and so must be tuned to the f /8 center frequency of the modulator. Figure 10.IMD Performance between Different Inductors CLK The inductors should be chosen such that their impedance at with LNA and Mixer at Full Bias and fCLK of 18 MHz fCLK/8 is about 140 Ω (i.e., L = 180/fCLK). An accuracy of 20% Both the LNA and mixer have four programmable bias settings so is considered to be adequate. For example, at fCLK = 18MHz, that current consumption can be minimized for a given application. L = 10 µH is a good choice. Once the inductors have been Figures 11a, 11b, and 11c show how the LNA and mixer’s noise selected, the required tank capacitance may be calculated using figure (NF), linearity (IIP3), IF clip point, current consumption, the relation fCLK/8 = 1/{2 (cid:1) (cid:5) (cid:1) (2L (cid:1) C)1/2}. and frequency response are affected for a given LNA/mixer bias For example, at f = 18 MHz and L = 10 µH, a capacitance of setting. The measurements were taken at an IF = 73.35MHz and CLK 250 pF is needed. However, in order to accommodate an induc- LO = 71.1 MHz, with supplies set to 3V. tor tolerance of (cid:6)10%, the tank capacitance must be adjustable 13 –20 from 227 pF to 278 pF. Selecting an external capacitor of 180pF ensures that even with a 10% tolerance and stray capaci- CLIP POINT tances as high as 30 pF, the total capacitance will be less than 12 –18 the minimum value needed by the tank. Extra capacitance is saltisehur areipsan pttyc ol.1ri leeS6edar0isna benpcdyecF etb,tsh hyt ehoe a feAp flArDaoocwD9gt or89car78o m4o7st’fm4s e1 ihox.n4antges4- r cr pnMahlaneiplHng cetpzoy ro mtooof gfp t 2rhroa6aenmn eMcgmnaetHp astab.oz clN eismto ooca tratke hpa eatar htruc aaifptyCto LfiirKofs / rf8aCtLK NOISE FIGURE – dB1110 NOISE FIGURE ––1164 CLIP POINT – dBm becomes 3.25 MHz, reducing L and C by approximately the same factor (i.e., L = 6.9µH and C = 120 pF) still satisfies the 9 –12 requirements stated above. The selection of the inductors is an important consideration in 8 –10 1_0 1_1 1_2 1_3 2_0 2_1 2_2 2_3 3_0 3_1 3_2 3_3 realizing the full linearity performance of the AD9874. This is LNA_MIXER BIAS SETTING true when operating the LNA and mixer at maximum bias and low clock frequency. Figure 10 shows how the two-tone input- Figure 11a.LNA/Mixer Noise Figure and referred IMD versus the input level performance at an IF of Conversion Gain vs. Bias Setting 109 MHz and f of 18 MHz varies between Toko’s FSLM CLK 5 9.50 series and Coilcraft’s 1812CS series inductors. The graph also shows the extrapolated point of intersection used to determine 0 8.25 the IIP3 performance. Note that the Coilcraft inductor provides LNA_MIXER CURRENT a 7 dB to 8 dB improvement in performance and closely approximates the 3:1 slope associated with a third order m –5 7.00 B lTminoaeknaocr eiit nysdi mcuocimltaorpr a.t orTe tdhh eat otC otohfi eltc h2rea. 6f1t5 81:1102 0sCl8oSCp Sese asresiesrsoie.c sIi ats thiesod ww woeidrtt hhp etnhrofeotirn-g PUT IIP3 – d–10 IIP3 5.75 IDDI – mA that the difference in IMD performance between these two IN–15 4.50 inductor families with an f of26MHz is insignificant. CLK –20 3.25 –25 2.00 1_0 1_1 1_2 1_3 2_0 2_1 2_2 2_3 3_0 3_1 3_2 3_3 LNA_MIXER BIAS SETTING Figure 11b.LNA/Mixer IIP3 and Current Consumption vs. Bias Setting REV. A –23–

AD9874 Based on these characterization curves, a LNA/mixer bias BAND-PASS SIGMA-DELTA ((cid:5)-(cid:6)) ADC setting of 3_3 is suitable for most applications since it will The ADC of the AD9874 is shown in Figure 12. The ADC provide the greatest dynamic range in the presence of multiple contains a sixth order multibit band-pass (cid:3)-(cid:4) modulator that unfiltered interferers. However, portable radio applications achieves very high instantaneous dynamic range over a narrow demanding the lowest possible power may benefit by changing frequency band. The loop filter of the band-pass (cid:3)-(cid:4) modulator the LNA/mixer bias setting based on the received signal consists of two continuous-time resonators followed by a discrete- strength power (i.e., RSSI) available from the SSI output data. time resonator, with each resonator stage contributing a pair of For instance, selecting an LNA_Mixer bias setting of 1_2 for complex poles. The first resonator is an external LC tank, while nominal input strength conditions (i.e., <–45 dBm) would the second is an on-chip active RC filter. The output of the LC result in 4 mA current savings (i.e., 18% reduction). If the resonator is ac-coupled to the second resonator input via 100 pF signal exceeds this level, a bias setting of 3_3 could be capacitors. The center frequencies of these two continuous-time selected. Refer to the Typical Performance Characteristics for resonators must be tuned to f /8 for the ADC to function CLK more performance graphs characterizing the LNA and mixer’s properly. The center frequency of the discrete-time resonator effect upon the AD9874’s noise and linearity performance automatically scales with f , thus no tuning is required. CLK under different operating conditions. EXTERNAL LC 0 –1 LNA_MIXER IF2P fCLK = 13 MSPS TO 26 MSPS 3_3 SETTING RC SC NINE- –2 IF2N RESO- RESO- LEVEL MXOP NATOR NATOR FLASH –3 MXON dB –4 LNA_MIXER –5 1_2 SETTING DAC1 ESL TO DIGITAL FILTER –6 MIXER OUTPUT GAIN –7 CONTROL –8 Figure 12.Equivalent Circuit of Sixth Order 0 100 200 300 400 500 Band-Pass (cid:3)-(cid:4) Modulator FREQUENCY – MHz Figure 13a shows the measured power spectral density measured Figure 11c.LNA/Mixer Frequency Response vs. Bias Setting at the output of the undecimated band-pass (cid:3)-(cid:4) modulator. A 16 dB step attenuator is also included within the LNA/ Note that the wide dynamic range achieved at the center fre- mixer circuitry to prevent large signals (i.e., >–18 dBm) quency, f /8, is achievedonce the LC and RC resonators of CLK from overdriving the (cid:3)-(cid:4) modulator. In such instances, the the (cid:3)-(cid:4) modulator have been successfully tuned. The out-of- (cid:3)-(cid:4) modulator will become unstable, thus severely desensitizing band noise is removed by the decimation filters following the receiver. The 16 dB step attenuator can be invoked by set- quadrature demodulation. ting the ATTEN bit (Register 0x03, Bit 7), causing the mixer gain to be reduced by 16 dB. The 16 dB step attenuator could 0 be used in applications in which a potential target or blocker –10 –2dBFS OUTPUT fCLK = 18MHz signal could exceed the IF input clip point. Although the LNA NBW = 3.3kHz –20 will be driven into compression, it may still be possible to recover the desired signal if it is FM. Refer to TPC 7c to see –30 the gain compression characteristics of the LNA and mixer W –40 with the 16 dB attenuator enabled. B N S/ –50 F B Table IX. SPI Registers Associated with LNA/Mixer d –60 –70 Address Bit Default (Hex) Breakdown Width Value Name –80 –90 0x00 (7:0) 8 0xFF STBY –100 0x01 (7:6) 2 0 LNAB 0 1 2 3 4 5 6 7 8 9 FREQUENCY – MHz 0x01 (5:4) 2 0 MIXB Figure 13a. Measured Undecimated Spectral Out- 0x03 (7) 1 0 ATTEN put of (cid:3)-(cid:4) Modulator ADC with f = 18 MSPS CLK and Noise Bandwidth of 3.3 kHz –24– REV. A

AD9874 The signal transfer function of the AD9874 possesses inherent Tuning of the (cid:1)-(cid:2) modulator’s two continuous-time resonators antialias filtering by virtue of the continuous-time portions of is essential in realizing the ADC’s full dynamic range and must the loop filter in the band-pass (cid:1)-(cid:2) modulator. Figure 13b be performed upon system startup. To facilitate tuning of the illustrates this property by plotting the nominal signal transfer LC tank, a capacitor array is internally connected to the MXOP function of the ADC for frequencies up to 2f . The notches and MXON pins. The capacitance of this array is program- CLK that naturally occur for all frequencies that alias to the f /8 mable from 0 pF to 200 pF (cid:7) 20% and can be programmed CLK pass band are clearly visible. Even at the widest bandwidth setting, either automatically or manually via the SPI port. The capaci- the notches are deep enough to provide greater than 80 dB of tors of the active RC resonator are similarly programmable. alias protection. Thus, the wideband IF filtering requirements Note that the AD9874 can be placed in and out of its standby preceding the AD9874 will be determined mostly by the mixer’s mode without retuning since the tuning codes are stored in the image band, which is offset from the desired IF input frequency SPI Registers. by f /4 (i.e., 2 3 f /8) rather than any aliasing associated CLK CLK When tuning the LC tank, the sampling clock frequency must with the ADC. be stable and the LNA/mixer, LO synthesizer, and ADC must all be placed in standby. Tuning is triggered when the ADC is 0 taken out of standby if the TUNE_LC bit of Register 0x1C has been set. This bit will clear when the tuning operation is com- –10 plete (less than 6 ms). The tuning codes can be read from the –20 3-bit CAPL1 (0x1D) and the 6-bit CAPL0 (0x1E) registers. –30 NOTCH AT ALL ALIAS FREQUENCIES In a similar manner, tuning of the RC resonator is activated if the TUNE_RC bit of Register 0x1C is set when the ADC is dB–40 taken out of standby. This bit will clear when tuning is com- plete. The tuning code can be read from the CAPR (0x1F) –50 register. Setting both the TUNE_LC and TUNE_RC bits tunes –60 the LC tank and the active RC resonator in succession. During tuning, the ADC is not operational and neither data nor a clock –70 is available from the SSI port. Table X lists the recommended sequence of the SPI commands for tuning the ADC, and Table XI –80 0 0.5 1.0 1.5 2.0 lists all of the SPI registers associated with band-pass (cid:1)-(cid:2) ADC. NORMALIZED FREQUENCY – RELATIVE TO fOUT Table X. Tuning Sequence Figure 13b.Signal Transfer Function of the Band-Pass (cid:1)-(cid:2) Modulator from 0 f to 2 f CLK CLK Address Value Comments Figure 13c shows the nominal signal transfer function magni- 0x00 0x45 LO synthesizer, LNA/mixer, and ADC are tude for frequencies near the f /8 pass band. The width of the CLK placed in standby.* pass band determines the transfer function droop, but even at the lowest oversampling ratio (48) where the pass band edges 0x1C 0x03 Set TUNE_LC and TUNE_RC. Wait for are at (cid:7) f /192 ((cid:7) 0.005 f ), the gain variation is less than CLK to stabilize if CLK synthesizer used. CLK CLK 0.5 dB. Note that the amount of attenuation offered by the 0x00 0x44 Take the ADC out of standby. Wait for signal transfer function near f /8 should also be considered CLK 0x1C to clear (<6 ms). LNA/mixer can now when determining the narrow-band IF filtering requirements be taken out of standby. preceding the AD9874. *If external CLK VCO or source used, the CLK oscillator must also be disabled. 0 Table XI. SPI Registers Associated with Band-Pass (cid:2)-(cid:3) ADC Address Bit Default –5 (Hex) Breakdown Width Value Name 0x00 (7:0) 8 0xFF STBY B–10 0x1C (1) 1 0 TUNE_LC d (0) 1 0 TUNE_RC 0x1D (2:0) 3 0 CAPL1(2:0) –15 0x1E (5:0) 6 0x00 CAPL1(5:0) 0x1F (7:0) 8 0x00 CAPR –20 –0.10 –0.05 0 0.05 0.10 NORMALIZED FREQUENCY – RELATIVE TO fCLK Figure 13c.Magnitude of the ADC’s Signal Transfer Function near f /8 CLK REV. A –25–

AD9874 Once the AD9874 has been tuned, the noise figure degradation Figure 15a shows the response of the decimation filter at a attributed solely to the temperature drift of the LC and RC decimation factor of 900 (K = 0, M = 14) and a sampling resonators is minimal. Since the drift of the RC resonator is clock frequency of 18MHz. In this example, the output data actually negligible compared to that of the LC resonator, the rate (f ) is 20 kSPS, with a usable complex signal band- OUT external Land C components’ temperature drift characteristics width of 10 kHz centered around dc. As this figure shows, tend to dominate. Figure 13d shows the degradation in noise the first and second alias bands (occurring at even integer figure as the product of the LC value is allowed to vary from multiples of f /2) have the least attenuation but provide at OUT –12.5% to +12.5%. Note that the noise figure remains relatively least 88 dB of attenuation. Note that signals falling around constant over a (cid:7)3.5% range (i.e., (cid:7)35,000 ppm), suggesting frequency offsets that are odd integer multiples of f /2 OUT that most applications will not be required to retune over the (i.e., 10 kHz, 30kHz, and 50 kHz) will fall back into the operating temperature range. transition band of the digital filter. 12 0 –20 BW = 75kHz (cid:9)5.0kHz PASS BAND 11 FOLD- –40 ING POINT dB –88dB –88dB F – 10 dB–60 N BW = 30kHz –101dB –103dB –80 9 BW = 10kHz –100 8 –120 –15 –10 –5 0 5 10 15 0 10 20 30 40 50 60 70 80 90 100 LC ERROR – % FREQUENCY – kHz Figure 13d.Typical Noise Figure Degradation Figure 15a.Decimation Filter Frequency Response from L and C Component Drift (fCLK = 18 MSPS, for fOUT = 20 kSPS (fCLK = 18 MHz, OSR = 900) fIF = 73.3501 MHz) Figure 15b shows the response of the decimation filter with a decimation factor of 48 and a sampling clock rate of 26 MHz. The DECIMATION FILTER alias attenuation is at least 94 dB and occurs for frequencies at the The decimation filter shown in Figure 14 consists of an fCLK/8 edges of the fourth alias band. The difference between the alias complex mixer and a cascade of three linear phase FIR filters: attenuation characteristics of Figure 15b and those of Figure 15a is DEC1, DEC2, and DEC3. DEC1 downsamples by a factor of due to the fact that the third decimation stage decimates by a factor 12 using a fourth order comb filter. DEC2 also uses a fourth of 5 for Figure 15a compared with a factor of 4 for Figure 15b. order comb filter, but its decimation factor is set by the M field of Register 0x07. DEC3 is either a decimate-by-5 FIR filter or a 0 decimate-by-4 FIR filter, depending on the value of the K bit within Register 0x07. Thus, the composite decimation factor –20 can be set to either 60 (cid:6) M or 48 (cid:6) M for K equal to 0 or 1, (cid:9)135.466kHz PASS BAND respectively. –40 The output data rate (f ) is equal to the modulator clock OUT frequency (f ) divided by the digital filter’s decimation factor. CLK B–60 d Due to the transition region associated with the decimation filter’s frequency response, the decimation factor must be –80 –98dB selected such that f is equal to or greater than twice the OUT –94dB signal bandwidth. This ensures low amplitude ripple in the pass –115dB –100 band along with the ability to provide further application-spe- cific digital filtering prior to demodulation. –120 0 0.5 1.0 1.5 2.0 2.5 COS M K FREQUENCY – MHz I Figure 15b.Decimation Filter Frequency Response DEC1 DEC2 DEC3 MOFDRUOLMAD TA(cid:2)OT-(cid:3)AR SIN SFIILNTCE4R 12 SFIILNTCE4R M + 1 FFIILRTER O 45R QCDSASOTIM APP OTLORETX for fOUT = 541.666 kSPS (fCLK = 26 MHz, OSR = 48) Figure 14.Decimation Filter Architecture –26– REV. A

AD9874 Figures 16a and 16b show expanded views of the pass band for the 0 two possible configurations of the third decimation filter. When decimating by 60n (K = 0), the pass-band gain variation is 1.2dB; –20 when decimating by 48n (K = 1), the pass-band gain variation is 0.9dB. Normalization of full scale at band center is accurate to –40 within 0.14dB across all decimation modes. Figures 17a and 17b show the folded frequency response of the decimator for K = 0 B –60 and K = 1, respectively. d 3 –80 MIN ALIAS ATTN = 87.7dB 2 –100 PASS-BAND GAIN FREQUENCY = 1.2dB 1 –120 0 0.25 0.50 NORMALIZED FREQUENCY – RELATIVE TO fOUT B 0 d Figure 17a.Folded Decimator Frequency Response for K = 0 –1 0 –2 –20 –3 –40 0 0.125 0.250 NORMALIZED FREQUENCY – RELATIVE TO fOUT B –60 Figure 16a.Pass-Band Frequency Response of d the Decimator for K = 0 –80 3 MIN ALIAS ATTN = 97.2dB –100 2 PASS-BAND GAIN VARIATION = 0.9dB –120 0 0.25 0.50 1 NORMALIZED FREQUENCY – RELATIVE TO fOUT Figure 17b.Folded Decimator Frequency Response for K = 1 B 0 d –1 –2 –3 0 0.125 0.250 NORMALIZED FREQUENCY – RELATIVE TO fOUT Figure 16b.Pass-Band Frequency Response of the Decimator for K = 1 REV. A –27–

AD9874 I/Q DATA (cid:2)-(cid:3) ADC DEC1 DEC2 TO SSI FS (cid:5)12 DAENCD3 DVGA AGCR REF LEVEL I + Q SELECT 1 LARGER + K (1 – Z–1) I + Q AGCA/AGCD AGCV VGA SCALING SETTING DAC RSSI DATA GCP TO SSI CDAC Figure 18.Functional Block Diagram of VGA and AGC VARIABLE GAIN AMPLIFIER OPERATION WITH Variable Gain Control AUTOMATIC GAIN CONTROL The variable gain control is enabled by setting the AGCR field The AD9874 contains both a variable gain amplifier (VGA) and of Register 0x06 to 0. In this mode, the gain of the VGA (and a digital VGA (DVGA) along with all of the necessary signal the DVGA) can be adjusted by writing to the 16-bit AGCG estimation and control circuitry required to implement auto- register. The maximum update rate of the AGCG register via matic gain control (AGC), as shown in Figure 18. The AGC the SPI port is f /240. The MSB of this register is the bit that CLK control circuitry provides a high degree of programmability, enables 16dB of attenuation in the mixer. This feature allows allowing users to optimize the AGC response as well as the the AD9874 to cope with large level signals beyond the VGA’s AD9874’s dynamic range for a given application. The VGA is range (i.e., > –18 dBm at LNA input) to prevent overloading programmable over a 12 dB range and implemented within the ofthe ADC. ADC by adjusting its full-scale reference level. Increasing the The lower 15 bits specify the attenuation in the remainder of ADC’s full scale is equivalent to attenuating the signal. An the signal path. If the DVGA is enabled, the attenuation range additional 12 dB of digital gain range is achieved by scaling the is from –12 dB to +12 dB since the DVGA provides 12 dB of output of the decimation filter in the DVGA. Note that a slight digital gain. In this case, all 15 bits are significant. However, increase in the supply current (i.e., 0.67 mA) is drawn from with the DVGA disabled, the attenuation range extends from VDDI and VDDF as the VGA changes from 0dB to 12dB 0 dB to 12dB and only the lower 14 bits are useful. Figure 19 attenuation. shows the relationship between the amount of attenuation and The purpose of the VGA is to extend the usable dynamic range the AGC register setting for both cases. of the AD9874 by allowing the ADC to digitize a desired signal over a large input power range as well as recover a low level 12 signal in the presence of larger unfiltered interferers without ONLY VGA ENABLED saturating or clipping the ADC. The DVGA is most useful in extending the dynamic range in narrow-band applications B 6 VGA requiring a 16-bit I and Q data format. In these applications, – d RANGE N quantization noise resulting from internal truncation to 16 bits TIO DVGA AND as well as external 16-bit fixed point post-processing can UA VGA ENABLED N 0 degrade the AD9874’s effective noise figure by 1 dB or more. E T T The DVGA is enabled by writing a 1 to the AGCV field. The A C VGA (and the DVGA) can operate in either a user controlled G A DVGA Variable Gain Mode or Automatic Gain Control (AGC) Mode. –6 RANGE It is worth noting that the VGA imparts negligible phase error upon the desired signal as its gain is varied over a 12 dB range. This is due to the bandwidth of the VGA being far greater than –102000 1FFF 3FFF 5FFF 7FFF the downconverted desired signal (centered about fCLK/8) and AGCG SETTING – HEX remaining relatively independent of gain setting. As a result, Figure 19.AGC Gain Range Characteristics vs. phase modulated signals should experience minimal phase error AGCG Register Setting with and without DVGA as the AGC varies the VGA gain while tracking an interferer or Enabled the desired signal under fading conditions. Note that the enve- lope of the signal will still be affected by the AGC settings. –28– REV. A

AD9874 Referring to Figure 18, the gain of the VGA is set by an 8-bit con- gain to ensure maximum digital gain while not exceeding the trol DAC that provides a control signal to the VGA appearing at programmable reference level. the gain control pin (GCP). For applications implementing auto- This programmable level can be set at 3 dB, 6 dB, 9 dB, 12 dB, matic gain control, the DAC’s output resistance can be reduced and 15 dB below the ADC saturation (clip) level by writing by a factor of 9 to decrease the attack time of the AGC response values from 1 to 5 to the 3-bit AGCR field. Note that the ADC for faster signal acquisition. An external capacitor, C , from DAC clip level is defined to be 2 dB below its full scale (i.e., –18 dBm GCP to analog ground is required to smooth the DAC’s output at the LNA input for a matched input and maximum attenua- each time it updates as well as to filter wideband noise. Note tion). If AGCR is 0, automatic gain control is disabled. Since that C , in combination with the DAC’s programmable out- DAC clipping of the ADC input will degrade the SNR performance, put resistance, sets the –3 dB bandwidth and time constant the reference level should also take into consideration the peak- associated with this RC network. to-rms characteristics of the target (or interferer) signals. A linear estimate of the received signal strength is performed at Referring again to Figure 18, the majority of the AGC loop the output of the first decimation stage (DEC1) and output of operates in the discrete time domain. The sample rate of the the DVGA (if enabled) as discussed in the AGC section. This loop is f /60; therefore, registers associated with the AGC data is available as a 6-bit RSSI field within an SSI frame with CLK algorithm are updated at this rate. The number of overload and 60 corresponding to a full-scale signal for a given AGC attenua- ADC reset occurrences within the final I/Q update rate of the tion setting. The RSSI field is updated at f /60 and can be CLK AD9874, as well as the AGC value (8 MSB), can be read from used with the 8-bit attenuation field (or AGCG attenuation the SSI data upon proper configuration. setting) to determine the absolute signal strength. The AGC performs digital signal estimation at the output of the The accuracy of the mean RSSI reading (relative to the IF input first decimation stage (DEC1) as well as the DVGA output that power) depends on the input signal’s frequency offset relative to follows the last decimation stage (DEC3). The rms power of the the IF frequency since both DEC1 filter’s response as well as I and Q signal is estimated by the equation the ADC’s signal transfer function attenuate the mixer’s [ ] ( [ ]) ( [ ]) downconverted signal level centered at f /8. As a result, the Xest n = Abs I n + AbsQ n (7) CLK estimated signal strength of input signals falling within prox- Signal estimation after the first decimation stage allows the imity to the IF is reported accurately, while those signals at AGC to cope with out-of-band interferers and in-band signals increasingly higher frequency offsets incur larger measure- that could otherwise overload the ADC. Signal estimation after ment errors. Figure20 shows the normalized error of the the DVGA allows the AGC to minimize the effects of the 16-bit RSSI reading as a function of the frequency offset from the truncation noise. IF frequency. Note that the significance of this error becomes When the estimated signal level falls within the range of the apparent when determining the maximum input interferer (or AGC, the AGC loop adjusts the VGA (or DVGA) attenuation blocker) levels with the AGC enabled. setting so that the estimated signal level is equal to the pro- grammed level specified in the AGCR field. The absolute signal 0 strength can be determined from the contents of the ATTN and RSSI field that is available in the SSI data frame when properly –3 B configured. Within this AGC tracking range, the 6-bit value in d – the RSSI field remains constant while the 8-bit ATTN field OR –6 varies according to the VGA/DVGA setting. Note that the R R E ATTN value is based on the 8MSB contained in the AGCG SSI –9 field of Registers 0x03 and 0x04. R D E A description of the AGC control algorithm and the user adjust- SUR –12 able parameters follows. First, consider the case in which the A E in-band target signal is bigger than all out-of-band interferers M –15 and the DVGA is disabled. With the DVGA disabled, a control loop based only on the target signal power measured after –18 DEC1 is used to control the VGA gain, and the target signal 0 0.01 0.02 0.03 0.04 0.05 will be tracked to the programmed reference level. If the signal NORMALIZED FREQUENCY OFFSET – (fIN – fIF) fCLK is too large, the attenuation is increased with a proportionality Figure 20.Normalized RSSI Error vs. Normalized constant determined by the AGCA setting. Large AGCA values IF Frequency Offset result in large gain changes, thus rapid tracking of changes in signal strength. If the target signal is too small relative to the Automatic Gain Control (AGC) reference level, the attenuation is reduced; but now the propor- The gain of the VGA (and DVGA) is automatically adjusted tionality constant is determined by both the AGCA and AGCD when the AGC is enabled via the AGCR field of Register 0x06. settings. The AGCD value is effectively subtracted from AGCA, In this mode, the gain of the VGA is continuously updated at so a large AGCD results in smaller gain changes and thus f /60 in an attempt to ensure that the maximum analog signal CLK slower tracking of fading signals. level into the ADC does not exceed the ADC clip level and that the rms output level of the ADC is equal to a programmable The 4-bit code in the AGCA field sets the raw bandwidth of the reference level. With the DVGA enabled, the AGC control loop AGC loop. With AGCA = 0, the AGC loop bandwidth is at its also attempts to minimize the effects of 16-bit truncation noise minimum of 50 Hz, assuming f = 18 MHz. Each increment CLK prior to the SSI output by continuously adjusting the DVGA’s of AGCA increases the loop bandwidth by a factor of 21/2, thus REV. A –29–

AD9874 the maximum bandwidth is 9 kHz. A general expression for the 128 attack bandwidth is: ( ) ( ) 112 BW =50× f 18MHz ×2AGCA2 Hz (8) A CLK G N 96 and the corresponding attack time is: TI AGCO = 7 T E tattack =2.2 100×π×2(AGCA2) =0.35 BWA (9) ON S 80 ATI 64 AGCO = 4 assuming that the loop dynamics are essentially those of a U N single-pole system. TE 48 T A The 4-bit code in the AGCD field sets the ratio of the attack A G 32 time to the decay time in the amplitude estimation circuitry. V AGCD = 0 When AGCD is zero, this ratio is one. Incrementing AGCD 16 multiplies the decay time constant by 21/2, allowing a 180:1 0 range in the decay time relative to the attack time. The decay 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 time may be computed from: TIME – ms ( ) tdecay =tattack ×2AGCD2 (10) Figure 21b.AGC Response for Different AGCO Settings with f = 18 MSPS, f = 300 kSPS, Figure 21a shows the AGC response to a 30 Hz pulse-modu- CLK CLKOUT Decimate by 60, and AGCA = AGCD = 0 lated IF burst for different AGCA and AGCD settings. Lastly, the AGCF bit reduces the DAC source resistance by at AGCA = 0 least a factor of 10. This facilitates fast acquisition by lowering 96 AGCD = 8 the RC time constant that is formed with the external capacitors 80 connected from the GCP pin-to-ground (GCN pin). For an 64 overshoot-free step response in the AGC loop, the capacitor 48 connected from the GCP pin to the GCN ground pin should be 32 AGCD = 0 chosen so that the RC time constant is less than one quarter of 16 the raw loop. Specifically: 0 RC <1(8πBW) (11) NG 96 AGCA = 4 TI where R is the resistance between the GCP pin and ground T 80 SE AGCD = 8 (72.5k(cid:3) (cid:7)30% if AGCF = 0, <8 k(cid:3) if AGCF = 1) and BW is N 64 O the raw loop bandwidth. Note that with C chosen at this upper TI 48 NUA 32 AGCD = 0 limit, the loop bandwidth increases by approximately 30%. E T Now consider the case described above but with the DVGA T 16 A GA 0 enabled to minimize the effects of 16-bit truncation. With the V AGCA = 8 DVGA enabled, a control loop based on the larger of the two 96 estimated signal levels (i.e., output of DEC1 and DVGA) is 80 AGCD = 8 used to control the DVGA gain. The DVGA multiplies the 64 output of the decimation filter by a factor of 1 to 4 (i.e., 0 dB to 48 12dB). When signals are small, the DVGA gain is 4 and the 32 16-bit output is extracted from the 24-bit data produced by the 16 AGCD = 0 decimation filter by dropping 2 MSB and taking the next 16 0 bits. As signals get larger, the DVGA gain decreases to the point 0 10 20 30 40 50 where the DVGA gain is 1 and the 16-bit output data is simply TIME – ms the 16MSB of the internal 24-bit data. As signals get even Figure 21a.AGC Response for Different AGCA larger, attenuation is accomplished by the normal method of and AGCD Settings with f = 18 MSPS, increasing the ADC’s full scale. CLK f = 20 kSPS, Decimate by 900, and AGCO = 0 CLKOUT The extra 12 dB of gain range provided by the DVGA reduces The 3-bit value in the AGCO field determines the amount of the input-referred truncation noise by 12 dB and makes the data attenuation added in response to a reset event in the ADC. more tolerant of LSB corruption within the DSP. The price Each increment in AGCO doubles the weighting factor. At the paid for this extension to the gain range is that the start of AGC highest AGCO setting, the attenuation will change from 0 dB to action is 12 dB lower and that the AGC loop will be unstable if its 12 dB in approximately 10 µs, while at the lowest setting the bandwidth is set too wide. The latter difficulty results from the attenuation will change from 0 dB to 12 dB in approximately large delay of the decimation filters, DEC2 and DEC3, when 1.2 ms. Both times assume f = 18 MHz. Figure 21b shows one implements a large decimation factor. As a result, given an CLK the AGC attack time response for different AGCO settings. option, the use of 24-bit data is preferable to using the DVGA. –30– REV. A

AD9874 Table XII indicates which AGCA values are reasonable for Table XIII. SPI Registers Associated with AGC various decimation factors. The white cells indicate that the Address Bit Default (decimation factor/AGCA) combination works well; the light (Hex) Breakdown Width Value Name gray cells indicate ringing and an increase in the AGC settling time; and the dark gray cells indicate that the combination 0x03 (7) 1 0 ATTEN results in instability or near instability in the AGC loop. Setting (6:0) 7 0x00 AGCG(14:8) AGCF = 1 improves the time-domain behavior at the expense 0x04 (7:0) 8 0x00 AGCG(7:0) of increased spectral spreading. 0x05 (7:4) 4 0 AGCA Table XII.AGCA Limits if the DVGA is Enabled (3:0) 4 0x00 AGCD 0x06 (7) 1 0 AGCV AGCA (6:4) 3 0 AGCO M 4 5 6 7 8 9 10 11 12 13 14 15 (3) 1 0 AGCF (2:0) 3 0 AGCR R O 60 0 T System Noise Figure (NF) vs. VGA (or AGC) Control C A 120 1 The AD9874’s system noise figure is a function of the ACG F N attenuation and output signal bandwidth. Figure 22a plots the O 300 4 I nominal system NF as a function of the AGC attenuation for T A both narrow-band (20 kHz) and wideband (150 kHz) modes M 540 8 CI with fCLK = 18 MHz. Also shown on the plot is the SNR that E 900 E would be observed at the output for a –2 dBFS input. The D high dynamic range of the ADC within the AD9874 ensures that the system NF increases gradually as the AGC attenuation Lastly, consider the case of a strong out-of-band interferer (i.e., is increased. In narrow-band (BW = 20 kHz) mode, the system –18dBm to –32 dBm for matched IF input) that is larger than noise figure increases by less than 3 dB over a 12 dB AGC the target signal and large enough to be tracked by the control range, while in wideband (BW = 150 kHz) mode, the degra- loop based on the output of the DEC1. The ability of the con- dation is about 5 dB. As a result, the highest instantaneous trol loop to track this interferer and set the VGA attenuation to dynamic range for the AD9874 occurs with 12 dB of AGC prevent clipping of the ADC is limited by the accuracy of the attenuation, since the AD9874 can accommodate an addi- digital signal estimation occurring at the output of DEC1. The tional 12 dB peak signal level with only a moderate increase accuracy of the digital signal estimation is a function of the in its noise floor. frequency offset of the out-of-band interferer relative to the IF frequency as shown in Figure 20. Interferers at increasingly As Figure 22a shows, the AD9874 can achieve an SNR in higher frequency offsets incur larger measurement errors, poten- excess of 100 dB in narrow-band applications. To realize the tially causing the control loop to inadvertently reduce the full performance of the AD9874 in such applications, it is recom- amount of VGA attenuation that may result in clipping of the mended that the I/Q data be represented with 24 bits. If 16-bit ADC. Figure 21c shows the maximum measured interferer data is used, the effective system NF will increase because of the signal level versus the normalized IF offset frequency (relative to quantization noise present in the 16-bit data after truncation. f ) tolerated by the AD9874 relative to its maximum target CLK input signal level (0 dBFS =–18 dBm). Note that the increase 15 SNR = 90.1dBFS in allowable interferer level occurring beyond 0.04 (cid:6) f CLK 14 results from the inherent signal attenuation provided by the ADC’s signal transfer function. B 13 d 0 URE – 12 BW = 50kHz G dBFS –3 OISE FI 11 BW = 150kHz T – N SNR = 82.9dBFS SNR = 103.2dB N 10 OI –6 P P BW = 10kHz LI 9 C E TO –9 8 SNR = 95.1dBFS V ATI 0 3 6 9 12 L VGA ATTENUATION – dB E–12 R Figure 22a.Nominal System Noise Figure and Peak SNR vs. AGCG Setting (f = 73.35 MHz, f = –15 IF CLK 0 0.01 0.02 0.03 0.04 0.05 18 MSPS, and 24-bit I/Q data) NORMALIZED FREQUENCY OFFSET = (fIN – fIF)/fCLK Figure 21c.Maximum Interferer (or Blocker) Input Level vs. Normalized IF Frequency Offset REV. A –31–

AD9874 Figure 22b plots the nominal system NF with 16-bit output APPLICATION CONSIDERATIONS data as a function of AGC in both narrow-band and wideband Frequency Planning mode. In wideband mode, the NF curve is virtually unchanged The LO frequency (and/or ADC clock frequency) must be relative to the 24-bit output data because the output SNR chosen carefully to prevent known internally generated spurs before truncation is always less than the 96dB SNR that 16-bit from mixing down along with the desired signal, thus degrad- data can support. ing the SNR performance. The major sources of spurs in the AD9874 are the ADC clock and digital circuitry operating at However, in narrow-band mode, where the output SNR 1/3 of f . Thus, the clock frequency (f ) is the most approaches or exceeds the SNR that can be supported with 16-bit CLK CLK important variable in determining which LO (and therefore data, the degradation in system NF is more severe. Further- IF) frequencies are viable. more, if the signal processing within the DSP adds noise at the level of an LSB, the system noise figure can be degraded even Many applications have frequency plans that take advantage of more than Figure22b shows. For example, this could occur in a industry-standard IF frequencies due to the large selection of fixed 16-bit DSP whose code is not optimized to process the low cost crystal or SAW filters. If the selected IF frequency and AD9874’s 16-bit data with minimal quantization effects. To ADC clock rate result in a problematic spurious component, an limit the quantization effects within the AD9874, the 24-bit alternative ADC clock rate should be selected by slightly modi- data undergoes noise shaping just prior to 16-bit truncation, fying the decimation factor and CLK synthesizer settings (if thus reducing the in-band quantization noise by 5 dB (with 23 used) such that the output sample rate remains the same. Also, oversampling). This explains why 98.8dBFS SNR performance applications requiring a certain degree of tuning range should is still achievable with 16-bit data in a 10kHz BW. take into consideration the location and magnitude of these spurs when determining the tuning range as well as optimum IF 17 and ADC clock frequency. SNR = 98.8dBFS 16 Figure 23a plots the measured in-band noise power as a func- tion of the LO frequency for f = 18 MHz and an output 15 CLK BW = 10kHz signal bandwidth of 150 kHz when no signal is present. Any LO dB 14 frequency resulting in large spurs should be avoided. As this URE – 13 faiwguarye fsrhoomw sa, hlaarrgme ospnuicr so rfe 1su8l tM wHhezn ( it.hee., LnO f is fC(cid:7)L Kf/8 =/ 82).2. 5A lMsoHz G CLK CLK FI 12 BW = 150kHz problematic are LO frequencies whose odd order harmonics E SNR = 89.9dBFS NOIS 11 SNR = 94.1dBFS (mi.eec.,h amn ifsLmO) ims aix r ewsiutlht hoaf rtmheo mniicxse or fb feCinLKg tino tfeCrLnKa/l8ly. dTrhivise ns pbuyr a 10 squared-up version of the LO input consisting of the LO fre- 9 BW = 50kHz quency and its odd order harmonics. These spur frequencies SNR = 83dBFS can be calculated from the relation 8 ( ) 0 3 6 9 12 m f = n±18 f (12) LO CLK VGA ATTENUATION – dB where m = 1, 3, 5... and n = 1, 2, 3... Figure 22b.Nominal System Noise Figure and Peak SNR A second source of spurs is a large block of digital circuitry that vs. AGCG Setting (f = 73.35 MHz, f = 18 MSPS, and IF CLK is clocked at f /3. Problematic LO frequencies associated with 16-bit I/Q data) CLK this spur source are given by: f = f /3+n f ± f 8 (13) LO CLK CLK CLK where n = 1, 2, 3 ... –50 S BF–60 d – R E OW–70 P D N A B–80 N- I –90 0 50 100 150 200 250 300 LO FREQUENCY – MHz Figure 23a.Total In-Band Noise + Spur Power with No Signal Applied as a Function of the LO Frequency (f = 18 MHz and Output Signal Bandwidth of 150 kHz) CLK –32– REV. A

AD9874 –50 S BF–60 d – R E OW–70 P D N A B–80 N- I –90 0 50 100 150 200 250 300 LO FREQUENCY – MHz Figure 23b.Same as Figure 23a Excluding LO Frequencies Known to Produce Large In-Band Spurs Figure 23b shows that omitting the LO frequencies given by Spurious Responses Equation 12 for m = 1, 3, and 5 and by Equation 13 accounts The spectral purity of the LO (including its phase noise) is an for most of the spurs. Some of the remaining low level spurs can important consideration since LO spurs can mix with undesired be attributed to coupling from the SSI digital output. As a signals present at the AD9874’s IFIN input to produce an in-band result, users are also advised to optimize the output bit rate response. To demonstrate the low LO spur level introduced within (f via the SSIORD register) and the digital output driver the AD9874, Figure 25 plots the demodulated output power as a CLKOUT strength to achieve the lowest spurious and noise figure perfor- function of the input IF frequency for an LO frequency of mance for a particular LO frequency and f setting. This is 71.1 MHz and a clock frequency of 18 MHz. CLK especially the case for particularly narrow-band channels in 0 which low level spurs can degrade the AD9874’s sensitivity performance. D = fCLK/4 = 4.5MHz –20 Despite the many spurs, sweet spots in the LO frequency are DESIRED generally wide enough to accommodate the maximum signal RESPONSES –40 bandwidth of the AD9874. As evidence of this property, Fig- ure24 shows that the in-band noise is quite constant for LO S frequencies ranging from 70 MHz to 71MHz. dBF –60 –50 –80 –100 –60 S BF –120 – d 50 60 70 80 90 100 R IF FREQUENCY – MHz E OW –70 Figure 25.Response of AD9874 to a –20 dBm IF P ND Input when fLO = 71.1MHz A B N- The two large –10 dBFS spikes near the center of the plot are I –80 the desired responses at f , (cid:7) f , where f = f /8, LO IF2_ADC IF2_ADC CLK i.e., at 68.85 MHz and 73.35 MHz. LO spurs at f (cid:7) f LO SPUR would result in spurious responses at offsets of (cid:7)f around the SPUR –90 desired responses. Close-in spurs of this kind are not visible on 70.0 70.5 71.0 the plot, but small spurious responses at f (cid:7) f (cid:7) f , i.e., LO FREQUENCY – MHz LO IF2_ADC CLK at 50.85 MHz, 55.35 MHz, 86.85 MHz, and 91.35 MHz, are Figure 24.Expanded View from 70 MHz to 71 MHz visible at the –90 dBFS level. This data indicates that the AD9874 does an excellent job of preserving the purity of the LO signal. Figure 25 can also be used to gauge how well the AD9874 rejects undesired signals. For example, the half-IF response (at 69.975MHz and 72.225MHz) is approximately –100 dBFS, giving a selectivity of 90 dB for this spurious response. The largest spurious response at approximately –70 dBFS occurs with input frequencies of 70.35 MHz and 71.85 MHz. These spurs result from third order nonlinearity in the signal path (i.e., abs [3 (cid:6) f – 3 (cid:6) f ] = f /8). LO IF_Input CLK REV. A –33–

AD9874 EXTERNAL PASSIVE COMPONENT REQUIREMENTS The LO, CLK, and IFIN signals are coupled to their respective Figure 26 shows an example circuit using the AD9874 and inputs using 10 nF capacitors. The output of the mixer is coupled TableXIV shows the nominal dc bias voltages seen at the differ- to the input of the ADC using 100 pF. An external 100kΩ resistor ent pins. The purpose is to show the various external passive from the RREF pin to GND sets up the AD9874’s internal bias components required by the AD9874, along with nominal dc currents. VREFP and VREFN provide a differential reference voltages for troubleshooting purposes. voltage to the AD9874’s (cid:1)-(cid:2) ADC and must be decoupled by a0.01 µF differential capacitor along with two 100 pF capacitors to GND. The remaining capacitors are used to decouple other sensi- nF nF nF tive internal nodes to GND. 0 0 0 50(cid:1) 1 1 1 Although power supply decoupling capacitors are not shown, nF nF F itis recommended that a 0.1 µF surface-mount capacitor be 0 0 n LC TANK (cid:6)10H 180pF (cid:6)10H 1 MXOP4VDDI8 4IFIN7104CXIF6 4GNDI5104CXVL4 4LOP34LON2 4CXVM114VDDL0 3VDDP9 3IOUTL8 3GNDPG7NDL 36 pmmexlauatectmcrehnd eia nfalf gseI Fccntl eiofvtislewtene oaerr.ssk sL p.u aoAsssetlssdliyob ,t l oneth omteto a sleohtacoochpwh tn fhpi leoits ewA rt ehDcreo 9 smi8un7ppp4pou’nltsy e i ImnpFitpn si e nafdposasruon tmc ctieaoaxt teih-de 100 2 MXON FREF 35 with the LO and CLK synthesizers are not shown. 100pF pF 3 GNDF GNDS 34 4 IF2N SYNCB 33 LC component values for fCLK = 18 MHz are given on the dia- 5 IF2P GNDH 32 gram. For other clock frequencies, the two inductors and the 2.2nF 6 VDDF AD9874 FS 31 capacitor of the LC tank should be scaled in inverse proportion to 7 GCP DOUTB 30 the clock. For example, if f = 26 MHz, then the two inductors 89 GVDCDNA DOUTA 29 should be = 6.9µH and theC LcKapacitor should be about 120 pF. A 100pF CLKOUT 28 10GNDA VDDH 27 tolerance of 10% is sufficient for these components since tuning 10nF 11VREFP VDDD 26 of the LCtank is performed upon system startup. 100pF 12VREFNRREF VDDQ IOUTC GNDQ VDDC GNDC CLKP CLKN GNDS GNDD PC PD PE 25 ASuPpPeLrhICetAeTroIdOyNnSe Receiver Example 13 14 1516 1718 19 20 2122 23 24 The AD9874 is well suited for analog and/or digital narrow- 100k(cid:1) band radio systems based on a superheterodyne receiver 10nF 10nF architecture. The superheterodyne architecture is noted for achieving exceptional dynamic range and selectivity by using Figure 26.Example Circuit Showing Recommended two or more downconversion stages to provide amplification Component Values of the target signal while filtering the undesired signals. The AD9874 greatly simplifies the design of these radio systems Table XIV. Nominal DC Bias Voltages by integrating the complete IFstrip (excluding the LO VCO) Pin Number Mnemonic Nominal DC Bias (V) while providing an I/Q digital output (along with other system parameters) for the demodulation of both analog and digital 1 MXOP VDDI – 0.2 modulated signals. The AD9874’s exceptional dynamic range 2 MXON VDDI – 0.2 often simplifies the IF filtering requirements and eliminates the 4 IF2N 1.3 – 1.7 need for an external AGC. 5 IF2P 1.3 – 1.7 11 VREFP VDDA/2 + 0.250 Figure 27 shows a typical dual conversion superheterodyne 12 VREFN VDDA/2 – 0.250 receiver using the AD9874. An RF tuner is used to select and 13 RREF 1.2 downconvert the target signal to a suitable first IF for the 19 CLKP VDDC – 1.3 AD9874. Apreselect filter may precede the tuner to limit the 20 CLKN VDDC – 1.3 RF input to the band of interest. The output of the tuner 35 FREF VDDC/2 drives an IF filter that provides partial suppression of adja- 41 CXVM 1.6 – 2.0 cent channels and interferers that could otherwise limit the 42 LON 1.65 – 1.9 receiver’s dynamic range. The conversion gain of the tuner 43 LOP 1.65 – 1.9 should be set such that the peak IF input signal level into the 44 CXVL VDDI – 0.05 AD9874 is no greater than –18dBm to prevent clipping. The 46 CXIF 1.6 – 2.0 AD9874 downconverts the first IF signal to a second IF that 47 IFIN 0.9 – 1.1 is exactly 1/8 of the (cid:1)-(cid:2) ADC’s clock rate (i.e., fCLK/8) to sim- plify the digital quadrature demodulation process. –34– REV. A

AD9874 VDDA IF2 = fCLK/8 P N P N P N RF PRESELECT IF CRYSTAL OR VXO VXO II-2 II-2 GC GC AD9874 INPUT FILTER TUNER SAW FILTER –16dB DAC AGC DOUTA IFIN LNA LNA (cid:3)-(cid:2) ADC DECFIILMTAETRION FORMATTING/SSI DOUTB TO FS DSP CLKOUT CONTROL LOGIC VCO LO SAMPLE CLOCK VOLTAGE SYNTH. SYNTHESIZER REFERENCE SPI APLDLF 4SR2YxENxFIN IOUTC LOP LON IOUTC CLKP CLKN VREFP VREFN RREF PC PD PE SYNCB LOOP VCO LOOP FILTER FILTER VDDC CRYSTAL OSCILLATOR FROM DSP Figure 27.Typical Dual Conversion Superheterodyne Application Using the AD9874 This second IF signal is then digitized by the (cid:1)-(cid:2) ADC, demodu- channel blocker(s) that could overdrive the AD9874’s input lated into its quadrature I and Q components, filtered via matching or generate in-band intermodulation components. Further decimation filters, and reformatted to enable a synchronous serial suppression is performed within the AD9874 by its inherent interface to a DSP. In this example, the AD9874’s LO and CLK band-pass response and digital decimation filters. Note that synthesizers are both enabled, requiring some additional passive some applications will require additional application-specific components (for the synthesizer’s loop filters and CLK oscillator) filtering performed in the DSP that follows the AD9874 to and a VCO for the LO synthesizer. Note that not all of the remove the adjacent channel and/or implement a matched required decoupling capacitors are shown. Refer to the previous filter for optimum signal detection. section and Figure 26 for more information on required external The output data rate of the AD9874, f , should be chosen passive components. OUT to be at least twice the bandwidth or symbol rate of the desired The selection of the first IF frequency is often based on the signal to ensure that the decimation filters provide a flat pass- availability of low cost standard crystal or SAW filters as well as band response as well as to allow for postprocessing by a DSP. system frequency planning considerations. In general, crystal Once f is determined, the decimation factor of the digital OUT filters are often used for narrow-band radios having channel filters should be set such that the input clock rate, f , falls CLK bandwidths below 50 kHz with IFs below 120 MHz, while SAW between the AD9874’s rated operating range of 13 MHz to filters are more suited for channel bandwidths greater than 26 MHz and no significant spurious products related to f fall CLK 50kHz with IFs greater than 70 MHz. The ultimate stop-band within the desired passband, resulting in a reduction in sensitiv- rejection required by the IF filter will depend on how much ity performance. If a spurious component is found to limit the suppression is required at the AD9874’s image band resulting sensitivity performance, the decimation factor can often be from downconversion to the second IF. This image band is modified slightly to find a spurious free pass band. Selecting a offset from the first IF by twice the second IF frequency (i.e., higher f is typically more desirable given a choice, since CLK (cid:7)f /4, depending on high or low side injection). the first IF’s filtering requirements often depend on the tran- CLK sition region between the IF frequency and the image band The selectivity and bandwidth of the IF filter will depend on (i.e., (cid:7)f /4 ). Lastly, the output SSI clock rate, f , both the magnitude and frequency offset(s) of the adjacent CLK CLKOUT REV. A –35–

AD9874 and digital driver strength should be set to their lowest pos- VDDC sible settings to minimize the potential harmful effects of LOOP digital induced noise while preserving a reliable data link to RBIAS FILTER the DSP. Note that the SSICRA, SSICRB, and SSIORD 0.1(cid:6)F COSC RD roefg filsetxeirbsi l(iit.ye .f,o 0r xo1p8t,i m0xiz1a9t,i oann do f0 txh1eA S)S pIr ionvtiedrefa ac ela.rge degree LOSC CVAR CP RF CZ Synchronization of Multiple AD9874s Some applications such as receiver diversity and beam steering 15 may require two or more AD9874s operating in parallel while maintaining synchronization. Figure 28 shows an example of IOUTC FROM fREF 35 CRYSTAL how multiple AD9874s can be cascaded, with one device serv- OSCILLATION 19 CLKP ing as the master and the other devices serving as the slaves. In this example, all of the devices have the same SPI register con- 20 CLKN AD9874 figuration since they share the same SPI interface to the DSP. 47 IFIN MASTER Since the state of each of the AD9874’s internal counters is FS 31 unknown upon initialization, synchronization of the devices is DOUTA 29 TO DSP required via a SYNCB pulse (see Figure 4) to synchronize their CLKOUT 28 digital filters and ensure precise time alignment of the data 43 LOP streams. 42 LON PE 25 PD 24 FROM Although all of the devices’ synthesizers are enabled, the LO PC 23 DSP and CLK signals for the slaves(s) are derived from the masters’ SYNCB 33 IOUTL synthesizers and are referenced to an external crystal oscillator. 38 All of the necessary external components (i.e., loop filters, VCO varactor, LC, and VCO) required to ensure proper closed-loop operation of these synthesizers are included. LOOP FILTER Note that although the VCO output of the LO synthesizer is ac-coupled to the slave’s LO input(s), all of the CLK inputs of 15 the devices must be dc-coupled if the AD9874’s CLK oscillators IOUTC are enabled. This is due to the dc current required by the CLK 47 IFIN PE 25 PD 24 oscillators in each device. In essence, these negative impedance PC23 cores are operating in parallel, increasing the effective Q of the 43 LOP LC resonator circuit. Note that RBIAS should be sized such 42 LON SYNCB 33 that the sum of the oscillators’ dc bias currents maintains a AD9874 common-mode voltage of around 1.6V. SLAVE TO OTHER 19 CLKP AD9874s 20 CLKN FS 31 DOUTA 29 TO DSP CLKOUT 28 TO OTHER AD9874s fREF 35 Figure 28.Example of Synchronizing Multiple AD9874s –36– REV. A

AD9874 VDDC LOOP RBIAS FILTER 0.1(cid:6)F COSC RD LOSC CP RF CVAR ATTENUATED PATH WITH CZ CLIP POINT = 7.0dBm 15 13MHz IOUTC 19 CLKP f 35 REF 20 CLKN 47 IFIN FS 31 DOUTA 29 36dB CLKOUT 28 PAD 43 LOP 42 LON AD9874 PE 25 MASTER PD 24 PC 23 SYNCB 33 IOUTL 38 VCO LOOP FILTER DSP OR ASIC DUPLEXER PRESELECT IF SAW 1 IF SAW 2 15 IOUTC LNA X IAFMP 47 IFIN PE 25 PD 24 MIXER PC 23 43 LOP GAIN = –2dB GAIN = 22dB GAIN = –3dB GAIN = 5dB GAIN = 15dB GAIN = –9dB 42 LON SYNCB 33 NF = 2dB NF = 1dB NF = 3dB NF = 12dB NF = 2dB NF = –9dB AD9874 DIRECT PATH WITH SLAVE FS 31 CLIP POINT = –17dBm 19 CLKP DOUTA 29 20 CLKN CLKOUT 28 fREF 35 Figure 29.Example of Split Path Rx Architecture to Increase Receiver Dynamic Range Capabilities Split Path Rx Architecture stage consists of two SAW filters isolated by a 15dB gain stage. A split path Rx architecture may be attractive for those applica- The cascaded SAW filter response must provide sufficient tions whose instantaneous dynamic range requirements exceed blocker rejection in order for the receiver to meet its sensitivity the capability of a single AD9874 device. To cope with these requirements under worst-case blocker conditions. A composite higher dynamic range requirements, two AD9874s can be oper- response having 27 dB, 60 dB, and 100dB rejection at frequency ated in parallel with their respective clip points offset by a fixed offsets of (cid:7)0.8 MHz, (cid:7)1.6 MHz, and (cid:7)6.5MHz, respectively, amount. Adding a fixed amount of attenuation in front of the provides enough blocker suppression to ensure that the AD9874 AD9874 and/or programming the attenuation setting of its with the lower clip point will not be overdriven by any blocker. internal VGA can adjust the input-referred clip point. To save This configuration results in the best possible receiver sensitivity power and simplify hardware, the LO and CLK circuits of the under all blocking conditions. device can also be shared. Connecting the SYNCB pins of the two The output of the last SAW filters drives the two AD9874s via a devices and pulsing this line low synchronizes the two devices. direct signal path and an attenuated signal path. The direct path An example of this concept for possible use in a GSM base station corresponds to the AD9874 having the lowest clip point and is shown in Figure 29. The signal chain consists of a high linearity provides the highest receiver sensitivity with a system noise RF front end and IF stage followed by two AD9874s operating in figure of 4.7 dB. The VGA of this device is set for maximum parallel. The RF front end consists of a duplexer and preselect attenuation, so its clip point is approximately –17 dBm. Since filter to pass the GSM RF band of interest. A high performance conversion gain from the antenna to the AD9874 is 19dB, the LNA isolates the duplexer from the preselect filter while providing digital output of this path will nominally be selected unless the sufficient gain to minimize system NF. An RF mixer is used to target signal’s power exceeds –36 dBm at the antenna. The downconvert the entire GSM band to a suitable IF, where much of attenuated path corresponds to the AD9874 having the highest the channel selectivity is accomplished. The 170.6MHz IF is input-referred clip point, and its digital output point of this path chosen to avoid any self-induced spurs from the AD9874. The IF is set to 7dBm by inserting a 30dB attenuator and setting the AD9874’s VGA to the middle of its 12dB range. This setting REV. A –37–

AD9874 results in a (cid:7)6dB adjustment of the clip point, allowing the clip LAYOUT EXAMPLE, EVALUATION BOARD, AND point difference to be calibrated to exactly 24 dB, so that a SOFTWARE simple 5-bit shift would make up the gain difference. The The evaluation board and its accompanying software provide attenuated path can handle signal levels up to –12dB at the a simple way to evaluate the AD9874. The block diagram in antenna before being overdriven. Since the SAW filters provide Figure31 shows the major blocks of the evaluation board, sufficient blocker suppression, the digital data from this path which is designed to be flexible, allowing configuration for need only be selected when the target signal exceeds –36dBm. different applications. Although the sensitivity of the receiver with the attenuated path The power supply distribution block provides filtered, adjustable is 20dB lower than the direct path, the strong target signal voltages to the various supply pins of the AD9874. In the IF ensures a sufficiently high carrier-to-noise ratio. input signal path, component pads are available to implement Since GSM is based on a TDMA scheme, digital data (or path) different IF impedance matching networks. The LO and CLK selection can occur on a slot-by-slot basis. The AD9874 would signals can be externally applied or internally derived from a be configured to provide Serial I and Q data at a frame rate of user-supplied VCO module interface daughter board. The refer- 541.67kSPS, as well as additional information including a 2-bit ence for the on-chip LO and CLK synthesizers can be applied reset field and a 6-bit RSSI field. These two fields contain the via the external f input or an on-board crystal oscillator. REF information needed to decide whether the direct or attenuated The evaluation board is designed to interface to a PC via a path should be used for the current time slot. National Instruments NI 6533 digital IO card. An XILINX Hung Mixer Mode FPGA formats the data between the AD9874 and digital The AD9874 can be operated in the hung mixer mode by tying I/O card. one of the LO’s self-biasing inputs to ground (i.e., GNDI) or the positive supply (VDDI). In this mode, the AD9874 acts as a narrow-band, band-pass (cid:1)-(cid:2) ADC, since its mixer passes the IF LO IFIN signal without any frequency translation. The IFIN signal INPUT INPUT VCO must be centered about the resonant frequency of the (cid:1)-(cid:2)ADC AD9874 INMTOEDRUFALCEE FREF (i.e., f /8) and the clock rate, f , and decimation factors INPUT CLK CLK MIXER must be selected to accommodate the bandwidth of the desired OUTPUT DUT input signal. Note that the LO synthesizer can be disabled CRYSTAL OSCILLATOR because it is no longer required. (OPTIONAL) NR Smmiiinxxcieenr g ti hso eph meigriahxteeiorr nrde,o steuhsle tn icnoogtn hivnae vrase i noanon myg alioninsas lte hisnr aopsuusgto hcc iltaihptee dp L owNiniAtth o atfnhde SPXFAIPLRGINTAOXN FIIDFTO DAQ 68-PIONNECTO –24 dBm. The linearity or IIP3 performance of the LNA and (OPTIONAL) NIC mixer remains roughly unchanged and similar to that shown POWER SUPPLY in Figure11b. The SNR performance is dependent of the DISTRIBUTION CLK EPROM INPUT VGA attenuation setting, I/Q data resolution, and output bandwidth as shown in Figure30. Applications requiring the highest instantaneous dynamic range should set the VGA for Figure 31.Evaluation Board Platform maximum attenuation. Also, several extra decibels in SNR Software developed using National Instruments’ LabVIEW™ performance can be gained at lower signal bandwidths by (and provided as Microsoft® Windows® executable programs) using 24-bit I/Q data. issupplied for the configuration of the SPI port registers and evaluation of the AD9874 output data. These programs have 105 aconvenient graphical user interface that allows for easy access fCLK = 18MSPS tothe various SPI port configuration registers and real-time 100 frequency analysis of the output data. MAX ATTEN w/ 24-BIT I/Q DATA For more information on the AD9874 evaluation board, includ- ing an example layout, please refer to the EVAL-AD9874EB 95 dB Data Sheet. – MAX ATTEN w/ R 16-BIT I/Q DATA N S 90 MIN ATTEN w/ 16-BIT I/Q DATA 85 MIN ATTEN w/ 24-BIT I/Q DATA 80 0 20 40 60 80 100 120 140 160 BW – kHz Figure 30.Hung Mixer SNR vs. BW and VGA –38– REV. A

AD9874 OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 1.60 MAX PIN 1 0.75 INDICATOR 9.00 BSC 0.60 0.45 48 37 1 36 SEATING 1.45 PLANE 1.40 0.20 TOP VIEW 7.00 0.09 (PINS DOWN) BSC 1.35 7(cid:1) VIEW A 3.5(cid:1) 0.15 0(cid:1) 12 25 0.05 SEATING 0.08 MAX 13 24 PLANE COPLANARITY 0.50 0.27 VIEW A BSC 0.22 ROTATED 90(cid:1) CCW 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BBC REV. A –39–

AD9874 Revision History Location Page 3/03—Data sheet changed from REV. 0 to REV. A Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 A) Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 03( 3/ Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 0– – 9 Replaced Figure 1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 63 2 0 Deleted Synchronization section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 C Added Synchronization Using SYNCB section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Changes to LO SYNTHESIZER section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Changes to Figure 7b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Changes to Figure 7c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Changes to Table X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Changes to Automatic Gain Control section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Changes to Figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Changes to LAYOUT EXAMPLE, EVALUATION BOARD, and SOFTWARE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 –40– RREEVV.. AA

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