Broadband Modem Mixed-Signal Front End Data Sheet AD9866 FEATURES FUNCTIONAL BLOCK DIAGRAM Low cost 3.3 V CMOS MxFE for broadband modems P+ P– T_ T_ 12-bit DAC OU OU I I 2×/4× interpolation filter 200 MSPS DAC update rate AD9866 IOUT_G+ Integrated 23 dBm line driver with 19.5 dB gain control PWRDWN 2-4X TxDAC IAMP IOUT_N+ 12-bit, 80 MSPS ADC MODE IOUT_N– IOUT_G– −12 dB to +48 dB low noise RxPGA (<2.5 nV/√Hz) TXEN/SYNC 0 TO–7.5dB 0 TO–12dB TXCLK 12 Third order, programmable low-pass filter CLK CLKOUT_1 ADIO[11:6]/ SYN. CLKOUT_2 Flexible digital data path interface Tx[5:0] 2M CLK OSCIN Half- and full-duplex operation MULTIPLIER XTAL Backward-compatible with AD9975 and AD9876 ADIO[5:0]/ Rx[5:0] Various power-down/reduction modes 12 Internal clock multiplier (PLL) RXER/SXYCNLKC 80AMDSCPS 2-PLPOFLE 1-PLPOFLE RRXX+– 2 auxiliary programmable clock outputs AGC[5:0] 6 0 TO 6dB – 6 TO 18dB –6 TO 24dB Available in 64-lead chip scale package or bare die 4 REGISTER ∆ = 1dB ∆ = 6dB ∆ = 6dB SPI CONTROL APoPwPeLrlIiCneA TneIOtwNoSrk ing 04560-0-001 Figure 1. VDSL and HPNA GENERAL DESCRIPTION The AD9866 is a mixed-signal front end (MxFE®) IC for or to an internal low distortion current amplifier. The current transceiver applications requiring Tx and Rx path functionality amplifier (IAMP) can be configured as a current- or voltage- with data rates up to 80 MSPS. Its flexible digital interface, power mode line driver (with two external npn transistors) capable of saving modes, and high Tx-to-Rx isolation make it well-suited delivering in excess of 23 dBm peak signal power. Tx power can for half- and full-duplex applications. The digital interface is be digitally controlled over a 19.5 dB range in 0.5 dB steps. extremely flexible allowing simple interfaces to digital back The receive path consists of a programmable amplifier ends that support half- or full-duplex data transfers, thus often (RxPGA), a tunable low pass filter (LPF), and a 12-bit ADC. allowing the AD9866 to replace discrete ADC and DAC The low noise RxPGA has a programmable gain range of solutions. Power saving modes include the ability to reduce −12 dB to +48 dB in 1 dB steps. Its input referred noise is less power consumption of individual functional blocks or to power than 3.3 nV/√Hz for gain settings beyond 30 dB. The receive down unused blocks in half-duplex applications. A serial port path LPF cutoff frequency can be set over a 15 MHz to 35 MHz interface (SPI®) allows software programming of the various range or simply bypassed. The 12-bit ADC achieves excellent functional blocks. An on-chip PLL clock multiplier and dynamic performance over a 5 MSPS to 80 MSPS span. Both synthesizer provide all the required internal clocks, as well as the RxPGA and the ADC offer scalable power consumption two external clocks from a single crystal or clock source. allowing power/performance optimization. The Tx signal path consists of a bypassable 2×/4× low-pass The AD9866 provides a highly integrated solution for many interpolation filter, a 12-bit TxDAC, and a line driver. The broadband modems. It is available in a space saving, 64-lead transmit path signal bandwidth can be as high as 34 MHz at an lead frame chip scale package (LFCSP), and is specified over the input data rate of 80 MSPS. The TxDAC provides differential commercial (−40°C to +85°C) temperature range. current outputs that can be steered directly to an external load Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD9866 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transmit Path .................................................................................. 28 Applications ....................................................................................... 1 Digital Interpolation Filters ...................................................... 28 Functional Block Diagram .............................................................. 1 TxDAC and IAMP Architecture .............................................. 29 General Description ......................................................................... 1 Tx Programmable Gain Control .............................................. 30 Revision History ............................................................................... 2 TxDAC Output Operation ........................................................ 30 Specifications ..................................................................................... 3 IAMP Current-Mode Operation .............................................. 30 Tx Path Specifications .................................................................. 3 IAMP Voltage-Mode Operation ............................................... 31 Rx Path Specifications .................................................................. 4 IAMP Current Consumption Considerations ........................ 32 Power Supply Specifications........................................................ 5 Receive Path .................................................................................... 33 Digital Specifications ................................................................... 6 Rx Programmable Gain Amplifier ........................................... 33 Serial Port Timing Specifications ............................................... 7 Low-Pass Filter............................................................................ 33 Half-Duplex Data Interface (ADIO Port) Timing Analog-to-Digital Converter (ADC) ....................................... 35 Specifications ................................................................................ 7 AGC Timing Considerations .................................................... 36 Full-Duplex Data Interface (Tx and Rx PORT) Timing Clock Synthesizer ........................................................................... 37 Specifications ................................................................................ 8 Power Control and Dissipation .................................................... 39 Absolute Maximum Ratings ............................................................ 9 Power-Down ............................................................................... 39 Thermal Resistance ...................................................................... 9 Half-Duplex Power Savings ...................................................... 39 ESD Caution .................................................................................. 9 Power Reduction Options ......................................................... 40 Pin Configuration and Function Descriptions ........................... 10 Power Dissipation....................................................................... 42 Typical Performance Characteristics ........................................... 12 Mode Select upon Power-Up and Reset .................................. 42 Rx Path Typical Performance Characteristics ........................ 12 Analog and Digital Loopback Test Modes .............................. 43 TxDAC Path Typical Performance Characteristics ............... 16 PCB Design Considerations .......................................................... 44 IAMP Path Typical Performance Characteristics .................. 18 Component Placement .............................................................. 44 Serial Port ........................................................................................ 19 Power Planes and Decoupling .................................................. 44 Register Map Description .......................................................... 21 Ground Planes ............................................................................ 44 Serial Port Interface (SPI) .......................................................... 21 Signal Routing ............................................................................. 45 Digital Interface .............................................................................. 23 Evaluation Board ............................................................................ 46 Half-Duplex Mode ..................................................................... 23 Outline Dimensions ....................................................................... 47 Full-Duplex Mode ...................................................................... 24 Ordering Guide .......................................................................... 47 RxPGA Control .......................................................................... 26 TxPGA Control .......................................................................... 27 REVISION HISTORY 8/2016—Rev. B to Rev. C Changes to Figure 59 ................................................................................. 28 Changed Thermal Characteristics Section to Thermal Resistance Section ........................................................................................................... 10 12/2004—Rev. 0 to Rev. A Changes to Thermal Resistance Section ............................................... 10 Changes to Specifications Tables ............................................................... 3 Added Table 9; Renumbered Sequentially ........................................... 10 Changes to Serial Table ............................................................................. 19 Changes to Full Duplex Mode section .................................................. 24 8/2011—Rev. A to Rev. B Changes to Table 14 ................................................................................... 25 Deleted Lead Temperature Range Parameter, Table 8 ......................... 9 Change to TxDAC and IAMP Architecture section ......................... 29 Moved Explanation of Test Levels ............................................................ 9 Change to TxDAC Output Operation section.................................... 30 Added EPAD Note to Figure 2 and Added EPAD Note Insert equation ............................................................................................ 37 to Table 9 ....................................................................................................... 10 Change to Figure 84 caption ................................................................... 42 Changes to Figure 53 ................................................................................. 24 Changes to Figure 54 ................................................................................. 25 11/2003—Revision 0: Initial Version Rev. C | Page 2 of 47

Data Sheet AD9866 SPECIFICATIONS Tx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; f = 50 MHz, f = 200 MHz, R = 2.0 kΩ, unless otherwise noted. OSCIN DAC SET Table 1. Parameter Temp Test Level Min Typ Max Unit TxDAC DC CHARACTERISTICS Resolution Full 12 Bits Update Rate Full II 200 MSPS Full-Scale Output Current (IOUTP_FS) Full IV 2 25 mA Gain Error1 25°C I ±2 % FS Offset Error 25°C V 2 µA Voltage Compliance Range Full −1 +1.5 V TxDAC GAIN CONTROL CHARACTERISTICS Minimum Gain 25°C V −7.5 dB Maximum Gain 25°C V 0 dB Gain Step Size 25°C V 0.5 dB Gain Step Accuracy 25°C IV Monotonic Gain Range Error 25°C V ±2 dB TxDAC AC CHARACTERISTICS2 Fundamental 0.5 dBm Signal-to-Noise and Distortion (SINAD) Full IV 66.6 69.2 dBc Signal-to-Noise Ratio (SNR) Full IV 68.4 69.8 dBc Total Harmonic Distortion (THD) Full IV −79 −68.7 dBc Spurious-Free Dynamic Range (SFDR) Full IV 68.5 81 dBc IAMP DC CHARACTERISTICS IOUTN Full-Scale Current = IOUTN+ + IOUTN− Full IV 2 105 mA IOUTG Full-Scale Current = IOUTG+ + IOUTG− Full IV 2 150 mA AC Voltage Compliance Range Full IV 1 7 V IAMPN AC CHARACTERISTICS3 Fundamental 25°C 13 dBm IOUTN SFDR (Third Harmonic) Full IV 43.3 45.2 dBc IAMP GAIN CONTROL CHARACTERISTICS Minimum Gain 25°C V −19.5 dB Maximum Gain 25°C V 0 dB Gain Step Size 25°C V 0.5 dB Gain Step Accuracy 25°C IV Monotonic dB IOUTN Gain Range Error 25°C V 0.5 dB REFERENCE Internal Reference Voltage4 25°C I 1.23 V Reference Error Full V 0.7 3.4 % Reference Drift Full V 30 ppm/oC Tx DIGITAL FILTER CHARACTERISTICS (2× INTERPOLATION) Latency (Relative to 1/f ) Full V 43 Cycles DAC −0.2 dB Bandwidth Full V 0.2187 f /f OUT DAC −3 dB Bandwidth Full V 0.2405 f /f OUT DAC Stop-Band Rejection (0.289 f to 0.711 f ) Full V 50 dB DAC DAC Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation) Latency (Relative to 1/f ) Full V 96 Cycles DAC −0.2 dB Bandwidth Full V 0.1095 f /f OUT DAC −3 dB Bandwidth Full V 0.1202 f /f OUT DAC Stop Band Rejection (0.289 f to 0.711 f ) Full V 50 dB OSCIN OSCIN Rev. C | Page 3 of 47

AD9866 Data Sheet Parameter Temp Test Level Min Typ Max Unit PLL CLK MULTIPLIER OSCIN Frequency Range Full IV 5 80 MHz Internal VCO Frequency Range Full IV 20 200 MHz Duty Cycle Full II 40 60 % OSCIN Impedance 25°C V 100//3 ΜΩ//pF CLKOUT1 Jitter5 25°C III 12 ps rms CLKOUT2 Jitter6 25°C III 6 ps rms CLKOUT1 and CLKOUT2 Duty Cycle7 Full III 45 55 % 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input). 2 TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, FOUT = 5 MHz, 4× interpolation. 3 IOUN full-scale current = 80 mA, fOSCIN= 80 MHz, fDAC=160 MHz, 2× interpolation. 4 Use external amplifier to drive additional load. 5 Internal VCO operates at 200 MHz , set to divide-by-1. 6 Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN. 7 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1. Rx PATH SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; half- or full-duplex operation with CONFIG = 0 default power bias settings, unless otherwise noted. Table 2. Parameter Temp Test Level Min Typ Max Unit Rx INPUT CHARACTERISTICS Input Voltage Span (RxPGA gain = −10 dB) Full III 6.33 V p-p Input Voltage Span (RxPGA gain = +48 dB) Full III 8 mV p-p Input Common-Mode Voltage 25°C III 1.3 V Differential Input Impedance 25°C III 400 Ω 4.0 pF Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB) 25°C III 53 MHz Input Voltage Noise Density (RxPGA Gain = 36 dB, f−3 dBF = 26 MHz) 25°C III 2.7 nV/√Hz Input Voltage Noise Density (RxPGA Gain = 48 dB, f−3 dBF = 26 MHz) 25°C III 2.4 nV/√Hz RxPGA CHARACTERISTICS Minimum Gain 25°C III −12 dB Maximum Gain 25°C III 48 dB Gain Step Size 25°C III 1 dB Gain Step Accuracy 25°C III Monotonic dB Gain Range Error 25°C III 0.5 dB RxLPF CHARACTERISTICS Cutoff Frequency (f−3 dBF ) range Full III 15 35 MHz Attenuation at 55.2 MHz with f−3 dBF = 21 MHz 25°C III 20 dB Pass-Band Ripple 25°C III ±1 dB Settling Time to 5 dB RxPGA Gain Step @ fADC = 50 MSPS 25°C III 20 ns Settling Time to 60 dB RxPGA Gain Step @ fADC = 50 MSPS 25°C III 100 ns ADC DC CHARACTERISTICS Resolution NA NA 12 Bits Conversion Rate FULL II 5 80 MSPS Rev. C | Page 4 of 47

Data Sheet AD9866 Parameter Temp Test Level Min Typ Max Unit Rx PATH LATENCY1 Full-Duplex Interface Full V 10.5 Cycles Half-Duplex Interface Full V 10.0 Cycles Rx PATH COMPOSITE AC PERFORMANCE @ f = 50 MSPS2 ADC RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise (SNR) 25°C III 43.7 dBc Total Harmonic Distortion (THD) 25°C III −71 dBc RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise (SNR) 25°C III 63.1 dBc Total Harmonic Distortion (THD) 25°C III −67.2 dBc RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise (SNR) Full IV 64.3 dBc Total Harmonic Distortion (THD) Full IV −67.3 dBc Rx PATH COMPOSITE AC PERFORMANCE @ f = 80 MSPS3 ADC RxPGA Gain = 48 dB (Full-Scale = 8.0 m V p-p) Signal-to-Noise (SNR) 25°C III 41.8 dBc Total Harmonic Distortion (THD) 25°C III −67 dBc RxPGA Gain = 24 dB (Full-Scale = 126 m V p-p) Signal-to-Noise (SNR) 25°C III 58.6 dBc Total Harmonic Distortion (THD) 25°C III −62.9 dBc RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise (SNR) 25°C II 61.1 62.9 dBc Total Harmonic Distortion (THD) 25°C II −70.8 −60.8 dBc Rx-to-Tx PATH FULL-DUPLEX ISOLATION (1 V p-p, 10 MHz Sine Wave Tx Output) RxPGA Gain = 40 dB IOUTP± Pins to RX± Pins 25°C III 83 dBc IOUTG± Pins to RX± Pins 25°C III 37 dBc RxPGA Gain = 0 dB IOUTP± Pins to RX± Pins 25°C III 123 dBc IOUTG± Pins to RX± Pins 25°C III 77 dBc 1 Includes RxPGA, ADC pipeline, and ADIO bus delay relative to fADC. 2 fIN = 5 MHz, AIN = −1.0 dBFS , LPF cutoff frequency set to 15.5 MHz with Reg. 0x08 = 0x80. 3 fIN = 5 MHz, AIN = −1.0 dBFS , LPF cutoff frequency set to 26 MHz with Reg. 0x08 = 0x80. POWER SUPPLY SPECIFICATIONS AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V; R = 2 kΩ, full-duplex operation with f = 80 MSPS,1 unless otherwise noted. SET DATA Table 3. Parameter Temp Test Level Min Typ Max Unit SUPPLY VOLTAGES AVDD Full V 3.135 3.3 3.465 V CLKVDD Full V 3.0 3.3 3.6 V DVDD Full V 3.0 3.3 3.6 V DRVDD Full V 3.0 3.3 3.6 V IS_TOTAL (Total Supply Current) Full II 406 475 mA POWER CONSUMPTION IAVDD + ICLKVDD (Analog Supply Current) IV 311 342 mA IDVDD + IDRVDD (Digital Supply Current) Full IV 95 133 mA Rev. C | Page 5 of 47

AD9866 Data Sheet Parameter Temp Test Level Min Typ Max Unit POWER CONSUMPTION (Half-Duplex Operation with f = 50 MSPS)1 DATA Tx Mode IAVDD + ICLKVDD 25°C IV 112 130 mA IDVDD + IDRVDD 25°C IV 46 49.5 mA Rx Mode IAVDD + ICLKVDD 25°C 225 253 mA IDVDD + IDRVDD 25°C 36.5 39 mA POWER CONSUMPTION OF FUNCTIONAL BLOCKS2 (I + I ) AVDD CLKVDD RxPGA and LPF 25°C III 87 mA ADC 25°C III 108 mA TxDAC 25°C III 38 mA IAMP (Programmable) 25°C III 10 120 mA Reference 25°C III 170 mA CLK PLL and Synthesizer 25°C III 107 mA MAXIMUM ALLOWABLE POWER DISSIPATION Full IV 1.66 W STANDBY POWER CONSUMPTION IS_TOTAL (Total Supply Current) Full 13 mA POWER-DOWN DELAY (USING PWR_DWN PIN) RxPGA and LPF 25°C III 440 ns ADC 25°C III 12 ns TxDAC 25°C III 20 ns IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 27 ns POWER-UP DELAY (USING PWR_DWN PIN) RxPGA and LPF 25°C III 7.8 µs ADC 25°C III 88 ns TxDAC 25°C III 13 µs IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 20 µs 1 Default power-up settings for MODE = LOW and CONFIG = LOW. 2 Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent. DIGITAL SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; R = 2 kΩ, unless otherwise noted. SET Table 4. Parameter Temp Test Level Min Typ Max Unit CMOS LOGIC INPUTS High Level Input Voltage Full VI DRVDD – 0.7 V Low Level Input Voltage Full VI 0.4 V Input Leakage Current 12 µA Input Capacitance Full VI 3 pF CMOS LOGIC OUTPUTS (C = 5 pF) LOAD High Level Output Voltage (I = 1 mA) Full VI DRVDD – 0.7 V OH Low Level Output Voltage (I = 1 mA) Full VI 0.4 V OH Output Rise/Fall Time (High Strength Mode and C = 15 pF) Full VI 1.5/2.3 ns LOAD Output Rise/Fall Time (Low Strength Mode and C = 15 pF) Full VI 1.9/2.7 ns LOAD Output Rise/Fall Time (High Strength Mode and C = 5 pF) Full VI 0.7/0.7 ns LOAD Output Rise/Fall Time (Low Strength Mode and C = 5 pF) Full VI 1.0/1.0 ns LOAD RESET Minimum Low Pulse Width (Relative to f ) 1 Clock cycles ADC Rev. C | Page 6 of 47

Data Sheet AD9866 SERIAL PORT TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 5. Parameter Temp Test Level Min Typ Max Unit WRITE OPERATION (See Figure 46) SCLK Clock Rate (f ) Full IV 32 MHz SCLK SCLK Clock High (t ) Full IV 14 ns HI SCLK Clock Low (t ) Full IV 14 ns LOW SDIO to SCLK Setup Time (t ) Full IV 14 ns DS SCLK to SDIO Hold Time (t ) Full IV 0 ns DH SEN to SCLK Setup Time (tS) Full IV 14 ns SCLK to SEN Hold Time (tH) Full IV 0 ns READ OPERATION (See Figure 47 and Figure 48) SCLK Clock Rate (f ) Full IV 32 MHz SCLK SCLK Clock High (t ) Full IV 14 ns HI SCLK Clock Low (t ) Full IV 14 ns LOW SDIO to SCLK Setup Time (t ) Full IV 14 ns DS SCLK to SDIO Hold Time (t ) Full IV 0 ns DH SCLK to SDIO (or SDO) Data Valid Time (t ) Full IV 14 ns DV SEN to SDIO Output Valid to Hi-Z (tEZ) Full IV 2 ns HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 6. Parameter Temp Test Level Min Typ Max Unit READ OPERATION1 (See Figure 50) Output Data Rate Full II 5 80 MSPS Three-State Output Enable Time (t ) Full II 3 ns PZL Three-State Output Disable Time (tPLZ) Full II 3 ns Rx Data Valid Time (t ) Full II 1.5 ns VT Rx Data Output Delay (t ) Full II 4 ns OD WRITE OPERATION (See Figure 49) Input Data Rate (1× Interpolation) Full II 20 80 MSPS Input Data Rate (2× Interpolation) Full II 10 80 MSPS Input Data Rate (4× Interpolation) Full II 5 50 MSPS Tx Data Setup Time (t ) Full II 1 ns DS Tx Data Hold Time (t ) Full II 2.5 ns DH Latch Enable Time (t ) Full II 3 ns EN Latch Disable Time (t ) Full II 3 ns DIS 1 CLOAD = 5 pF for digital data outputs. Rev. C | Page 7 of 47

AD9866 Data Sheet FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted. Table 7. Parameter Temp Test Level Min Typ Max Unit Tx PATH INTERFACE (See Figure 53) Input Nibble Rate (2× Interpolation) Full II 20 160 MSPS Input Nibble Rate (4× Interpolation) Full II 10 100 MSPS Tx Data Setup Time (t ) Full II 2.5 ns DS Tx Data Hold Time (t ) Full II 1.5 ns DH Rx PATH INTERFACE1 (See Figure 54) Output Nibble Rate Full II 10 160 MSPS Rx Data Valid Time (t ) Full II 3 ns DV Rx Data Hold Time (t ) Full II 0 ns DH 1 CLOAD = 5 pF for digital data outputs. Rev. C | Page 8 of 47

Data Sheet AD9866 ABSOLUTE MAXIMUM RATINGS Junction temperature (T) can be estimated using the following J Table 8. equations: Parameter Rating T = T + (Ψ × P), ELECTRICAL J T JT AVDD, CLKVDD Voltage 3.9 V maximum or DVDD, DRVDD Voltage 3.9 V maximum T = T + (Ψ × P) J B JB RX+, RX−, REFT, REFB −0.3 V to AVDD + 0.3 V where: IOUTP+, IOUTP− −1.5 V to AVDD + 0.3 V T is the temperature measured at the top of the package. IOUTN+, IOUTN−, IOUTG+, IOUTG− −0.3 V to 7 V T P is the total device power dissipation. OSCIN, XTAL −0.3 V to CLVDD + 0.3 VS T is the temperature measured at the board. REFIO, REFADJ −0.3 V to AVDD + 0.3 V B Ψ and Ψ are thermal characteristic parameters obtained with Digital Input and Output Voltage −0.3 V to DRVDD + 0.3 V JT JB θ in still air test conditions. Digital Output Current 5 mA maximum JA ENVIRONMENTAL Table 9. Thermal Resistance Operating Temperature Range −40°C to +85°C Package θ θ Unit JA JC (Ambient) CP-64-31 23.32 0.7 °C/W Maximum Junction Temperature 125°C Storage Temperature Range −65°C to +150°C 1 Test condition 1: typical θJA and θJC values are specified for a 4-layer, JESD51-7 (Ambient) high effective thermal conductivity test board for leaded surface-mount packages. θJA is obtained in still air conditions (JESD51-2). Airflow increases Stresses at or above those listed under Absolute Maximum heat dissipation, effectively reducing θJA. θJC is obtained with the test case temperature monitored at the bottom of the exposed pad. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational EXPLANATION OF TEST LEVELS section of this specification is not implied. Operation beyond I 100% production tested. the maximum operating conditions for extended periods may II 100% production tested at 25°C and guaranteed by design affect product reliability. and characterization at specified temperatures. III Sample tested only. THERMAL RESISTANCE IV Parameter is guaranteed by design and characterization Thermal performance is directly linked to printed circuit board testing. (PCB) design and operating environment. Careful attention to V Parameter is a typical value only. PCB thermal design is required. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. The exposed pad (EPAD) must be soldered to the ground plane for the 64-lead LFCSP. The EPAD provides an electrical, thermal, and mechanical connection to the board. ESD CAUTION Rev. C | Page 9 of 47

AD9866 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS N DRVDD DRVSS PWR_DW CLKOUT2 DVDD DVSS CLKVDD OSCIN XTAL CLKVSS CONFIG MODE IOUT_P+ IOUT_P– IOUT_N+ IOUT_G+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ADIO11/Tx[5] 1 48 AVSS ADIO10/Tx[4] 2 47 AVSS PIN 1 ADIO9/Tx[3] 3 IDENTIFIER 46 IOUT_N– ADIO8/Tx[2] 4 45 IOUT_G– ADIO7/Tx[1] 5 44 AVSS ADIO6/Tx[0] 6 43 AVDD AD9866 ADIO5/Rx[5] 7 42 REFIO ADIO4/Rx[4] 8 TOP VIEW 41 REFADJ (Not to Scale) ADIO3/Rx[3] 9 40 AVDD ADIO2/Rx[2] 10 39 AVSS ADIO1/Rx[1] 11 38 RX+ ADIO0/Rx[0] 12 37 RX– RXEN/RXSYNC 13 36 AVSS TXEN/TXSYNC 14 35 AVDD TXCLK/TXQUIET 15 34 AVSS RXCLK 16 33 REFT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DRVDD DRVSS KOUT1 SDIO SDO SCLK SEN PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] RESET AVSS REFB CL AIN/ N1.O TTHEES EXPOSED PAD MUST BE SOLDERED TO GND.G 04560-0-002 Figure 2. Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Mode1 Description 1 ADIO11 HD MSB of ADIO Buffer Tx[5] FD MSB of Tx Nibble Input 2 to 5 ADIO10 to 7 HD Bits 10 to 7 of ADIO Buffer Tx[4 to 1] FD Bits 4 to 1 of Tx Nibble Input 6 ADIO6 HD Bit 6 of ADIO Buffer Tx[0] FD LSB of Tx Nibble Input 7 ADIO5 HD Bit 5 of ADIO Buffer Rx[5] FD MSB of Rx Nibble Output 8, 9 ADIO4, 3 HD Bits 4 to 3 of ADIO Buffer Rx[4, 3] FD Bits 4 to 3 of Rx Nibble Output 10 ADIO2 HD Bit 2 of ADIO Buffer Rx[2] FD Bit 2 of Rx Nibble Output 11 ADIO1 HD Bit 1 of ADIO Buffer Rx[1] FD Bit 1 of Rx Nibble Output 12 ADIO0 HD LSB of ADIO Buffer Rx[0] FD LSB of Rx Nibble Output 13 RXEN HD ADIO Buffer Control Input RXSYNC FD Rx Data Synchronization Output 14 TXEN HD Tx Path Enable Input TXSYNC FD Tx Data Synchronization Input Rev. C | Page 10 of 47

Data Sheet AD9866 Pin No. Mnemonic Mode1 Description 15 TXCLK HD ADIO Sample Clock Input TXQUIET FD Fast TxDAC/IAMP Power-Down 16 RXCLK HD ADIO Request Clock Input FD Rx and Tx Clock Output at 2 × fADC 17, 64 DRVDD Digital Output Driver Supply Input 18, 63 DRVSS Digital Output Driver Supply Return 19 CLKOUT1 fDAC/N Clock Output (L = 1, 2, 4, or 8) 20 SDIO Serial Port Data Input/Output 21 SDO Serial Port Data Output 22 SCLK Serial Port Clock Input 23 SEN Serial Port Enable Input 24 GAIN FD Tx Data Port (Tx[5:0]) Mode Select PGA[5] HD or FD MSB of PGA Input Data Port 25 to 29 PGA[4 to 0] HD or FD Bits 4 to 0 of PGA Input Data Port 30 RESET Reset Input (Active Low) 31, 34, 36, 39, 44, 47, 48 AVSS Analog Ground 32, 33 REFB, REFT ADC Reference Decoupling Nodes 35, 40, 43 AVDD Analog Power Supply Input 37, 38 RX−, RX+ Receive Path − and + Analog Inputs 41 REFADJ TxDAC Full-Scale Current Adjust 42 REFIO TxDAC Reference Input/Output 45 IOUT_G− −Tx Amp Current Output_Sink 46 IOUT_N− −Tx Mirror Current Output_Sink 49 IOUT_G+ +Tx Amp Current Output_Sink 50 IOUT_N+ +Tx Mirror Current Output_Sink 51 IOUT_P− −TxDAC Current Output_Source 52 IOUT_P+ +TxDAC Current Output_Source 53 MODE Digital Interface Mode Select Input LOW = HD, HIGH = FD 54 CONFIG Power-Up SPI Register Default Setting Input 55 CLKVSS Clock Oscillator/Synthesizer Supply Return 56 XTAL Crystal Oscillator Inverter Output 57 OSCIN Crystal Oscillator Inverter Input 58 CLKVDD Clock Oscillator/Synthesizer Supply 59 DVSS Digital Supply Return 60 DVDD Digital Supply Input 61 CLKOUT2 f /L Clock Output, (L = 1, 2, or 4) OSCIN 62 PWR_DWN Power-Down Input EPAD The exposed pad must be soldered to GND. 1 HD = half-duplex mode; FD = full-duplex mode. Rev. C | Page 11 of 47

AD9866 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = f = 50 MSPS, low-pass filter’s f = 22 MHz, AIN = −1 dBFS, OSCIN ADC −3 dB RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 10 65 10.5 FUND =–1dBFS m) 0 SEINNOABD == 1601B.9ITdSBFS 62 15MMHHzz 10.0 RUM (dB––2100 STSRHNFBDDRWR = == =– 6164–25.6.5.244d1.dB9kBdFHBFSzSc (THIRD HARMONIC) 59 112050MMMHHHzzz 9.5 T TO INPUT SPEC––––65430000 SINAD (dBFS) 555630 889...050 ENOB (Bits) D RE–70 47 7.5 R REFE–1––098000 04560-0-003 4414 67..50 04560-0-006 0 6.25 12.50 18.75 25.00 –6 0 6 12 18 24 30 36 42 48 FREQUENCY (MHz) RxPGA GAIN (dB) Figure 3. Spectral Plot with 4k FFT of Input Sinusoid Figure 6. SINAD/ENOB vs. RxPGA Gain and Frequency with RxPGA = 0 dB and PIN = 9 dBm –30 –55 RBW = 12.2kHz 1MHz –40 5MHz Bm)–50 –60 1105MMHHzz M (d 20MHz U–60 R –65 T EC–70 c) P B RRED S––9800 THD (d–70 E REF–100 –75 T INPU–––111321000 04493-0-041 ––8850 04560-0-007 0 5 10 15 20 25 –6 0 6 12 18 24 30 36 42 48 FREQUENCY (MHz) RxPGA GAIN (dB) Figure 4. Spectral Plot with 4k FFT of 84-Carrier DMT Signal Figure 7. THD vs. RxPGA Gain and Frequency with PAR = 10.2 dB, PIN = −33.7 dBm, and RxPGA = 36 dB 66 –50 65 –45 SINAD @ +25C SINAD @ +85C 63 –56 62 SINAD @–40C –50 SINAD @ 3.14V SINAD @ 3.3V 60 SINAD @ 3.46V –62 59 –55 THD @ +25C SINAD (dBFS) 5574 TTTHHHDDD @@@ 333...1344V6VV ––7648 THD (dBFS) SINAD (dBFS) 5536 TTHHDD @@ –+4805CC ––6650 THD (dBc) 51 –80 50 –70 4458 ––9826 04560-0-005 4447 ––8705 04560-0-008 –21 –18 –15 –12 –9 –6 –3 0 –6 0 6 12 18 24 30 36 42 48 INPUT AMPLITUDE (dBFS) RxPGA GAIN (dB) (0dBFS = 2V p-p) Figure 5. SINAD and THD vs. Input Amplitude and Supply Figure 8. SINAD/THD Performance vs. RxPGA Gain (fIN = 8 MHz, LPF f−3 dB = 26 MHz; Rx PGA = 0 dB) and Temperature ( fIN = 5 MHz) Rev. C | Page 12 of 47

Data Sheet AD9866 Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = f = 80 MSPS, low-pass filter’s f = 30 MHz, AIN = −1 dBFS, OSCIN ADC −3 dB RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 10 65 10.5 FUND =–1dBFS RUM (dBm)––21000 SESTSRHINNFBNDDORWAR B= D== = =– 6=1 63– 1969.70.42.50.3d.13.4dB5BkdBdFHIBTBFSzFSScS (THIRD HARMONIC) 6529 51123M0500MMMMHHHHHzzzzz 190.5.0 T TO INPUT SPEC––––65430000 SINAD (dBFS) 555036 889...050 ENOB (Bits) D E–70 RR 47 7.5 REFE–1––0980000 10 20 30 4004560-0-009 4414–6 0 6 12 18 24 30 36 42 4867..50 04560-0-012 FREQUENCY (MHz) RxPGA GAIN (dB) Figure 9. Spectral Plot with 4k FFT of Input Sinusoid Figure 12. SINAD/ENOB vs. RxPGA Gain and Frequency with RxPGA = 0 dB and PIN = 9 dBm –30 –55 RBW = 19.53kHz –40 Bm)–50 –60 d M ( U–60 R –65 T PEC–70 Bc) RED S–80 HD (d–70 R–90 T E REF–100 –75 5MHz PUT –110 1105MMHHzz IN––113200 04560-0-010 ––8805 2300MMHHzz 04560-0-013 0 10 20 30 40 –6 0 6 12 18 24 30 36 42 48 FREQUENCY (MHz) RxPGA GAIN (dB) Figure 10. Spectral Plot with 4K FFT of 111-Carrier DMT Signal Figure 13. THD vs. RxPGA Gain and Frequency with PAR = 11 dB, PIN = −33.7 dBm, LPF's f−3 dB = 32 MHz and RxPGA = 36 dB 66 –50 65 –40 SINAD @ +25C 63 SINAD @ 3.14V –56 61 SINAD @ +85C –45 SINAD @ 3.3V SINAD @–40C SINAD @ 3.46V 59 –50 60 –62 SINAD (dBFS) 5574 TTHHDD @@ 33..134VV ––7648 THD (dBFS) SINAD (dBFS) 555630 –––665505 THD (dBc) THD @ 3.46V 51 –80 47 –70 4458–21 –18 –15 –12 –9 –6 –3 0––9826 04560-0-011 4441 TTTHHHDDD @@@ ++–428055CCC ––8705 04560-0-014 –6 0 6 12 18 24 30 36 42 48 INPUT AMPLITUDE (dBFS) (0dBFS = 2V p-p) RxPGA GAIN (dB) Figure 11. SINAD and THD vs. Input Amplitude and Supply Figure 14. SINAD/THD Performance vs. RxPGA Gain and Temperature (fIN = 8 MHz, LPF f−3 dB = 26 MHz; RxPGA = 0 dB) (fIN = 10 MHz) Rev. C | Page 13 of 47

AD9866 Data Sheet 65.0 –52 63 –20 SNR @ 3.14V 64.5 SNR @ 3.3V –54 62 –25 SNR @ 3.47V 64.0 –56 61 –30 63.5 –58 60 SNR vs. MSPS @ 3.0VSUP –35 SNR vs. MSPS @ 346VSUP SNR (dBFS)666223...050 TTTHHHDDD @@@ 333...1344V7VV –––666024 THD (dBc) SNR (dBFS) 555789 SNR @ 3.13V TTHHDD @@ 33..1436VV –––544050 THD (dBc) THD @ 3.3V 61.5 –66 56 –55 61.0 –68 55 –60 6600..50 ––7702 04560-0-015 5534 ––7605 04560-0-018 0 5 10 15 20 35 30 20 30 40 50 60 70 80 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 15. SNR and THD vs. Input Frequency and Supply Figure 18. SNR and THD vs. Sample Rate and Supply ( LPF f−3 dB = 26 MHz; RxPGA = 0 dB) (LPF Disabled; RxPGA = 0 dB; fIN = 8 MHz) 109.4 20 45 98.5 18 Hz) 44 V rms)7867..65 1164 Y (nV/ 43 RATED NOISE (455346...876 –40C 11820 ECTRAL DENSIT SNR (dB) 4412 INTEG2312..98 +85C 64 OISE SP 40 10.90 +25C 20 N04560-0-016 3389 04560-0-019 18 24 30 36 42 48 0 10 20 30 40 50 60 70 80 RxPGA GAIN (dB) CUTOFF FREQUENCY (MHz) Figure 16. Input Referred Integrated Noise and Noise Spectral Density Figure 19. SNR vs. Filter Cutoff Frequency vs. RxPGA Gain (LPF f−3 dB = 26 MHz) (50 MSPS; fIN = 5 MHz; AIN = −1 dB; RxPGA = 48 dB) 5 0.5 4 0.4 3 0.3 e) scal 2 dB) 0.2 FFSET (% of full – 011 N STEP ERROR (–00..011 C O –2 GAI–0.2 D DEVICE 1 –3 DEVICE 2 –0.3 ––54 DDEEVVIICCEE 34 04560-0-017 ––00..54 AAADDD999888666666::: GGGAAAIIINNN SSSTTTEEEPPP EEERRRRRROOORRR @@@ –++428055CCC 04560-0-020 –6 0 6 12 18 24 30 36 42 48 –6 0 6 12 18 24 30 36 42 48 GAIN (dB) RxPGA GAIN (dB) Figure 17. Rx DC Offset vs. RxPGA Gain Figure 20. RxPGA Gain Step Error vs. Gain (fIN = 10 MHz) Rev. C | Page 14 of 47

Data Sheet AD9866 Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = f = 50 MSPS, low-pass filter disabled, RxPGA = 0 dB, AIN = −1 dBFS, OSCIN ADC RIN = 50 Ω, half- or full-duplex interface, default power bias settings. 2048 1408 1280 1792 1152 1536 1024 E1280 E 896 D D O O C1024 C 768 640 768 512 255162 04560-0-021 235864 04560-0-024 0 80 160 240 320 400 480 560 640 720 0 80 160 240 320 400 480 560 640 720 TIME (ns) TIME (ns) Figure 21. RxPGA Settling Time −12 dB to +48 dB Transition for DC Input Figure 24. RxPGA Settling Time for 0 dB to +5 dB Transition for DC Input (fADC = 50 MSPS, LPF Disabled) (fADC = 50 MSPS, LPF Disabled) 0 0 3.3V –6dB GAIN 3.0V –2 0dB GAIN 3.6V +6dB GAIN –3 –4 B) d SE ( –6 dB) –6 ON L ( –8 P A RES –9 ENT–10 PLITUDE –12 FUNDAM––1142 +++134802dddBBB GGGAAAIIINNN M A –16 –15 –18 04560-0-022 ––2108 04560-0-025 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 22. Rx Low-Pass Filter Amplitude Response vs. Supply Figure 25. Rx Low-Pass Filter Amplitude Response vs. RxPGA Gain (fADC = 50 MSPS, f−3 dB = 33 MHz, RxPGA = 0 dB) (LPF's f−3 dB = 33 MHz) 140 420 10 410 9 130 TxDAC ISOLATION @ 0dB 400 8 B)120 N (d@RxPGA = 0dB11901000 ESISTANCE ()333367890000 RIN 4567 PACITANCE (pF) TTE R350 CIN 3 CA A 80 IAMP ISOLATION @ 0dB 340 2 6700 04560-0-023 332300 01 04493-0-026 0 5 10 15 20 25 30 35 5 15 25 35 45 55 65 75 85 95 105 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. Rx to Tx Full-Duplex Isolation @ 0 RxPGA Setting Figure 26. Rx Input Impedance vs. Frequency (Note: ATTEN @ RxPGA = x dB = ATTEN @ RxPGA = 0 dB − RxPGA Gain) Rev. C | Page 15 of 47

AD9866 Data Sheet TxDAC PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = 50 MSPS and 80 MSPS, RSET = 1.96 kΩ, 2:1 transformer coupled output (see Figure 63) into 50 Ω load half-or full-duplex interface, default power bias settings. 10 10 0 0 –10 –10 –20 –20 –30 –30 m m B B d–40 d–40 –50 –50 –60 –60 ––8700 04493-0-072 ––8700 04560-0-030 0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 27. Dual-Tone Spectral Plot of TxDAC's Output Figure 30. Dual-Tone Spectral Plot of TxDAC's Output (fDATA = 50 MSPS, 4× Interpolation, 10 dBm Peak Power, (fDATA = 80 MSPS, 2× Interpolation, 10 dBm Peak Power, F1 = 17 MHz, F2 = 18 MHz) F1 = 27.1 MHz, F2 = 28.7 MHz) –65 –65 –70 –70 R) R) 10dBm E E W W O O S)K P–75 S)K P–75 BFEA 4dBm BFEA 4dBm IMD (dATIVE TO P–80 7dBm IMD (dATIVE TO P–80 7dBm EL EL R R ( 10dBm ( –85 –85 –90 04560-0-028 –90 04560-0-031 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 0 5 10 15 20 25 30 2-TONE CENTER FREQUENCY (MHz) 2-TONE CENTER FREQUENCY (MHz) Figure 28. 2-Tone IMD Frequency Sweep vs. Peak Power Figure 31. 2-Tone IMD Frequency Sweep vs. Peak Power with fDATA = 50 MSPS, 4× Interpolation with fDATA = 80 MSPS, 2× Interpolation –65 –65 –70 –70 R) R) WE WE 10dBm O O SFDR (dBFS)ATIVE TO PEAK P––8705 10dBm 7dBm 4dBm SFDR (dBFS)ATIVE TO PEAK P––8705 4dBm EL EL (R (R 7dBm –85 –85 –90 04560-0-029 –90 04560-0-032 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 0 5 10 15 20 25 30 2-TONE CENTER FREQUENCY (MHz) 2-TONE CENTER FREQUENCY (MHz) Figure 29. 2-Tone Worst Spur Frequency Sweep vs. Peak Power Figure 32. 2-Tone Worst Spur Frequency Sweep vs. Peak Power with fDATA = 50 MSPS, 4× Interpolation with fDATA = 80 MSPS, 2× Interpolation Rev. C | Page 16 of 47

Data Sheet AD9866 –20 PAR = 11.4 –20 RMS =–1.4 PAR = 11.4 –30 dBm RMS =–1.4dBm –30 –40 –40 –50 –50 m dB–60 Bm–60 d –70 –70 –80 –80 ––109000 5 10 15 20 2504560-0-033 –1–0900 04493-0-081 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. Spectral Plot of 84-Carrier OFDM Test Vector Figure 36. Spectral Plot of 111-Carrier OFDM Test Vector fDATA = 50 MSPS, 4× Interpolation) (fDATA = 80 MSPS, 2× Interpolation) –20 PAR = 11.4 –20 PAR = 11.4 RMS =–1.4dBm RMS =–1.4dBm –30 –30 –40 –40 –50 –50 m dB–60 Bm–60 d –70 –70 –80 –80 ––109000 25 50 75 100 125 150 175 20004493-0-079 –1–0900 04493-0-082 0 20 40 60 80 100 120 140 160 FREQUENCY (MHz) FREQUENCY (MHz) Figure 34. Wideband Spectral Plot of 88-Subcarrier OFDM Test Vector Figure 37. Wideband Spectral Plot of 111-Carrier OFDM Test Vector (fDATA = 50 MSPS, 4× Interpolation) (fDATA = 80 MSPS, 2× Interpolation) 105 100 100 95 2-TONE IMD SNR AND 2-TONE IMD (dBFS)(RELATIVE TO PEAK POWER) 67788995050505 SNR SNR AND 2-TONE IMD (dBFS)(RELATIVE TO PEAK POWER) 677889505050 2-TONSEN RIMD 5650–24 –21 –18 –15 –12 –9 –6 –3 004560-0-035 5650–24 –21 –18 –15 –12 –9 –6 –3 004560-0-038 AOUT (dBFS) AOUT (dBFS) Figure 35. SNR and SFDR vs. POUT Figure 38. SNR and SFDR vs. POUT (fOUT = 12.55 MHz, fDATA = 50 MSPS, 4× Interpolation) (fOUT = 20 MHz, fDATA = 80 MSPS, 2× Interpolation) Rev. C | Page 17 of 47

AD9866 Data Sheet IAMP PATH TYPICAL PERFORMANCE CHARACTERISTICS AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, f = 50 MSPS, R = 1.58 kΩ, 1:1 transformer coupled output (see Figure 64 and OSCIN SET Figure 65) into 50 Ω load, half- or full-duplex interface, default power bias settings. 20 48 15 RBW = 2.3kHz 2.5MHz 10 46 5MHz 5 44 0 –5 42 –10 m) dBm–––221505 P3 (dB 4308 10MHz –30 OI 15MHz 20MHz –35 36 –40 34 –45 –––655050 04493-0-084 3302 04493-0-087 0 5 10 15 20 25 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) VCM (V) Figure 39. Dual-Tone Spectral Plot of IAMPN Output (IAMP Settings of Figure 42. IOUTN Third-Order Intercept vs. Common-Mode Voltage I = 12.5 mA, N = 4, G = 0, 2:1 Transformer into 75 Ω Loader, VCM = 4.8 V) (IAMP Settings of I = 12.5 mA, N = 4, G = 0, 2:1 Transformer into 75 Ω Load) 0 42 PAR = 11.4 RMS = 10.3dBm –10 40 2.5MHz –20 38 –30 m) dBm–40 P3 (dB 36 5MHz OI –50 10MHz 34 –60 15MHz 32 ––8700 04493-0-085 30 20MHz 04493-0-088 0 5 10 15 20 25 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) VCM (V) Figure 40. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMPN in Figure 43. IOUTG Third-Order Intercept vs. Common-Mode Voltage Current-Mode Configuration (IAMP Settings of I = 4.25 mA, N = 0, G = 6, 2:1 Transformer into 75 Ω Load) (IAMP Settings of I = 10 mA, N = 4, G = 0; VCM = 4.8 V) 0 0 PAR = 11.4 PAR = 11.4 RMS = 10.4dBm RMS = 9.8dBm –10 –10 RBW = 10kHz –20 –20 –30 –30 m m B–40 B–40 d d –50 –50 –60 –60 ––8700 04493-0-086 ––8700 04493-0-089 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 41. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMP in Figure 44. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMP in Voltage-Mode Configuration with AVDD = 5 V Voltage-Mode Configuration with AVDD = 3.3 V (PBR951 Transistors, IAMP Settings of I = 6 mA, N = 2, G = 6) (PBR951 Transistors, IAMP Settings of I = 6 mA, N = 2, G = 6) Rev. C | Page 18 of 47

Data Sheet AD9866 SERIAL PORT Table 11. SPI Register Mapping Power-Up Default Value Bit Address Break- MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex) (Hex) 1 down Description Width CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 Comments SPI PORT CONFIGURATION AND SOFTWARE RESET 0x00 (7) 4-Wire SPI 1 0 0 0 0 Default SPI configuration is (6) LSB First 1 0 0 0 0 3-wire, MSB first. (5) S/W Reset 1 0 0 0 0 POWER CONTROL REGISTERS (VIA PWR_DWN PIN) 0x01 (7) Clock Syn. 1 0 0 0 0 PWR_DWN = 0. (6) TxDAC/IAMP 1 0 0 0 0 Default setting is for all blocks powered on. (5) Tx Digital 1 0 0 0 0 (4) REF 1 0 0 0 0 (3) ADC CML 1 0 0 0 0 (2) ADC 1 0 0 0 0 (1) PGA Bias 1 0 0 0 0 (0) RxPGA 1 0 0 0 0 0x02 (7) CLK Syn. 1 0 0 0 1* PWR_DWN = 1. (6) TxDAC/IAMP 1 1 1 1 1 Default setting* is for all functional blocks powered (5) Tx Digital 1 1 1 1 1 down except PLL. (4) REF 1 1 1 1 1 *MODE = CONFIG = 1. (3) ADC CML 1 1 1 1 1 Setting has PLL powered (2) ADC 1 1 1 1 1 down with OSCIN input routed to RXCLK output. (1) PGA Bias 1 1 1 1 1 (0) RxPGA 1 1 1 1 1 HALF-DUPLEX POWER CONTROL 0x03 (7:3) Tx OFF Delay 5 Default setting is for TXEN (2) Rx _TXEN 1 input to control power 0xFF 0xFF N/A N/A on/off of Tx/Rx path. (1) Tx PWRDN 1 Tx driver delayed by 31 (0) Rx PWRDN 1 1/f clock cycles. DATA PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL 0x04 (5) Duty Cycle Enable 1 0 0 0 0 Default setting is Duty Cycle (4) fADC from PLL 1 0 0 0 0 Restore disabled, ADC CLK from OSCIN input, and PLL (3:2) PLL Divide-N 2 00 00 00 00 multiplier × 2 setting. (1:0) PLL Multiplier-M 2 01 10* 01 01 *PLL multiplier × 4 setting. 0x05 (2) OSCIN to RXCLK 1 0 0 0 1* Full-duplex RXCLK normally (1) Invert RXCLK 1 0 0 0 0 at nibble rate. *Exception on power-up. (0) Disabled RXCLK 1 0 0 0 0 0x06 (7:6) CLKOUT2 Divide 2 01 01 01 01 Default setting is CLKOUT2 (5) CLKOUT2 Invert 1 0 0 0 0 and CLKOUT1 enabled with divide-by-2. (4) CLKOUT2 Disable 1 0 0 0 1* *CLKOUT1 and CLKOUT2 (3:2) CLKOUT1 Divide 2 01 01 01 01 disabled. (1) CLKOUT1 Invert 1 0 0 0 0 (0) CLKOUT1 Disable 1 0 0 0 1* Rev. C | Page 19 of 47

AD9866 Data Sheet Power-Up Default Value Bit Address Break- MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex) (Hex) 1 down Description Width CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 Comments Rx PATH CONTROL 0x07 (5) Initiate Offset Cal. 1 0 0 0 0 Default setting has LPF ON (4) Rx Low Power 1 0 1* 0 1* and Rx path at nominal power bias setting. (0) Rx Filter ON 1 1 1 1 1 *Rx path to low power. 0x08 (7:0) Rx Filter Tuning 8 Refer to Low-Pass Filter 0x80 0x61 0x80 0x80 Cutoff Frequency section. Tx/Rx PATH GAIN CONTROL 0x09 (6) Use SPI Rx Gain 1 Default setting is for hardware (5:0) Rx Gain Code 6 0x00 0x00 0x00 0x00 Rx gain code via PGA or Tx data port. 0x0A (6) Use SPI Tx Gain 1 Default setting is for Tx gain (5:0) Tx Gain Code 6 0x7F 0x7F 0x7F 0x7F code via SPI control. Tx AND Rx PGA CONTROL 0x0B (6) PGA Code for Tx 1 0 0 0 0 Default setting is RxPGA (5) PGA Code for Rx 1 1 1 1 1 control active. *Tx port with GAIN strobe (3) Force GAIN strobe 1 0 0 0 0 (AD9875/AD9876 (2) Rx Gain on Tx Port 1 0 0 1* 1* compatible). (1) 3-Bit RxPGA Port 1 0 1** 0 0 **3-bit RxPGA gain map (AD9975 compatible). Tx DIGITAL FILTER AND INTERFACE 0x0C (7:6) Interpolation 2 01 00 01 01 Default setting is 2× interpo- Factor lation with LPF response. (4) Invert 1 0 0 0 0 Data format is straight binary TXEN/TXSYNC for half-duplex and twos complement for full-duplex (2) LS Nibble First* 1 N/A N/A 0 0 interface. (1) TXCLK neg. edge 1 0 0 0 0 *Full-duplex only. (0) Twos complement 1 0 0 1 1 Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK 0x0D (7) Analog Loopback 1 0 0 0 0 Data format is straight (6) Digital Loopback* 1 0 0 0 0 binary for half-duplex and twos complement for full- (5) Rx Port 3-State 1 N/A N/A 0 0 duplex interface. (4) Invert 1 0 0 0 0 Analog loopback: ADC Rx RXEN/RXSYNC data fed back to TxDAC. (2) LS Nibble First* 1 N/A N/A 0 0 Digital loopback: Tx input (1) RXCLK neg. edge 1 0 0 0 0 data to Rx output port. *Full-duplex only. (0) Twos complement 1 0 0 1 1 DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID 0x0E (7) Low Drive 1 0 0 0 0 Default setting is for high Strength drive strength and IAMP (0) TxDAC Output 1 0 0 0 0 enabled. 0x0F (3:0) REV ID Number 4 0x00 0x00 0x00 0x00 Rev. C | Page 20 of 47

Data Sheet AD9866 Power-Up Default Value Bit Address Break- MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex) (Hex) 1 down Description Width CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 Comments Tx IAMP GAIN AND BIAS CONTROL 0x10 (7) Select Tx Gain 1 Secondary path G1 = 0, 1, 2, (6:4) G1 3 0x44 0x44 0x44 0x44 3, 4. Primary path N = 0, 1, 2, 3, 4. (2:0) N 3 0x11 (6:4) G2 3 Secondary path stages: (2:0) G3 3 0x62 0x62 0x62 0x62 G2 = 0 to 1.50 in 0.25 steps and G3 = 0 to 6. 0x12 (6:4) Stand Secondary 3 Standing current of primary (2:0) Stand Primary 3 0x01 0x01 0x01 0x01 and secondary path. 0x13 (7:5) CPGA Bias Adjust 3 Current bias setting for Rx (4:3) SPGA Bias Adjust 2 0x00 0x00 0x00 0x00 path’s functional blocks. Refer to Page 41. (2:0) ADC Bias Adjust 4 1 Bits that are undefined should always be assigned a 0. REGISTER MAP DESCRIPTION Table 12. SPI Registers Pertaining to SPI Options Address (Hex) Bit Description The AD9866 contains a set of programmable registers described in Table 11 that are used to optimize its numerous features, 0x00 (7) Enable 4-wire SPI interface options, and performance parameters from its default (6) Enable SPI LSB first register settings. Registers pertaining to similar functions have A 4-wire SPI can be enabled by setting the 4-wire SPI bit high, been grouped together and assigned adjacent addresses to causing the output data to appear on the SDO pin instead of on minimize the update time when using the multibyte serial port the SDIO pin. The SDIO pin serves as an input-only throughout interface (SPI) read/write feature. Bits that are undefined within the read operation. Note that the SDO pin is active only during a register should be assigned a 0 when writing to that register. the transmission of data and remains three-stated at any other The default register settings were intended to allow some time. applications to operate without the use of an SPI. The AD9866 An 8-bit instruction header must accompany each read and can be configured to support a half- or full-duplex digital write operation. The instruction header is shown in Table 13. interface via the MODE pin, with each interface having two The MSB is an R/Windicator bit with logic high indicating a possible default register settings determined by the setting of read operation. The next two bits, N1 and N0, specify the the CONFIG pin. number of bytes (one to four bytes) to be transferred during the For instance, applications that need to use only the Tx or Rx data transfer cycle. The remaining five bits specify the address path functionality of the AD9866 can configure it for a half- bits to be accessed during the data transfer portion. The data duplex interface (MODE = 0), and use the TXEN pin to select bits immediately follow the instruction header for both read between the Tx or Rx signal path with the unused path and write operations. remaining in a reduced power state. The CONFIG pin can be used to select the default interpolation ratio of the Tx path and Table 13. Instruction Header Information RxPGA gain mapping. MSB LSB 17 16 15 14 13 12 11 10 SERIAL PORT INTERFACE (SPI) R/W N1 N0 A4 A3 A2 A1 A0 The serial port of the AD9866 has 3- or 4-wire SPI capability allowing read/write access to all registers that configure the The AD9866 serial port can support both MSB (most significant device’s internal parameters. Registers pertaining to the SPI are bit) first and LSB (least significant bit) first data formats. Figure 45 listed in Table 12. The default 3-wire serial communication port illustrates how the serial port words are built for the MSB first and consists of a clock (SCLK), serial port enable (SEN), and a LSB first modes. The bit order is controlled by the SPI LSB first bit (Register 0, Bit 6). The default value is 0, MSB first. Multibyte data bidirectional data (SDIO) signal. SEN is an active low control transfers in MSB format can be completed by writing an instruc- gating read and write cycle. When SEN is high, SDO and SDIO tion byte that includes the register address of the last address to be are three-stated. The inputs to SCLK, SEN, and SDIO contain a accessed. The AD9866 automatically decrements the address for Schmitt trigger with a nominal hysteresis of 0.4 V centered each successive byte required for the multibyte communication about VDDH/2. The SDO pin remains three-stated in a 3-wire cycle. SPI interface. Rev. C | Page 21 of 47

AD9866 Data Sheet SEN INSTRUCTIONCYCLE DATATRANSFERCYCLE SEN tS1/fSCLK tH SCLK tHI tLOW SCLK SDATA R/W N1 N2 A4 A3 A2 A1 A0 D71 D61 D1N D0N tDS SDIO RtD/WH N1 N0 A0 D7 D6 D1 D0 04560-0-046 Figure 46. SPI Write Operation Timing INSTRUCTIONCYCLE DATATRANSFERCYCLE SEN Figure 47 illustrates the timing for a 3-wire read operation to SCLK the SPI port. After SEN goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of SCLK. A read SDATA A0 A1 A2 A3 A4 N2 N1 R/W D01D11 D6N D7N 04560-0-045 Aopfteerra ttihoen a odcdcruersss ibf itths eo fr ethade /innostt-rwucrtiitoe nin hdeiacdateorr a irse s reeta hdi,g thh.e eight data bits pertaining to the specified register are shifted out Figure 45. SPI Timing, MSB First (Upper) and LSB First (Lower) of the SDIO pin on the falling edges of the next eight clock When the SPI LSB first bit is set high, the serial port interprets cycles. If a multibyte communication cycle is specified in the both instruction and data bytes LSB first. Multibyte data trans- instruction header, a similar process as previously described for fers in LSB format can be completed by writing an instruction a multibyte SPI write operation applies. The SDO pin remains byte that includes the register address of the first address to be three-stated in a 3-wire read operation. accessed. The AD9866 automatically increments the address for tS1/fSCLK each successive byte required for the multibyte communication SEN cycle. tHI tLOW SCLK Ftiiognu rteo 4th6e i lSluPsIt rpaotrets. tAhfet etirm thine gs erreiqaul iproemrt eenntasb floer ( aS EwNri)t es iogpnearl a- SDIO tDS RtD/WH N1 A2 A1 A0 tDVD7 D6 D1 D0 tEZ 04560-0-047 goes low, data (SDIO) pertaining to the instruction header is Figure 47. SPI 3-Wire Read Operation Timing read on the rising edges of the clock (SCLK). To initiate a write Figure 48 illustrates the timing for a 4-wire read operation to operation, the read/not-write bit is set low. After the instruction the SPI port. The timing is similar to the 3-wire read operation header is read, the eight data bits pertaining to the specified with the exception that data appears at the SDO pin, while the register are shifted into the SDIO pin on the rising edge of the SDIO pin remains high impedance throughout the operation. next eight clock cycles. If a multibyte communication cycle is The SDO pin is an active output only during the data transfer specified, the destination address is decremented (MSB first) phase and remains three-stated at all other times. and shifts in another eight bits of data. This process repeats until all the bytes specified in the instruction header (N1, N0 tS 1/fSCLK SEN bits) are shifted into the SDIO pin. SEN must remain low tHI tLOW during the data transfer operation, only going high after the last SCLK bit is shifted into the SDIO pin. tDS tDH tEZ SDIO R/W N1 A2 A1 A0 SDO tDVD7 D6 D1 D0 tEZ 04560-0-048 Figure 48. SPI 4-Wire Read Operation Timing Rev. C | Page 22 of 47

Data Sheet AD9866 DIGITAL INTERFACE internal FIFO delay. Note that Rx data is not latched back into The digital interface port is configurable for half-duplex or full- the Tx path, if TXEN is high during this interval with TXCLK duplex operation by pin-strapping the MODE pin low or high, present. The ADIO bus becomes three-stated once the RXEN respectively. In half-duplex mode, the digital interface port pin returns low. Figure 50 shows the receive path output timing. becomes a 10-bit bidirectional bus called the ADIO port. In full-duplex mode, the digital interface port is divided into two RXCLK 6-bit ports called Tx[5:0] and Rx[5:0] for simultaneous Tx and RAflexSx IoiCbp leaern dadtii gAointDasl.9 iI8nn6t e6trh ifinas c 6me- bfooidtr e nu, ipdbdabtalaet isin.s g Tt rhtahene As RfeDxrP9re8Gd6A 6b eaatlnwsdoe eTfenxa PttuhGreeA s a ADIOR[X9E:0N] tPZL tVTRX0 RX1 tRPXtL2OZDRX3 04560-0-050 gain registers via a 6-bit PGA port or Tx[5:0] port for fast Figure 50. Receive Data Output Timing Diagram updates, or via the SPI port for slower updates. See the RXPGA To add flexibility to the digital interface port, several program- Control section for more information. ming options are available in the SPI registers. These options HALF-DUPLEX MODE are listed in Table 14. The default Tx and Rx data input formats are straight binary, but can be changed to twos complement. The half-duplex mode functions as follows when the MODE The default TXEN and RXEN settings are active high, but can pin is tied low. The bidirectional ADIO port is typically shared be set to opposite polarities, thus allowing them to share the in burst fashion between the transmit path and receive path. same control. In this case, the ADIO port can still be placed Two control signals, TXEN and RXEN, from a DSP (or digital onto a shared bus by disabling its input latch via the control ASIC) control the bus direction by enabling the ADIO port’s signal, and disabling the output driver via the SPI register. The input latch and output driver, respectively. Two clock signals are clock timing can be independently changed on the transmit and also used: TXCLK to latch the Tx input data, and RXCLK to receive paths by selecting either the rising or falling clock edge clock the Rx output data. The ADIO port can also be disabled as the validating/sampling edge of the clock. Lastly, the output by setting TXEN and RXEN low (default setting), thus allowing driver’s strength can be reduced for lower data rate applications. it to be connected to a shared bus. Internally, the ADIO port consists of an input latch for the Tx Table 14. SPI Registers for Half-Duplex Interface path in parallel with an output latch with three-state outputs for Address (Hex) Bit Description the Rx path. TXEN is used to enable the input latch; RXEN is 0x0C (4) Invert TXEN used to three-state the output latch. A five-sample-deep FIFO is (1) TXCLK negative edge used on the Tx and Rx paths to absorb any phase difference be- (0) Twos complement tween the AD9866’s internal clocks and the externally supplied 0x0D (5) Rx port three-state clocks (TXCLK, RXCLK). The ADIO bus accepts input data- (4) Invert RXEN words into the transmit path when the TXEN pin is high, the (1) RXCLK negative edge RXEN pin is low, and a clock is present on the TXCLK pin, as (0) Twos complement shown in Figure 49. 0x0E (7) Low digital drive strength tDS TXCLK The half-duplex interface can be configured to act like a slave or a master to the digital ASIC. An example of a slave configura- TXEN tEN tDH tDIS tion is shown in Figure 51. In this example, the AD9866 accepts ADIO[9:0] TX0 TX1 TX2 TX3 TX4 all the clock and control signals from the digital ASIC. Because RXEN 04560-0-049 tnhaell ysa fmropmlin tgh ec lOocSkCsI fNor s tighne aDl,A itC is a rnedq uAirDeCd tahraet d tehrei vTeXd CinLtKer -and RXCLK signals be at exactly the same frequency as the OSCIN Figure 49. Transmit Data Input Timing Diagram signal. The phase relationships among the TXCLK, RXCLK, The Tx interpolation filter(s) following the ADIO port can be and OSCIN signals can be arbitrary. If the digital ASIC cannot flushed with zeros, if the clock signal into the TXCLK pin is provide a low jitter clock source to OSCIN, use the AD9866 to present for 33 clock cycles after TXEN goes low. Note that the generate the clock for its DAC and ADC, and pass the desired data on the ADIO bus is irrelevant over this interval. clock signal to the digital ASIC via CLKOUT1 or CLKOUT2. The output from the receive path is driven onto the ADIO bus when the RXEN pin is high, and a clock is present on the RXCLK pin. While the output latch is enabled by RXEN, valid data appears on the bus after a 6-clock-cycle delay due to the Rev. C | Page 23 of 47

AD9866 Data Sheet DIGITAL ASIC AD9866 The AD9866 acts as the master, providing RXCLK as an output clock that is used for the timing of both the Tx[5:0] and Rx[5:0] ADIO 12 TO [11:0] Tx DIGITAL ports. RXCLK always runs at the nibble rate and can be inverted Tx/Rx FILTER or disabled via an SPI register. Because RXCLK is derived from Data[11:0] 12 FROM the clock synthesizer, it remains active, provided that this func- Rx ADC tional block remains powered on. A buffered version of the RXEN RXEN signal appearing at OSCIN can also be directed to RXCLK by TXEN TXEN setting Bit 2 of Register 0x05. This feature allows the AD9866 to DAC_CLK TXCLK be completely powered down (including the clock synthesizer) ADC_CLK RXCLK CLKOUT OSCIN 04560-0-051 wThheil eT sxe[r5v:0in] gp oasr tt hoep emraatsetse ri.n the following manner with the SPI Figure 51. Example of a Half-Duplex Digital Interface register default settings. Two consecutive nibbles of the Tx data are with AD9866 Serving as the Slave multiplexed together to form a 10-bit data-word in twos complement format. The clock appearing on the RXCLK pin is a buffered version Figure 52 shows a half-duplex interface with the AD9866 acting of the internal clock used by the Tx[5:0] port’s input latch with a as the master, generating all the required clocks. CLKOUT1 frequency that is always twice the ADC sample rate (2 × f ). Data provides a clock equal to the bus data rate that is fed to the ADC from the Tx[5:0] port is read on the rising edge of this sampling ASIC as well as back to the TXCLK and RXCLK inputs. This clock, as illustrated in the timing diagram shown in Figure 53. interface has the advantage of reducing the digital ASIC’s pin Note, TXQUIET must remain high for the reconstructed Tx data to count by three. The ASIC needs only to generate a bus control signal that controls the data flow on the bidirectional bus. appear as an analog signal at the output of the TxDAC or IAMP. tDS DIGITAL ASIC AD9866 RXCLK ADIO 12 TO tDH [11:0] Tx DIGITAL TXSYNC Tx/Rx FILTER Data[11:0] 12 FRRx OAMDC Tx[5:0] Tx0LSB Tx1MSB Tx1LSB Tx2MSB TTxx22LLSSBB Tx3MSB 04560-0-053 Figure 53. Tx[5:0] Port Full-Duplex Timing Diagram RXEN BUS_CTR TXEN The TXSYNC signal is used to indicate to which word a nibble TXCLK belongs. While TXSYNC is low, the first nibble of every word is RXCLK read as the most significant nibble. The second nibble of that CLKIN CLKOUT1 same word is read on the following TXSYNC high level as the OSCIN least significant nibble. If TXSYNC is low for more than one FCORRROY MMSATSATLER CLK 04560-0-052 cTlXocSkY cNyCcl eis, tbhreo ulagsht tt rhaingshm foitr d tahtea sies croenadd cnoibnbtilne uoof uas nlye wun ttrial ns- Figure 52. Example of a Half-Duplex Digital Interface mit word. This feature can be used to flush the interpolator with AD9866 Serving as the Master filters with zeros. Note that the GAIN signal must be kept low FULL-DUPLEX MODE during a Tx operation. The Rx[5:0] port operates in the following manner with the SPI The full-duplex mode interface is selected when the MODE pin register default settings. Two consecutive nibbles of the Rx data is tied high. It can be used for full- or half-duplex applications. are multiplexed together to form a 12-bit data-word in twos The digital interface port is divided into two 6-bit ports called complement format. The Rx data is valid on the rising edge of Tx[5:0] and Rx[5:0], allowing simultaneous Tx and Rx opera- RXCLK, as illustrated in the timing diagram shown in Figure 54. tions for full-duplex applications. In half-duplex applications, The RXSYNC signal is used to indicate to which word a nibble the Tx[5:0] port can also be used to provide a fast update of the belongs. While RXSYNC is low, the first nibble of every word is RxPGA (AD9876 backward compatible) during an Rx opera- transmitted as the most significant nibble. The second nibble of tion. This feature is enabled by default and can be used to that same word is transmitted on the following RXSYNC high reduce the required pin count of the ASIC (refer to RxPGA level as the least significant nibble. Control section for details). In either application, Tx and Rx data are transferred between the ASIC and AD9866 in 6-bit nibbles at twice the internal input/output word rates of the Tx interpolation filter and ADC. Note that the TxDAC update rate must not be less than the nibble rate. Therefore, the 2× or 4× interpolation filter must be used with a full-duplex interface. Rev. C | Page 24 of 47

Data Sheet AD9866 tDH Figure 55 shows a possible digital interface between an ASIC RXCLK and the AD9866. The AD9866 serves as the master generating the required clocks for the ASIC. This interface requires that the RXSYNC tDV ASIC reserve 16 pins for the interface, assuming a 6-bit nibble Rx[5:0] Rx0LSB Rx1MSB Rx1LSB Rx2MSB Rx2LSB Rx3MSB 04560-0-054 wthiadtt thh ea nAdS ItChe p uins ea lolof ctahteio Tnx c pano rbte f orerd RuxcePdG bAy g3a, iifn a c 5o-nbtirt onli.b Nbloet e Figure 54. Full-Duplex Rx Port Timing width is used and the gain (or gain strobe) of the RxPGA is controlled via the SPI port. To add flexibility to the full-duplex digital interface port, several DIGITAL ASIC AD9865/AD9866 programming options are available in the SPI registers. These 6 options are listed in Table 15. The timing for the Tx[5:0] and/or OPTIONAL GAIN TROxPGA Rx[5:0] ports can be independently changed by selecting either the rising or falling clock edge as the sampling/validating edge of Tx[5:0] UX 10/12 TO Tx Data[5:0] M Tx DIGITAL the clock. Inverting RXCLK (via Bit 1 or Register 0x05) affects DE FILTER both the Rx and Tx interface, because they both use RXCLK. Rx[5:0] Table 15. SPI Registers for Full-Duplex Interface RxData[5:0] UX 10/12 FROM Address (Hex) Bit Description M RxADC 0x05 (2) OSCIN to RXCLK (1) Invert RXCLK RX_SYNC RXSYNC TX_SYNC TXSYNC (0) Disable RXCLK 0x0B (2) Rx gain on Tx port CLKIN RXCLK 0x0C (4) Invert TXSYNC CLKOUT1 CLKOUT2 (3) NA (2) LS nibble first OSCIN 0x0D (((105))) TRTwXx CopLso Kcr ton tmehgrpealeeti-mvsetea entdet g e FCORRROY MMSATSATLER CLK 04560-0-055 Figure 55. Example of a Full-Duplex Digital Interface (4) Invert RXSYNC with Optional RxPGA Gain Control via Tx[5:0] (3) NA (2) LS nibble first (1) RXCLK negative edge (0) Twos complement 0x0E (7) Low drive strength The default Tx and Rx data input formats are twos complement, but can be changed to straight binary. The default TXSYNC and RXSYNC settings can be changed such that the first nibble of the word appears while TXSYNC, RXSYNC, or both are high. Also, the least significant nibble can be selected as the first nibble of the word (LS nibble first). The output driver strength can also be reduced for lower data rate applications. Rev. C | Page 25 of 47

AD9866 Data Sheet RxPGA CONTROL interface should be considered when upgrading existing designs from the AD9876 MxFE product or half-duplex applications The AD9866 contains a digital PGA in the Rx path that is used trying to minimize an ASIC’s pin count. to extend the dynamic range. The RxPGA can be programmed over a −12 dB to +48 dB with 1 dB resolution using a 6-bit word, tSU and with a 0 dB setting corresponding to a 2 V p-p input signal. RXCLK The 6-bit word is fed into a LUT that is used to distribute the t desired gain over three amplification stages within the Rx path. TxSYNC HD Upon power-up, the RxPGA gain register is set to its minimum gain of −12 dB. The RxPGA gain mapping is shown in Figure 56. Tx[5:0] GAIN Table 164 8lists the SPI registers pertaining to the RxPGA. GAIN 04560-0-057 42 Figure 57. Updating RxPGA via Tx[5:0] in Full-Duplex Mode 36 Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an 30 option for both the half-duplex3 and full-duplex interfaces. The 24 PGA port consists of an input buffer that passes the 6-bit data AIN (dB) 18 arepgpiestaerrin wgi taht intso ignaptuint gd siriegcntalyl rteoq tuhiere Rdx. PBGit A5 o(or rB Titx 6P GofA ) gain G 12 Register 0x0B is used to select whether the data updates the 6 RxPGA or TxPGA gain register. In applications that switch 0 between RxPGA and TxPGA gain control via PGA[5:0], be –1–26 04560-0-056 cwairtehf uthl eth wart otnheg RdaxtPaG dAur (ionrg Ta xtPraGnAsi)t iiosn n. oInt itnhaed cvaesrete onft layn l oaded 0 6 12 18 24 30 36 42 48 54 60 66 RxPGA to TxPGA transition, first deselect the RxPGA gain 6-BIT DIGITAL WORD-DECIMAL EQUIVALENT Figure 56. Digital Gain Mapping of RxPGA register, update the PGA[5:0] port with the desired TxPGA gain setting, and then select the TxPGA gain register. Table 16. SPI Registers RxPGA Control The RxPGA also offers an alternative 3-bit word gain mapping Address option4 that provides a −12 dB to +36 dB span in 8 dB increments (Hex) Bit Description as shown in Table 17. The 3-bit word is directed to PGA[5:3] with 0x09 (6) Enable RxPGA update via SPI PGA[5] being the MSB. This feature is backward-compatible with (5:0) RxPGA gain code the AD9975 MxFE, and allows direct interfacing to the CX11647 or 0x0B (6) Select TxPGA via PGA[5:0] INT5130 HomePlug 1.0 PHYs. (5) Select RxPGA via PGA[5:0] (3) Enable software GAIN strobe – full-duplex Table 17. PGA Timing for AD9975 Backward-Compatible (2) Enable RxPGA update via Tx[5:0] – full-duplex Mode (1) 3-bit RxPGA gain mapping – half-duplex Digital Gain Setting The RxPGA gain register can be updated via the Tx[5:0] port, PGA[5:3] Decimal Gain (dB) the PGA[5:0] port, or the SPI port. The first two methods allow 000 0 −12 fast updates of the RxPGA gain register and should be consid- 001 1 −12 ered for digital AGC functions requiring a fast closed-loop 010 2 −4 response. The SPI port allows direct update and readback of the 011 3 4 RxPGA gain register via Register 0x09 with an update rate 100 4 12 limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6 of 101 5 20 Register 0x09 must be set for a read or write operation. 110 6 28 111 7 36 Updating the RxPGA via the Tx[5:0] port is an option only in full-duplex mode.1 In this case, a high level on the GAIN pin2 with TXSYNC low, programs the PGA setting on either the rising edge or falling edge of RXCLK, as shown in Figure 57. 1 Default setting for full-duplex mode (MODE = 1). 2 The GAIN strobe can also be set in software via Register 0x0B, Bit 3 for The GAIN pin must be held high, TXSYNC must be held low, continuous updating. This eliminates the requirement for external GAIN and GAIN data must be stable for one or more clock cycles to signal, reducing the ASIC pin count by 1. update the RxPGA gain setting. A low level on the GAIN pin 3 Default setting for half-duplex mode (MODE = 0). 4 Default setting for MODE = 0 and CONFIG =1. enables data to be fed to the digital interpolation filter. This Rev. C | Page 26 of 47

Data Sheet AD9866 TXPGA CONTROL The TxPGA register can be updated via the PGA[5:0] port or SPI port. The first method should be considered for fast updates The AD9866 also contains a digital PGA in the Tx path of the TxPGA register. Its operation is similar to the description distributed between the TxDAC and IAMP. The TxPGA is used in the RxPGA Control section. The SPI port allows direct update to control the peak current from the TxDAC and IAMP over a and readback of the TxPGA register via Register 0x0A with an 7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. A update rate limited to 1.6 MSPS (SCLK = 32 MHz). Bit 6 of 6-bit word is used to set the TxPGA attenuation according to Register 0x0A must be set for a read or write operation. Table 18 the mapping shown in Figure 58. The TxDAC gain mapping is lists the SPI registers pertaining to the TxPGA. The TxPGA applicable only when Bit 0 of Register 0x0E is set, and only the control register default setting is for minimum attenuation four LSBs of the 6-bit gain word are relevant. (0 dBFS) with the PGA[5:0] port disabled for Tx gain control. 0 –1 –2 Table 18. SPI Registers TxPGA Control –3 Address (Hex) Bit Description –4 S) –5 0x0A (6) Enable TxPGA update via SPI F –6 B d –7 (5:0) TxPGA gain code N ( –8 O –9 TxDACs IOUTP OUTPUT 0x0B (6) Select TxPGA via PGA[5:0] ATI–10 HAS 7.5dB RANGE NU–11 (5) Select RxPGA via PGA[5:0] E–12 TT–13 0x0E (0) TxDAC output (IAMP disabled) A x –14 T–15 –16 IAMPs IOUTN AND IOUTG ––––21110879 OUTPUTS HAS 19.5dB RANGE 04560-0-058 0 8 16 24 32 40 48 56 64 6-BIT DIGITAL CODE (Decimal Equivalent) Figure 58. Digital Gain Mapping of TxPGA Rev. C | Page 27 of 47

AD9866 Data Sheet TRANSMIT PATH The AD9866 (or AD9865) transmit path consists of a selectable The pipeline delays of the 2× and 4× filter responses are 21.5 digital 2×/4× interpolation filter, a 12-bit (or 10-bit) TxDAC, and 24 clock cycles, respectively, relative to f . The filter delay DATA and a current-output amplifier (IAMP), as shown in Figure 59. is also taken into consideration for applications configured for a Note that the additional two bits of resolution offered by the half-duplex interface with the half-duplex power-down mode AD9866 (vs. the AD9865) result in a 10 dB to 12 dB reduction enabled. This feature allows the user to set a programmable in the pass-band noise floor. The digital interpolation filter delay that powers down the TxDAC and IAMP only after the relaxes the Tx analog filtering requirements by simultaneously last Tx input sample has propagated through the digital filter. reducing the images from the DAC reconstruction process See the Power Control and Dissipation section for more details. while increasing the analog filter’s transition band. The digital 10 2.5 interpolation filter can also be bypassed, resulting in lower WIDE BAND 0 2.0 digital current consumption. AADDIIOORT[[x1x1[1[155:::6:600]]]/]/ 10/12 2A-4DX9865/AD9T0x8 DT6AO6C –7.5IOUT_P+dBIOUT_P– 0 TIOA M–1P2dB IIIIOOOOUUUUTTTT____NGNG–+–+ WIDE BAND RESPONSE (dB)–––––––76543210000000 PASS BAND –1.0dB @ 0.441fDATA 11–––00...110505...505 PASS-BAND RESPONSE (dB) TXENT/SXYCNLCK 04560-0-059 ––9800 ––22..50 04560-0-060 Figure 59. Functional Block Diagram of Tx Path 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 NORMALIZED FREQUENCY (Relative tofDATA) DIGITAL INTERPOLATION FILTERS Figure 60. Frequency Response of 2× Interpolation Filter The input data from the Tx port can be fed into a selectable (Normalized to fDATA) 2×/4× interpolation filter or directly into the TxDAC (for a half- 10 2.5 duplex only). The interpolation factor for the digital filter is set WIDE BAND 0 2.0 via SPI Register 0x0C with the settings shown in Table 19. The 8fmcw2Toa0×aoran berMxi d,nbli ema Ster epPn1aurpt9Sepmelf;.io s ictIt lhi banafntetertipi oetoomwurmnnpteas . owe x 4wnli×oam i r5ttidhuin0o mt riMnenar tpDFpSeuaP,oA tcflS CDatw Aota iTounroAr pd,nSd di ,en 8 rawt0tat ove thMe i itraslhaeS Saet Peat Pi S poniI spr ct Re l2abirenc0epag0 lbotoi iMselwoatnnet Sei5rsoPf0 i0nwSt Mx . if f0tTrihSloCthP mei enrSr peisu- t WIDE BAND RESPONSE (dB)–––––––76543210000000 PA–S1S.0 BdABN @D 0.45fDATA –––0011...110505...505 PASS-BAND RESPONSE (dB) B00it s [7:6] I4n terpolation Factor ––9800 ––22..50 04560-0-061 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 01 2 NORMALIZED FREQUENCY (Relative tofDATA) 10 1 (half-duplex only) 11 Do not use Figure 61. Frequency Response of 4× Interpolation Filter (Normalized to fDATA) The interpolation filter consists of two cascaded half-band filter stages with each stage providing 2× interpolation. The first stage filter consists of 43 taps. The second stage filter, operating at the higher data rate, consists of 11 taps. The normalized wide band and pass-band filter responses (relative f ) for the 2× DATA and 4× low-pass interpolation filters are shown in Figure 60 and Figure 61, respectively. These responses also include the inherent sinc(x) from the TxDAC reconstruction process and can be used to estimate any post analog filtering requirements. Rev. C | Page 28 of 47

Data Sheet AD9866 TxDAC AND IAMP ARCHITECTURE The value of I is determined by the R value at the REFADJ SET pin along with the Tx path’s digital attenuation setting. With The Tx path contains a TxDAC with a current amplifier, IAMP. 0 dB attenuation, the value of I is The TxDAC reconstructs the output of the interpolation filter and sources a differential current output that can be directed to I = 16 × (1.23/RSET) (1) an external load or fed into the IAMP for further amplification. For example, an R value of 1.96 kΩ results in I equal to SET The TxDAC’s and IAMPS’s peak current outputs are digitally 10.0 mA with IOUTFS equal to 20.0 mA. Note that the REFIO programmable over a 0 to −7.5 dB and 0 to −19.5 dB range, pin provides a nominal band gap reference voltage of 1.23 V and respectively, in 0.5 dB increments. Note that this assumes should be decoupled to analog ground via a 0.1 µF capacitor. default register settings for Register 0x10 and Register 0x11. The differential current output of the TxDAC is always con- Applications demanding the highest spectral performance nected to the IOUTP pins, but can be directed to the IAMP by and/or lowest power consumption can use the TxDAC output clearing Bit 0 of Register 0x0E. As a result, the IOUTP pins directly. The TxDAC is capable of delivering a peak signal must remain completely open, if the IAMP is to be used. The power-up to 10 dBm while maintaining respectable linearity IAMP contains two sets of current mirrors that are used to performance, as shown in Figure 27 through Figure 38. For replicate the TxDAC’s current output with a selectable gain. The power-sensitive applications requiring the highest Tx power first set of current mirrors is designated as the primary path, efficiency, the TxDAC’s full-scale current output can be reduced providing a gain factor of N that is programmable from 0 to 4 in to as low as 2 mA, and its load resistors sized to provide a steps of 1 via Bits 2:0 of Register 0x10 with a default setting of suitable voltage swing that can be amplified by a low-power op N = 4. Bit 7 of this register must be set to overwrite the default amp-based driver. settings of this register. This differential path exhibits the best Most applications requiring higher peak signal powers (up to linearity performance (see Figure 42) and is available at the 23 dBm) should consider using the IAMP. The IAMP can be IOUTN+ and IOUTN− pins. The maximum peak current per configured as a current source for loads having a well defined output is 100 mA and occurs when the TxDAC’s standing impedance (50 Ω or 75 Ω systems), or a voltage source (with the current, I, is set for 12.5 mA (IOUTFS = 25 mA). addition of a pair of npn transistors) for poorly defined loads The second set of current mirrors is designated as the secon- having varying impedance (such as power lines). dary path providing a gain factor of G that is programmable Figure 62 shows the equivalent schematic of the TxDAC and from 0 to 36 via Bits 6:4 of Register 0x10, and Bits 6:0 of Register 0x11 IAMP. The TxDAC provides a differential current output with a default setting of G = 12. This differential path is intended appearing at IOUTP+ and IOUTP−. It can be modeled as a to be used in the voltage mode configuration to bias the external differential current source generating a signal-dependent ac npn transistors, because it exhibits degraded linearity perform- current, when ∆I has a peak current of I along with two dc ance (see Figure 43) relative to the primary path. It is capable of S current sources, sourcing a standing current equal to I. The full- sinking up to 180 mA of peak current into either its IOUTG+ or scale output current, IOUTFS, is equal to the sum of these IOUTG− pins. The secondary path actually consists of three standing current sources (IOUTFS = 2 × I). gain stages (G1, G2, and G3), which are individually programmable ×∆ (I+I) ×∆ (I–I) ×∆ (I+I) ×∆ (I–I) apsr osvhiodwe na ifnix Tedab glaei 2n0 o. fW Gh, itlhe em lianneya rpiteyr mpeurtfaotriomnasn mcea yo fe ax ist to N N G G secondary path remains relatively independent of the various TxDAC N+ N– G+ G– individual gain settings that are possible to achieve a particular I I UT UT UT UT overall gain factor. REFADJ ±∆IS IO IO IO IO Both sets of mirrors sink current, because they originate from REFIO RSET 0.1µF NMOS devices. Therefore, each output pin requires a dc current I +∆I IOUTP+ IOFF1 IOFF1 IOFF2 IOFF2 path to a positive supply. Although the voltage output of each output pin can swing between 0.5 V and 7 V, optimum ac per- I–∆I IOUTP– formance is typically achieved by limiting the ac voltage swing xN xN xG xG with a dc bias voltage set between 4 V to 5 V. Lastly, both the IAMP 04560-0-062 satmanpdliifniegd c buyr rtehnet ,g Ia,i nan fdac tthoer a(cN c aunrdre Gnt), w∆iItSh, f trhoem t othtael TstxaDndAiCng a re current drawn from the positive supply being equal to Figure 62. Equivalent Schematic of TxDAC and IAMP 2 × (N + G) × I Programmable current sources I and I via Register 0x12 OFF1 OFF2 can be used to improve the primary and secondary path mirrors’ linearity performance under certain conditions by increasing their signal-to-standing current ratio. This feature provides a Rev. C | Page 29 of 47

AD9866 Data Sheet marginal improvement in distortion performance under large 1:1 signal conditions when the peak ac current of the reconstructed RS RL waveform frequently approaches the dc standing current within the 0.1µF RSET TxDAC (0 to −1 dBFS sine wave) causing the internal mirrors tdinoim ctruiernaniss eohsfef.s . M Hasoo tswht eea vcperpre,l sittch faeat ciimotonprs r( ocpaveneam kd-eitsnoat-b rimlne dst hirsaettosierot )ci oounfr rtpheener tfa oscro smuigrancneaclse REFIO REFADJ IOUT_P+ IOUT_P– IIOOUUTTNG++ (set to 0 mA via Register 0x12) to reduce the IAMP’s current TxDAC IAMP consumption. 0 TO–7.5dB 0 TO–12dB IOUTN– Table 20. SPI Registers for TxDAC and IAMP A0xd0dEr ess (Hex) B(0i)t DTxeDsAcrCi potuiotpnu t IOUTG– 04560-0-063 0x10 (7) Enable current mirror gain settings Figure 63. TxDAC Output Directly via Center-Tap Transformer (6:4) Secondary path first stage gain of 0 The TxDAC is capable of delivering up to 10 dBm peak power to 4 with ∆ = 1 to a load, R. To increase the peak power for a fixed standing L (3) Not used current, one must increase V p-p across IOUTP+ and IOUTP− (2:0) Primary path NMOS gain of 0 to 4 by increasing one or more of the following parameters: R, R (if S L with ∆ = 1 possible), and/or the turns ratio, N, of transformer. For exam- 0x11 (7) Don’t care ple, the removal of R and the use of a 2:1 impedance ratio S (6:4) Secondary path second stage gain of transformer in the previous example results in 10 dBm of peak 0 to 1.5 with ∆ = 0.25 power capabilities to the load. Note that increasing the power (3) Not used output capabilities of the TxDAC reduces the distortion (2:0) Secondary path third stage gain of 0 performance due to the higher voltage swings seen at IOUTP+ to 5 with ∆ = 1 and IOUTP−. See Figure 27 through Figure 38 for performance 0x12 (6:4) IOFF2, secondary path standing plots on the TxDAC’s ac performance. Optimum distortion current performance can typically be achieved by: (2:0) IOFF1, primary path standing current • Limiting the peak positive VIOUTP+ and VIOUTP− to 0.8 V to avoid onset of TxDAC’s output compression. (TxDAC’s Tx PROGRAMMABLE GAIN CONTROL voltage compliance is around 1.2 V.) TxPGA functionality is also available to set the peak output • Limiting V p-p seen at IOUTP+ and IOUTP− to less current from the TxDAC or IAMP. The TxDAC and IAMP are than 1.6 V. digitally programmable via the PGA[5:0] port or SPI over a Applications demanding higher output voltage swings and 0 dB to −7.5 dB and 0 dB to −19.5 dB range, respectively, in power drive capabilities can benefit from using the IAMP. 0.5 dB increments. IAMP CURRENT-MODE OPERATION The TxPGA can be considered as two cascaded attenuators with The IAMP can be configured for the current-mode operation as the TxDAC providing 7.5 dB range in 0.5 dB increments, and shown in Figure 64 for loads remaining relatively constant. In the IAMP providing 12 dB range in 6 dB increments. As a result, this mode, the primary path mirrors should be used to deliver the IAMP’s composite 19.5 dB span is valid only if Register 0x10 the signal-dependent current to the load via a center-tapped remains at its default setting of 0x44. Modifying this register transformer, because it provides the best linearity performance. setting corrupts the LUT and results in an invalid gain mapping. Because the mirrors exhibit a high output impedance, they can TxDAC OUTPUT OPERATION be easily back-terminated (if required). The differential current output of the TxDAC is available at the For peak signal currents (IOUT up to 50 mA), only the primary PK IOUTP+ and IOUTP− pins and the IAMP should be disabled path mirror gain should be used for optimum distortion by setting Bit 0 of Register 0x0E. Any load connected to these performance and power efficiency. The primary path’s gain pins must be ground referenced to provide a dc path for the should be set to 4, with the secondary path’s gain stages set to 0 current sources. Figure 63 shows the outputs of the TxDAC (Register 0x10 = 0x84). The TxDAC’s standing current, I, can be driving a doubly terminated 1:1 transformer with its center-tap set between 2.5 mA and 12.5 mA with the IOUTP outputs left tied to ground. The peak-to-peak voltage, V p-p, across RL (and open. The IOUTN outputs should be connected to the transformer, IOUT+ to IOUT−) is equal to 2 × I × (RL//RS). With I = 10 mA with the IOUTG (and IOUTP) and R = R = 50 Ω, V p-p is equal to 0.5 V with 1 dBm of peak L S power being delivered to R and 1 dBm being dissipated in R. L S Rev. C | Page 30 of 47

Data Sheet AD9866 outputs left open for optimum linearity performance. The IAMP VOLTAGE-MODE OPERATION transformer1 should be specified to handle the dc standing The voltage-mode configuration is shown in Figure 65. This current, I , drawn by the IAMP. Also, because I remains BIAS BIAS configuration is suited for applications having a poorly defined signal independent, a series resistor (not shown) can be inserted load that can vary over a considerable range. A low impedance between AVDD and the transformer’s center-tap to reduce the voltage driver can be realized with the addition of two external IAMP’s common-mode voltage, V , and reduce the power CM RF bipolar npn transistors (Phillips PBR951) and resistors. In dissipation on the IC. The V bias should not exceed 5.0 V and CM this configuration, the current mirrors in the primary path the power dissipated in the IAMP alone is as follows: (IOUTN outputs) feed into scaling resistors, R, generating a PIAMP = 2 × (N + G) × I × VCM (2) differential voltage into the bases of the npn transistors. These transistors are configured as source followers with the secon- 0.1µF RSET AVDD dary path current mirrors appearing at IOUTG+ and IOUTG− providing a signal-dependent bias current. Note that the REFIO REFADJ OUT_P+ OUT_P– IIOOUUTTNG++ 0.1µF IBIAS = 2× (N+G)× 1 IOUTP outputs must remain open for proper operation. I I T:1 0.1µF RSET AVDD TxD0A CTO–7.5dB 0 TO–1IA2MdBP IOUTN– IOUTPK RL REFIO REFADJ IOUT_P+ IOUT_P– IIOOUUTTNG++ R R DPHUIALRLLS INP0PS.1N PµBFR951 IOUTG– PIO_UOTUPTKP =K (=N (+IOGU)×T P1K)2× T2× RL 04560-0-064 TxD0A CTO–7.5dB 0 TO–I1A2MdBP IOUTN– IOUTPK AVDD TO LOAD A step-down tranFsifgourrme 6e4r.1 C wurirtehn ta- Mtuordne Orapteiroa,t iTo,n c an be used to IOUTG– RS0.1µF 04560-0-065 increase the output power, P_OUT, delivered to the load. This Figure 65. Voltage-Mode Operation causes the output load, RL, to be reflected back to the IAMP’s The peak differential voltage signal developed across the npn’s differential output by T2, resulting in a larger differential voltage bases is as follows: swing seen at the IAMP’s output. For example, the IAMP can VOUT = R × (N × I) (4) deliver 24 dBm of peak power to a 50 Ω load, if a 1.41:1 step- PK down transformer is used. This results in 5 V p-p voltage swings where: appearing at IOUTN+ and IOUTN− pins. Figure 42 shows how N is the gain setting of the primary mirror. the third order intercept point, OIP3, of the IAMP varies as a I is the standing current of the TxDAC defined in Equation 1. function of common-mode voltage over a 2.5 MHz to 20.0 MHz span with a 2-tone signal having a peak power of approximately The common-mode bias voltage seen at IOUTN+ and IOUTN− 24 dBm with IOUTPK = 50 mA. is approximately AVDD − VOUTPK, while the common-mode voltage seen at IOUTG+ and IOUTG− is approximately the For applications requiring an IOUT exceeding 50 mA, set the PK npn’s V drop below this level (AVDD − VOUT − 0.65). In secondary’s path to deliver the additional current to the load. BE PK the voltage-mode configuration, the total power dissipated IOUTG+ and IOUTN+ should be shorted as well as IOUTG− within the IAMP is as follows: and IOUTN−. If IOUT represents the peak current to be PK delivered to the load, then the current gain in the secondary PIAMP = 2 × I {(AVDD − VOUTPK) × N path, G, can be set by the following equation: + (AVDD − VOUTPK − 0.65) × G} (5) G = IOUT /12.5 – 4 (3) The emitters of the npn transistors are ac-coupled to the trans- PK former1 via a 0.1 µF blocking capacitor and series resistor of 1 Ω The linearity performance becomes limited by the secondary to 2 Ω. Note that protection diodes are not shown for clarity mirror path’s distortion. purposes, but should be considered if interfacing to a power or phone line. 1 The B6080 and BX6090 transformers from Pulse Engineering are worthy of consideration for current and voltage modes. Rev. C | Page 31 of 47

AD9866 Data Sheet The amount of standing and signal-dependent current used to 100 bias the npn transistors depends on the peak current, IOUT , PK 90 required by the load. If the load is variable, determine the worst 80 case, IOUT , and add 3 mA of margin to ensure that the npn PK transistors remain in the active region during peak load 70 A) currents. The gain of the secondary path, G, and the TxDAC’s m 60 standing current, I, can be set using the following equation: (LY IAMPN OUTPUT PP 50 U IOUTPK + 3 mA = G × I (6) IS 40 The voltage output driver exhibits a high output impedance if TxDACs AVDD 30 the bias currents for the npn transistors are removed. This feexaatmurpel eis, padovwaenrt laigneeos)u sin i nw hhaiclfh-d tuhpe lTexx aopuptpliucat tdiornivse (rf moru st go 1200 04560-0-066 1 2 3 4 5 6 7 8 9 10 11 12 13 into a high impedance state while in Rx mode. If the AD9866 is I (mA) configured for the half-duplex mode (MODE = 0), the IAMP, Figure 66. Current Consumption of TxDAC and IAMP in Current-Mode TxDAC, and interpolation filter are automatically powered Operation with IOUTN Only (Default IAMP Settings) down after a Tx burst (via TXEN), thus placing the Tx driver 150 into a high impedance state while reducing its power 140 consumption. 130 IOUTG OUTPUT 120 IAMP CURRENT CONSUMPTION 110 CONSIDERATIONS 100 A) m 90 The Tx path’s analog current consumption is an important (LY 80 consideration when determining its contribution to the overall UPP 70 S on-chip power dissipation. This is especially the case in full- I 60 duplex applications, where the power dissipation can exceed the 50 TxDAC AVDD maximum limit of 1.66 W, if the IAMP’s IOUT is set to high. 40 PK Tsuhpep alyn a(Ploign c4u3r)r aelnotn cgo wnsiuthm tphtei osnta nindcilnugd ecsu rthreen Tt xfrDoAmC t’hs ea nalog 123000 IOUTN OUTPUT 04560-0-067 IAMP’s outputs. Equation 2 and Equation 5 can be used to 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 I (mA) calculate the power dissipated in the IAMP for the current and Figure 67. Current Consumption of TxDAC and IAMP in Current-Mode voltage-mode configuration. Figure 66 shows the current Operation with IOUTN Only (Default IAMP Settings) consumption for the TxDAC and IAMP as a function of the TxDAC’s standing current, I,when only the IOUTN outputs are used. Figure 67 shows the current consumption for the TxDAC and IAMP as a function of the TxDAC’s standing current, I, when the IOUTN and IOUTG outputs are used. Both figures are with the default current mirror gain settings of N = 4 and G = 12. Rev. C | Page 32 of 47

Data Sheet AD9866 RECEIVE PATH The receive path block diagram for the AD9866 (or AD9865) is To limit the RxPGA’s self-induced input offset, an offset shown in Figure 68. The receive signal path consists of a 3-stage cancellation loop is included. This cancellation loop is RxPGA, a 3-pole programmable LPF, and a 12-bit (or 10-bit) automatically performed upon power-up and can also be ADC. Note that the additional 2 bits of resolution offered by the initiated via SPI. During calibration, the RxPGA’s first stage is AD9866 (vs. the AD9865) result in a 3 dB to 5 dB lower noise internally shorted, and each gain stage set to a high gain setting. floor depending on the RxPGA gain setting and LPF cutoff A digital servo loop slaves a calibration DAC, which forces the frequency. Also working in conjunction with the receive path is Rx input offset to be within ±32 LSB for this particular high an offset correction circuit. These blocks are discussed in detail gain setting. Although the offset varies for other gain settings, in the following sections. Note that the power consumption of the offset is typically limited to ±5% of the ADC’s 2 V input the RxPGA can be modified via Register 0x13 as discussed in span. Note that the offset cancellation circuitry is intended to the Power Control and Dissipation section. reduce the voltage offset attributed to only the RxPGA’s input stage, not any dc offsets attributed to an external source. ADIO[11:6]/ The gain of the RxPGA should be set to minimize clipping of Tx[5:0] CLK CLKOUT_1 SYN. CLKOUT_2 the ADC while utilizing most of its dynamic range. The maxi- ADIOR[x1[15::60]]/ MU2LMT CIPLLKIER OXTSACLIN mum peak-to-peak differential voltage that does not result in clipping of the ADC is shown in Figure 69. While the graph 10/12 RXENR/SXYCNLCK 80AMDSCPS SPGA 2-PLPOFLE 1-PLPOFLE RRXX+– suggests that maximum input signal for a gain setting of −12 dB is 8.0 V p-p, the maximum input voltage into the PGA should 0 TO 6dB –6 TO 18dB –6 TO 24dB ∆ = 1dB ∆ = 6dB ∆ = 6dB be limited to less than 6 V p-p to prevent turning on ESD 6 GAIN protection diodes. For applications having higher maximum PGA[5:0] MAPPING LUT input signals, consider adding an external resistive attenuator SPORT 4 RCEOGNITSRTOELR AD9865/AD9866 04560-0-068 network. While the input sensitivity of the Rx path is degraded by the amount of attenuation on a dB-to-dB basis, the low noise Figure 68. Functional Block Diagram of Rx Path characteristics of the RxPGA provide some design margin such RX PROGRAMMABLE GAIN AMPLIFIER that the external line noise remains the dominant source. The RxPGA has a digitally programmable gain range from 8.0000 V) −12 dB to +48 dB with 1 dB resolution via a 6-bit word. Its N (4.0000 A purpose is to extend the dynamic range of the Rx path such that P the input of the ADC is presented with a signal that scales UT S2.0000 P within its fixed 2 V input span. There are multiple ways of K IN1.0000 setting the RxPGA’s gain as discussed in the RxPGA Control EA0.5000 P section, as well as an alternative 3-bit gain mapping having a TO-0.2500 range of −12 dB to +36 dB with 8 dB resolution. EAK-0.1250 P The RxPGA is comprised of two sections: a continuous time E L0.0625 A PGA (CPGA) for course gain and a switched capacitor PGA C (cSaPscGaAde)d f ogra ifnin set aggaeins prerosovliudtiinogn a. Tghaien C rPanGgAe fcroonmsi s−t1s 2o fd tBw too FULL-S000...000311150260 04560-0-069 +42 dB with 6 dB resolution. The first stage features a low noise –12 –6 0 6 12 18 24 30 36 42 48 preamplifier (< 3.0 nV/√Hz), thereby eliminating the need for GAIN (dB) Figure 69. Maximum Peak-to-Peak Input vs. RxPGA Gain Setting an external preamplifier. The SPGA provides a gain range from that Does Not Result in ADC Clipping 0 dB to 6 dB with 1 dB resolution. A look-up table (LUT) is LOW-PASS FILTER used to select the appropriate gain setting for each stage. The nominal differential input impedance of the RxPGA input The low-pass filter (LPF) provides a third order response with a appearing at the device RX+ and RX− input pins is 400 Ω//4 pF cutoff frequency that is typically programmable over a 15 MHz (±20%) and remains relatively independent of gain setting. The to 35 MHz span. Figure 68 shows that the first real pole is im- PGA input is self-biased at a 1.3 V common-mode level allowing plemented within the first CPGA gain stage, and the complex maximum input voltage swings of ±1.5 V at RX+ and RX−. AC pole pair is implemented in the second CPGA gain stage. Capacitor coupling the input signal to this stage via coupling capacitors arrays are used to vary the different R-C time constants within (0.1 µF) is recommended to ensure that any external dc offset these two stages in a manner that changes the cutoff frequency does not get amplified with high RxPGA gain settings, while preserving the normalized frequency response. Because potentially exceeding the ADC input range. absolute resistor and capacitor values are process-dependent, a Rev. C | Page 33 of 47

AD9866 Data Sheet calibration routine lasting less than 100 μs automatically occurs The −3 dB cutoff frequency, f , is programmable by writing −3 dB each time the target cutoff frequency register (Register 0x08) is an 8-bit word, referred to as the target, to Register 0x08. The updated, ensuring a repeatable cutoff frequency from device to cutoff frequency is a function of the ADC sample rate, f , and ADC device. to a lesser extent, the RxPGA gain setting (in dB). Figure 72 shows how the frequency response, f , varies as a function of Although the default setting specifies that the LPF be active, it −3 dB the RxPGA gain setting. can also be bypassed providing a nominal f of 55 MHz. −3 dB Table 21 shows the SPI registers pertaining to the LPF. 3 –6dB GAIN 0dB GAIN Table 21. SPI Registers for Rx Low-Pass Filter 0 +6dB GAIN +18dB GAIN Address (Hex) Bit Description +30dB GAIN –3 +42dB GAIN 0x07 (0) Enable Rx LPF B) d 0x08 (7:0) Target value AL ( –6 T N The normalized wideband gain response is shown in Figure 70. E The normalized pass-band gain and group delay responses are DAM –9 N shown in Figure 71. The normalized cutoff frequency, f−3 dB, FU–12 results in −3 dB attenuation. Also, the actual group delay time (frGeDquTe)n rceys puosinnsge tchaen f boell ocwalicnugla etqedu agtiivoenn: a programmed cutoff ––1158 04560-0-072 Actual GDT = Normalized GDT/(2.45 × f ) (7) 0 5 10 15 20 25 30 35 40 45 50 −3 dB INPUT FREQUENCY (MHz) 5 Figure 72. Effects of RxPGA Gain on LPF Frequency Response ( f−3 dB = 32 MHz (@ 0 dB and fADC = 80 MSPS) 0 The following formula1 can be used to estimate f for a −3 dB –5 RxPGA gain setting of 0 dB: –10 f = (128/target) × (f /80) × (f /30 + 23.83) (8) −3 dB_0 dB ADC ADC B) N (d–15 Figure 73 compares the measured and calculated f−3 dB using this AI formula. G–20 35 –25 33 ––33500 0.5 1.0 1.5 2.0 2.5 3.004560-0-070 Hz) 2391 FREQUENCY Y (M 27 Figure 70. LPF’s Normalized Wideband Gain Response NC 25 80 MSPS MEASURED E 0.25 1.30 QU 23 80 MSPS CALCULATED E 0 1.25 FR 21 NORMALIZED GAIN RESPONSE –0.25 1.20 19 –––100...075050 111...011505 UP DELAYE (GDT) 1157 5500 MMSSPPSS CMAELACSUULRAETDED 04560-0-073 GAIN (dB)–––––22111.....2075250505 00001.....8899005050 NORMALIZED GROTIME RESPONS Fi4g8ure 6743. M8e0faosru TfA9rAeD6RCdG = aE1 n5T1d0-2D MCEa1CS2lIPcM8uSA laaL1nt 4Eed4Qd 8 Uf01−IV 36M d0ABSL vPE1sSN7. 6TTar1g9e2t V2a0lu8e 224 NORMALIZED GROUP DELAY –––322...075050 000...677505 04560-0-071 1 Etom 8p0i rMicaSlPlyS dweirtihv eadn fRoxrP aG fA−3 =dB 0r adnBg. e of 15 MHz to 35 MHz and fADC of 40 MSPS 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY Figure 71. LPF’s Normalized Pass-Band Gain and Group Delay Responses Rev. C | Page 34 of 47

Data Sheet AD9866 The following scaling factor can be applied to the previous duty cycle clock even when presented with a clock source with formula to compensate for the RxPGA gain setting on f : poor symmetry (35/65). This circuit should be enabled, if the −3 dB ADC sampling clock is a buffered version of the reference signal Scale Factor = 1 − (RxPGA in dB)/382 (9) appearing at OSCIN (see the Clock Synthesizer section) and if This scaling factor reduces the calculated f as the RxPGA is −3 dB this reference signal is derived from an oscillator or crystal whose increased. Applications that need to maintain a minimum cut- specified symmetry cannot be guaranteed to be within 45/55 off frequency, f , for all RxPGA gain settings should first −3 dB_MIN (or 55/45). This circuit can remain disabled, if the ADC determine the scaling factor for the highest RxPGA gain setting sampling clock is derived from a divided down version of the to be used. Next, the f should be divided by this scale −3 dB_MIN clock synthesizer’s VCO, because this clock is near 50%. factor to normalize to the 0 dB RxPGA gain setting (f ). −3 dB_0 dB The ADC’s power consumption can be reduced by 25 mA, with Equation 8 can then be used to calculate the target value. minimal effect on its performance, by setting Bit 4 of Register 0x07. The LPF frequency response shows a slight sensitivity to Alternative power bias settings are also available via Register 0x13, temperature, as shown in Figure 74. Applications sensitive to as discussed in the Power Control and Dissipation section. temperature drift can recalibrate the LPF by rewriting the target Lastly, the ADC can be completely powered down for half- value to Register 0x08. duplex operation, further reducing the AD9866’s peak power 35 consumption. REFT 30 C3 MHz) FOUT ACTUAL 80MHz AND–40°C ATDOCs C0.11µF 0.1µF C102µF ENCY (25 FOUT ACTUAL 80MHz AND +25°C REFB C0.41µF QU FOUT ACTUAL 80MHz AND +85°C 1.0V E R F 20 15 04560-0-074 TOP 96 112 128 144 160 176 192 208 224 240 VIEW TARGET-DECIMAL EQUIVALENT Figure 74. Temperature Drift of f−3 dB for fADC = 80 MSPS and RxPGA = 0 dB C3 AThNe AALDO98G66-T feOat-uDreIsG aI 1T2A-bLit CanOalNogV-tEoR-dTigEitRal (cAonDvCer)t er (ADC) C1C4 C2 04560-0-075 capable of up to 80 MSPS. Referring to Figure 68, the ADC is Figure 75. ADC Reference and Decoupling driven by the SPGA stage, which performs both the sample- The ADC has an internal voltage reference and reference ampli- and-hold and the fine gain adjust functions. A buffer amplifier fier as shown in Figure 75. The internal band gap reference (not shown) isolates the last CPGA gain stage from the dynamic generates a stable 1 V reference level that is converted to a dif- load presented by the SPGA stage. The full-scale input span of ferential 1 V reference centered about mid-supply (AVDD/2). the ADC is 2 V p-p, and depending on the PGA gain setting, The outputs of the differential reference amplifier are available the full-scale input span into the SPGA is adjustable from 1 V to at the REFT and REFB pins and must be properly decoupled for 2 V in 1 dB increments. optimum performance. The REFT and REFB pins are conven- A pipelined multistage ADC architecture is used to achieve high iently situated at the corners of the CSP package such that C1 sample rates while consuming low power. The ADC distributes (0603 type) can be placed directly across its pins. C3 and C4 can the conversion over several smaller A/D subblocks, refining the be placed underneath C1, and C2 (10 µF tantalum) can be conversion with progressively higher accuracy as it passes the placed furthest from the package. results from stage to stage on each clock edge. The ADC typi- cally performs best when driven internally by a 50% duty cycle Table 22. SPI Registers for Rx ADC clock. This is especially the case when operating the ADC at Address (Hex) Bit Description high sample rate (55 MSPS to 80 MSPS) and/or lower internal 0x04 (5) Duty cycle restore circuit bias levels, which adversely affect interstage settling time (4) ADC clock from PLL requirements. 0x07 (4) ADC low power mode 0x13 (2:0) ADC power bias adjust The ADC sampling clock path also includes a duty cycle restorer circuit, which ensures that the ADC gets a near 50% Rev. C | Page 35 of 47

AD9866 Data Sheet AGC TIMING CONSIDERATIONS amount of delay or latency depends on whether a half- or full- duplex is selected. An impulse response at the RxPGA’s input When implementing a digital AGC timing loop, it is important can be observed after 10.0 ADC clock cycles (1/f ) in the case to consider the Rx path latency and settling time of the Rx path ADC of a half-duplex interface and 10.5 ADC clock cycles in the case in response to a change in gain setting. Figure 21 and Figure 24 of a full-duplex interface. This latency along with the RxPGA show the RxPGA’s settling response to a 60 dB and 5 dB change settling time should be considered to ensure stability of the in gain setting when using the Tx[5:0] or PGA[5:0] port. While AGC loop. the RxPGA settling time may also show a slight dependency on the LPF’s cutoff frequency, the ADC’s pipeline delay along with the ADIO bus interface presents a more significant delay. The Rev. C | Page 36 of 47

Data Sheet AD9866 CLOCK SYNTHESIZER The AD9866 generates all its internal sampling clocks, as well as where f is a factor of 2 or 4 less than the f . In this case, OSCIN ADC two user-programmable clock outputs appearing at CLKOUT1 the divider ratio, N, is chosen such that the divided down VCO and CLKOUT2, from a single reference source as shown in output is equal to the ADC sample rate, as shown in the Figure 76. The reference source can be either a fundamental following equation: frequency or an overtone quartz crystal connected between f = f /2N (12) ADC DAC OSCIN and XTAL with the parallel resonant load components where N = 0, 1, or 2. as specified by the crystal manufacturer. It can also be a TTL- level clock applied to OSCIN with XTAL left unconnected. Figure 77 shows the degradation in phase noise performance imparted onto the ADC’s sampling clock for different VCO The data rate, f , for the Tx and Rx data paths must always be DATA output frequencies. In this case, a 25 MHz, 1 V p-p sine wave equal. Therefore, the ADC’s sample rate, f , is always equal to ADC was used to drive OSCIN and the PLL’s M and N factor were f , while the TxDAC update rate is a factor of 1, 2, or 4 of DATA selected to provide an f of 50 MHz for a VCO operating f , depending on the interpolation factor selected. The data ADC DATA frequency of 50, 100, and 200 MHz. The RxPGA input was rate refers to the word rate and should not be confused with the driven with a near full-scale, 12.5 MHz input signal with a gain nibble rate in full-duplex interface. setting of 0 dB. Operating the VCO at the highest possible frequency results in the best narrow and wideband phase noise XTAL ÷2N TOADC characteristics. For comparison purposes, the clock source for XTAL OSCIN 2M CLK the ADC was taken directly from OSCIN when driven by a MULTIPLIER TOTxDAC C1 C2 50 MHz square wave. CLKOUT2 ÷2L 0 DIRECT CLKOUT1 ÷2R 04560-0-076 ––2100 VVCCOO == 5100M0MHHzz VCO = 200MHz Figure 76. Clock Oscillator and Synthesizer –30 The 2M CLK multiplier contains a PLL (with integrated loop –40 filter) and VCO capable of generating an output frequency that S–50 F B is a multiple of 1, 2, 4, or 8 of its input reference frequency, d–60 fOSCIN, appearing at OSCIN. The input frequency range of fOSCIN –70 is between 20 MHz and 80 MHz, while the VCO can operate –80 over a 40 MHz to 200 MHz span. For the best phase noise/jitter –90 cqhuaernaccyt ebreisttwicese,n it 1 i0s 0a dMvHisazb alne dto 2 o0p0e MraHtez t.h Teh VeC VOC Owi othu tap furte - ––111000 04560-0-077 drives the TxDAC directly such that its update rate, f , is 2.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 DAC related to f by the following equation: FREQUENCY (MHz) OSCIN Figure 77. Comparison of Phase Noise Performance when ADC Clock Source fDAC = 2M × fOSCIN (10) is Derived from Different VCO Output Frequencies where M = 0, 1, 2, or 3. The CLK synthesizer also has two clock outputs appearing at CLKOUT1 and CLKOUT2. They are programmable via M is the PLL’s multiplication factor set in Register 0x04. The Register 0x06. Both outputs can be inverted or disabled. The value of M is determined by the Tx path’s word rate, f , and DATA voltage levels appearing at these outputs are relative to DRVDD digital interpolation factor, F, as shown in the following and remain active during a hardware or software reset. Table 23 equation: shows the SPI registers pertaining to the clock synthesizer. M = log (F × f /f ) (11) 2 DATA OSCIN CLKOUT1 is a divided version of the VCO output and can be Note: if the reference frequency appearing at OSCIN is chosen set to be a submultiple integer of f (f /2R, where R = 0, 1, 2, DAC DAC to be equal to the AD9866’s Tx and Rx path’s word rate, then M or 3). Because this clock is actually derived from the same set of is simply equal to log(F). 2 dividers used within the PLL core, it is phase-locked to them The clock source for the ADC can be selected in Register 0x04 such that its phase relationship relative to the signal appearing as a buffered version of the reference frequency appearing at at OSCIN (or RXCLK) can be determined upon power-up. OSCIN (default setting) or a divided version of the VCO output Also, this clock has near 50% duty cycle, because it is derived (fDAC). The first option is the default setting and most desirable from the VCO. As a result, CLKOUT1 should be selected before if fOSCIN is equal to the ADC sample rate, fADC. This option CLKOUT2 as the primary source for system clock distribution. typically results in the best jitter/phase noise performance for the ADC sampling clock. The second option is suitable in cases Rev. C | Page 37 of 47

AD9866 Data Sheet CLKOUT2 is a divided version of the reference frequency, f , OSCIN Table 23. SPI Registers for CLK Synthesizer and can be set to be a submultiple integer of f (f /2L, OSCIN OSCIN Address (Hex) Bit Description where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is 0x04 (4) ADC CLK from PLL a delayed version of the signal appearing at OSCIN, exhibiting (3:2) PLL divide factor (P) the same duty cycle characteristics. With L set to 1 or 2, the (1:0) PLL multiplication factor (M ) output of CLKOUT2 is a divided version of the OSCIN signal, 0x06 (7:6) CLKOUT2 divide number exhibiting a near 50% duty cycle, but without having a determi- (5) CLKOUT2 invert nistic phase relationship relative to CLKOUT1 (or RXCLK). (4) CLKOUT2 disable (3:2) CLKOUT1 divide number (1) CLKOUT1 invert (0) CLKOUT1 disable Rev. C | Page 38 of 47

Data Sheet AD9866 POWER CONTROL AND DISSIPATION POWER-DOWN HALF-DUPLEX POWER SAVINGS The AD9866 provides the ability to control the power-on state Significant power savings can be realized in applications having of various functional blocks. The state of the PWRDWN pin, a half-duplex protocol allowing only the Rx or Tx path to be along with the contents of Register 0x01 and Register 0x02, operational at any instance. The power savings method depends allow two user-defined power settings that are pin selectable. on whether the AD9866 is configured for a full- or half-duplex The default settings1 are such that Register 0x01 has all blocks interface. Functional blocks having fast power on/off times for powered on (all Bits 0), while Register 0x02 has all blocks the Tx and Rx path are controlled by the following bits: powered, down excluding the PLL, such that the clock signal TxDAC/IAMP, TX Digital, ADC, and RxPGA. remains available at CLKOUT1 and CLKOUT2. When the In the case of a full-duplex digital interface (MODE = 1), one PWRDWN pin is low, the functional blocks corresponding to can set Register 0x01 to 0x60 and Register 0x02 to 0x05 (or vice the bits in Register 0x01 are powered down. When the versa) such that the AD9866’s Tx and Rx path are never PWRDWN is high, the functional blocks corresponding to the powered on simultaneously. The PWRDWN pin can then be bits in Register 0x02 are powered down. PWRDWN used to control what path is powered on, depending on the immediately affects the designated functional blocks with burst type. During a Tx burst, the Rx path’s PGA and ADC minimum digital delay. blocks can typically be powered down within 100 ns, while the Table 24. SPI Registers Associated with Power-Down and Tx paths DAC, IAMP, and digital filter blocks are powered up Half-Duplex Power Savings within 0.5 µs. For an Rx burst, the Tx path’s can be powered Address (Hex) Bit Description Comments down within 100 ns, while the Rx circuitry is powered up 0x01 (7) PLL PWRDWN = 0. within 2 µs. (6) TxDAC/IAMP Setting the TXQUIET pin low allows it to be used with the full- Default setting is all (5) TX Digital duplex interface to quickly power down the IAMP and disable functional blocks (4) REF the interpolation filter. This is meant to maintain backward powered on. (3) ADC CML compatibility with the AD9875/AD9876 MxFEs with the excep- (2) ADC tion that the TxDAC remains powered if its IOUTP outputs are (1) PGA BIAS used. In most applications, the interpolation filter needs to be (0) RxPGA flushed with 0s before or after being powered down. This ensures that, upon power-up, the TxDAC (and IAMP) have a 0x02 (7) PLL PWRDWN = 1. (6) TxDAC/IAMP negligible differential dc offset, thus preventing spectral splatter Default setting is all due to an impulse transient. (5) TX Digital functional blocks (4) REF Applications using a half-duplex interface (MODE = 0) can powered off, (3) ADC CML excluding PLL. benefit from an additional power savings feature made available (2) ADC in Register 0x03. This register is effective only for a half-duplex interface. Besides providing power savings for half-duplex (1) PGA BIAS applications, this feature allows the AD9866 to be used in (0) RxPGA applications that need only its Rx (or Tx) path functionality 0x03 (7:3) Tx OFF Delay Half-duplex power through pin-strapping, making a serial port interface (SPI) (2) Rx PWRDWN savings. optional. This feature also allows the PWRDWN pin to retain via TXEN its default function as a master power control, as defined in (1) Enable Tx Table 11. PWRDWN (0) Enable Rx The default settings for Register 0x03 provide fast power control PWRDWN of the functional blocks in the Tx and Rx signal paths (outlined above) using the TXEN pin. The TxDAC still remains powered 1 With MODE = 1 and CONFIG = 1, Reg. 0x02 default settings are with all on in this mode, while the IAMP is powered down. Significant blocks powered off, with RXCLK providing a buffered version of the signal current savings are typically realized when the IAMP is appearing at OSCIN. This setting results in the lowest power consumption powered down. upon power-up while still allowing AD9865 to generate the system clock via a crystal. Rev. C | Page 39 of 47

AD9866 Data Sheet For a Tx burst, the falling edge of TXEN is used to generate an 55 internal delayed signal for powering down the Tx circuitry. 50 Upon receipt of this signal, power-down of the Tx circuitry 45 occurs within 100 ns. The user-programmable delay for the Tx path power-down is meant to match the pipeline delay of the A) 40 m last Tx burst sample such that power-down of the TxDAC and (C 35 A IAMP does not impact its transmission. A 5-bit field in DTxD 30 Register 0x03 sets the delay from 0 to 31 TXCLK clock cycles, D V with the default being 31 (0.62 μs with fTxCLK = 50 MSPS). The IA 25 digital interpolation filter is automatically flushed with midscale 20 sTreaXtmuCprLnleKss l popwirni.o iFrs o tpror aepnsoe wRnxet r fb-oduror 3sw3t,n at,hd iedf itrthiisoei nncaglol eccdklog sceik go ncf ayTlc XilneEst oNa ft tihese ru TseXdE tNo 1105 04560-0-078 0 1 2 3 4 5 6 7 8 9 10 11 12 13 generate an internal signal (with no delay) that powers up the ISTANDING(mA) Tx circuitry within 0.5 μs. Figure 78. Reduction in TxDAC’s Supply Current vs. Standing Current The Rx path power-on/power-off can be controlled by either 65 TXEN or RXEN by setting Bit 2 of Register 0x03. In the default 60 setting, the falling edge of TXEN powers up the Rx circuitry 4 INTERPOLATION 55 within 2 μs, while the rising edge of TXEN powers down the Rx circuitry within 0.5 μs. If RXEN is selected as the control signal, 50 then its rising edge powers up the Rx circuitry and the falling A) 45 m edge powers it down. To disable the fast power-down of the Tx (D 40 and/or Rx circuitry, set Bit 1 and/or Bit 0 to 0. IDVD 35 2 INTERPOLATION POWER REDUCTION OPTIONS 30 1 (HALF-DUPLEX ONLY) The power consumption of the AD9866 can be significantly 25 rceodnusucemdp ftrioomn vitss. pdeerfafourltm saenttcine go fb yth oep vtaimrioizuins gfu tnhcet ipoonwael rb locks 1250 04560-0-079 in the Tx and Rx signal path. On the Tx path, minimum power 20 30 40 50 60 70 80 INPUT DATA RATE (MSPS) consumption is realized when the TxDAC output is used directly Figure 79. Digital Supply Current Consumption vs. Input Data Rate and its standing current, I, is reduced to as low as 1 mA. Although (DVDD = DRVDD = 3.3 V and fOUT = fDATA/10) a slight degradation in THD performance results at reduced Power consumption on the Rx path can be achieved by reduc- standing currents, it often remains adequate for most applica- ing the bias levels of the various amplifiers contained within the tions, because the op amp driver typically limits the overall RxPGA and ADC. As previously noted, the RxPGA consists of linearity performance of the Tx path. The load resistors used at two CPGA amplifiers and one SPGA amplifier. The bias levels the TxDAC outputs (IOUTP+ and IOUTP−) can be increased of each of these amplifiers along with the ADC can be con- to generate an adequate differential voltage that can be further trolled via Register 0x13 as shown in Table 25. The default amplified via a power efficient op amp based driver solution. setting for Register 0x13 is 0x00. Figure 78 shows how the supply current for the TxDAC (Pin 43) is reduced from 55 mA to 14 mA as the standing current is Table 25. SPI Register for RxPGA and ADC Biasing reduced from 12.5 mA to 1.25 mA. Further Tx power savings Address (Hex) Bit Description can be achieved by bypassing or reducing the interpolation 0x07 (4) ADC low power factor of the digital filter as shown in Figure 79. 0x13 (7:5) CPGA bias adjust (4:3) SPGA bias adjust (2:0) ADC power bias adjust Rev. C | Page 40 of 47

Data Sheet AD9866 Because the CPGA processes signals in the continuous time The SPGA is implemented as a switched capacitor amplifier; domain, its performance vs. bias setting remains mostly therefore, its performance vs. bias level is mostly dependent on independent of the sample rate. Table 26 shows how the typical the sample rate. Figure 81 shows how the typical current current consumption seen at AVDD (Pins 35 and 40) varies as a consumption seen at AVDD (Pin 35 and Pin 40) varies as a function of Bits (7:5), while the remaining bits are maintained at function of Bits (4:3) and sample rate, while the remaining bits their default settings of 0. Only four of the possible settings are maintained at the default setting of 0. Figure 82 shows how result in any reduction in current consumption relative to the the SNR and THD performance is affected for a 10 MHz sine default setting. Reducing the bias level typically results in a wave input as the ADC sample rate is swept from 20 MHz to degradation in the THD vs. frequency performance as shown in 80 MHz. Figure 80. This is due to a reduction of the amplifier’s unity gain 210 bandwidth, while the SNR performance remains relatively unaffected. 205 200 Table 26. Analog Supply Current vs. CPGA Bias Settings at 01 fADC = 65 MSPS 195 A) Bit 7 Bit 6 Bit 5 ∆ mA (mD190 00 D 0 0 0 0 V A I185 0 0 1 −27 10 0 1 0 −42 180 0 1 1 −51 11 11 00 01 −275 5 117705 04560-0-081 20 30 40 50 60 70 80 1 1 0 69 ADC SAMPLE RATE (MSPS) 1 1 1 27 Figure 81. AVDD Current vs. SPGA Bias Setting and Sample Rate 65 –54 65.0 –20 64 –56 SNR_RxPGA = 0dB 62.5 –25 63 –58 SNR-00 60.0 –30 62 SNR-01 –60 SNR-10 57.5 –35 c) 61 SNR-11 –62 c) B B SNR (dBFS)555025...050 SNR_RxPGA = 36dB –––544050 THD (dBc) SNR (d 556890 TTTHHHDDD---001010 –––666864 THD (d 47.5 THD_RxPGA = 0dB –55 57 THD-11 –70 444025...050 THD_RxPGA = 36dB –––766050 04560-0-080 555620 30 4S0AMPLE R5A0TE (MSP6S0) 70 80––7742 04560-0-082 000 001 010 011 100 Figure 82. SNR and THD Performance vs. fADC and SPGA Bias Setting with CPGA BIAS SETTING-BITS (7:5) RxPGA = 0 dB, fIN = 10 MHz. AIN = −1 dBFS Figure 80. THD vs. fIN Performance and RxPGA Bias Settings (000,001,010,100 with RxPGA = 0 and +36 dB and AIN = −1 dBFS, LPF set to 26 MHz and fADC = 50 MSPS) Rev. C | Page 41 of 47

AD9866 Data Sheet The ADC is based on a pipeline architecture with each stage POWER DISSIPATION consisting of a switched capacitor amplifier. Therefore, its per- The power dissipation of the AD9866 can become quite high in formance vs. bias level is mostly dependent on the sample rate. full-duplex applications in which the Tx and Rx paths are si- Figure 83 shows how the typical current consumption seen at multaneously operating with nominal power bias settings. In AVDD (Pin 35 and Pin 40) varies as a function of Bits (2:0) and fact, some applications that use the IAMP may need to either sample rate, while the remaining bits are maintained at the reduce its peak power capabilities or reduce the power con- default setting of 0. Setting Bit 4 or Register 0x07 corresponds sumption of the Rx path, so that the device’s maximum to the 011 setting, and the settings of 101 and 111 result in allowable power consumption, P , is not exceeded. MAX higher current consumption. Figure 84 shows how the SNR and P is specified at 1.66 W to ensure that the die temperature THD performance are affected for a 10 MHz sine wave input MAX does not exceed 125oC at an ambient temperature of 85oC. This for the lower power settings as the ADC sample rate is swept specification is based on the 64-pin LFSCP having a thermal from 20 MHz to 80 MHz. resistance, θ , of 24oC/W with its heat slug soldered. (The θ is JA JA 220 101 OR 111 30.8oC/W, if the heat slug remains unsoldered.) If a particular 210 application’s maximum ambient temperature, T , falls below A 200 85oC, the maximum allowable power dissipation can be deter- 000 190 mined by the following equation: 001 mA)180 010 PMAX = 1.66 + (85 − TA)/24 (13) (DD170 Assuming the IAMP’s common-mode bias voltage is operating V IA160 off the same analog supply as the AD9866, the following equa- 011 101 150 100 tion can be used to calculate the maximum total current consumption, I , of the IC: 140 MAX 11230020 30 40 50 60 70 8004560-0-083 WithI ManAX a =m (bPiMenAXt −te mPIpAMePr)a/t3u.r4e7 of up to 85°C, IMAX is 478 mA. ( 14) SAMPLE RATE (MSPS) If the IAMP is operating off a different supply or in the voltage Figure 83. AVDD Current vs. ADC Bias Setting and Sample Rate mode configuration, first calculate the power dissipated in the 65 –54 IAMP, PIAMP, using Equation 2 or Equation 5, and then recalcu- late I , using Equation 14. 64 –56 MAX 63 –58 Figure 78, Figure 79, Figure 81, and Figure 83 can be used to SNR-000 calculate the current consumption of the Rx and Tx paths for a 62 SNR-001 –60 SNR-010 given setting. c) 61 SNR-011 –62 c) R (dB 60 SSNNRR--110001 –64 D (dB MODE SELECT UPON POWER-UP AND RESET N H S 59 –66 T The AD9866 power-up state is determined by the logic levels appearing at the MODE and CONFIG pins. The MODE pin is 58 THD-000 –68 THD-001 used to select a half- or full-duplex interface by pin strapping it 57 THD-010 –70 555620 30 40TTTHHHDDD---01110010150 60 70 80––7742 04560-0-084 lttohiowen S owPrI iht rhieg gthhi,se tr eMersspO aeDsc toEivu petlliyinn. teTodh deine Ct TeOrambNlieFn I1eG1 t .hp ein d iesf auusletd s eintt icnognsj ufonrc - SAMPLE RATE (MSPS) The intent of these particular default settings is to allow some Figure 84. SNR and THD Performance vs. fADC and ADC Bias Setting with applications to avoid using the SPI (disabled by pin-strapping RxPGA = 0 dB, fIN = 10 MHz, AIN = −1 dBFS SEN high), thereby reducing implementation costs. For A sine wave input is a standard and convenient method of example, setting MODE low and CONFIG high configures the analyzing the performance of a system. However, the amount of AD9866 to be backward-compatible with the AD9975, while power reduction that is possible is application dependent, based setting MODE high and CONFIG low makes it backward- on the nature of the input waveform (such as frequency content, compatible with the AD9875. Other applications must use the peak-to-rms ratio), the minimum ADC sample, and the mini- SPI to configure the device. mum acceptable level of performance. Thus, it is advisable that power-sensitive applications optimize the power bias setting of the Rx path using an input waveform that is representative of the application. Rev. C | Page 42 of 47

Data Sheet AD9866 A hardware (RESET pin) or software (Bit 5 of Register 0x00) For example, the user can configure the AD9866 with similar reset can be used to place the AD9866 into a known state of settings as the target system, inject an input signal (sinusoidal operation as determined by the state of the MODE and CONFIG waveform) into the Rx input, and monitor the quality of the pins. A dc offset calibration and filter tuning routine is also reconstructed output from the TxDAC or IAMP to ensure a initiated upon a hardware reset, but not with a software reset. minimum level of performance. In this test, the user can Neither reset method flushes the digital interpolation filters in exercise the RxPGA as well as validate the attenuation char- the Tx path. Refer to the Half-Duplex Mode and Full-Duplex acteristics of the RxLPF. Note that the RxPGA gain setting Mode sections for information on flushing the digital filters. should be selected such that the input does not result in clipping of the ADC. A hardware reset can be triggered by pulsing the RESET pin low for a minimum of 50 ns. The SPI registers are instantly reset to Digital loopback can be used to test the full-duplex digital their default settings upon RESET going low, while the dc offset interface of the AD9866. In this test, data appearing on the Tx[5:0] port is routed back to the Rx[5:0] port, thereby calibration and filter tuning routine is initiated upon RESET confirming proper bus operation. The Rx port can also be returning high. To ensure sufficient power-on time of the various three-stated for half- and full-duplex interfaces. functional blocks, RESET returning high should occur no less than 10 ms upon power-up. If a digital reset signal from a Table 27. SPI Registers for Test Modes microprocessor reset circuit (such as ADM1818) is not available, a Address (Hex) Bit Description simple R-C network referenced to DVDD can be used to hold 0x0D (7) Analog loopback RESET low for approximately 10 ms upon power-up. (6) Digital loopback ANALOG AND DIGITAL LOOPBACK TEST MODES (5) Rx port three-state The AD9866 features analog and digital loopback capabilities that can assist in system debug and final test. Analog loopback routes the digital output of the ADC back into the Tx data path prior to the interpolation filters such that the Rx input signal can be monitored at the output of the TxDAC or IAMP. As a result, the analog loopback feature can be used for a half- or full-duplex interface to allow testing of the functionality of the entire IC (excluding the digital data interface). Rev. C | Page 43 of 47

AD9866 Data Sheet PCB DESIGN CONSIDERATIONS Although the AD9866 is a mixed-signal device, the part should POWER PLANES AND DECOUPLING be treated as an analog component. The on-chip digital cir- While the AD9866 evaluation board demonstrates a very good cuitry has been specially designed to minimize the impact of its power supply distribution and decoupling strategy, it can be digital switching noise on the MxFE’s analog performance. further simplified for many applications. The board has four To achieve the best performance, the power, grounding, and layers: two signal layers, one ground plane, and one power layout recommendations in this section should be followed. plane. While the power plane on the evaluation board is split Assembly instructions for the micro-lead frame package can be into multiple analog and digital subsections, a permissible found in an application note from Amkor at: www.amkor.com/ alternative would be to have AVDD and CLKVDD share the products/notes_papers/MLF_AppNote_0902.pdf. same analog 3.3 V power plane. A separate analog plane/supply COMPONENT PLACEMENT may be allocated to the IAMP, if its supply voltage differs from the 3.3 V required by AVDD and CLKVDD. On the digital If the three following guidelines of component placement are side, DVDD and DRVDD can share the same 3.3 V digital followed, chances for getting the best performance from the power plane. This digital power plane brings the current used MxFE are greatly increased. First, manage the path of return to power the digital portion of the MxFE and its output drivers. currents flowing in the ground plane so that high frequency This digital plane should be kept from going underneath the switching currents from the digital circuits do not flow on the analog components. ground plane under the MxFE or analog circuits. Second, keep The analog and digital power planes allocated to the MxFE may noisy digital signal paths and sensitive receive signal paths as be fed from the same low noise voltage source; however, they short as possible. Third, keep digital (noise generating) and should be decoupled from each other to prevent the noise analog (noise susceptible) circuits as far away from each other generated in the digital portion of the MxFE from corrupting as possible. the AVDD supply. This can be done by using ferrite beads be- To best manage the return currents, pure digital circuits that tween the voltage source and the respective analog and digital generate high switching currents should be closest to the power power planes with a low ESR, bulk decoupling capacitor on the supply entry. This keeps the highest frequency return current MxFE side of the ferrite. Each of the MxFE’s supply pins (AVDD, paths short and prevents them from traveling over the sensitive CLKVDD, DVDD, and DRVDD) should also have dedicated MxFE and analog portions of the ground plane. Also, these low ESR, ESL decoupling capacitors. The decoupling capacitors circuits should be generously bypassed at each device, which should be placed as close to the MxFE supply pins as possible. further reduces the high frequency ground currents. The MxFE GROUND PLANES should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections do not flow in The AD9866 evaluation board uses a single serrated ground plane the ground plane under the MxFE. to help prevent any high frequency digital ground currents from coupling over to the analog portion of the ground plane. The The AD9866 has several pins that are used to decouple sensitive digital currents affiliated with the high speed data bus interface internal nodes. These pins are REFIO, REFB, and REFT. The (Pin 1 to Pin 16) have the highest potential of generating decoupling capacitors connected to these points should have problematic high frequency noise. A ground serration that contains low ESR and ESL. These capacitors should be placed as close to these currents should reduce the effects of this potential noise source. the MxFE as possible (see Figure 75) and be connected directly to the analog ground plane. The resistor connected to the The ground plane directly underneath the MxFE should be REFADJ pin should also be placed close to the device and continuous and uniform. The 64-lead LFCSP package is designed connected directly to the analog ground plane. to provide excellent thermal conductivity. This is partly achieved by incorporating an exposed die paddle on the bottom surface of the package. However, to take full advantage of this feature, the PCB must have features to effectively conduct heat away from the package. This can be achieved by incorporating thermal pad and thermal vias on the PCB. While a thermal pad provides a solderable surface on the top surface of the PCB (to solder the package die paddle on the board), thermal vias are needed to provide a thermal path to inner and/or bottom layers of the PCB to remove the heat. Lastly, all ground connections should be made as short as possible. This results in the lowest impedance return paths and the quietest ground connections. Rev. C | Page 44 of 47

Data Sheet AD9866 SIGNAL ROUTING The receive RX+ and RX− signals are the most sensitive signals on the entire board. Careful routing of these signals is essential The digital Rx and Tx signal paths should be kept as short as for good receive path performance. The RX+ and RX− signals possible. Also, the impedance of these traces should have a form a differential pair and should be routed together as a pair. controlled characteristic impedance of about 50 Ω. This By keeping the traces adjacent to each other, noise coupled prevents poor signal integrity and the high currents that can onto the signals appears as common mode and is largely occur during undershoot or overshoot caused by ringing. If the rejected by the MxFE receive input. Keeping the driving point signal traces cannot be kept shorter than about 1.5 inches, impedance of the receive signal low and placing any low-pass series termination resistors (33 Ω to 47 Ω) should be placed filtering of the signals close to the MxFE further reduces the close to all digital signal sources. It is a good idea to series- possibility of noise corrupting these signals. terminate all clock signals at their source, regardless of trace length. Rev. C | Page 45 of 47

AD9866 Data Sheet EVALUATION BOARD Alternatively, the evaluation board allows independent evalua- An evaluation board is available for the AD9865 and AD9866. tion of the TxDAC, IAMP, and Rx paths via SMA connectors. The digital interface to the evaluation board can be configured The IAMP can be easily configured for a voltage or current for a half- or full-duplex interface. Two 40-pin and one 26-pin mode interface via jumper settings. The TxDAC’s performance male right angle headers (0.100 inches) provide easy interfacing can be evaluated directly or via an optional dual op amp driver to test equipment such as digital data capture boards, pattern stage. The Rx path includes a transformer and termination generators, or custom digital evaluation boards (FPGA, DSP, or resistor, allowing for a calibrated differential input signal to be ASIC). The reference clock source can originate from an exter- injected into its front end. nal generator, crystal oscillator, or crystal. Software and an interface cable are included to allow for programming of the SPI The Analog Devices, Inc. website offers more information on registers via a PC. the AD9865/AD9866 evaluation board. The analog interface on the evaluation board provides a full analog front-end reference design for power line applications. It includes a power line socket, line transformer, protection diodes, and passive filtering components. An auxiliary path allows independent monitoring of the ac power line. The evaluation board allows complete optimization of power line reference designs based around the AD9865 or AD9866. Rev. C | Page 46 of 47

Data Sheet AD9866 OUTLINE DIMENSIONS 9.10 0.60 9.00 SQ 0.60 0.42 8.90 0.42 0.24 PIN 1 0.24 INDICATOR 49 64 1 48 PIN 1 INDICATOR 8.85 0.50 EXPOSED 7.25 8.75 SQ BSC PAD 7.10 SQ 8.65 6.95 0.50 0.40 3332 1716 0.30 0.25 MIN TOP VIEW BOTTOM VIEW 7.50 REF 1.00 12° MAX 0.80 MAX 0.65 NOM 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND SEATING 0.30 FUNCTION DESCRIPTIONS PLANE 0.23 0.20 REF SECTION OF THIS DATA SHEET. PKG-001152 0.18COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 01-22-2015-D Figure 85. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9866BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 AD9866BCPZRL −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-3 1 Z = RoHS Compliant Part. ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04560-0-8/16(C) Rev. C | Page 47 of 47

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9866BCPZ AD9866BCPZRL