Mixed-Signal Front-End (MxFE™) Baseband Transceiver for Broadband Applications Data Sheet AD9861 FEATURES FUNCTIONAL BLOCK DIAGRAM Receive path includes dual 10-bit analog-to-digital converters VIN+A with internal or external reference, 50 MSPS and 80 MSPS versions VIN–A ADC DMAUTXA Rx DATA VIN+B AND Transmit path includes dual 10-bit, 200 MSPS digital-to-analog ADC LATCH VIN–B converters with 1×, 2×, or 4× interpolation and programmable I/O gain control I/O ICNOTNETRRFOACLE INTERFACE Internal clock distribution block includes a programmable phase- LOW-PASS CONFIGURATION FLEXIBLE INTERPOLATION BLOCK I/O BUS locked loop and timing generation circuitry, allowing single- FILTER [0:19] reference clock operation IOUT+A DAC DATA 20-pin flexible I/O data interface allows various interleaved or IOUT–A LATCH AND noninterleaved data transfers in half-duplex mode and IOUT+B DEMUX Tx DATA DAC interleaved data transfers in full-duplex mode IOUT–B Configurable through register programmability or optionally AUX limited programmability through mode pins ADC Independent Rx and Tx power-down control pins AUX 64-lead LFCSP package (9 mm × 9 mm footprint) DAC ADC CLOCK CLKIN 3 configurable auxiliary converter pins AUX APPLICATIONS DAC DAC CLOCK PLL Broadband access AUX ADC Broadband LAN Communications (modems) AD9861 AUX DAC 03606-0-001 Figure 1. GENERAL DESCRIPTION The AD9861 is a member of the MxFE family—a group of integrated In half-duplex systems, the interface supports 20-bit parallel converters for the communications market. The AD9861 integrates transfers or 10-bit interleaved transfers. In full-duplex systems, dual 10-bit analog-to-digital converters (ADC) and dual 10-bit the interface supports an interleaved 10-bit ADC bus and an digital-to-analog converters (TxDAC®). Two speed grades are interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin available, -50 and -80. The -50 is optimized for ADC sampling of 50 count and, therefore, reduces the required package size on the MSPS and less, while the -80 is optimized for ADC sample rates AD9861 and the device to which it connects. between 50 MSPS and 80 MSPS. The dual TxDACs operate at speeds The AD9861 can use either mode pins or a serial program- up to 200 MHz and include a bypassable 2× or 4× interpolation mable interface (SPI) to configure the interface bus, operate the filter. Three auxiliary converters are also available to provide ADC in a low power mode, configure the TxDAC interpolation required system level control voltages or to monitor system signals. rate, and control ADC and TxDAC power-down. The SPI The AD9861 is optimized for high performance, low power, small provides more programmable options for both the TxDAC path form factor, and to provide a cost-effective solution for the (for example, coarse and fine gain control and offset control for broadband communication market. channel matching) and the ADC path (for example, the internal The AD9861 uses a single input clock pin (CLKIN) to generate all duty cycle stabilizer, and twos complement data format). system clocks. The ADC and TxDAC clocks are generated within a The AD9861 is packaged in a 64-lead LFCSP (low profile, fine timing generation block that provides user programmable options pitched, chip scale package). The 64-lead LFCSP footprint is such as divide circuits, PLL multipliers, and switches. only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into A flexible, bidirectional 20-bit I/O bus accommodates a variety of tightly spaced applications such as PCMCIA cards custom digital back ends or open market DSPs. Rev. A | Page 1 of 51

AD9861 Data Sheet TABLE OF CONTENTS Features ....................................................................................................... 1 Typical Performance Characteristics .................................................... 10 Applications ................................................................................................ 1 Terminology ............................................................................................. 21 Functional Block Diagram ....................................................................... 1 Theory of Operation ............................................................................... 22 General Description .................................................................................. 1 System Block ........................................................................................ 22 TABLE OF CONTENTS ........................................................................... 2 Rx Path Block ...................................................................................... 22 Tx Path Specifications ............................................................................... 3 Tx Path Block ...................................................................................... 24 Rx Path Specifications ............................................................................... 4 Auxiliary Converters .......................................................................... 27 Power Specifications .................................................................................. 5 Digital Block ........................................................................................ 30 Digital Specifications ................................................................................. 5 Programmable Registers .................................................................... 42 Timing Specifications ................................................................................ 6 Clock Distribution Block ................................................................... 45 Absolute Maximum Ratings ..................................................................... 7 Outline Dimensions ................................................................................ 49 ESD Caution ........................................................................................... 7 Ordering Guide ................................................................................... 49 Pin Configuration and Pin Function Descriptions ............................... 8 REVISION HISTORY 4/2017—Rev. 0 to Rev. A Changes to Figure 3 and Table 8 ..................................................... 8 Updated Outline Dimensions ....................................................... 44 Changes to Ordering Guide .......................................................... 44 11/2003—Revision 0: Initial Version Rev. A | Page 2 of 51

Data Sheet AD9861 TX PATH SPECIFICATIONS Table 1. AD9861-50 and AD9861-80 F = 200 MSPS; 4× interpolation; R = 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB, AVDD = DVDD = 3.3 V, DAC SET unless otherwise noted Parameter Temp Test Level Min Typ Max Unit Tx PATH GENERAL Resolution Full IV 10 Bits Maximum DAC Update Rate Full IV 200 MHz Maximum Full-Scale Output Current Full IV 20 mA Full-Scale Error Full V 1% Gain Mismatch Error 25°C IV –3.5 +3.5 % FS Offset Mismatch Error Full IV –0.1 +0.1 % FS Reference Voltage Full V 1.23 V Output Capacitance Full V 5 pF Phase Noise (1 kHz Offset, 6 MHz Tone) 25°C V –115 dBc/Hz Output Voltage Compliance Range Full IV –1.0 +1.0 V TxPGA Gain Range Full V 20 dB TxPGA Step Size Full V 0.10 dB Tx PATH DYNAMIC PERFORMANCE (I = 20 mA; F = 1 MHz) OUTFS OUT SNR Full IV 60.2 60.8 dB SINAD Full IV 59.7 60.7 dB THD Full IV −77.5 −65.8 dBc SFDR, Wideband (DC to Nyquist) Full IV 64.6 76.0 dBc SFDR, Narrowband (1 MHz Window) Full IV 72.5 81.0 dBc 1 See Figure 2 for description of the TxDAC termination scheme. TxDAC 50Ω 50Ω 03606-0-030 Figure 2. Diagram Showing Termination of 100 Ω Differential Load for Some TxDAC Measurements Rev. A | Page 3 of 51

AD9861 Data Sheet Rx PATH SPECIFICATIONS Table 2. AD9861-50 and AD9861-80 F = 50 MSPS for the AD9861-50, 80 MSPS for the AD9861-80; internal reference; differential analog inputs, ADC ADC_AVDD = DVDD = 3.3V, unless otherwise noted Parameter Temp Test Level Min Typ Max Unit Rx PATH GENERAL Resolution Full V 10 Bits Maximum ADC Sample Rate Full IV 50/80 MSPS Gain Mismatch Error Full V ±0.2 % FS Offset Mismatch Error Full V ±0.1 % FS Reference Voltage Full V 1.0 V Reference Voltage (REFT–REFB) Error Full IV –30 ±6 +30 mV Input Resistance (Differential) Full V 2 kΩ Input Capacitance Full V 5 pF Input Bandwidth Full V 30 MHz Differential Analog Input Voltage Range Full V 2 V p-p differential Rx PATH DC ACCURACY Integral Nonlinearity (INL) 25°C V ±0.75 LSB Differential Nonlinearity (DNL) 25°C V ±0.75 LSB Aperature Delay 25°C V 2.0 ns Aperature Uncertainty (Jitter) 25°C V 1.2 ps rms Input Referred Noise 25°C V 450 uV AD9861-50 Rx PATH DYNAMIC PERFORMANCE (V = –0.5 dBFS; F = 10 MHz) IN IN SNR Full IV 55.5 60 dBc SINAD Full IV 55.6 60 dBc SINAD 25°C IV 58.5 60 dBc THD (Second to Ninth Harmonics) Full IV −71.5 −64.6 dBc SFDR, Wideband (DC to Nyquist) Full IV 65.7 73.5 dBc Crosstalk between ADC Inputs Full V 80 dB AD9861-80 Rx PATH DYNAMIC PERFORMANCE (V = –0.5 dBFS; F = 10 MHz) IN IN SNR Full IV 55.4 59.5 dBc SINAD Full IV 52.7 59.0 dBc THD (Second to Ninth Harmonics) Full IV −67 dBc SFDR, Wideband (DC to Nyquist) Full IV 67 dBc Crosstalk between ADC Inputs Full V 80 dB Rev. A | Page 4 of 51

Data Sheet AD9861 POWER SPECIFICATIONS Table 3. AD9861-50 and AD9861-80 Analog and digital supplies = 3.3 V; F = 50 MHz; PLL 4× setting; normal timing mode CLKIN Parameter Temp Test Level Min Typ Max Unit POWER SUPPLY RANGE Analog Supply Voltage (AVDD) Full IV 2.7 3.6 V Digital Supply Voltage (DVDD) Full IV 2.7 3.6 V Driver Supply Voltage (DRVDD) Full IV 2.7 3.6 V ANALOG SUPPLY CURRENTS TxPath (20 mA Full-Scale Outputs) Full V 70 mA TxPath (2 mA Full-Scale Outputs) Full V 20 mA Rx Path (-80, at 80 MSPS) Full V 165 mA RxPath (-80, at 40 MSPS, Low Power Mode) Full V 82 mA RxPath (-80, at 20 MSPS, Ultralow Power Mode) Full V 35 mA Rx Path (-50, at 50 MSPS) Full V 103 mA RxPath (-50, at 50 MSPS, Low Power Mode) Full V 69 mA RxPath (-50, at 16 MSPS, Ultralow Power Mode) Full V 28 mA TxPath, Power-Down Mode Full V 2 mA RxPath, Power-Down Mode Full V 5 mA PLL Full V 12 mA DIGITAL SUPPLY CURRENTS TxPath, 1× Interpolation, Full V 20 mA 50 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode TxPath, 2× Interpolation, Full V 50 mA 100 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode TxPath, 4× Interpolation, Full V 80 mA 200 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode RxPath Digital, Half-Duplex 24 Mode Full V 15 mA DIGITAL SPECIFICATIONS Table 4. AD9861-50 and AD9861-80 Parameter Temp Test Level Min Typ Max Unit LOGIC LEVELS Input Logic High Voltage, V Full IV DRVDD – 0.7 V IH Input Logic Low Voltage, V Full IV 0.4 V IL Output Logic High Voltage, V (1 mA Load) Full IV DRVDD – 0.6 V OH Output Logic Low Voltage, V (1 mA Load) Full IV 0.4 V OL DIGITAL PIN Input Leakage Current Full IV 12 µA Input Capacitance Full IV 3 pF Minimum RESET Low Pulse Width Full IV 5 Input Clock Cycles Digital Output Rise/Fall Time Full IV 2.8 4 ns Rev. A | Page 5 of 51

AD9861 Data Sheet TIMING SPECIFICATIONS Table 5. AD9861-50 and AD9861-80 Parameter Temp Test Level Min Typ Max Unit INPUT CLOCK CLKIN Clock Rate (PLL Bypassed) Full IV 1 200 MHz PLL Input Frequency Full IV 16 200 MHz PLL Ouput Frequency Full IV 32 350 MHz TxPATH DATA Setup Time (HD20 Mode, Time Required Before Data Latching Full V 5 ns (see Clock Edge) Distribution Block section) Hold Time (HD20 Mode, Time Required After Data Latching Edge) Full V –1.5 ns (see Clock Distribution Block section) Latency 1× Interpolation (data in until peak output response) Full V 7 DAC Clock Cycles Latency 2× Interpolation (data in until peak output response) Full V 35 DAC Clock Cycles Latency 4× Interpolation (data in until peak output response) Full V 83 DAC Clock Cycles RxPATH DATA Output Delay (HD20 Mode, t ) Full V –1.5 ns (see Clock OD Distribution Block section) Latency Full V 5 ADC Clock Cycles Table 6. Explanation of Test Levels Level Description I 100% production tested. II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. Rev. A | Page 6 of 51

Data Sheet AD9861 ABSOLUTE MAXIMUM RATINGS Thermal Resistance Table 7. 64-lead LFCSP (4-layer board): Parameter Rating θ = 24.2 (paddle soldered to ground plan, 0 LPM Air) Electrical JA θ = 30.8 (paddle not soldered to ground plan, 0 LPM Air) AVDD Voltage 3.9 V max JA DRVDD Voltage 3.9 V max Stresses at or above those listed under Absolute Maximum Ratings Analog Input Voltage –0.3 V to AVDD + 0.3 V may cause permanent damage to the product. This is a stress Digital Input Voltage –0.3 V to DVDD – 0.3 V rating only; functional operation of the product at these or any Digital Output Current 5 mA max other conditions above those indicated in the operational section Environmental of this Operating Temperature Range ESD CAUTION –40°C to +85°C (Ambient) Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range –65°C to +150°C (Ambient) Rev. A | Page 7 of 51

AD9861 Data Sheet PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS SPI_CSTxPWRDWNRxPWRDWNADC_AVDDREFTADC_AVSSVIN+AVIN–AVREFVIN–BVIN+BADC_AVSSREFBADC_AVDDPLL_AVDDPLL_AVSS 4321098765432109 6666655555555554 SPI_DIO 1 48 CLKIN SPI_CLK 2 47 AUXADC_REF SPI_SDO/AUX_SPI_SDO 3 46 RESET ADC_LO_PWR/AUX_SPI_CS 4 45 AUX_DACC/AUX_ADCB DVDD 5 44 L0 DVSS 6 43 L1 AVDD 7 AD9861 42 L2 IOUT–A 8 41 L3 TOP VIEW IOUT+A 9 (Not to Scale) 40 L4 AGND10 39 L5 REFIO 11 38 L6 FSADJ12 37 L7 AGND13 36 L8 IOUT+B14 35 L9 IOUT–B15 34 AUX_SPI_CLK AVDD16 33 IFACE1 7890123456789012 1112222222222333 E2E3U9U8U7U6U5U4U3U2U1U0A2A1DDSS CC CCVV IFAIFA _AD_ADDRDR XX UU AA A/B/ CC AA DD __ XX UU AA N1.O ETXEPSOSED PAD. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE. 03606-019 Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Name1 Description2, 3 1 SPI_DIO SPI: Serial Port Data Input. (Interp1) No SPI: Tx Interpolation Pin, MSB. 2 SPI_CLK SPI: Serial Port Shift Clock. (Interp0) No SPI: Tx Interpolation Pin, LSB. 3 SPI_SDO/AUXSPI_SDO SPI: 4-Wire Serial Port Data Output/Data Output Pin for AuxSPI. (FD/HD) No SPI: Configures Full-Duplex or Half-Duplex Mode. 4 ADC_LO_PWR/AUX_SPI_CS ADC Low Power Mode Enable. Defined at power-up. CS for AuxSPI. 5, 31 DVDD Digital Supply. 6, 32 DVSS Digital Ground. 7, 16, 50, 51, 61 AVDD Analog Supply. 8, 9 IOUT–A, IOUT+A DAC A Differential Output. 10, 13, 49, 53, 59 AGND, AVSS Analog Ground. 11 REFIO Tx DAC Band Gap Reference Decoupling Pin. 12 FSADJ Tx DAC Full-Scale Adjust Pin. 14, 15 IOUT+B, IOUT−B DAC B Differential Output. 17 IFACE2 SPI: Buffered CLKIN. Can be configured as system clock output. (10/20) No SPI: For FD: Buffered CLKIN; For HD20 or HD10 : 10/20 Configuration Pin. 18 IFACE3 Clock Output. 19–28 U9–U0 Upper Data Bit 9 to Upper Data Bit 0. 29 AUX1 Configurable as either AuxADC_A2 or AuxDAC_A. 30 AUX2 Configurable as either AuxADC_A1 or AuxDAC_B. 33 IFACE1 SPI: For FD: TxSYNC; For HD20, HD10, or Clone: Tx/Rx. No SPI: FD >> TxSYNC; HD20 or HD10: Tx/Rx. 34 AUX_SPI_CLK CLK for AuxSPI. 35–44 L9–L0 Lower Data Bit 9 to Lower Data Bit 0. Rev. A | Page 8 of 51

Data Sheet AD9861 Pin No. Name1 Description2, 3 45 AUX3 Configurable as either AuxADC_B or AuxDAC_C. 46 RESET Chip Reset When Low. 47 AUX_ADC_REF Decoupling for AuxADC On-Chip Reference. 48 CLKIN Clock Input. 52 REFB ADC Bottom Reference. 54, 55 VIN+B, VIN−B ADC B Differential Input. 56 VREF ADC Band Gap Reference. 57, 58 VIN−A, VIN+A ADC A Differential Input. 60 REFT ADC Top Reference. 62 RxPwrDwn Rx Analog Power-Down Control. 63 TxPwrDwn Tx Analog Power-Down Control. 64 SPI_CS SPI: Serial Port Chip Select. At power-up or reset, this must be high. No SPI: Tie low to disable SPI and use mode pins. This pin must be tied low. EPAD Exposed Pad. The exposed pad must be securely connected to the ground plane. 1 Underlined pin names and descriptions apply when the device is configured without a serial port interface, referred to as no SPI mode. 2 Pin function depends if the serial port is used to configure the AD9861 (called SPI mode) or if mode pins are used to configure the AD9861 (called No SPI mode). The differences are indicated by the SPI and No SPI labels in the description column. 3 Some pin descriptions depend on the interface configuration, full-duplex (FD), half-duplex interleaved data (HD10), half-duplex parallel data (HD20), and a half-duplex interface similar to the AD9860 and AD9862 data interface called clone mode (Clone). Clone mode requires a serial port interface. Rev. A | Page 9 of 51

AD9861 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –10 –10 –20 –20 –30 –30 S) S) F –40 F –40 B B d d E ( –50 E ( –50 D D TU –60 TU –60 LI LI MP –70 MP –70 A A –80 –80 –90 –90 ––110100 03606-0-031 ––110100 03606-0-032 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Figure 7. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 2 MHz Tone Digitizing 1 MHz and 2 MHz Tones 0 0 –10 –10 –20 –20 –30 –30 S) S) F –40 F –40 B B d d E ( –50 E ( –50 D D TU –60 TU –60 LI LI MP –70 MP –70 A A –80 –80 –90 –90 ––110100 03606-0-033 ––110100 03606-0-034 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Figure 8. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 5 MHz Tone Digitizing 5 MHz and 8 MHz Tones 0 0 –10 –10 –20 –20 –30 –30 S) S) F –40 F –40 B B d d E ( –50 E ( –50 D D TU –60 TU –60 LI LI MP –70 MP –70 A A –80 –80 –90 –90 ––110100 03606-0-035 ––110100 03606-0-036 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Figure 9. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 24 MHz Tone Digitizing 20 MHz and 25 MHz Tones Rev. A | Page 10 of 51

Data Sheet AD9861 0 0 –10 –10 –20 –20 –30 –30 S) S) F –40 F –40 B B d d E ( –50 E ( –50 D D TU –60 TU –60 LI LI MP –70 MP –70 A A –80 –80 –90 –90 ––110100 03606-0-037 ––110100 03606-0-038 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Figure 13. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 76 MHz Tone Digitizing 70 MHz and 72 MHz Tones 62 62 10.0 NORMAL POWER @ 50MSPS NORMAL POWER @ 50MSPS 9.8 LOW POWER ADC @ 25MSPS LOW POWER ADC @ 25MSPS 9.6 59 59 9.4 SNR (dBc) 56 SINAD (dBc) 56 899...802 ENOB (Bits) ULTRALOW POWER ADC ULTRALOW POWER ADC @ 16MSPS @ 16MSPS 8.6 53 53 8.4 50 03606-0-039 50 88..02 03606-0-040 0 5 10 15 20 25 0 5 10 15 20 25 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 11. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone Figure 14. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Frequency SINAD Performance vs. Input Frequency 80 –50 LOW POWER ADC @ 25MSPS 75 –55 70 NORMAL POWER @ 50MSPS –60 ULTRALOW POWER ADC Bc) Bc) @ 16MSPS FDR (d 65 THD (d –65 NORMAL POWER @ 50MSPS S –70 60 ULTRALOW POWER ADC @ 16MSPS –75 5550 03606-0-041 –800 LOW 5POWER ADC1 0@ 25MSPS15 20 2503606-0-042 0 5 10 15 20 25 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 12. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone Figure 15. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SFDR Performance vs. Input Frequency THD Performance vs. Input Frequency Rev. A | Page 11 of 51

AD9861 Data Sheet 70 90 –90 SFDR 60 80 –80 50 70 –70 SNR (dBc) 3400 IDEAL SNR SFDR (dBFS) 5600 THD ––6500THD (dBFS) SNR 20 40 –40 100 03606-0-043 2300 ––3200 03606-0-044 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 0 –5 –10 –15 –20 –25 –30 –35 –40 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 16. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone Figure 19. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude THD and SFDR Performance vs. Input Amplitude 62 62 10.0 9.9 AVE (–40C) 61 61 AVE (+25C) AVE (–40C) 9.8 AVE (+25C) 9.7 60 60 SNR (dBc) 59 AVE (+85C) SINAD (dBc) 59 AVE (+85C) 999...654 ENOB (Bits) 58 58 9.3 9.2 57 57 56 03606-0-045 56 99..10 03606-0-046 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 ADC_AVDD VOLTAGE (V) ADC_AVDD VOLTAGE (V) Figure 17. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone Figure 20. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. ADC_AVDD and Temperature SINAD Performance vs. ADC_AVDD and Temperature –70.0 70 –70.5 71 –71.0 AVE (+85C) 72 –71.5 AVE (+85C) 73 THD (dBc)–––777322...050 AVE (+25C) SFDR (dBc) 7745 AVE (+25C) –73.5 AVE (–40C) AVE (–40C) 76 –74.0 ––7754..05 03606-0-047 7787 03606-0-048 3.6 3.3 3.0 2.7 3.6 3.3 3.0 2.7 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 18. AD9861-50 Rx Path Single-Tone THD Performance vs. Figure 21. AD9861-50 Rx Path Single-Tone SFDR Performance vs. ADC_AVDD and Temperature ADC_AVDD and Temperature Rev. A | Page 12 of 51

Data Sheet AD9861 0 0 –10 –10 –20 –20 –30 –30 S) S) F –40 F –40 B B d d E ( –50 E ( –50 D D TU –60 TU –60 LI LI MP –70 MP –70 A A –80 –80 –90 –90 ––110100 03606-0-049 ––110100 03606-0-050 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Figure 25. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 2 MHz Tone Digitizing 1 MHz and 2 MHz Tones 0 0 –10 –10 –20 –20 –30 –30 S) S) F –40 F –40 B B d d E ( –50 E ( –50 D D TU –60 TU –60 LI LI MP –70 MP –70 A A –80 –80 –90 –90 ––110100 03606-0-051 ––110100 03606-0-052 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 23. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Figure 26. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 5 MHz Tone Digitizing 5 MHz and 8 MHz Tones 0 0 –10 –10 –20 –20 –30 –30 S) S) F –40 F –40 B B d d E ( –50 E ( –50 D D TU –60 TU –60 LI LI MP –70 MP –70 A A –80 –80 –90 –90 ––110100 03606-0-053 ––110100 03606-0-054 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Figure 27. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 24 MHz Tone Digitizing 20 MHz and 25 MHz Tones Rev. A | Page 13 of 51

AD9861 Data Sheet 62 62 10.0 LOW POWER ADC @ 40MSPS LOW POWER ADC @ 40MSPS ULTRALOW POWER ADC @ 16MSPS 9.8 ULTRALOW POWER ADC @ 16MSPS 9.6 59 59 9.4 NORMAL POWER @ 80MSPS Bc) dBc) NORMAL POWER @ 80MSPS 9.2 Bits) SNR (d 56 SINAD ( 56 98..08 ENOB ( 8.6 53 53 8.4 50 03606-0-055 50 88..20 03606-0-056 0 5 10 15 20 25 30 0 5 10 15 20 25 30 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 28. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone Figure 31. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. Input Frequency and Power Setting SINAD Performance vs. Input Frequency and Power Setting 85 –50 LOW POWER ADC @ 40MSPS –55 80 ULTRALOW POWER ADC @ 16MSPS –60 SFDR (dBc) 7750 THD (dBc) –65 LOW POWER ADC @ 40MSPS –70 NORMAL POWER @ 80MSPS 65 –75 60 03606-0-057 –80 NORMAL POWER @ 80MSPUSLTRAADLCO @W 1P6OMWSPESR 03606-0-058 0 5 10 15 20 25 0 5 10 15 20 25 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 29. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone Figure 32. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SFDR Performance vs. Input Frequency and Power Setting THD Performance vs. Input Frequency and Power Setting 70 –80 80 60 –70 70 50 –60 SFDR 60 SNR (dBc) 3400 IDEAL SNR THD (dBFS) –50 THD 50 SFDR (dBFS) –40 40 20 SNR –30 30 100 03606-0-059 –20 20 03606-0-060 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 0 –5 –10 –15 –20 –25 –30 –35 –40 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) Figure 30. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone Figure 33. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude THD Performance vs. Input Amplitude Rev. A | Page 14 of 51

Data Sheet AD9861 62 62 10.0 9.9 61 61 9.8 AVE (+85C) AVE (–40C) 9.7 60 60 Bc) dBc) AVE (+A25VEC )(+85C) 9.6 Bits) SNR (d 59 AVE (+25C) SINAD ( 59 99..54 ENOB ( 58 58 9.3 AVE (–40C) 9.2 57 57 56 03606-0-065 56 99..01 03606-0-066 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 ADC_AVDD VOLTAGE (V) ADC_AVDD VOLTAGE (V) Figure 34. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone Figure 37. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. AVDD and Temperature SINAD Performance vs. AVDD and Temperature 70 65 AVE (+85C) 69 66 AVE (–40C) 68 67 AVE (+25C) 67 AVE (–40C) 68 AVE (+25C) THD (dBc) 666456 AVE (+85C) SFDR (dBc) 776109 63 72 62 73 6601 03606-0-061 7754 03606-0-062 2.7 3.0 3.3 3.6 2.7 3.0 3.3 3.6 ADC_AVDD VOLTAGE (V) ADC_AVDD VOLTAGE (V) Figure 35. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone Figure 38. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone THD Performance vs. AVDD and Temperature SFDR Performance vs. AVDD and Temperature 120 180 NORM 160 100 NORM 140 A) A) m m T ( 80 T ( 120 N N E E RR LP RR 100 U 60 U LP C C D D 80 D D V V A 40 A 60 C C AD ULP AD 40 20 0 03606-0-063 200 ULP 03606-0-064 0 10 20 30 40 50 0 10 20 30 40 50 60 70 80 FCLK (MHz) FCLK (MHz) Figure 36. AD9861-50 ADC_AVDD Current vs. Sampling Rate for Figure 39. AD9861-80 ADC_AVDD Current vs. ADC Sampling Rate for Different ADC Power Levels Different ADC Power Levels Rev. A | Page 15 of 51

AD9861 Data Sheet 0 0 –10 –10 –20 –20 –30 –30 Bc) –40 Bc) –40 d d E ( –50 E ( –50 D D U U T –60 T –60 LI LI P P M –70 M –70 A A –80 –80 –90 –90 ––110100 03606-0-068 ––110100 03606-0-069 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 40. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path Figure 43. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 33 Ω Differential Load with 20 mA Full-Scale Output into 33 Ω Differential Load 0 0 –10 –10 –20 –20 –30 –30 Bc) –40 Bc) –40 d d E ( –50 E ( –50 D D U U T –60 T –60 LI LI P P M –70 M –70 A A –80 –80 –90 –90 ––110100 03606-0-070 ––110100 03606-0-071 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 41. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path Figure 44. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 60 Ω Differential Load with 20 mA Full-Scale Output into 60 Ω Differential Load 0 0 –10 –10 –20 –20 –30 –30 Bc) –40 Bc) –40 d d E ( –50 E ( –50 D D U U T –60 T –60 LI LI P P M –70 M –70 A A –80 –80 –90 –90 ––110100 03606-0-072 ––110100 03606-0-073 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 42. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path Figure 45. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 2 mA Full-Scale Output into 600 Ω Differential Load with 2 mA Full-Scale Output into 600 Ω Differential Load Rev. A | Page 16 of 51

Data Sheet AD9861 –50 –50 –60 –60 –70 –70 c) c) B B d d D ( D ( H H T –80 T –80 –90 –90 –100 03606-0-074 –100 03606-0-075 0 5 10 15 20 25 0 5 10 15 20 25 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) Figure 46. AD9861 Tx Path THD vs. Output Frequency of Tx Path with Figure 49. AD9861 Tx Path THD vs. Output Frequency of Tx Path 20 mA Full-Scale Output into 60 Ω Differential Load with 2 mA Full-Scale Output into 600 Ω Differential Load 62 62 61 61 60 60 c) c) B B d d D ( 59 D ( 59 A A N N SI SI 58 58 57 57 56 03606-0-076 56 03606-0-077 0 5 10 15 20 25 0 5 10 15 20 25 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) Figure 47. AD9861 Tx Path SINAD vs. Output Frequency of Tx Path, with Figure 50. AD9861 Tx Path SINAD vs. Output Frequency of Tx Path, with 20 mA Full-Scale Output into 60 Ω Differential Load 2 mA Full-Scale Output into 600 Ω Differential Load –70 –70 –75 –75 –80 –80 c) c) B B d d D ( D ( M M I –85 I –85 –90 –90 –95 03606-0-078 –95 03606-0-079 0 5 10 15 20 25 0 5 10 15 20 25 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) Figure 48. AD9861 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs. Figure 51. AD9861 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs. Output Frequency of Tx Path, with Output Frequency of Tx Path, with 20 mA Full-Scale Output into 60 Ω Differential Load 2 mA Full-Scale Output into 600 Ω Differential Load Rev. A | Page 17 of 51

AD9861 Data Sheet Figure 52 to Figure 57 use the same input data to the Tx path, a 64-carrier OFDM signal over a 20 MHz bandwidth, centered at 20 MHz. The center two carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output. –30 –30 –40 –40 –50 –50 –60 –60 c) c) B B d –70 d –70 E ( E ( UD –80 UD –80 T T PLI –90 PLI –90 M M A A –100 –100 –110 –110 ––113200 03606-0-080 ––113200 03606-0-081 7.5 12.5 17.5 22.5 27.5 32.5 18.75 19.25 19.75 20.25 20.75 21.25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 52. AD9861 Tx Path FFT, 64-Carrier (Center Two Carriers Removed) Figure 55. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal over 20 MHz Bandwidth, Centered at 20 MHz, with OFDM Signal in Figure 52 20 mA Full-Scale Output into 60 Ω Differential Load –30 –30 –40 –40 –50 –50 –60 –60 c) c) B B d –70 d –70 E ( E ( UD –80 UD –80 T T PLI –90 PLI –90 M M A A –100 –100 –110 –110 ––113200 03606-0-082 ––113200 03606-0-083 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 53. AD9861 Tx Path FFT, Lower-Band IMD Products of Figure 56. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 52 OFDM Signal in Figure 52 –30 –30 –40 –40 –50 –50 –60 –60 c) c) B B d –70 d –70 E ( E ( UD –80 UD –80 T T PLI –90 PLI –90 M M A A –100 –100 –110 –110 ––113200 03606-0-084 ––113200 03606-0-085 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) FREQUENCY (MHz) Figure 54. AD9861 Tx Path FFT of OFDM Signal in Figure 52, Figure 57. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 1× Interpolation with 4× Interpolation Rev. A | Page 18 of 51

Data Sheet AD9861 Figure 58 to Figure 63 use the same input data to the Tx path, a 256-carrier OFDM signal over a 1.75 MHz bandwidth, centered at 7 MHz. The center four carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output. –40 –40 –50 –50 –60 –60 –70 –70 c) c) B B d –80 d –80 E ( E ( UD –90 UD –90 T T PLI–100 PLI–100 M M A A –110 –110 –120 –120 ––113400 03606-0-086 ––113400 03606-0-087 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 6.97 6.98 6.99 7.00 7.01 7.02 7.03 FREQUENCY (MHz) FREQUENCY (MHz) Figure 58. AD9861 Tx Path FFT, 256-Carrier (Center Four Carriers Removed) Figure 61. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal over 1.75 MHz Bandwidth, Centered at 7 MHz, with OFDM Signal in Figure 58 20 mA Full-Scale Output into 60 Ω Differential Load –40 –40 –50 –50 –60 –60 –70 –70 c) c) B B d –80 d –80 E ( E ( UD –90 UD –90 T T PLI–100 PLI–100 M M A A –110 –110 –120 –120 ––113400 03606-0-088 ––113400 03606-0-089 6.06 6.08 6.10 6.12 6.14 6.16 6.18 7.81 7.83 7.85 7.87 7.89 7.91 7.93 FREQUENCY (MHz) FREQUENCY (MHz) Figure 59. AD9861 Tx Path FFT, Lower-Band IMD Products of Figure 62. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 58 OFDM Signal in Figure 52 –30 –30 –40 –40 –50 –50 –60 –60 c) c) dB –70 dB –70 E ( E ( UD –80 UD –80 T T PLI –90 PLI –90 M M A A –100 –100 –110 –110 ––113200 03606-0-090 ––113200 03606-0-091 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 60. AD9861 Tx Path FFT of OFDM Signal in Figure 52, Figure 63. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 1× Interpolation with 4× Interpolation Rev. A | Page 19 of 51

AD9861 Data Sheet Figure 64 to Figure 69 use the same input data to the Tx path, a 256-carrier OFDM signal over a 23 MHz bandwidth, centered at 23 MHz. The center four carriers are removed from the signal to observe the in-band intermodulation distortion (IMD) from the DAC output. –40 –40 –50 –50 –60 –60 –70 –70 c) c) B B d –80 d –80 E ( E ( UD –90 UD –90 T T PLI–100 PLI–100 M M A A –110 –110 –120 –120 ––113400 03606-0-092 ––113400 03606-0-093 9 14 19 24 29 34 22.6 22.7 22.8 22.9 23.0 23.1 23.2 23.3 23.4 FREQUENCY (MHz) FREQUENCY (MHz) Figure 64. AD9861 Tx Path FFT, 256-Carrier (Center Four Carriers Removed) Figure 67. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal over 23 MHz Bandwidth, Centered at 7 MHz, with OFDM Signal in Figure 64 20 mA Full-Scale Output into 60 Ω Differential Load –40 –40 –50 –50 –60 –60 –70 –70 c) c) B B d –80 d –80 E ( E ( UD –90 UD –90 T T PLI–100 PLI–100 M M A A –110 –110 –120 –120 ––113400 03606-0-094 ––113400 03606-0-095 10.5 10.7 10.9 11.1 11.3 11.5 11.7 11.9 12.1 12.3 12.5 33.5 33.7 33.9 34.1 34.3 34.5 34.7 34.9 35.1 35.3 35.5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 65. AD9861 Tx Path FFT, Lower-Band IMD Products of Figure 68. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 64 OFDM Signal in Figure 64 –30 –30 –40 –40 –50 –50 –60 –60 c) c) B B d –70 d –70 E ( E ( UD –80 UD –80 T T PLI –90 PLI –90 M M A A –100 –100 –110 –110 ––113200 03606-0-096 ––113200 03606-0-097 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 FREQUENCY (MHz) FREQUENCY (MHz) Figure 66. AD9861 Tx Path FFT of OFDM Signal in Figure 52 Figure 69. AD9861 Tx Path FFT of OFDM Signal in Figure 52 with 1× Interpolation with 4× Interpolation Rev. A | Page 20 of 51

Data Sheet AD9861 TERMINOLOGY Input Bandwidth Harmonic Distortion, Second The analog input frequency at which the spectral power of the The ratio of the rms signal amplitude to the rms value of the fundamental frequency (as determined by the FFT analysis) is second harmonic component, reported in dBc. reduced by 3 dB. Harmonic Distortion, Third Aperture Delay The ratio of the rms signal amplitude to the rms value of the The delay between the 50% point of the rising edge of the CLKIN third harmonic component, reported in dBc. signal and the instant at which the analog input is actually sampled. Integral Nonlinearity Aperture Uncertainty (Jitter) The deviation of the transfer function from a reference line The sample-to-sample variation in aperture delay. measured in fractions of an LSB using a “best straight line” determined by a least square curve fit. Crosstalk Coupling onto one channel being driven by a –0.5 dBFS signal when Minimum Conversion Rate the adjacent interfering channel is driven by a full-scale signal. The encode rate at which the SNR of the lowest analog signal Differential Analog Input Voltage Range frequency drops by no more than 3 dB below the guaranteed The peak-to-peak differential voltage that must be applied to the limit. converter to generate a full-scale response. Peak differential voltage Maximum Conversion Rate is computed by observing the voltage on a single pin and subtracting The encode rate at which parametric testing is performed. the voltage from the other pin, which is 180° out of phase. Peak-to- Output Propagation Delay peak differential is computed by rotating the input phase 180° and The delay between a differential crossing of CLK+ and CLK− taking the peak measurement again. Then the difference is and the time when all output data bits are within valid logic computed between both peak measurements. levels. Differential Nonlinearity Power Supply Rejection Ratio The deviation of any code width from an ideal 1 LSB step. The ratio of a change in input offset voltage to a change in Effective Number of Bits (ENOB) power supply voltage. The effective number of bits is calculated from the measured SNR Signal-to-Noise and Distortion (SINAD) based on the following equation: The ratio of the rms signal amplitude (set 1 dB below full-scale) SNR −1.76dB ENOB= MEASURED to the rms value of the sum of all other spectral components, 6.02 including harmonics, but excluding dc. Pulse Width/Duty Cycle Signal-to-Noise Ratio (without Harmonics) Pulse width high is the minimum amount of time that a signal must The ratio of the rms signal amplitude (set at 1 dB below full be left in the logic high state to achieve rated performance; pulse scale) to the rms value of the sum of all other spectral width low is the minimum time a signal must be left in the low state, components, excluding the first five harmonics and dc. logic low. Spurious-Free Dynamic Range (SFDR) Full-Scale Input Power The ratio of the rms signal amplitude to the rms value of the Expressed in dBm, full-scale input power is computed using the peak spurious spectral component. The peak spurious following equation: component may or may not be a harmonic. It also may be V2 Z  reported in dBc (i.e., degrades as signal level is lowered) or PowerFULLSCALE =10log FULLSCALE−RMS INPUT  dBFS (i.e., always related back to converter full scale). SFDR  0.001  does not include harmonic distortion components. Gain Error Worst Other Spur Gain error is the difference between the measured and ideal full- The ratio of the rms signal amplitude to the rms value of the scale input voltage range of the ADC. worst spurious component (excluding the second and third harmonics) reported in dBc. Rev. A | Page 21 of 51

AD9861 Data Sheet THEORY OF OPERATION SYSTEM BLOCK The differential input stage is dc self-biased and allows differential or single-ended inputs. The output-staging block The AD9861 is targeted to cover the mixed-signal front end needs of aligns the data, carries out the error correction, and passes the multiple wireless communication systems. It features a receive path data to the output buffers. that consists of dual 10-bit receive ADCs, and a transmit path that consists of dual 10-bit transmit DACs (TxDAC). The AD9861 The latency of the Rx path is about 5 clock cycles. integrates additional functionality typically required in most Rx Path Analog Input Equivalent Circuit systems, such as power scalability, additional auxiliary converters, Tx The Rx path analog inputs of the AD9861 incorporate a novel gain control, and clock multiplication circuitry. structure that merges the function of the input sample-and-hold The AD9861 minimizes both size and power consumption to amplifiers (SHAs) and the first pipeline residue amplifiers into a address the needs of a range of applications from the low power single, compact switched capacitor circuit. This structure portable market to the high performance base station market. The achieves considerable noise and power savings over a conven- part is provided in a 64-lead lead frame chip scale package (LFCSP) tional implementation that uses separate amplifiers by eliminating that has a footprint of only 9 mm × 9 mm. Power consumption can one amplifier in the pipeline. be optimized to suit the particular application beyond just a speed Figure 70 illustrates the equivalent analog inputs of the AD9861 grade option by incorporating power-down controls, low power (a switched capacitor input). Bringing CLK to logic high opens ADC modes, TxDAC power scaling, and a half-duplex mode, which switch S3 and closes switches S1 and S2; this is the sample mode automatically disables the unused digital path. of the input circuit. The input source connected to VIN+ and The AD9861 uses two 10-bit buses to transfer Rx path data and Tx VIN− must charge capacitor C during this time. Bringing CLK H path data. These two buses support 20-bit parallel data transfers or to a logic low opens S2, and then switch S1 opens followed by 10-bit interleaved data transfers. The bus is configurable through closing S3. This puts the input circuit into hold mode. either external mode pins or through internal registers settings. The registers allow many more options for configuring the entire device. S1 CH VIN+ + The following sections discuss the various blocks of the AD9861: Rx RIN CIN block, Tx block, the auxiliary converters, the digital block, VCM S3 S2 RIN CH programmable registers and the clock distribution block. VIN– – Rx PATH BLOCK CIN Rx Path General Description 03606-0-002 Figure 70. Differential Input Architecture The AD9861 Rx path consists of two 10-bit, 50 MSPS (for the The structure of the input SHA places certain requirements on AD9861-50) or 80 MSPS (for the AD9861-80) analog-to-digital the input drive source. The differential input resistors are converters (ADCs). The dual ADC paths share the same clocking typically 2 kΩ each. The combination of the pin capacitance, and reference circuitry to provide optimal matching characteristics. C , and the hold capacitance, C , is typically less than 5 pF. The Each of the ADCs consists of a 9-stage differential pipelined IN H input source must be able to charge or discharge this capaci- switched capacitor architecture with output error correction logic. tance to 10-bit accuracy in one-half of a clock cycle. When the The pipelined architecture permits the first stage to operate on a new SHA goes into sample mode, the input source must charge or input sample, while the remaining stages operate on preceding discharge capacitor C from the voltage already stored on it to H samples. Sampling occurs on the falling edge of the input clock. Each the new voltage. In the worst case, a full-scale voltage step on stage of the pipeline, excluding the last, consists of a low resolution the input source must provide the charging current through the flash ADC and a residual multiplier to drive the next stage of the R of switch S1 (typically 100 Ω) to a settled voltage within ON pipeline. The residual multiplier uses the flash ADC output to one-half of the ADC sample period. This situation corresponds control a switched capacitor digital-to-analog converter (DAC) of to driving a low input impedance. On the other hand, when the the same resolution. The DAC output is subtracted from the stage’s source voltage equals the value previously stored on C , the H input signal, and the residual is amplified (multiplied) to drive the hold capacitor requires no input current and the equivalent next pipeline stage. The residual multiplier stage is also called a input impedance is extremely high. multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Rev. A | Page 22 of 51

Data Sheet AD9861 Rx Path Application Section REFT = AVDD/2 + 0.5 V REFB = AVDD/2 – 0.5 V Adding series resistance between the output of the signal source and the VIN pins reduces the drive requirements placed on the signal AD9861 source. Figure 71 shows this configuration. REFT AD9861 0.1µF TO ADCs 0.1µF RSERIES REFB 10µF VIN+ CSHUNT 0.1µF VREF VIN– RSERIES 10µF 0.1µF 0.5V 03606-0-003 Figure 71. Typical Input The bandwidth of the particular application limits the size of this resistor. For applications with signal bandwidths less than 10 MHz, 03606-0-020 the user may insert series input resistors and a shunt capacitor to Figure 72. Typical Rx Path Decoupling produce a low-pass filter for the input signal. Additionally, adding a An external reference may be used for systems that require a shunt capacitance between the VIN pins can lower the ac load different input voltage range, high accuracy gain matching impedance. The value of this capacitance depends on the source between multiple devices, or improvements in temperature drift resistance and the required signal bandwidth. and noise characteristics. When an external reference is desired, The Rx input pins are self-biased to provide this midsupply, the internal Rx band gap reference must be powered down common-mode bias voltage, so it is recommended to ac couple the using the VREF2 register [Register 0x5, Bit 4] and the external signal to the inputs using dc blocking capacitors. In systems that reference driving the voltage level on the VREF pin. The must use dc coupling, use an op amp to comply with the input external voltage level must be one-half of the desired peak-to- requirements of the AD9861. The inputs accept a signal with a 2 V peak differential voltage swing. The result is that the differential p-p differential input swing centered about one-half of the supply voltage references are driven to new voltages: voltage (AVDD/2). If the dc bias is supplied externally, the internal REFT = AVDD/2 +V /2 V REF input bias circuit must be powered down by writing to registers REFB = AVDD/2 – V /2 V REF Rx_A dc bias [Register 0x3, Bit 6] and Rx_B dc bias [Register 0x4, If an external reference is used, it is recommended not to exceed Bit 7]. a differential offset voltage for the reference greater than 1 V. The ADCs in the AD9861 are designed to sample differential input Clock Input and Considerations signals. The differential input provides improved noise immunity and better THD and SFDR performance for the Rx path. In systems Typical high speed ADCs use both clock edges to generate a that use single-ended signals, these inputs can be digitized, but it is variety of internal timing signals and, as a result, may be recommended that a single-ended-to-differential conversion be sensitive to clock duty cycle. Commonly, a 5% tolerance is performed. A single-ended-to-differential conversion can be required on the clock duty cycle to maintain dynamic perform- performed by using a transformer coupling circuit (typically for ance characteristics. The AD9861 contains clock duty cycle signals above 10 MHz) or by using an operational amplifier, such as stabilizer circuitry (DCS). The DCS retimes the internal ADC the AD8138 (typically for signals below 10 MHz). clock (nonsampling edge) and provides the ADC with a nominal 50% duty cycle. Input clock rates of over 40 MHz can ADC Voltage References use the DCS so that a wide range of input clock duty cycles can be The AD9861 10-bit ADCs use internal references that are designed accommodated. Conversely, DCS must not be used for Rx to provide for a 2 V p-p differential input range. The internal band sampling below 40 MSPS. Maintaining a 50% duty cycle clock is gap reference generates a stable 1 V reference level and is decoupled particularly important in high speed applications when proper through the VREF pin. REFT and REFB are the differential sample-and-hold times for the converter are required to references generated based on the voltage level of VREF. Figure 72 maintain high performance. The DCS can be enabled by shows the proper decoupling of the reference pins VREF, REFT, and writing highs to the Rx_A/Rx_B CLK duty register bits REFB when using the internal reference. Decoupling capacitors must [Register 0x06/0x07, Bit 4]. be placed as close to the reference pins as possible. The duty cycle stabilizer uses a delay-locked loop to create the External references REFT and REFB are centered at AVDD/2 with a nonsampling edge. As a result, any changes to the sampling differential voltage equal to the voltage at VREF (by default 1 V frequency require approximately 2 µs to 3 µs to allow the DLL when using the internal reference), allowing a peak-to-peak to adjust to the new rate and settle. High speed, high resolution differential voltage swing of 2× VREF. For example, the default 1 V ADCs are sensitive to the quality of the clock input. VREF reference accepts a 2 V p-p differential input swing and the offset voltage must be Rev. A | Page 23 of 51

AD9861 Data Sheet The degradation in SNR at a given full-scale input frequency (f ), When either or both of the channel paths are enabled after a INPUT due only to aperture jitter (t ), can be calculated with the following power-down, the wake-up time is directly related to the A equation: recharging of the REFT and REFB decoupling capacitors and the duration of the power-down. Typically, it takes approxi- SNR degradation = 20 log [(½)πF t )] INA mately 5 ms to restore full operation with fully discharged 0.1 µF In the equation, the rms aperture jitter, t , represents the root-sum- A and 10 µF decoupling capacitors on REFT and REFB. square of all jitter sources, which includes the clock input, analog Tx PATH BLOCK input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input is a The AD9861 transmit (Tx) path includes dual interpolating digital signal that must be treated as an analog signal with logic level 10-bit current output DACs that can be operated independently threshold voltages, especially in cases where aperture jitter may or can be coupled to form a complex spectrum in an image affect the dynamic range of the AD9861. Power supplies for clock reject transmit architecture. Each channel includes two FIR drivers must be separated from the ADC output driver supplies to filters, making the AD9861 capable of 1×, 2×, or 4× interpola- avoid modulating the clock signal with digital noise. Low jitter tion. High speed input and output data rates can be achieved crystal-controlled oscillators make the best clock sources. If the within the limitations of Table 9. clock is generated from another type of source (by gating, dividing, Table 9. AD9861 Tx Path Maximum Data Rate or other methods), it must be retimed by the original clock at the last Input Data DAC step. Rate per Sampling Power Dissipation and Standby Mode Interpolation 20-Bit Interface Channel Rate Rate Mode (MSPS) (MSPS) The power dissipation of the AD9861 Rx path is proportional to its FD, HD10, Clone 80 80 sampling rate. The Rx path portion of the digital (DRVDD) power 1× HD20 160 160 dissipation is determined primarily by the strength of the digital FD, HD10, Clone 80 160 drivers and the load on each output bit. The digital drive current can 2× HD20 80 160 be calculated by FD, HD10, Clone 50 200 I = V × C × f × N 4× DRVDD DRVDD LOAD CLOCK HD20 50 200 where N is the number of bits changing and C is the average load LOAD By using the dual DAC outputs to form a complex signal, an on the digital pins that changed. external analog quadrature modulator, such as the Analog The analog circuitry is optimally biased so that each speed grade Devices AD8349, can enable an image rejection architecture. provides excellent performance while affording reduced power (Note: the AD9861 evaluation board includes a quadrature consumption. Each speed grade dissipates a baseline power at low modulator in the Tx path that accommodates the AD8345, sample rates, which increases with clock frequency. The baseline AD8346 and the AD8345 footprints.) To optimize the image power dissipation for either speed grade can be reduced by asserting rejection capability, as well as LO feedthrough suppression in the ADC_LO_PWR pin, which reduces internal ADC bias currents this architecture, the AD9861 offers programmable (via the SPI by half, in some case resulting in degraded performance. port) fine (trim) gain and offset adjustment for each DAC. To further reduce power consumption of the ADC, the Also included in the AD9861 are a phase-locked loop (PLL) ADC_LO_PWR pin can be combined with a serial programmable clock multiplier and a 1.2 V band gap voltage reference. With register setting to configure an ultralow power mode. The ultralow the PLL enabled, a clock applied to the CLKIN input is multi- power mode reduces the power consumption by a fourth of the plied internally and generates all necessary internal synchronization normal power consumption. The ultralow power mode can be used clocks. Each 10-bit DAC provides two complementary current at slower sampling frequencies or if reduced performance is outputs whose full-scale currents can be determined from a acceptable. To configure the ultralow power mode, assert the single external resistor. ADC_LO_PWR pin and write the following register settings: An external pin, TxPWRDWN, can be used to power down the Register 0x08 (MSB) ‘0000 1100’ Tx path, when not used, to optimize system power consumption. Register 0x09 (MSB) ‘0111 0000’ Using the TxPWRDWN pin disables clocks and some analog Register 0x0A (MSB) ‘0111 0000’ circuitry, saving both digital and analog power. The power-down mode leaves the biases enabled to facilitate a quick recovery Either of the ADCs in the AD9861 Rx path can be placed in standby time, typically <10 µs. Additionally, a sleep mode is available, mode independently by writing to the appropriate SPI register bits in which turns off the DAC output current, but leaves all other Registers 3, 4, and 5. The minimum standby power is achieved when circuits active, for a modest power savings. An SPI compliant both channels are placed in full power-down mode using the serial port is used to program the many features of the AD9861. appropriate SPI register bits in Registers 3, 4, and 5. Under this Note that in power-down mode, the SPI port is still active. condition, the internal references are powered down. Rev. A | Page 24 of 51

Data Sheet AD9861 DAC Equivalent Circuits 1.2V REFERENCE DAC A AND DAC B The AD9861 Tx path consisting of dual 10-bit DACs is shown in REFERENCE BIASES Figure 73. The DACs integrate a high performance TxDAC core, a IOUTFSMAX programmable gain control through a programmable gain amplifier REFIO CURRENT (TxPGA), coarse gain control, and offset adjustment and fine gain SOURCE ARRAY control to compensate for system mismatches. Coarse gain applies a FSADJ IREF gross scaling to either DAC by 1×, (1/2)×, or (1/11)×. The TxPGA provides gain control from 0 dB to 0.1µF RSET≥ 4kΩ –20 dB in steps of 0.1 dB and is controlled via the 8-bit TxPGA 03606-0-005 Figure 74. Reference Circuitry setting. A fine gain adjustment of ±4% for each channel is controlled through a 6-bit fine gain register. By default, coarse gain is 1×, the Referring to the transfer function of the following equation, TxPGA is set to 0 dB, and the fine gain is set to 0%. I is the maximum current output of the DAC with the OUTFSMAX The TxDAC core of the AD9861 provides dual, differential, default gain setting (0 dB), and is based on a reference current, complementary current outputs generated from the 10-bit data. The IREF. IREF is set by the internal 1.2 V reference and the external 10-bit dual DACs support update rates up to 200 MSPS. The RSET resistor. differential outputs (IOUT+ and IOUT–) of each dual DAC are I = 64 × (REFIO/R ) OUTFSMAX SET complementary, meaning that they always add up to the full-scale Typically, R is 4 kΩ, which sets I to 20 mA, the SET OUTFSMAX current output of the DAC, I . Optimum ac performance loads or OUTFS optimal dynamic setting for the TxDACs. Increasing R by a SET a transformer. factor of 2 proportionally decreases I by a factor of 2. OUTFSMAX I of each DAC can be rescaled either simultaneously OFFSET OUTFSMAX DAC using the TxPGA gain register or independently using the + DAC A/DAC B coarse gain registers. IOUT+A + TxDAC PGA + The TxPGA function provides 20 dB of simultaneous gain IOUT–A + range for both DACs, and is controlled by writing to the SPI register TxPGA gain for a programmable full-scale output of REFERENCE 10% to 100% of IOUTFSMAX. The gain curve is linear in dB, with BIAS steps of about 0.1 dB. Internally, the gain is controlled by changing the main DAC bias currents with an internal TxPGA + IOUT+B DAC whose output is heavily filtered via an on-chip R-C filter TxDAC PGA + + IOUT–B to provide continuous gain transitions. Note that the settling + time and bandwidth of the TxPGA DAC can be improved by a factor of 2 by writing to the TxPGA fast register. OFFSET DAC 03606-0-004 Each DAC has independent coarse gain control. Coarse gain Figure 73. TxDAC Output Structure Block Diagram control can be used to accommodate different IOUTFS from the dual DACs. The coarse full-scale output control can be adjusted The fine gain control provides improved balance of QAM modulated by using the DAC A/DAC B coarse gain registers to 1/2 or 1/11 signals, resulting in improved modulation accuracy and image of the nominal full-scale current. rejection. Fine gain controls and dc offset controls can be used to The independent DAC A and DAC B offset control adds a small dc compensate for mismatches (for system level calibration), current to either IOUT+ or IOUT– (not both). The selection of allowing improved matching characteristics of the two Tx which IOUT this offset current is directed toward is programmable channels and aiding in suppressing LO feedthrough. This is via register setting. Offset control can be used for suppression of an especially useful in image rejection architectures. The 10-bit dc LO leakage signal that typically results at the output of the offset control of each DAC can be used independently to modulator. If the AD9861 is dc-coupled to an external modulator, provide an offset of up to ±12% of I to either differential OUTFSMAX this feature can be used to cancel the output offset on the AD9861 as pin, thus allowing calibration of any system offsets. The fine well as the input offset on the modulator. The reference circuitry is gain control with 5-bit resolution allows the I of each OUTFSMAX shown in Figure 74. DAC to be varied over a ±4% range, allowing compensation of any DAC or system gain mismatches. Fine gain control is set through the DAC A/DAC B fine gain registers, and the offset control of each DAC is accomplished using the DAC A/DAC B offset registers. Rev. A | Page 25 of 51

AD9861 Data Sheet Clock Input Configuration The sleep mode, when activated, turns off the DAC output currents, but the rest of the chip remains functioning. When The quality of the clock and data input signals is important in coming out of sleep mode, the AD9861 immediately returns to achieving optimum performance. The external clock driver circuitry full operation. provides the AD9861 with a low jitter clock input that meets the min/max logic levels while providing fast edges. When a driver is A full power-down mode can be enabled through the SPI used to buffer the clock input, it must be placed very close to the register, which turns off all Tx path related analog and digital AD9861 clock input, thereby negating any transmission line effects circuitry in the AD9861. When returning from full power- such as reflections due to mismatch. down mode, enough clock cycles must be allowed to flush the Programmable PLL digital filters of random data acquired during the power-down cycle. CLKIN can function either as an input data rate clock (PLL enabled) Interpolation Stage or as a DAC data rate clock (PLL disabled). Interpolation filters are available for use in the AD9861 transmit The PLL clock multiplier and distribution circuitry produce the path, providing 1× (bypassed), 2×, or 4× interpolation. necessary internal timing to synchronize the rising edge triggered latches for the enabled interpolation filters and DACs. This circuitry The interpolation filters effectively increase the Tx data rate consists of a phase detector, charge pump, voltage controlled while suppressing the original images. The interpolation filters oscillator (VCO), and clock distribution block, all under SPI port digitally shift the worst-case image further away from the control. The charge pump, phase detector, and VCO are powered desired signal, thus reducing the requirements on the analog from PLL_AVDD, while the clock distribution circuits are powered output reconstruction filter. from the DVDD supply. There are two 2× interpolation filters available in the Tx path. To ensure optimum phase noise performance from the PLL clock An interpolation rate of 4× is achieved using both interpolation multiplier circuits, PLL_AVDD must originate from a clean analog filters; an interpolation rate of 2× is achieved by enabling only supply. The speed of the VCO within the PLL also has an effect on the first 2× interpolation filter. phase noise. The first interpolation filter provides 2× interpolation using a The PLL locks with VCO speeds as low as 32 MHz up to 350 MHz, 39-tap filter. It suppresses out-of-band signals by 60 dB or more but optimal phase noise with respect to VCO speed is achieved by and has a flat pass-band response (less than 0.1 dB ripple) running it in the range of 64 MHz to 200 MHz. extending to 38% of the input Tx data rate (19% of the DAC Power Dissipation update rate, fDAC). The maximum input data rate is 80 MSPS per channel when using 2× interpolation. The AD9861 Tx path power is derived from three voltage supplies: AVDD, DVDD, and DRVDD. The second interpolation filter provides an additional 2× interpola- tion for an overall 4× interpolation. The second filter is a 15-tap IDRVDD and IDVDD are very dependent on the input data rate, the filter, which suppresses out-of-band signals by 60 dB or more. interpolation rate, and the activation of the internal digital modulator. IAVDD has the same type of sensitivity to data, The flat pass-band response (less than 0.1 dB attenuation) is interpolation rate, and the modulator function, but to a much lesser 38% of the Tx input data rate (9.5% of fDAC). The maximum degree (< 10%). input data rate per channel is 50 MSPS per channel when using 4× interpolation. Sleep/Power-Down Modes Latch/Demultiplexer The AD9861 provides multiple methods for programming power saving modes. The externally controlled TxPWRDWN or SPI Data for the dual-channel Tx path can be latched in parallel programmed sleep mode and full power-down mode are the main through two ports in half-duplex operations (HD20 mode) or options. through a single port by interleaving the data (FD, HD10, and Clone modes). See the Flexible I/O Interface Options section in TxPWRDWN is used to disable all clocks and much of the analog the Digital Block description and the Clock Distribution Block circuitry in the Tx path when asserted. In this mode, the biases section for further descriptions of each mode. remain active, therefore reducing the time required for re-enabling the Tx path. The time of recovery from power-down for this mode is typically less than 10 µs. Rev. A | Page 26 of 51

Data Sheet AD9861 AUXILIARY CONVERTERS Another synchronization mode allows any combination of AuxDACs to be updated along with an externally applied rising The AD9861 contains auxiliary analog-to-digital converters edge to the TxPwrDwn pin. (AuxADCs) and auxiliary digital-to-analog converters (AuxDACs). These auxiliary converters can be used to measure or force system- Typical settling time for the AuxDAC output is less than 0.5 µs, wide control signals. but is dependent on the load. By default, the auxiliary converters are disabled and powered down. Auxiliary ADCs Enabling and controlling the auxiliary converters is achieved Two auxiliary 10-bit SAR analog-to-digital converters through the serial programmable registers. (AuxADCs) are available for monitoring various external Pins 29, 30, and 46 are configurable either as AuxDAC outputs or as signals throughout the system, such as a receive signal strength AuxADC inputs. The respective AuxADC inputs are connected to indicator (RSSI) function or temperature indicator. The the external pin when a conversion is initiated and are disconnected AuxADCs have many SPI programmable options. Register when the conversion is complete. The AuxDAC outputs are enabled settings can be used to configure various full-scale reference by writing to the respective power-up registers in Register 0x29. options, change the sampling rate, and average multiple sample readings. By default, the AuxADC start conversion and output • Pin 29 can be connected to AuxDAC_A and/or AuxADC_A value is accessed through the register map. Additionally an Channel 2. auxiliary serial port can be enabled and used to initiate a • Pin 30 can be connected to AuxDAC_B and/or AuxADC_A conversion and read back the AuxADC data. The auxiliary Channel 1. serial port interface is available so that the normal SPI can be • Pin 46 can be connected to AuxDAC_C and/or AuxADC_B. used to program other options while the AuxADC is accessed. Auxiliary DACs By default, the AuxADCs are powered down and automatically powered up when a conversion is initiated. The AD9861 integrates three 8-bit voltage output auxiliary digital- to-analog converters (AuxDACs), which can be used for supplying The two AuxADCs (AuxADC_A and AuxADC_B) can monitor various control voltages throughout the system such as a VCXO up to three system signals. AuxADC_A has multiplexed inputs voltage control or external VGA gain control. The AuxDACs have a that control whether pin AUX_ADC_A1 or pin AUX_ADC_A2 programmable full-scale output voltage, V , and can be is connected to the input of AuxADC_A. The multiplexer is OUTFS synchronized to update with a single register write or a rising edge programmed through Register 0x22, Bit 1, SelectA. By default, on the TxPwrDwn pin. the register is low, which connects the AUX_ADC_A2 pin to the input. By default, the AuxDAC outputs are powered down and require a serial write to the power-up registers [Register 0x29, Bits 2–0] to The full-scale AuxADC reference can be generated from the enable them. analog supply (supply dependent), an internal reference, or from an external applied reference. Table 10 shows the register The full-scale output of each AuxDAC is independently settings required to select the AuxADC full-scale reference. programmable to the full scales of 2.5 V, 2.7 V, 3.0 V, or 3.3 V by using Serial Register 0x17. The AuxDAC outputs have an I-to-V By default, an internal reference provides a buffered full-scale driver that produces a voltage output that settles to ±1 LSB within 0.5 reference for both of the AuxADCs, which is equal to the supply µs. The output driver is capable of sinking or sourcing up to 6 mA. voltage for the AuxADCs (PLL_AVDD). A supply independent Using the AuxDAC requires the SPI to be operational. 2.5 V or 3.0 V internal full-scale reference can be enabled by writing to register AuxADC Ref Enable and AuxADC Ref FS in The AuxDACs are based on a resistor divider network. The Register 0x17. This internal reference is based on the main Rx AuxDACs output level is proportional to the straight binary input path ADC VREF voltage, so it requires the main Rx path VREF codes from the appropriate SPI registers, Registers 0x24 to 0x26. By to be enabled. default, the AuxDAC output is updated immediately following the register write, but the update can occur synchronously to a single Another AuxADC full-scale reference option is an externally register write or to the TxPwrDwn rising edge. supplied full-scale reference. The external reference can be applied to either or both of the AuxADCs by setting the In slave mode, the AuxDAC update occurs when a logic high is appropriate bit(s) in Registers 0x22 and 0x17. Setting either or written to the appropriate update registers [Register 0x28, Bits 2–0, both of these bits high disconnects the internal reference buffer Update C, B, and A]. Slave mode is enabled by writing a high to the and enables the externally applied reference from the slave mode register bit [Register 0x28, Bit 7, Slave Enable]. AuxADC_Ref pin to the respective channel(s). Rev. A | Page 27 of 51

AD9861 Data Sheet Table 10. Configuring AuxADC Reference Refsel A/B AuxADC_A Reference AuxADC Ref Enable AuxADC Ref FS [Register 0x22, Configuration [Register 0x17, Bit 1] [Register 0x17, Bit 0] Bit 2/Bit 5] Notes Buffered PLL_VDD 0 0 0 Default mode. Internal 3.0 V (3 x VREF) 1 0 1 Decouple at AUXADC_REF pin. VREF voltage from Rx path. Internal 2.5 V (2.5 x VREF) 1 1 1 Decouple at AUXADC_REF pin. Externally forced 0 Don't Care 1 Force and decouple at AUXADC_REF pin. The AuxADCs can convert at rates of up to 5.33 MSPS (0.1875 µs The AuxSPI can be enabled and configured by setting register maximum conversion time) and have a bandwidth of around 200 AuxSPI enable [Register 0x22, Bit 7]. Also required is that the kHz. The conversion time, including setup, requires 12 clock cycles. normal serial port interface be configured for 3-wire mode (the The maximum clock rate for the AuxADCs is 64 MHz and is SPI_SDO pin must be disabled to use the Aux_SPI_SDO pin) generated from a divided down Rx ADC clock. The divide down by setting the SDIO BiDir register bit [Register 0x00, Bit 7]. ratio is controlled by register AuxADC Clock Div [Register 0x23, Register bit Sel BnotA [Register 0x22, Bit 6] configures whether Bits 1, 0]. By default, the Rx ADC clock is divided by 4. At an Rx AuxADC_A or AuxADC_B is controlled by the AuxSPI. ADC rate greater than 64 MHz, the AuxADC Clock Div register AuxADC_A has two inputs: AuxADC_A1 and AuxADC_A2. must be set to divide-by-2 or divide-by-4. Setting the Select A bit [Register 0x22, Bit 1] determines which of the multiplexed inputs is connected to AuxADC_A. On-chip averaging of 2, 4, 8, 16, 32, or 64 samples can be enabled through Register 0x18 for AuxADC_A or through Register 0x19 for The AuxSPI consists of a chip select pin (AUX_SPI_CS, pin AuxADC_B. When the averaging option is enabled, the AuxADC number 4), a clock pin (AUX_SPI_CLK), and a data output pin continually converts the number of samples specified and outputs (AUX_SPI_SDO multiplex with the SPI_SDO pin). A conversion the average value. is initiated by pulsing the AUX_SPI_CS pin low (AUX_SPI_CS must remain low during the entire conversion cycle, including There are three modes of operating the AuxADC: SPI operation the readback phase). When the conversion is complete, the data mode (default), SPI with external start convert operation mode, and pin, AUX_SPI_SDO, transitions from a logic low to a logic Aux_SPI operation mode. high. At this point, the user supplies an external clock on the In the default SPI operation mode, a conversion is initiated by AUX_SPI_CLK pin. The AUX_SPI_CLK pin must be tied low writing a logic high to one or both of the start register bits, Start A or when not in use. No data is present on the first rising edge. The Start B [Register 0x22, Bit 0 or Bit 3]. If AuxADC is configured as data output bit is updated on the falling edge of the clock pulse averaging mode, the proper start bit is the Start Average AuxADC and is settled by and can be latched on the next clock rising A/B register [Register 0x18, Bit 7/Register 0x19, Bit 7]. edge. The data arrives serially, MSB first. The AuxSPI runs at a When the conversion is complete, the straight binary, 10-bit output rate up to 16 MHz. data of the AuxADC is written to one of three reserved locations in Operation of the Aux_SPI requires that 3-wire SPI mode be the register map, depending on which AuxADC and which used, disabling the SDO pin. If the controller is a 4-wire multiplexed input is selected. Because the AuxADCs output 10 bits, interface, a method of connecting the 3-wire AD9861 interface two register addresses are needed for each data location. to the 4-wire controller is suggested in Figure 75. In the optional SPI with external start convert operation mode, the An example of an AuxSPI access is shown in Figure 75. In the conversion is initiated by asserting AuxSPI_csb, and data retrieval is AuxSPI configuration, a start convert is initiated by applying a accomplished through the SPI interface (data retrieval is similar to rising edge to the Aux_SPI_CS pin. A rising edge on the the default operation). The AuxSPI_csb can be configured to initiate Aux_SPI_DO pin indicates that a conversion is done. Supplying the conversion of either one of the AuxADCs. This mode is a clock to the Aux_SPI_CLK then outputs data on the configured by setting the AuxSPI enable register bit [Register 0x22, Aux_SPI_DO pin, MSB first. Bit 7]. CONTROLLER AD986x An optional auxiliary serial port interface (AuxSPI) can be used to SPI_CS[x] SPI_CS access an AuxADC. The AuxSPI can initiate an AuxADC conversion SPI_CLK SPI_CLK and can be used to retrieve the data. The AuxSPI can be configured SPI_SDIO to allow dedicated control of one of the AuxADCs and is available so SPI_DI that the SPI is not continually busy retrieving AuxADC data. 03606-0-006 Figure 75. Diagram to Connect 3-Wire SPI to a 4-Wire SPI Controller Rev. A | Page 28 of 51

AD9861 Data Sheet Figure 76 shows a timing diagram of the AuxSPI when it is used to control and access an AuxADC. Figure 77 shows the timing for each of the three AuxADC modes of operation. 1 2 3 AUXSPI_CS AUXSPI_CLK AUXSPI_SDO D9D8 D0 1. AUXADC CONVERSION START SIGNAL 2. AUXADC CONVERSION DONE 3. AUXADC OUTPUT UDATE (MSB) 03606-0-021 Figure 76. Timing Diagram of AuxSPI NORMAL SPI READOUT tCONVERSION =tC 16 SPI CLK 16 SPI CLK 16 SPI CLKs USED TO CONFIGURE AND INITIATE A START CONVERSION 16 SPI CLKs USED TO READ BACK 8 REGISTER BITS EXTERNAL START COVERT BIT AND SPI READOUT MODE EXTERNAL PIN USED TO INITIATE A START CONVERSION 16 SPI CLKs USED TO READ BACK 8 REGISTER BITS READOUT MODE WITH AUXILIARY SPI EXTERNAL PIN USED TO INITIATE A START CONVERSION 8-BIT SERIAL OUTPUT READOUT MODE WITH AUXILIARY SPI CYCLE TIME =tC + 8 SPI CLK EXTERNAL START COVERT BIT AND SPI READOUT MODE CYCLE TIME =tC + 16 SPI CLK NORMAL SPI READOUT CYCLE TIME = 16 SPI CLK +tC + 16 SPI CLK 03606-0-007 Figure 77. AuxADC Data Cycle Times for Various Readout Methods Rev. A | Page 29 of 51

AD9861 Data Sheet DIGITAL BLOCK Flexible I/O Interface Options The AD9861 digital block allows the device to be configured in The AD9861 can accommodate various data interface transfer various timing and operation modes. The following sections discuss options (flexible I/O). The AD9861 uses two 10-bit buses, an the flexible I/O interfaces, the clock distribution block, and the upper bus (U10) and a lower bus (L10), to transfer the dual- programming of the device through mode pins or SPI registers. channel 10-bit ADC data and dual-channel 10-bit DAC data by means of interleaved data, parallel data, or a mix of both. Table 11 shows the different I/O configurations of the modes depending on half-duplex or full-duplex operation. Table 12 and Table 13 summarize the pin configurations versus the modes. Table 11. Flexible Data Interface Modes Mode Concurrent Tx + Rx Mode Name Tx Only Mode (Half-Duplex) Rx Only Mode (Half-Duplex) (Full-Duplex) General Notes HD20 AD9861 AD9861 Rx Data Rate Tx_A DATA Rx_A DATA = 1 × ADC Sample U[0:9] L[0:9] Rate Tx_B DATA Rx_B DATA L[0:9] Tx/Rx DIGITAL U[0:9] Tx/Rx DIGITAL Two 10-Bit Parallel Rx Data IFACE1 BACK IFACE1 BACK Buses OUTPUT CLOCK END OUTPUT CLOCK END N/A IFACE2 IFACE2 Tx Data Rate IFACE3 OUTPUT CLOCK IFACE3 OUTPUT CLOCK = 1 × ADC Sample Rate 03606-0-008 03606-0-012 Two 10-Bit Parallel Tx Data Buses HD10 AD9861 AD9861 Rx Data Rate Tx_A/B DATA RxSYNC = 2 × ADC Sample U[0:9] U[9] Rate TxSYNC Rx_A/B DATA L[9] Tx/Rx DIGITAL L[0:9] Tx/Rx DIGITAL One 10-Bit Interleaved Rx IFACE1 BACK IFACE1 BACK Data Bus OUTPUT CLOCK END OUTPUT CLOCK END N/A IFACE2 IFACE2 Tx Data Rate IFACE3 OUTPUT CLOCK IFACE3 OUTPUT CLOCK = 2 × ADC Sample Rate 03606-0-009 03606-0-013 One 10-Bit Interleaved Tx Data Bus FD AD9861 AD9861 AD9861 Rx Data Rate Tx_A/B DATA Tx_A/B DATA = 2 × ADC Sample U[0:9] U[0:9] U[0:9] Rate Rx_A/B DATA Rx_A/B DATA L[0:9] TxSYNC DIGITAL L[0:9] DIGITAL L[0:9] TxSYNC DIGITAL One 10-Bit Interleaved Rx IFACE1 BACK IFACE1 BACK IFACE1 BACK Data Bus OUTPUT CLOCK END OUTPUT CLOCK END OUTPUT CLOCK END IFACE2 IFACE2 IFACE2 Tx Data Rate IFACE3 OUTPUT CLOCK IFACE3 OUTPUT CLOCK IFACE3 OUTPUT CLOCK = 2 × ADC Sample Rate 03606-0-010 03606-0-014 03606-0-016 One 10-Bit Interleaved Tx Data Bus Clone AD9861 AD9861 Rx Data Rate Tx_A/B DATA Rx_A DATA = 1 × ADC Sample U[0:9] U[0:9] Rate TxSYNC Rx_B DATA L[9] Tx/Rx DIGITAL L[0:9] Tx/Rx DIGITAL Two 10-Bit Parallel Rx Data IFACE1 BACK IFACE1 BACK Buses OUTPUT CLOCK END OUTPUT CLOCK END IFACE2 IFACE2 Tx Data Rate IFACE3 OUTPUT CLOCK IFACE3 OUTPUT CLOCK N/A = 2 × ADC Sample Rate 03606-0-011 03606-0-015 One 10-Bit Interleaved Tx Data Bus Requires SPI Interface to Configure; Similar to AD9860 Data Interface Rev. A | Page 30 of 51

Data Sheet AD9861 Table 12 describes AD9861 pin function (when mode pins are used) relative to I/O mode, and for half-duplex modes whether transmitting or receiving. Table 12. AD9861 Pin Function vs. Interface Mode (No SPI Cases) Mode Name U10 L10 IFACE1 IFACE2 IFACE3 FD Interleaved Tx Data Interleaved Rx Data TxSYNC Buffered Rx Clock Buffered Tx Clock HD10 Interleaved Tx Data MSB = TxSYNC Tx/Rx = Tied High 10/20 Pin Control Tied High Buffered Tx Clock (Tx/Rx = High) Others = Three-state HD10 MSB = RxSYNC Interleaved Rx Data Tx/Rx = Tied Low 10/20 Pin Control Tied High Buffered Rx Clock (Tx/Rx = Low) Others = Three-state HD20 Tx_A Data Tx_B Data Tx/Rx = Tied High 10/20 Pin Control Tied Low Buffered Tx Clock (Tx/Rx = High) HD20 Rx_B Data Rx_A Data Tx/Rx = Tied Low 10/20 Pin Control Tied Low Buffered Rx Clock (Tx/Rx = Low) Clone Mode Clone mode not available without SPI. (Tx/Rx = High) Clone Mode Clone mode not available without SPI. (Tx/Rx = Low) Table 13 describes AD9861 pin function (when SPI programming is used) relative to flexible I/O mode, and for half-duplex modes whether transmitting or receiving. Table 13. AD9861 Pin Function vs. Interface Mode (Configured through the SPI Registers) Mode Name U10 L10 IFACE1 IFACE2 IFACE3 FD Interleaved Tx Data Interleaved Rx Data TxSYNC Buffered System Buffered Tx Clock Clock HD10, Tx Mode Interleaved Tx Data MSB = TxSYNC Tx/Rx = Tied High Optional Buffered Buffered Tx Clock (Tx/Rx = High) Others = Three-state System Clock HD10, Rx Mode MSB = RxSYNC Interleaved Tx Data Tx/Rx = Tied Low Optional Buffered Buffered Rx Clock (Tx/Rx = Low) Other = Three-state System Clock HD20, Tx Mode Tx_A Data Tx_B Data Tx/Rx = Tied High Optional Buffered Buffered Tx Clock (Tx/Rx = High) System Clock HD20, Rx Mode Rx_B Data Rx_A Data Tx/Rx = Tied Low Optional Buffered Buffered Rx Clock (Tx/Rx = Low) System Clock Clone Mode , Interleaved Tx Data MSB = TxSYNC Tx/Rx = Tied High Optional Buffered Buffered Tx Clock Tx Mode Others = Three-state System Clock (Tx/Rx = High) Clone Mode , Rx_B Data Rx_A Data Tx/Rx = Tied Low Optional Buffered Buffered Rx Clock Rx Mode System Clock (Tx/Rx = Low) Summary of Flexible I/O Modes The following notes provide a general description of the FD FD Mode mode configuration. For more information, refer to Table 16. The full-duplex (FD) mode can be configured by using mode pins or Note the following about the Tx path in FD mode: with SPI programming. Using the SPI allows additional • Interpolation rate of 2× or 4× can be programmed with configuration flexibility of the device. mode pins or SPI. FD mode is the only mode that supports full-duplex, receive, and • Max DAC update rate = 200 MSPS. transmit concurrent operation. The upper 10-bit bus (U10) is used Max Tx input data rate = 80 MSPS/channel (160 MSPS to accept interleaved Tx data, and the lower 10-bit bus (L10) is used interleaved). to output interleaved Rx data. Either the Rx path or the Tx path (or • TxSYNC is used to direct Tx input data. both) can be independently powered down using either (or both) the TxSYNC = high indicates channel Tx_A data. RxPwrDwn and TxPwrDwn pins. FD mode requires interpolation of TxSYNC = low indicates channel Tx_B data. 2× or 4×. • Buffered Tx clock output (from IFACE3 pin) equals 2× the DAC update rate; one rising edge per interleaved Tx sample. Rev. A | Page 31 of 51

AD9861 Data Sheet Note the following about the Rx path in FD mode: HD20 Mode • ADC CLK Div register can be used to divide down the clock The half-duplex 20-bit parallel output, HD20, can be configured driving the ADC, which accepts up to 50 MHz (AD9861-50) or using mode pins or through SPI programming. up to 80 MHz (AD9861-80). HD20 mode supports half-duplex only operations and can • Max ADC sampling rate = 50 MSPS (AD9861-50) or 80 MSPS interface to a single 20-bit data bus (two parallel 10-bit buses). (AD9861-80). Both the U10 and L10 buses are used on the AD9861. The logic level of the Tx/Rx selector (controlled through IFACE1 pin) is • The Rx path output data rate is 2× the ADC sample rate used to configure the buses as Rx outputs (during Rx operation) (interleaved). or as Tx inputs (during Tx operation). A single pin is used to • Rx_A output when IFACE2 logic level = low. output the clocks for Rx and Tx data latching (from the IFACE3 Rx_B output when IFACE2 logic level = high. pin) switching, depending on which path is enabled. HD10 Mode The following notes provide a general description of the HD20 The half-duplex, 10-bit interleaved outputs mode, HD10 can be mode configuration. For more information, refer to Table 16. configured using mode pins or the SPI. Note the following about the Tx Path in HD20 mode: HD10 mode supports half-duplex only operations and can interface • Interpolation rate of 1×, 2×, or 4× can be programmed to a single 10-bit data bus with independent Rx and Tx with mode pins or SPI. synchronization pins (RxSYNC and TxSYNC). Both the U10 and • Max DAC update rate = 200 MSPS. L10 buses are used on the AD9861, but the logic level of the Tx/Rx Max Tx input data rate = 160 MSPS/channel with bypassed selector (controlled through IFACE1 pin) is used to disable and interpolation filters, 100 MSPS for 2× interpolation or three-state the unused bus, allowing U10 and L10 to be tied together. 50 MSPS for 4× interpolation. The MSB of the unused bus acts as the RxSYNC (during Rx operation) or TxSYNC (during Tx operation). A single pin is used to • Tx_A DAC data is accepted from the U10 bus; Tx_B DAC output the clocks for Rx and Tx data latching (from the IFACE3 pin) data is accepted from the L10 bus. switching, depending on which path is enabled. HD10 mode Note the following about the Rx path in HD20 mode: requires interpolation of 2× or 4×. • ADC CLK Div register can be used to divide down the The following notes provide a general description of the HD10 mode clock driving the ADC, which accepts up to 50 MHz configuration. For more information, refer to Table 16. (AD9861-50) or up to 80 MHz (AD9861-80). Note the following about the Tx path in HD10 mode: • Max ADC sampling rate = 50 MSPS (AD9861-50) or • Interpolation rate of 2× or 4× can be programmed with mode 80 MSPS (AD9861-80). pins or SPI. • The Rx_A output data is output on L10 bus; the Rx_B • Interleaved Tx data accepted on U10 bus, L10 bus MSB acts as output data is output on U10 bus. TxSYNC. Clone Mode • Max DAC update rate = 200 MSPS. An interface mode provides a similar interface to the AD9860 Max Tx input data rate = 80 MSPS/channel (160 MSPS when used in half-duplex mode. This mode is referred to as interleaved). clone mode and requires SPI to configure. • TxSYNC is used to direct Tx input data. Clone mode provides a parallel Rx data output (20 bits) while in TxSYNC = high indicates channel Tx_A data. Rx mode, and accepts interleaved Tx data (10-bit) while in Tx TxSYNC = low indicates channel Tx_B data. mode. Both the U10 and L10 buses are used on the AD9861. Note the following about the Rx path in HD10 mode: The logic level of the Tx/Rx selector (controlled through the IFACE1 pin) is used to configure the buses for Rx outputs • ADC CLK Div register can be used to divide down the clock (during Rx operation) or as Tx inputs (during Tx operation). A driving the ADC, which accepts up to 50 MHz (AD9861-50) or single pin is used to output the clocks for Rx and Tx data up to 80 MHz (AD9861-80). latching (from the IFACE3 pin), depending on which path is • Max ADC sampling rate = 50 MSPS (AD9861-50) or 80 MSPS enabled. Clone mode requires interpolation of 2× or 4×. (AD9861-80). The following notes provide a general description of the clone • Output data rate = 2× ADC sample rate. mode configuration. For more information, refer to Table 16. • Interleaved Rx data output from L10 bus. Note the following about the Tx path in clone mode: • Rx_A output when IFACE2 (or RxSYNC) logic level = low. • Interpolation rate of 2× or 4× can be programmed with Rx_B output when IFACE2 (or RxSYNC) logic level = high. mode pins or SPI. Rev. A | Page 32 of 51

Data Sheet AD9861 • Max DAC update rate = 200 MSPS. Configuring with Mode Pins Max Tx input data rate = 80 MSPS/channel (160 MSPS The flexible interface can be configured with or without the SPI, interleaved). although more options and flexibility are available when using • TxSYNC is used to direct Tx input data. the SPI to program the AD9861. Mode pins can be used to TxSYNC = high indicates channel Tx_A data. power down sections of the device, reduce overall power consump- TxSYNC = low indicates channel Tx_B data. tion, configure the flexible I/O interface, and program the interpolation setting. The SPI register map, which provides • Buffered Tx clock output (from IFACE3 pin) uses one rising many more options, is discussed in the Configuring with SPI edge per interleaved Tx sample. section. Note the following about the Rx path in clone mode: Mode Pins/Power-Up Configuration Options • ADC CLK Div register can be used to divide down the clock Various options are configurable at power-up through mode driving the ADC, which accepts up to 50 MHz (AD9861-50) or pins, and also through control pins for power-down modes. The up to 80 MHz (AD9851-80). logic value of the configuration mode pins are latched when the • Max ADC sampling rate = 50 MSPS (AD9861-50) or 80 MSPS device is brought out of reset (rising edge of RESET). The mode (AD9861-80). pin names and their functions are shown in Table 14. Table 15 • Output data rate = ADC sample rate, that is, two 10-bit parallel provides a detailed description of the mode pins. outputs per one buffer Rx clock output cycle. • The Rx_A output data is output on L10 bus; the Rx_B output data is output on U10 bus. Table 14. Mode Pin Names and Functions Pin Name Duration Function RxPwrDwn Permanent When high, digital clocks to Rx block are disabled. Analog circuitry that require <10 µs to power up are powered off. TxPwrDwn Permanent When high, digital clocks to Tx block are disabled (PLL remains powered to maintain output clock with an optional SPI shut off). Analog circuitry that require <10 µs to power up are powered off. Tx/Rx (IFACE1) Permanent only for When high, digital clocks to Tx block are disabled (PLL remains powered to maintain output HD Flex I/O interface clock with an optional SPI shutoff). Tx analog blocks remain powered up unless Tx_PwrDwn is asserted. When low, digital clocks to Rx block are disabled. Rx analog circuitry remain powered up unless Rx_PwrDwn is asserted. ADC_LO_PWR Defined at Reset or When enabled, this bit scales the ADC power-down by 40%. Power-Up SPI_Bus_Enable Defined at Reset or This function is controlled through the SPI_CS pin. This pin must remain low to maintain mode (SPI_CS) Power-Up pin functionality (the SPI port remains nonfunctional). This pin must be high when coming out of reset to enable the SPI. FD/HD Defined at Reset or Configures the flex I/O for FD or HD mode. This control applies only if the SPI bus is disabled. Power-Up 10/20 only valid for Defined at Reset or If the flex I/O bus is in HD mode, this bit is used to configure parallel or interleaved data mode. HD mode Power-Up This control applies only if the SPI bus is disabled. Interp0 and Interp1 Defined at Reset or The Interp1 and Interp0 bits configure the PLL and the interpolation rate to 1× [00], 2× [01], or Power-Up 4× [10]. This control applies only if the SPI bus is disabled. Table 15. Mode Pin Names and Descriptions Pin Name Description ADC_LO_PWR ADC Low Power Mode Option. ADC_LO_PWR is latched during the rising edge of RESET. Logic low results in ADC operation at nominal power mode. Logic high results in ADC consuming 40% less power than the nominal power mode. FD/HD (SDO) For Flex I/O Configuration, this control applies only if the SPI bus is disabled. FD/HD (SDO) is latched during the rising edge of RESET. Logic low identifies that the DUT flex I/O port will be configured for half-duplex operation. 10/20 (IFACE2) is also latched during the rising edge of RESET to identify interleaved data mode or parallel data modes. Logic low indicates that the flex I/O will configure itself for parallel data mode. Rev. A | Page 33 of 51

AD9861 Data Sheet Pin Name Description Logic high indicates that the flex I/O will configure itself for interleaved data mode. 10/ 20 For flex I/O Configuration, The 10/20 pin control applies only if the SPI bus is disabled and the device is configured for HD mode. 10/20 is latched during the rising edge of RESET. 10/20 (IFACE2) is used to identify interleaved data mode or parallel data modes. Logic low indicates that the flex I/O will configure itself for HD20 mode. Logic high indicates that the flex I/O will configure itself for HD10 mode. SPI_Bus_Enable (SPI_CS) SPI_CS is latched during the rising edge of RESET. Logic low results in the SPI being disabled and SPI_DIO, SPI_CLK and SPI_SDO act as mode pins. Logic high results in the SPI being fully operational, and some of the mode pins are disabled. Interp0 and Interp1 Interpolation/PLL Factor Configuration. This control applies only if the SPI bus is disabled. SPI_DIO (Interp1) and SPI_CLK (Interp0) configure the Tx path for 1× [00], 2× [01], or 4× [10] interpolation and also enable the PLL of the same multiplication factor. RxPwrDwn Power-Down Control. RxPwrDwn logic level controls the power-down function of the Rx path. Logic low results in the Rx path operating at normal power levels. Logic high disables the ADC clock and disables some bias circuitry to reduce power consumption. TxPwrDwn Power-Down Control. TxPwrDwn logic level controls the power-down function of the Tx path. Logic low results in the Tx path operating at normal power levels. Logic high disables the DAC clocks and disables some bias circuitry to reduce power consumption. Tx/Rx Power-Down Control. Tx/Rx pin enables the appropriate Tx or Rx path in the half-duplex mode. A logic low disables the Tx digital clock and the I/O bus is configured as an output or three-stated. A logic high disables the Rx digital clocks and the I/O bus is configured as high impedance inputs. Rev. A | Page 34 of 51

Data Sheet AD9861 Configuring with SPI The flexible interface can be configured with register settings. Using the register allows more device programmability. Table 16 shows the required register writes to configure the AD9861 for FD, optional FD, HD20, optional HD20, HD10, optional HD10, and clone mode. Note that for modes that use interleaved data buses, enabling 2× or 4× interpolation is required. Table 16. Registers for Configuring SPI Register Address Setting Description FD, Mode 1 Register 0x01 [7:5] [000]; clk_mode—Configures timing mode. Register 0x14 [4] High SpiFDnHD—Configures FD mode. Register 0x14 [2] High SpiB10n20—Configures FD mode. Register 0x13 [1:0] [01] or [10] Interpolation Control—Configures 2× or 4× interpolation. Optional FD, Mode 2 Register 0x01 [7:5] [001] clk_mode—Configures timing mode. Register 0x14 [4] High SpiFDnHD—Configures FD mode. Register 0x14 [2] High SpiB10n20—Configures FD mode. Register 0x13 [1:0] [01] or [10] Interpolation Control—Configures 2× or 4× interpolation. HD20, Mode 4 Register 0x01 [7:5] [000]; clk_mode—Configures timing mode. Register 0x14 [4] Low SpiFDnHD—Configures HD mode. Register 0x14 [2] Low SpiB10n20—Configures HD20 mode. Register 0x13 [1:0] [00], [01] or [10] Interpolation Control—Configures 1×, 2×, or 4× interpolation. Optional HD20, Mode 5 Register 0x01 [7:5] [011] clk_mode—Configures timing mode. Register 0x14 [4] Low SpiFDnHD—Configures HD mode. Register 0x14 [2] Low SpiB10n20—Configures HD20 mode. Register 0x13 [1:0] [00], [01] or [10] Interpolation Control—Configures 1×, 2×, or 4× interpolation. HD10, Mode 7 Register 0x01 [7:5] [000] clk_mode—Configures timing mode. Register 0x14 [4] Low SpiFDnHD—Configures HD mode. Register 0x14 [2] High SpiB10n20—Configures HD10 mode. Register 0x13 [1:0] [01] or [10] Interpolation Control—Configures 2× or 4× interpolation. Optional HD10, Mode 8 Register 0x01 [7:5] [101] clk_mode—Configures timing mode. Register 0x14 [4] Low SpiFDnHD—Configures HD mode. Register 0x14 [2] High SpiB10n20—Configures HD10 mode. Register 0x13 [1:0] [01] or [10] Interpolation Control—Configures 2× or 4× interpolation. Clone, Mode 10 Register 0x01 [7:5] [111] clk_mode—Configures timing mode. Register 0x14 [0] High SpiClone—Configures clone mode. Register 0x13 [1:0] [01] or [10] Interpolation Control—Configures 2× or 4× interpolation. Rev. A | Page 35 of 51

AD9861 Data Sheet SPI Register Map Registers 0x00 to 0x29 of the AD9861 provide flexible operation of the device. The SPI allows access to many configurable options. Detailed descriptions of the bit functions are found in Table 18. Table 17. Register Map Reg. Name Addr 7 6 5 4 3 2 1 0 General 0x00 SDIO BiDir LSB First Soft Reset Clock Mode 0x01 clk_mode[2:0] Enable IFACE2 Inv clkout clkout (IFACE3) Power-Down 0x02 Tx Analog TxDigital RxDigital PLL Power- PLL Output Down Disconnect RxA Power-Down 0x03 Rx_A Analog Rx_A DC Bias RxB Power-Down 0x04 Rx_B Analog Rx_B DC Bias Rx Power-Down 0x05 Rx Analog Bias RxRef DiffRef VREF Rx Path 0x06 Rx_A Twos Rx_A Clk Complement Duty Rx Path 0x07 Rx_B Twos Rx_B Clk Complement Duty Rx Path 0x08 Rx Ultralow Rx Ultralow Power Control Power Control Rx path 0x09 Rx Ultralow Rx Ultralow Rx Ultralow Power Control Power Control Power Control Rx Path 0x0A Rx Ultralow Rx Ultralow Rx Ultralow Power Control Power Control Power Control Tx Path 0B DAC A Offset [9:2] Tx Path 0C DAC A Offset [1:0] DAC A Offset Direction Tx Path 0D DAC A Coarse Gain Control DAC A Fine Gain [5:0] Tx Path 0E DAC B Offset [9:2] Tx Path 0F DAC B Offset [1:0] DAC B Offset Direction Tx Path 10 DAC B Coarse Gain Control DAC B Fine Gain [5:0] Tx Path 11 TxPGA Gain [7:0] Tx Path 12 TxPGA Slave TxPGA Fast Enable Update I/O Configuration 13 Tx Twos Rx Twos Tx Inverse Interpolation Control [1:0] Complement Complement Sample I/O Configuration 14 Dig Loop On SpiFDnHD SpiTxnRx SpiB10n20 SPI IO Control SpiClone Clock 15 PLL Bypass ADC Clock Div Alt Timing Mode PLL Div5 PLL Multiplier [2:0] Clock 16 PLL to IFACE2 PLL Slow Auxiliary 17 AuxDAC A FS [1:0] AuxDAC B FS [1:0] AuxDAC C FS [1:0] AuxADC Ref AuxADC Ref Converters Enable FS AuxADC 18 Start Average Number of AuxADC A Samples [2:0] AuxADC A AuxADC 19 Start Average Number of AuxADC B Samples [2:0] AuxADC B AuxADC 1A AuxADC A2 [1:0] AuxADC 1B AuxADC A2 [9:2] AuxADC 1C AuxADC A1 [1:0] AuxADC 1D AuxADC A1 [9:2] AuxADC 1E AuxADC B [1:0] AuxADC 1F AuxADC B [9:2] AuxADC 22 AuxSPI Enable Sel 2not1 Refsel B Start B Refsel A Select A Start A AuxADC 23 AuxADC Clock Div[1:0] AuxDAC 24 AuxDAC A [7:0] 25 AuxDAC B [7:0] 26 AuxDAC C [7:0] 28 Slave Enable Update C Update B Update A 29 AuxDAC C Sync AuxDAC B Sync AuxDAC A Sync Power-Up C Power-Up B Power-Up A TxPwrDwn TxPwrDwn TxPwrDwn Rev. A | Page 36 of 51

Data Sheet AD9861 Table 18. Register Bit Descriptions Register Bit Description Register 0: General Bit 7: SDIO BiDir (Bidirectional) Default setting is low, which indicates that the SPI serial port uses dedicated input and output lines (4- wire interface), SDIO and SDO pins, respectively. Setting this bit high configures the serial port to use the SDIO pin as a bidirectional data pin. Bit 6: LSB First Default setting is low, which indicates MSB first SPI port access mode. Setting this bit high configures the SPI port access to LSB first mode. Bit 5: Soft Reset Writing a high to this register resets all the registers to their default values and forces the PLL to relock to the input clock. The soft reset bit is a one-shot register, and is cleared immediately after the register write is completed. Register 1: Clock Mode Bits 7–5: Clk Mode These bits represent the clocking interface for the various modes. Setting 000 is default. Setting 111 is used for clone mode. Refer to the Summary of Flexible I/O Modes section for definition of clone mode. Setting Mode 000 Standard FD, HD10, HD20 Clock (Modes 1, 4, 7) 001 Optional FD timing (Mode 2) 010 Not Used 011 Optional HD20 timing (Mode 5) 100 Not Used 101 Optional HD10 timing (Mode 8) 110 Not Used 111 Clone Mode (Mode 10) Bit 2: Enable IFACE2 clkout Enables the IFACE2 port to be an output clock. Also inverts the IFACE2 output clock in full-duplex mode. Bit 1: Inv clkout (IFACE3) Invert the output clock on IFACE3. Register 2: Power-Down Bits 7–5: Tx Analog (Power-Down) Three options are available to reduce analog power consumption for the Tx channels. The first two options disable the analog output from Tx Channel A or B independently, and the third option disables the output of both channels and reduces the power consumption of some of the additional analog support circuitry for maximum power savings. With all three options, the DAC bias current is not powered down so recovery times are fast (typically a few clock cycles). The list below explains the different modes and settings used to configure them. Power-Down Option Bits Setting [7:5] Power-Down Tx A Channel Analog Output [1 0 0] Power-Down Tx B Channel Analog Output [0 1 0] Power-Down Tx A and Tx B Analog Outputs [1 1 1] Bit 4: Tx Digital (Power-Down) Default setting is low, which enables the transmit path digital to operate as programmed through other registers. By setting this bit high, the digital blocks are not clocked to reduce power consumption. When enabled, the Tx outputs are static, holding their last update values. Bit 3: Rx Digital (Power-Down) Setting this bit high powers down the digital section of the receive path of the chip. Typically, any unused digital blocks are automatically powered down. Bit 2: PLL Power-Down Setting this register bit high forces the CLKIN multiplier to a power-down state. This mode can be used to conserve power or to bypass the internal PLL. To operate the AD9861 when the PLL is bypassed, an external clock equal to the fastest on-chip clock is supplied to the CLKIN. Bit 1: PLL Output Disconnect Setting this register bit high disconnects the PLL output from the clock path. If the PLL is enabled, it locks or stays locked as normal. Register 3/4: Rx Power-Down Bit 7: Rx_A Analog/ Either ADC or both ADCs can be powered down by setting the appropriate register bit high. The entire Rx_B Analog (Power-Down) analog circuitry of Rx channel is powered down, including the differential references, input buffer, and the internal digital block. The band gap reference remains active for quick recovery. Bit 6: Rx_A DC Bias/ Setting either of these bits high powers down the input common-mode bias network for the respective Rx_B DC Bias (Power-Down) channel and requires an input signal to be properly dc-biased. By default, these bits are low, and the Rx inputs are self-biased to approximately AVDD/2 and accept an ac-coupled input. Register 5: Rx Power-Down Bit 7: Rx Analog Bias (Power- Setting this bit high powers down all analog bias circuits related to the receive path (including the Down) differential reference buffer). Because bias circuits are powered down, an additional power saving, but also a longer recovery time relative to other Rx power-down options, will result. Bit 6: RxREF (Power-Down) Setting this register bit high powers down internal ADC reference circuits. Powering down these Rev. A | Page 37 of 51

AD9861 Data Sheet Register Bit Description circuits provides additional power saving over other power-down modes. The Rx path wake-up time depends on the recovery of these references typically of the order of a few milliseconds. Bit 5: DiffRef (Power-Down) Setting this bit high powers down the ADC’s differential references, REFT and REFB. Recovery time depends on the value of the REFT and REFB decoupling capacitors. Bit 4: VREF (Power-Down) Setting this register bit high powers down the ADC reference circuit, VREF. Powering down the Rx band gap reference allows an external reference to drive the VREF pin setting full-scale range of the Rx paths. Registers 6/7: Rx Path Bit 5: Rx_A Twos Complement/ Default data format for the Rx data is straight binary. Setting this bit high generates twos complement Rx_B Twos Complement data. Bit 4: Rx_A Clk Duty/Rx_B Clk Duty Setting either of these bits high enables the respective channels on-chip duty cycle stabilizer (DCS) circuit to generate the internal clock for the Rx block. This option is useful for adjusting for high speed input clocks with skewed duty cycle. The DCS mode can be used with ADC sampling frequencies over 40 MHz. Registers 8/9/A: Rx Path Rx Ultralow Power Control Bits Set all bits high, in combination with asserting the ADC_LO_PWR pin, to reduce the power consumption of the Rx path by a fourth of normal Rx path power consumption. Registers 0B/0C/0E/0F: Tx Path DAC A/DAC B Offset These 10-bit, twos complement registers control a dc current offset that is combined with the Tx A or Tx B output signal. An offset current of up to ±12% IOUTFS (2.4 mA for a 20 mA full-scale output) can be applied to either differential pin on each channel. The offset current can be used to compensate for offsets that are present in an external mixer stage, reducing LO leakage at its output. The default setting is 0x00, no offset current. The offset current magnitude is set by using the lower nine bits. Setting the MSB high adds the offset current to the selected differential pin, while an MSB low setting subtracts the offset value. DAC A/DAC B Offset Direction This bit determines to which of the differential output pins for the selected channel the offset current is applied. Setting this bit low applies the offset to the negative differential pin. Setting this bit high applies the offset to the positive differential pin. Registers 0D/10: Tx Path Bits 7, 6: DAC A/DAC B Coarse Gain These register bits scale the full-scale output current (IOUTFS) of either Tx channel independently. IOUT of Control the Tx channels is a function of the RSET resistor, the TxPGA setting, and the coarse gain control setting. 00 Output current scaling by 1/11 01 Output current scaling by ½ 10 No output current scaling 11 No output current scaling Bits 5–0: DAC A/DAC B Fine Gain The DAC output curve can be adjusted fractionally through the gain trim control. Gain trim of up to ±4% can be achieved on each channel individually. The gain trim register bits are a twos complement attention control word. MSB, LSB 100000 Maximum positive gain adjustment 111111 Minimum positive gain adjustment 000000 No adjustment (default) 000001 Minimum negative gain adjustment 011111 Maximum negative gain adjustment Register 11: Tx Path Bits 0–7: TxPGA Gain This 8-bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) register controls for the Tx programmable gain amplifier (TxPGA). The TxPGA provides a 20 dB continuous gain range with 0.1 dB steps (linear in dB) simultaneously to both Tx channels. By default, this register setting is 0xFF. MSB, LSB 0000 0000 Minimum gain scaling –20 dB 1111 1111 Maximum gain scaling 0 dB Register 12: Tx Path Bit 6: TxPGA Slave Enable The TxPGA gain is controlled through register TxPGA gain setting and, by default, is updated immediately after the register write. If this bit is set, the TxPGA gain update is synchronized with the falling edge of a signal applied to the TxPwrDwn pin and is enabled during the wake-up from power- down. Rev. A | Page 38 of 51

Data Sheet AD9861 Register Bit Description Bit 4: TxPGA Fast Update (Mode) The TxPGA fast bit controls the update speed of the TxPGA. When fast update mode is enabled, the TxPGA provides fast gain settling within a few clock cycles, which may introduce spurious signals at the output of the Tx path. The default setting for this bit is low, and the TxPGA gives a smooth transition between gain settings. Fast mode is enabled when this bit is set high. Register 13: I/O Configuration Bit 7: Tx Twos Complement The default data format for Tx data is straight binary. Set this bit high when providing twos complement Tx data. Bit 6: Rx Twos Complement The default data format for Rx data is straight binary. Set this bit high when providing twos complement Rx data. Bit 5: Tx Inverse Sample By default, the transmit data is sampled on the rising edge of the CLKOUT. Setting this bit high changes this, and the transmit data is sampled on the falling edge. Bits 1,0: Interpolation Control These register bits control the interpolation rate of the transmit path. The default settings are both bits low, indicating that both interpolation filters are bypassed. The MSB and LSB are Address Bits 1 and 0, respectively. Setting binary 01 provides an interpolation rate of 2×; binary 10 provides an interpolation rate of 4×. Register 14: I/O Configuration Bit 5: Dig Loop On When enabled, this bit enables a digital loop back mode. The digital loop-back mode provides a means of testing digital interfaces and functionality at the system level. In digital loop-back mode, the full- duplex interface must be enabled. (Refer to the Flexible I/O Interface Options section.) The device accepts digital input from the bus according to the FD mode timing and uses the Tx digital path (with enabled interpolation and other digital settings); the processed data is then output from the Rx path bus. Bit 4: SPI_FDnHD Control bit to configure full-duplex (high) or half-duplex (low) interface mode. This register, in combination with the SpiB10n20 register, configures the interface mode of FD, HD10, or HD20. The register setting is ignored for clone mode operation. By default, this register is set high, and the device is in FD mode. Bit 3: SpiTxnRx Control bit used for toggling between transmit or receive mode for the half-duplex clock modes. High represents Tx and low represents Rx. Bit 2: SpiB10n20 Control bit for 10-bit or 20-bit modes. High represents 10-bit mode and Low represents 20-bit mode. Bit 1: SPI IO Control Use in conjunction with SpiTxnRx [Register14, Bit 3] to override external TxnRx pin operation. Bit 0: SpiClone Set high when in clone mode (see the Flexible I/O Interface Options section for definition of clone mode). Clk_mode must also be set to binary 111, i.e., [Register 01[7:5] = 111. Register 15: Clock Bit 7: PLL_Bypass Setting this bit high bypasses the PLL. When bypassed, the PLL remains active. Bits 5: ADC Clock Div By default, the ADCs are driven directly from CLKIN in normal timing operation or from the PLL output clock in the alternative timing operation. This bit is used to divide the source of the ADC clock prior to the ADCs. The default setting is low and performs no division. Setting this bit high divides the clock by 2. Bit 4: Alt Timing Mode The timing table in the data sheet describes two timing modes: the normal timing operation mode and the alternative timing operation mode. The default configuration is normal timing mode and the CLKIN drives the Rx path. In alternative timing mode, the PLL output is used to drive the Rx path. The alternative operation mode is configured by setting this bit high. Bit 3: PLL Div5 The output of the PLL can be divided by 5 by setting this bit high. By default, the PLL directly drives the Tx digital path with no division of its output. Bits 2–0: PLL Multiplier These bits control the PLL multiplication factor. A default setting is binary 000, which configures the PLL to 1× multiplication factor. This register, in combination with the PLL Div5 register, sets the PLL output frequency. The programmable multiplication factors are 000 1× 001 2× 010 4× 011 8× 100 16× 101 – 111 not used Register 16: Clock Bit 5: PLL to IFACE2 Setting this bit high switches the IFACE2 output signal to the PLL output clock. It is valid only if Register 0x01, Bit 2 is enabled or if full-duplex mode is configured. Bit 2: PLL Slow Changes the PLL loop bandwidth and changes the profile of the phase noise generated from the PLL clock. Rev. A | Page 39 of 51

AD9861 Data Sheet Register Bit Description Register 17: Auxiliary Converters Bits 7–2: AuxDAC A FS/AuxDAC B These register bits independently scale the full-scale output voltage for the AuxDACs. If the full-scale FS/AuxDAC C FS voltage is programmed to a value greater than PLL_VDD – 0.2 V, the AuxDAC becomes nonlinear in this region. MSB, LSB AuxDAC Full-Scale Output Voltage 00 3.0 V 01 3.3 V 10 2.5 V 11 2.7 V Bit 1: AuxADC Ref Enable This bit enables the on-chip, supply independent reference for the AuxADC. By default, the AuxADC uses the PLL_AVDD supply for its full-scale voltage level. Bit 0: AuxADC Ref FS When the AuxADC Ref Enable bit is set high, this bit allows the user to select the full-scale value of the AuxADC. A low setting sets the full-scale value to 3.0 V; a high setting sets the full-scale value to 2.5 V. If the full-scale voltage is programmed to a value greater than PLL_VDD – 0.2 V, the AuxADC is not linear in this region. Registers 18/19 : AuxADC Bit 7: Start Average AuxADC A/ These registers are used to initiate a conversion cycle of the AuxADCs for a number of consecutive Start Average AuxADC B samples and then report the average result. The number of consecutive samples is programmed in the number of AuxADC A/AuxADCB samples register. The external pin Aux_SPI_CS can be configured to allow it to initiate the start average conversion cycle. The result is placed in the appropriate register corresponding to the AuxADC output [Registers 0x1A to 0x21]. Bit 7: Number of AuxADC A/ These bits control the number of samples that the AuxADC collects and uses to calculate an average AuxADC B Samples value. This register is used in conjunction with the start average AuxADC register. MSB, LSB Number of Samples to Average 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 Not Used Registers 1A–21: AuxADC These 10-bit, offset binary registers are read-only and store the last corresponding AuxADC output values. The AD9861 has two AuxADC SAR converters: AuxADC A and AuxADC B. AuxADC A has a multiplexed input, which allows the user to select either input by using the Select A register. The 10 bits are broken into two registers, one containing the upper eight bits and the other containing the lower two bits. Register 22: AuxADC Bit 7: AuxSPI (Enable) Enables the AuxSPI, which can be used to initiate a conversion and read back one of the AuxADCs. Bit 6: Sel 2not1 If the auxiliary serial port is used, this bit selects which AuxADC, 1 or 2, uses the dedicated auxiliary serial port. By default (low setting), the auxiliary serial port controls AuxADC A. Setting this bit high allows the auxiliary serial port to control AuxADC B. Bits 5, 2: Refsel B/A By default, the AuxADCs use an external reference applied to the AUX_REF pin. This voltage acts as the full-scale reference for the selected AuxADC. Either AuxADC can use an internally generated reference, which can be a buffered version of the analog supply voltage or a supply independent, 3.0 V or 2.5 V internal reference. To enable use of the internal reference for either of the AuxADCs, set the respective Refsel register high. For internal reference configuration, see Register 17. Bit 1: Select A This bit is used to select which of the two inputs is connected to the AuxADC. By default (setting low), the AUX_ADC_A2 (Aux2 pin) is connected to AuxADC A. Setting the respective bit high connects the AUX_ADC_A1 (Aux1 pin) to AuxADC A. Bit 3, 0: Start B/A Setting either of these bits to high initiates a conversion of the respective AuxADC, A or B. The register bit always reads back a low. Rev. A | Page 40 of 51

Data Sheet AD9861 Register Bit Description Register 23: AuxADC Bits 1,0: AuxADC Clock Div The AuxADCs clock can be based on either the clock driving the Rx ADC, or it can be driven from the SPI_CLK. The conversion rate of the AuxADCs must be less than 40 MHz. In order to facilitate a slower speed clock for the AuxADC, these bits are used to divide down the Rx ADC clock prior to driving the AuxADC. The following options are programmable through this register: MSB, LSB AuxADC Sampling Rate 00 Rx ADC Clock/4 01 Rx ADC Clock/2 10 Rx ADC Clock 11 SPI_CLK drives AuxADC Registers 24, 25, 26: AuxDAC AuxDAC A, B, and C Output Three 8-bit, straight binary words are used to control the output of three on-chip AuxDACs. The Control Word AuxDAC output changes take effect immediately after any of the serial writes are completed. The DAC output control words have default values of 0. The smaller programmed output controlled words correspond to lower DAC output levels. Register 28: AuxDAC Bit 7: Slave Enable A low setting (default) updates the AuxDACs after the respective register is written to. To synchronize the AuxDAC outputs to each other, a slave mode can be enabled by setting this bit high and then setting the appropriate update registers high. Bits 2/1/0: Update C, B, and A Setting a high bit to any of these bits initiates an update of the respective AuxDAC, A, B or C, when slave mode is enabled using the slave enable register. The register bit is a one-shot and always reads back a low. Be sure to keep the slave enable bit high when using the AuxDAC synchronization option. Register 29: AuxDAC Bits 7/6/5: AuxDAC C/B/A Sync Setting any of these bits high synchronizes AuxDAC updates only when the TxPwrDwn rising edge TxPwrDwn occurs. This syncronizes the AuxDAC update to the Tx path power-up. Bits 2/1/0: Power Up C, B, and A Setting any of these bits high powers up the appropriate AuxDAC. By default, these bits are low and the AuxDACs are disabled. Rev. A | Page 41 of 51

AD9861 Data Sheet PROGRAMMABLE REGISTERS The AD9861 contains internal registers that are used to configure the Normally, using one communication cycle in a multibyte device. A serial port interface provides read/write access to the transfer is the preferred method; however, single byte internal registers. Single-byte or dual-byte transfers are supported as communication cycles are useful to reduce CPU overhead when well as MSB first or LSB first transfer formats. The AD9861’s serial register access requires only one byte. An example of this is to interface port can be configured as a single pin I/O (SDIO) or as two write the AD9861 power-down bits. unidirectional pins for in/out (SDIO/SDO). The serial port is a All data input to the AD9861 is registered on the rising edge of flexible, serial communications port, allowing easy interface to many SCLK. All data is driven out of the AD9861 on the falling edge industry-standard microcontrollers and microprocessors. of SCLK. General Operation of the Serial Interface Instruction Byte By default, the serial port accepts data in MSB first mode and uses The instruction byte contains the information shown in four pins: SEN, SCLK, SDIO, and SDO by default. SEN is a serial Table 19, and the bits are described in detail after the table. clock enable pin; SCLK is the serial clock pin; SDIO is a bidirectional data line; and SDO is a serial output pin. Table 19. Instruction Byte MSB D6 D5 D4 D3 D2 D1 LSB SEN is an active low control gating read and write cycles. When SEN R/nW 2/n1 A5 A4 A3 A2 A1 A0 is high, SDO and SDIO go into a high impedance state. Byte SCLK is used to synchronize SPI read and writes at a maximum bit R/nW—Bit 7 of the instruction byte determines whether a read rate of 30 MHz. Input data is registered on the rising edge, and or write data transfer will occur after the instruction byte write. output data transitions are registered on the falling edge. During Logic high indicates a read operation. Logic low indicates a write operations, the registers are updated after the 16th rising clock write operation. edge (and 24th rising clock edge for the dual-byte case). Incomplete 2/n1 Byte—Bit 6 of the instruction byte determines the number write operations are ignored. of bytes to be transferred during the data transfer cycle of the SDIO is an input data only pin by default. Optionally, a 3-pin communication cycle. Logic high indicates a 2-byte transfer. interface may be configured using the SDIO for both input and Logic low indicates a 1-byte transfer. output operations and three-stating the SDO pin. Refer to the SDIO A5, A4, A3, A2, A1, A0—Bits 5, 4, 3, 2, 1, and 0 of the BiDir bit in Register 0x00 (Table 18). instruction byte determine which register is accessed during the SDO is a serial output data pin used for readback operations in 4- data transfer portion of the communication cycle. For 2-byte wire mode and is three-stated when SDIO is configured for transfers, this address is the starting byte address. The second bidirectional operation. byte address is automatically decremented when the interface is There are two phases to a communication cycle with the AD9861. configured for MSB first transfers. For LSB first transfers, the Phase 1 is the instruction cycle, which is the writing of an address of the second byte is automatically incremented. instruction byte into the AD9861, coincident with the first eight Table 20. Serial Port Interface Timing SCLK rising edges. The instruction byte provides the AD9861 serial Maximum SCLK Frequency (f ) 40 MHz port controller with information regarding the data transfer cycle, SCLK Minimum SCLK High Pulse Width (t ) 12.5 ns which is Phase 2 of the communication cycle. The Phase 1 PWH Minimum SCLK Low Pulse Width (t ) 12.5 ns instruction byte defines whether the upcoming data transfer is read PWL Maximum Clock Rise/Fall Time 1 ms or write, the number of bytes in the data transfer (one or two), and Data to SCLK timing (t ) 12.5 ns the starting register address for the first byte of the data transfer. DS Data Hold Time (t ) 0 ns DH The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9861. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9861 and the system controller. Phase 2 of the communication cycle is a transfer of one or two data bytes as determined by the instruction byte. Rev. A | Page 42 of 51

Data Sheet AD9861 Write Operations The SPI write operation uses the instruction header to configure a 1- Figure 78 to Figure 80 are examples of writing data into the byte or 2-byte register write using the 2/n1 byte setting. The device. Figure 78 shows a 1-byte write with MSB first; Figure 79 instruction byte followed by the register data is written serially into shows a 2-byte write with MSB first; and Figure 80 shows a the device through the SDIO pin on rising edges of the interface 2-byte write with LSB first. Note the differences between LSB clock, SCLK. The data can be transferred MSB first or LSB first and MSB first modes: both the instruction header and data are depending on the setting of the LSB first register bit. The write reversed, and the second data byte register location is different. operation is the same regardless of SDIO BiDir register setting. In the default MSB first mode, the second data byte is written to a decremented register address. In LSB first mode, the second data byte is written to an incremented register address. tDS tHI tCLK tH tS tDH tLO SEN SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W 2/1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE INSTRUCTION HEADER REGISTER DATA 03606-0-022 Figure 78. 1-Byte Serial Register Write in MSB First Mode tS tHI tH tLO tDH SEN tDS tCLK SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W 2/1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE INSTRUCTION HEADER (REGISTER N) REGISTER (N) DATA REGISTER (N–1) DATA 03606-0-023 Figure 79. 2-Byte Serial Register Write in MSB First Mode tS tDtSDH tLO tHI tCLK tH SEN SCLK DON'T CARE DON'T CARE SDIO DON'T CARE A0 A1 A2 A3 A4 A5 2/1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE INSTRUCTION HEADER (REGISTER N) REGISTER (N) DATA REGISTER (N+1) DATA 03606-0-024 Figure 80. 2-Byte Serial Register Write in LSB First Mode Rev. A | Page 43 of 51

AD9861 Data Sheet Read Operation The readback of registers can be a single or dual data byte operation. Three-wire operation can be configured by setting the SDIO The readback can be configured to use 3-wire or BiDir register. In 3-wire mode, the SDIO pin becomes an output 4-wire and can be formatted with MSB first or LSB first. The pin after receiving the 8-bit instruction header with a readback instruction header is written to the device either MSB or LSB first request. (depending on the mode) followed by the 8-bit output data Figure 81 shows a 4-wire SPI read with MSB first; Figure 82 (appropriately MSB or LSB justified). By default, the output data is shows a 3-wire read with MSB first; and Figure 83 shows a sent to the dedicated output pin (SDO). 4-wire read with LSB first. tS tDS tHI tCLK tH tDH tLO tDV SEN SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W 2/1 A5 A4 A3 A2 A1 A0 DON'T CARE INSTRUCTION HEADER SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE OUTPUT REGISTER DATA 03606-0-025 Figure 81. 1-Byte Serial Register Readback In MSB First Mode, SDIO BiDir Bit Set Logic Low (Default, 4-Wire Mode) tS tDS tHI tCLK tH SEN tDH tLO tDV SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W 2/1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE INSTRUCTION HEADER OUTPUT REGISTER DATA 03606-0-026 Figure 82. 1-Byte Serial Register Readback in MSB First Mode, SDIO BiDir Bit Set Logic High (Default, 3-Wire Mode) tS tDS tHI tCLK tH SEN tDH tLO tDV SCLK DON'T CARE DON'T CARE SDIO DON'T CARE A0 A1 A2 A3 A4 A5 2/1 R/W DON'T CARE INSTRUCTION HEADER SDO DON'T CARE D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE OUTPUT REGISTER DATA 03606-0-027 Figure 83. 1-Byte Serial Register Readback in LSB First Mode, SDIO BiDir Bit Set Logic Low (Default, 4-Wire Mode) Rev. A | Page 44 of 51

Data Sheet AD9861 CLOCK DISTRIBUTION BLOCK Table 21. PLL Input and Output Minimum and Maximum Theory/Description Clock Rates Input Clock Output Clock The AD9861 uses a clock distribution block to distribute the timing PLL Setting (Min/Max) (MHz) (Min/Max) (MHz) derived from the input clock (applied to the CLKIN pin, referred to 1× (PLL Bypassed) 1/200 1/200 here as CLKIN) to the Rx and Tx paths. There are many options for 1× (PLL Enabled) 32/200 32/200 configuring the clock distribution block, which are available through 2× 16/100 32/200 internal register settings. The Clock Distribution Block Diagram 4× 16/50 64/200 section describes the timing block diagram breakdown, followed by 8× 16/25 128/200 the data timing for the different data interface options. * 1/5 × 32/200 6.4/40 The clock distribution block contains a PLL, which includes an * 2/5 × 16/175 6.4/70 optional output divide-by-5 circuit, an ADC divide-by-2 circuit, * 4/5 × 16/87.5 12.8/70 multiplexers, and other digital logic. * 8/5 × 16/43.75 25.6/70 There are two main methods of configuring the Rx path timing of * 16/5 × 16/21.875 51.2/70 * Indicates PLL output divide-by-5 circuit enabled. the AD9861, normal timing mode and alternative timing mode, which are controlled through register Alt timing mode [Register Clock Distribution Block Diagram 0x15, Bit 4]. In normal timing mode, the Rx path clock is driven The Clock Distribution Block diagram is shown in Figure 84. directly from the CLKIN input and the Tx path is driven by a clock An output clock formatter configures the output synchroniza- derived from CLKIN multiplied by the on chip PLL. In alternative tion signals, IFACE1, IFACE2, and IFACE3. These interface pin timing mode, the input clock is applied to the PLL circuitry, and the signals depend on clock mode setting, data I/O configuration, PLL output clock drives both the Rx path clock and Tx path clock. and other operational settings. Clock mode and data I/O Because alternative timing mode uses the PLL to derive the Rx path configuration are defined in register settings of clk_mode, clock, the ADC performance may degrade slightly. This degradation SpiFDnHD, and SpiB10n20. is due to the phase noise from the PLL. Typically it occurs in Table 22 shows the configuration of the IFACE1, IFACE2 and undersampling applications when the input signal is above the first IFACE3 pins relative to clock mode (for half-duplex cases, the Nyquist zone of the ADC. IFACE1 pin is an input that identifies if the device is in Rx or Tx The PLL can provide 1×, 2×, 4×, 8×, and 16× multiplication or can be operation mode). The clock mode is used to specify the timing bypassed and powered down through register PLL bypass [Register for each data interface operation modes, which are discussed in 0x15, Bit 7] and through register PLL power-down [Register 0x2, Bit 2]. detail in the Flexible I/O Interface Options section. The T and R The PLL requires a minimum input clock frequency of 16 MHz and extensions after the half-duplex Modes 4, 5, 7, 8, and 10 in the needs to provide a minimum PLL output clock of 32 MHz. This limit Table 22 indicate that the device is in transmit or receive applies to the PLL output prior to the optional divide-by-5 circuitry. For operation mode. The default clock mode setting [Register 0x01, clock frequencies below these limits, the PLL must be bypassed. The Bits 5–7, clk_mode] of ‘000’ configures clock Mode 1 for the PLL maximum output frequency before the divide-by-5 circuitry is 350 full-duplex operation, Mode 4 for half-duplex 20 operation and MHz. Table 21 shows the input and output clock rates for all the Mode 7 for half-duplex 10 operation. Modes 2, 5, 8, and 10 are multiplication settings. optional timing configurations for the AD9861 that can be programmed through Register 0x01 clk_mode. Rev. A | Page 45 of 51

AD9861 Data Sheet 80MHz MAX CLKIN 1, 2 Rx Rx PATH DIGITAL 4 BLOCK IFACE2 1 OUTPUT CLOCK 1, 2, 4, 8, 16 1, 5 FORMATTER Tx IFACE3 Tx PATH DIGITAL 3 BLOCK 5 6 2 1. ALTERNATE TIMING MODE: REG 0x15, BIT 4 2. PLL MULTIPLICATION SETTING: REG 0x15, BITS 2–0 3456.... PRPINLLxTL LPE OBARYUTPHPT CAP DOUSINVSTTI DDPREAIOV TBILDH,Y E:T 2 RxB:E/ YRRG xE5 0;GI NxR V01Ex5 GI1,F 5B A0,I CxTB1E I75T3, , 5 BCILTK 3 MODE, INV IFACE2, FD/HD, 10/20 03606-0-067 Figure 84. Clock Distribution Block Diagram Table 22. Interface Pins (IFACE1, IFACE2, IFACE3) Configuration Definition for Flexible Interface Operation Clock 1 2 4T 4R 5T 5R 7T 7R 8T 8R 10T 10R Mode PIN Full-Duplex Half-Duplex, 20-Bit Half-Duplex, 10-Bit Clone Mode IFACE1 TxSync Tx/Rx Tx/Rx Tx/Rx IFACE2 Buff_CLKIN RxSync Optional CLKOUT Optional CLKOUT Optional CLKOUT IFACE3 Tx Clock Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Clock Clock Clock Clock Clock Clock Clock Clock Clock Clock The Tx clock output frequency depends on whether the data is in An optional CLKOUT from IFACE2 is available as a stable interleaved or parallel (noninterleaved) configuration. Modes 1, 2, 7, system clock running at the CLKIN frequency or the TxDAC 8, and 10 use Tx interleaved data and require either 2× or 4× update rate, which is equal to CLKIN × PLL setting. Setting the interpolation to be enabled. enable IFACE2 register [Register 0x01, Bit 2] enables the IFACE2 optional clock output. In FD mode, the IFACE2 pin • DAC update rate = CLKIN × PLL setting. always acts as a clock output; the enable IFACE2 pin can be • Noninterleaved Tx data clock frequency = CLKIN × PLL setting used to invert the IFACE2 output. × 1/(interpolation rate). Configuration • Interleaved Tx data clock frequency = 2 × CLKIN × PLL setting The AD9861 timing for the transmit path and for the receive × 1/(interpolation rate). path depend on the mode setting and various programmable The Rx clock does not depend on whether the data is interleaved or options. The registers that affect the output clock timing and parallel, but does depend on the configuration of the timing mode: data input/output timing are clk_mode [2:0]; enable IFACE2; normal or alternative. inv clkout (IFACE3); Tx inverse sample; interpolation control; • Normal timing mode, Rx clock frequency = CLKIN × ADC Div PLL bypass; ADC clock div; Alt timing mode; PLL Div5; PLL multiplication; and PLL to IFACE2. The clk_mode register is factor (if enabled). discussed previously. Table 23 shows the other register bits that • Alternative timing mode, Rx clock frequency = CLKIN × PLL are used to configure the output clock timing and data latching setting × ADC Div factor (if enabled). options available in the AD9861. Rev. A | Page 46 of 51

Data Sheet AD9861 Table 23. Serial Registers Related to the Clock Distribution Block Register Address, Register Name Bit(s) Function Enable IFACE2 Register 0x01, Bit 2 0: There is no clock output from IFACE2 pin, except in FD mode. 1: The IFACE2 pin outputs a continuous reference clock from the PLL output. In FD mode, this inverts the IFACE2 output. Inv clkout (IFACE3) Register 0x01, Bit 1 0: The IFACE3 clock output is not inverted. 1: The IFACE3 clock output is inverted. Tx Inverse Sample Register 0x13, Bit 5 0: The Tx path data is latched relative to the output Tx clock rising edge. 1: The Tx path data is latched relative to the output Tx clock falling edge. Interpolation Control Register 0x13, Bit 1:0 Sets interpolation of 1×, 2×, or 4× for the Tx path. PLL Bypass Register 0x15, Bit 7 0: The PLL block is used to generate system clock. 1: The PLL block is bypassed to generate system clock. ADC Clock Div Register 0x15, Bit 5 0: ADC clock rate equals the Rx path frequency. 1: ADC clock is one-half the Rx path frequency. Alt Timing Mode Register 0x15, Bit 4 0: CLKIN is used to drive the Rx path clock. 1: PLL block output is used to drive the Rx path clock. PLL Div5 Register 0x15, Bit 3 0: PLL block output clock is not divided down. 1: PLL block output clock is divided by 5. PLL Multiplier Register 0x15, Bit 2:0 Sets multiplication factor of the PLL block to 1× (000), 2× (001), 4× (010), 8× (011), or 16x (100). PLL to IFACE2 Register 0x16, Bit 5 0: If enable IFACE2 register is set, IFACE2 outputs buffered CLKIN. 1: If enable IFACE2 register is set, IFACE2 outputs buffered PLL output clock. Transmit (Tx) timing requires specific setup and hold times to Table 24. AD9861 Typical Tx Data Latch Timing Relative to properly latch data through the data interface bus. These timing IFACE3 Falling Edge parameters are specified relative to an internally generated output Mode No. Mode Name t (ns) t (ns) setup hold reference clock. The AD9861 has two interface clocks provided 1 FD 5 –2.5 through the IFACE3 and IFACE2 pins. The transmit timing 2 Optional FD 5 –2.5 specifications, setup and hold time, provide a minimum required 4 HD20 5 –1.5 window of valid data. 5 Optional HD20 5 –1.5 Setup time (t ) is the time required for data to initially settle to a SETUP 7 HD10 5 –2.5 valid logic level prior to the relative output timing edge. Hold time 8 Optional HD10 5 –2.5 (t ) is the time after the output timing edge that valid data must HOLD 10 Clone 5 –1.5 remain on the data bus to be properly latched. Figure 85 shows t SETUP and t relative to IFACE3 falling edge. Note that in some cases HOLD negative time is specified, for example with tHOLD timing, which Receive (Rx) path data is output after a reference output clock means that the hold time edge occurs before the relative output clock edge. The time delay of the Rx data relative to a reference edge. output clock is called the output delay, t . The AD9861 has two OD tSETUP possible interface clocks provided through the IFACE3 and IFACE2 pins. Figure 86 shows t relative to IFACE3 rising tHOLD OD edge. Note that in some cases negative time is specified, which IFACE3 (CLKOUT) means that the output data transition occurs prior to the relative Tx DATA output clock edge. 03606-0-028 Figure 85. Tx Data Timing Diagram tOD IFACE3 (CLKOUT) Table 24 shows typical setup-and-hold times for the AD9861 in the Rx DATA various mode configurations. 03606-0-029 Figure 86. Rx Data Timing Diagram Rev. A | Page 47 of 51

AD9861 Data Sheet Table 25 shows typical output delay times for the AD9861 in the various mode configurations. Table 25. AD9861 Rx Data Latch Timing Mode No. Mode Name t Data Delay [ns] Relative to: OD 1 FD +2.5 ns Relative to IFACE2 rising edge +1 ns Relative to IFACE3 rising edge 2 Optional FD +1 ns Relative To IFACE3 rising edge +2 ns IFACE2 (RxSYNC) relative to LSB 4 HD20 −1.5 ns Relative to IFACE3 rising edge 5 Optional HD20 −0.5 ns Relative to IFACE3 rising edge 7 HD10 −1.5 ns Relative to IFACE3 rising edge 8 Optional HD10 +0.5 ns Relative to IFACE3 rising edge +0 ns U12 (RxSYNC) relative to LSB 10 Clone +1.5 ns Relative to IFACE3 rising edge Configuration without Serial Port Interface (Using Mode Pins) The AD9861 can be configured using mode pins if a serial port interface is not available. This section applies only to configuring the AD9861 without an SPI. Refer is the Digital Block, Configuring with Mode Pins section for further information. When using the mode pin option, the pins shown in Table 26 are used to configured the AD9861. Table 26. Using Mode Pin (SPI Disabled) to Configure Timing (SPI_CS, Pin 64, Must Be Tied Low) Interpolation FD/HD 10/20 Interp1,Interp0 Clock Mode Setting PLL Setting Pin 3 Pin 17 Pin 1, Pin 2 Mode 1 (FD) 2× 2× 1 N/A1 0, 1 4× 4× 1, 0 Mode 4 (HD20) 1× Bypassed 0 0 0, 0 2× 2× 0, 1 4× 4× 1, 0 Mode 7 (HD10) 2× 2× 0 1 0, 1 4× 4× 1, 0 1 Pin 17 (IFACE2) is an output clock in FD mode. Rev. A | Page 48 of 51

Data Sheet AD9861 OUTLINE DIMENSIONS DETAIL A 9.10 (JEDEC 95) 9.00 SQ 0.30 8.90 0.25 PIN 1 0.18 INDICATOR PIN 1 4948 641 I(NSDEEIC DAETTAOIRL AAR)EA OPTIONS 0.50 7.25 BSC EXPOSED 7.10 SQ PAD 6.95 33 16 TOP VIEW 0.50 32 BOTTOM VIEW 17 0.25 MIN 0.40 7.50 REF 0.30 0.80 0.75 SIDE VIEW 0.05 MAX FTOHER EPXRPOOPSEERD C POANDN, ERCETFIEORN TOOF 0.70 0.02 NOM THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PKG-004351 PLANE COMPLIANT TO JEDEC S0.T2A0N RDEAFRDS MO-220-WMMD-4. 03-24-2017-B Figure 87. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm × 9 mm Body and 0.75 mm Package Height (CP-64-12) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9861BCPZ-50 –40°C to +85°C (Ambient) 64-Lead LFCSP CP-64-12 AD9861BCPZ-80 –40°C to +85°C (Ambient) 64-Lead LFCSP CP-64-12 AD9861BCPZRL-50 –40°C to +85°C (Ambient) 64-Lead LFCSP CP-64-12 AD9861BCPZRL-80 –40°C to +85°C (Ambient) 64-Lead LFCSP CP-64-12 1 Z = RoHS Compliant Part. Rev. A | Page 49 of 51

AD9861 Data Sheet NOTES Rev. A | Page 50 of 51

Data Sheet AD9861 NOTES ©2003–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03606-0-4/17(A) Rev. A | Page 51 of 51