a Mixed-Signal Front-End (MxFE™) Processor for Broadband Communications AD9860/AD9862* FEATURES FUNCTIONAL BLOCK DIAGRAM Mixed-Signal Front-End Processor with Dual Converter Receive and Dual Converter Transmit Signal Paths VIN+A Receive Signal Path Includes: 1x PGA ADC RxA DATA VIN–A [0:11] Two 10-/12-Bit, 64 MSPS Sampling A/D Converters BYPASSABLE LOW-PASS HILBERT DECIMATION FILTER FILTER with Internal or External Independent References, VIN+B Input Buffers, Programmable Gain Amplifiers, VIN–B 1x PGA ADC TrLaonwsm-Pita sSsi gDneacli mPaatthio nIn Fcillutderess,: and a Digital Hilbert Filter SIGDELT (cid:1)-(cid:2) AD9860/AD9862 LOGIC LOW R[0x:1B1 D]ATA Two 12-/14-Bit, 128 MSPS D/A Converters with Programmable Full-Scale Output Current, Channel AUX_DAC_A AUX DAC SPI REGISTERS SINPTIERFACE Independent Fine Gain and Offset Control, Digital AUX_DAC_B AUX DAC Hilbert and Interpolation Filters, and Digitally Tunable AUX_DAC_C AUX DAC Rx PATH Real or Complex Up-Converters TIMING CLOCK DLL OSC1 Delay-Locked Loop Clock Multiplier and Integrated Tx PATH DISTBRLIOBCUKTION 1(cid:3), 2(cid:3), 4(cid:3) OSC2 AUX_ADC_A1 TIMING Timing Generation Circuitry Allow for Single Crystal AUX_ADC_A2 AUX ADC or Clock Operation AUX_ADC_B1 AUX ADC CLKOUT1 Programmable Output Clocks, Serial Programmable AUX_ADC_B2 CLKOUT2 Interface, Programmable Sigma-Delta, Three Auxiliary BYPASSABLE BYPASSABLE DIGITAL DIGITAL DAC Outputs and Two Auxiliary ADCs with Dual QUADRATURE QUADRATURE MIXER MIXER Multiplexed Inputs IOUT+A PGA DAC IOUT–A HILBERT Tx DATA APPLICATIONS IOUT+B FILTER [0:13] PGA DAC Broadband Wireless Systems IOUT–B BrFoiaxdebda Wndir Weleirsesl,i nWe LSAyNst, eMmMsDS, LMDS FFSS//48 INBTYLEPORAWPS-OSPLAAASBTSLIOEN NCO FILTER Cable Modems, VDSL, PowerPlug Digital Communications Set-Top Boxes, Data Modems range for both channels. The output data bus can be multi- plexed to accommodate a variety of interface types. GENERAL DESCRIPTION The AD9860/AD9862 transmit path (Tx) consists of two chan- The AD9860 and AD9862 (AD9860/AD9862) are versatile nels that contain high performance, 12-/14-bit, 128 MSPS integrated mixed-signal front-ends (MxFE) that are optimized digital-to-analog converters (DAC), programmable gain amplifiers for broadband communication markets. The AD9860/AD9862 (TxPGA), interpolation filters, a Hilbert filter, and digital mixers are cost effective, mixed signal solutions for wireless or wireline for complex or real signal frequency modulation. The Tx latch standards based or proprietary broadband modem systems where and demultiplexer circuitry can process real or I/Q data. Interpo- dynamic performance, power dissipation, cost, and size are all lation rates of 2(cid:1) and 4(cid:1) are available to ease requirements on critical attributes. The AD9860 has 10-bit ADCs and 12-bitDACs; an external reconstruction filter. For single channel systems, the the AD9862 has 12-bit ADCs and 14-bit DACs. digital Hilbert filter can be used with an external quadrature modulator to create an image rejection architecture. The two The AD9860/AD9862 receive path (Rx) consists of two channels 12-/14-bit, high performance DACs produce an output signal that each include a high performance, 10-/12-bit, 64 MSPS analog- that can bescaled over a 20 dB range by the TxPGA. to-digital converter (ADC), input buffer, Programmable Gain Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The A programmable delay-locked loop (DLL) clock multiplier and Rx can be used to receive real, diversity, or I/Q data at baseband or integrated timing circuits enable the use of a single external low IF. The input buffers provide a constant input impedance for reference clock or an external crystal to generate clocking for all both channels to ease impedance matching with external com- internal blocks and also provides two external clock outputs. ponents (e.g., SAW filter). The RxPGA provides a 20dB gain Additional features include a programmable sigma-delta output, four auxiliary ADC inputs and three auxiliary DAC outputs. *Protected by U.S.Patent No. Device programmability is facilitated by a serial port interface MxFE is a trademark of Analog Devices, Inc. (SPI) combined with a register bank. The AD9860/AD9862 is available in a space saving 128-lead LQFP. REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD9860/AD9862–SPECIFICATIONS(V = 3.3 V (cid:4) 5%, V = 3.3 V (cid:4) 10%, f = 128 MHz, f = 64 MHz A D DAC ADC Normal Timing Mode, 2(cid:3) DLL Setting, R = 4 k(cid:5), 50 (cid:5) DAC Load, SET RxPGA = +6 dB Gain, TxPGA = +20 dB Gain.) Test AD9860/AD9862 Tx PARAMETERS Temp Level Min Typ Max Unit 12-/14-BIT DAC CHARACTERISTICS Resolution NA NA 12/14 Bits Maximum Update Rate 128 MSPS Full-Scale Output Current Full I 2 20 mA Gain Error (Using Internal Reference) 25ºC I –5.5 +0.5 +5.5 %FS Offset Error 25ºC I –1 0.0 +1 %FS Reference Voltage (REFIO Level) 25ºC I 1.15 1.22 1.28 V Negative Differential Nonlinearity (–DNL) 25ºC III –0.5/–0.5 LSB Positive Differential Nonlinearity (+DNL) 25ºC III 1/2 LSB Integral Nonlinearity (INL) 25ºC III –1/–3 LSB Output Capacitance 25ºC III 5 pF Phase Noise @ 1 kHz Offset, 6 MHz Tone Crystal and OSC IN Multiplier Enabled at 4(cid:1) 25ºC III –115 dBc/Hz Output Voltage Compliance Range Full II –0.5 +1.5 V TRANSMIT TxPGA CHARACTERISTICS Gain Range 25ºC III 20 dB Step Size Accuracy 25ºC III –0.1 dB Step Size 25ºC III 0.08 dB Tx DIGITAL FILTER CHARACTERISTICS Hilbert Filter Pass Band (<0.1 dB Ripple) Full II 12.5 38 % f 1 DATA 2(cid:1)/4(cid:1) Interpolator Stop Band2 Full II –38 % fDATA DYNAMIC PERFORMANCE (A = 20 mA FS, f = 1 MHz) OUT Differential Phase 25ºC III <0.1 Degree Differential Gain 25ºC III <1 LSB AD9860 Signal-to-Noise Ratio (SNR) Full I 68.2 70.7 dB AD9860 Signal-to-Noise and Distortion Ratio Full I 62.5 66.1 dB AD9860 Total Harmonic Distortion (THD) Full I –74.5 –64.0 dB AD9860 Wideband SFDR (to Nyquist) 1 MHz Analog Out, I = 2 mA 25ºC III 70.6 dBc OUT 1 MHz Analog Out, I = 20 mA 25ºC I 64.4 75 dBc OUT 6 MHz Analog Out, I = 20 mA 25ºC III 75 dBc OUT AD9860 Narrowband SFDR (1 MHz Window) 1 MHz Analog Out, I = 2 mA 25ºC III 70.2 dBc OUT 1 MHz Analog Out, I = 20 mA 25ºC I 83 90 dBc OUT AD9862 Signal-to-Noise Ratio (SNR) Full I 68.9 72.0 dB AD9862 Signal-to-Noise and Distortion Ratio Full I 64.75 69.8 dB AD9862 Total Harmonic Distortion (THD) Full I –75.5 –65.0 dB AD9862 Wideband SFDR (to Nyquist) 1 MHz Analog Out, I = 2 mA 25ºC III 70.6 dBc OUT 1 MHz Analog Out, I = 20 mA 25ºC I 64.9 76.0 dBc OUT 6 MHz Analog Out, I = 20 mA 25ºC III 76.0 dBc OUT AD9862 Narrowband SFDR (1 MHz Window) 1 MHz Analog Out, I = 2 mA 25ºC III 70.2 dBc OUT 1 MHz Analog Out, I = 20 mA 25ºC I 83 90 dBc OUT Rx PARAMETERS RECEIVE BUFFER Input Resistance (Differential) Full III 200 W Input Capacitance (Each Input) Full III 5 pF Maximum Input Bandwidth (–3 dB) Full III 140 MHz Analog Input Range (Best Noise Performance) Full II 2 V p-p Diff Analog Input Range (Best THD Performance) Full II 1 V p-p Diff RECEIVE PGA CHARACTERISTICS Gain Error 25ºC I –0.3 dB Gain Range 25ºC I 19 20 21 dB Step Size Accuracy 25ºC I –0.2 dB Step Size 25ºC I 1 dB Input Bandwidth (–3 dB, Rx Buffer Bypassed) 25ºC III 250 MHz 10-/12-BIT ADC CHARACTERISTICS Resolution NA NA 10/12 Bits Maximum Conversion Rate Full I 64 MHz –2– REV. 0

AD9860/AD9862 Test AD9860/AD9862 Rx PARAMETERS (continued) Temp Level Min Typ Max Unit DC ACCURACY Differential Nonlinearity 25ºC III –0.3/–0.4 LSB Integral Nonlinearity 25ºC III –1.2/–5 LSB Offset Error 25ºC III –0.1 %FSR Gain Error 25ºC III –0.2 %FSR Aperture Delay 25ºC III 2.0 ns Aperture Uncertainty (Jitter) 25ºC III 1.2 ps rms Input Referred Noise 25ºC III 250 µV Reference Voltage Error REFT-REFB Error (1 V) 25ºC I –1 –4 mV AD9860 DYNAMIC PERFORMANCE (A = –0.5 dBFS, f = 5 MHz) IN Signal-to-Noise Ratio 25∞C I 59.0 60.66 dBc Signal-to-Noise and Distortion Ratio 25∞C I 56.0 58.0 dBc Total Harmonic Distortion 25∞C I –76.5 –70.5 dBc Spurious Free Dynamic Range 25∞C I 70.3 81.0 dBc AD9862 DYNAMIC PERFORMANCE (A = –0.5 dBFS, f = 5 MHz) IN Signal-to-Noise Ratio 25∞C I 62.6 64.2 dBc Signal-to-Noise and Distortion Ratio 25∞C I 62.5 64.14 dBc Total Harmonic Distortion 25∞C I –79.22 –73.2 dBc Spurious Free Dynamic Range 25∞C I 77.09 85.13 dBc CHANNEL-TO-CHANNEL ISOLATION Tx-to-Rx (A = 0 dBFS, f = 7 MHz) 25ºC III >90 dB OUT OUT Rx Channel Crosstalk (f = 6 MHz, f = 9 MHz) 25ºC III >80 dB 1 2 PARAMETERS CMOS LOGIC INPUTS Logic “1” Voltage, V 25ºC II DRVDD – 0.7 V IH Logic “0” Voltage, V 25ºC II 0.4 V IL Logic “1” Current 25ºC II 12 µA Logic “0” Current 25ºC II 12 µA Input Capacitance 25ºC III 3 pF CMOS LOGIC OUTPUTS (1 mA Load) Logic “1” Voltage, V 25ºC II DRVDD – 0.6 V OH Logic “0” Voltage, V 25ºC II 0.4 V OL POWER SUPPLY Analog Supply Currents Tx (Both Channels, 20 mA FS Output) 25ºC I 70 76 mA Tx Powered Down 25ºC I 2.5 5.0 mA Rx (Both Channels, Input Buffer Enabled) 25ºC I 275 307 mA Rx (Both Channels, Input Buffer Disabled) 25ºC III 245 mA Rx (32 MSPS, Low Power Mode, Buffer Disabled) 25ºC III 155 mA Rx (16 MSPS, Low Power Mode, Buffer Disabled) 25ºC III 80 mA Rx Path Powered Down 25ºC I 5.0 6.0 mA DLL 25ºC III 12 mA Digital Supply Current AD9860 Both Rx and Tx Path (All Channels Enabled) 2(cid:1) Interpolation, f = f = 64 MSPS 25ºC I 92 112 mA DAC ADC AD9862 Both Rx and Tx Path (All Channels Enabled) 2(cid:1) Interpolation, f = f = 64 MSPS 25ºC I 104 124 mA DAC ADC Tx Path (f = 128 MSPS) DAC Processing Blocks Disabled 25ºC III 45 mA 4(cid:1) Interpolation 25ºC III 90 mA 4(cid:1) Interpolation, Coarse Modulation 25ºC III 110 mA 4(cid:1) Interpolation, Fine Modulation 25ºC III 110 mA 4(cid:1) Interpolation, Coarse and Fine Modulation 25ºC III 130 mA REV. 0 –3–

AD9860/AD9862 Test AD9860/AD9862 PARAMETERS (continued) Temp Level Min Typ Max Unit POWER SUPPLY (continued) Rx Path (f = 64 MSPS) ADC Processing Blocks Disabled 25ºC III 9 mA Decimation Filter Enabled 25ºC III 15 mA Hilbert Filter Enabled 25ºC III 16 mA Hilbert and Decimation Filter Enabled 25ºC III 18.5 mA NOTES 1% f refers to the input data rate of the digital block. DATA 2Interpolation filter stop band is defined by image suppression of 50 dB or greater. Specifications subject to change without notice. TIMING CHARACTERISTICS Test AD9860/AD9862 (20 pF Load) Temp Level Min Typ Max Unit Minimum Reset Pulsewidth Low (t ) NA NA 5 ClockCycles RL Digital Output Rise/Fall Time 25ºC III 2.8 4 ns DLL Output Clock 25ºC III 32 128 MHz DLL Output Duty Cycle 25ºC III 50 % Tx–/Rx–Interface (See Figures 11 and 12) TxSYNC/TxIQ Setup Time (t , t ) 25ºC III 3 ns Tx1 Tx3 TxSYNC/TxIQ Hold Time (t , t ) 25ºC III 3 ns Tx2 Tx4 RxSYNC/RxIQ/IF to Valid Time(t , t ) 25ºC III 5.2 ns Rx1 Rx3 RxSYNC/RxIQ/IF Hold Time (t , t ) 25ºC III 0.2 ns Rx2 Rx4 Serial Control Bus(See Figures 1 and 2) Maximum SCLK Frequency (f ) Full III 16 MHz SCLK Minimum Clock Pulsewidth High (t ) Full III 30 ns HI Minimum Clock Pulsewidth Low (t ) Full III 30 ns LOW Maximum Clock Rise/Fall Time Full III 1 ms Minimum Data/SEN Setup Time (t ) Full III 25 ns S Minimum SEN/Data Hold Time (t ) Full III 0 ns H Minimum Data/SCLK Setup Time (t ) Full III 25 ns DS Minimum Data Hold Time (t ) Full III 0 ns DH Output Data Valid/SCLK Time (t ) Full III 30 ns DV AUXILARY ADC Conversion Rate 25ºC III 1.25 MHz Input Range 25ºC III 3 V Resolution 25ºC III 10 Bits AUXILARY DAC Settling Time 25ºC III 8 ms Output Range 25ºC III 3 V Resolution 25ºC III 8 Bits ADC TIMING Latency (All Digital Processing Blocks Disabled) 25ºC III 7 Cycles DAC Timing Latency (All Digital Processing Blocks Disabled) 25ºC III 3 Cycles Latency (2(cid:1) Interpolation Enabled) 25ºC III 30 Cycles Latency (4(cid:1) Interpolation Enabled) 25ºC III 72 Cycles Additional Latency (Hilbert Filter Enabled) 25ºC III 36 Cycles Additional Latency (Coarse Modulation Enabled) 25ºC III 5 Cycles Additional Latency (Fine Modulation Enabled) 25ºC III 8 Cycles Output Settling Time (TST) (to 0.1%) 25ºC III 35 ns Specifications subject to change without notice. –4– REV. 0

AD9860/AD9862 ABSOLUTE MAXIMUM RATINGS1 EXPLANATION OF TEST LEVELS Power Supply (V , V ) . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V I. Devices are 100% production tested at 25ºC and guaranteed AS DS Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA by design and characterization testing for the extended Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V industrial temperature range (–40ºC to +70ºC). Analog Inputs . . . . . . . . . . . . . .–0.3 V to AVDD (IQ) + 0.3 V II. Parameter is guaranteed by design and/or characterization Operating Temperature2 . . . . . . . . . . . . . . . . .–40(cid:6)C to +70(cid:6)C testing. Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150(cid:6)C Storage Temperature . . . . . . . . . . . . . . . . . . .–65(cid:6)C to +150(cid:6)C III. Parameter is a typical value only. Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300(cid:6)C NA. Test level definition is not applicable. NOTES 1Absolute maximum ratings are limiting values, to be applied individually, and THERMAL CHARACTERISTICS beyond which the serviceability of the circuit may be impaired. Functional operability Thermal Resistance under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device 128-Lead LQFP (cid:2)JA = 29ºC/W reliability. 2The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40(cid:6)C to +85(cid:6)C) when operated in Half Duplex Mode. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9860BST –40∞C to +70∞C* 128-Lead Low Profile Plastic Quad Flatpack (LQFP) ST-128B AD9862BST –40∞C to +70∞C* 128-Lead Low Profile Plastic Quad Flatpack (LQFP) ST-128B AD9860PCB Evaluation Board with AD9860 AD9862PCB Evaluation Board with AD9862 *The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40(cid:6)C to +85(cid:6)C) when operated in Half Duplex Mode. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9860/AD9862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5–

AD9860/AD9862 PIN CONFIGURATION F 2 E 1 2 A R B B _ _ _ _ C C C C D D D D A A AUX_A AUX_A AUX_A AUX_A AVDD AVDD AGND REFT_ REFB_ AGND AVDD AVDD AGND VIN+A VIN–A AGND AGND VREF AGND AGND VIN–B VIN+B AGND AVDD AVDD AGND 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 AUX_ADC_A1 1 102 REFB_B AGND 2 PIN 1 101 REFT_B IDENTIFIER AVDD 3 100 AGND AVDD 4 99 AVDD SIGDELT 5 98 AVDD AUX_DAC_A 6 97 AUX_SPI_csb AUX_DAC_B 7 96 AUX_SPI_clk AUX_DAC_C 8 95 AUX_SPI_do AGND 9 94 DGND DLL_Lock 10 93 DVDD AGND 11 92 RxSYNC NC 12 91 D9/D11B (MSB) AVDD 13 90 D8/D10B OSC1 14 89 D7/D9B OSC2 15 88 D6/D8B AGND 16 87 D5/D7B CLKSEL 17 AD9860/AD9862 86 D4/D6B AVDD 18 TOP VIEW 85 D3/D5B AGND 19 (Not to Scale) 84 D2/D4B AVDD 20 83 D1/D3B REFIO 21 82 D0/D2B FSADJ 22 81 NC/D1B AVDD 23 80 NC/D0B AGND 24 79 D9/D11A (MSB) IOUT–A 25 78 D8/D10A IOUT+A 26 77 D7/D9A AGND 27 76 D6/D8A AGND 28 75 D5/D7A IOUT+B 29 74 D4/D6A IOUT–B 30 73 D3/D5A AGND 31 72 D2/D4A AVDD 32 71 D1/D3A DVDD 33 70 D0/D2A DGND 34 69 NC/D1A DGND 35 68 NC/D0A DVDD 36 67 DGND Tx11/13 (MSB) 37 66 DVDD Tx10/12 38 65 CLKOUT1 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 9 87 65 4 32 10 C D D K O O N D D D D K B 2 Tx9/1Tx8/1 Tx7/ Tx6/Tx5/ Tx4/Tx3/ Tx2/ Tx1/Tx0/ NC/TxNC/Tx xSYN DGN DVD SCL SD SDI SE DGN DVD DGN DVD BLAN ESET KOUT T Tx R CL E/ D O M NC = NO CONNECT –6– REV. 0

AD9860/AD9862 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function Pin No. Mnemonic Function Receive Pins Clock Pins 68/70–79 D0A to 10-/12-Bit ADC Output of 10 DLL_Lock DLL Lock Indicator Pin D9A/D11A Receive Channel A 11, 16 AGND DLL Analog Ground Pins 80/82–91 D0B to 10-/12-Bit ADC Output of 12 NC No Connect D9B/D11B Receive Channel B 13 AVDD DLL Analog Supply Pin 92 RxSYNC Synchronization Clock for 14 OSC1 Single Ended Input Clock Channel A and Channel B Rx Paths (or Crystal Oscillator Input) 98, 99, AVDD Analog Supply Pins 15 OSC2 Crystal Oscillator Input 104, 105, 17 CLKSEL Controls CLKOUT1 Rate 117, 118, 64 CLKOUT2 Clock Output Generated from Input 123, 124, Clock (DLL Multiplier Setting 100, 103, AGND Analog Ground Pins and CLKOUT2 Divide Factor) 106, 109, 65 CLKOUT1 Clock Output Generated from 110, 112, Input Clock (1(cid:1) if CLKSEL = 1 113, 116, 119, 122, or /2 if CLKSEL = 0) 101 REFT_B Top Reference Decoupling for Various Pins Channel B ADC 1 AUX_ADC_A1 Auxiliary ADC A Input 1 102 REFB_B Bottom Reference Decoupling 3, 4, 13 AVDD Analog Power Pins for Channel B ADC 2, 9 AGND Analog Ground Pins 107 VIN+B Receive Channel B Differential (+) Input 5 SIGDELT Digital Output from 108 VIN–B Receive Channel B Differential ((cid:7)) Input Programmable Sigma-Delta 111 VREF Internal ADC Voltage Reference 6 AUX_DAC_A Auxiliary DAC A Output 114 VIN–A Receive Channel A Differential ((cid:7)) Input 7 AUX_DAC_B Auxiliary DAC B Output 115 VIN+A Receive Channel A Differential (+) Input 8 AUX_DAC_C Auxiliary DAC C Output 120 REFB_A Bottom Reference Decoupling for 33, 36, 53, DVDD Digital Power Supply Pin Channel A ADC 59, 61, 66, 121 REFT_A Top Reference Decoupling for 93 Channel A ADC 34, 35, 52, DGND Digital Ground Pin Transmit Pins 58, 60, 67, 94 18, 20 AVDD Analog Supply Pins 54 SCLK Serial Bus Clock Input 23, 32 55 SDO Serial Bus Data Bit 19, 24, AGND Analog Ground Pins 27, 28, 31 56 SDIO Serial Bus Data Bit 21 REFIO Reference Output, 1.2 V Nominal 57 SEN Serial Bus Enable 22 FSADJ Full-Scale Current Adjust 63 RESETB Reset (SPI Registers and Logic) 25 IOUT–A Transmit Channel A DAC 95 AUX_SPI_do Optional Auxiliary ADC Serial Bus Differential ((cid:7)) Output Data Out Bit 26 IOUT+A Transmit Channel A DAC 96 AUX_SPI_clk Optional Auxiliary ADC Serial Bus Differential (+) Output Data Out Latch Clock 29 IOUT+B Transmit Channel B DAC 97 AUX_SPI_csb Optional Auxiliary ADC Serial Bus Differential (+) Output Chip Select Bit 30 IOUT–B Transmit Channel B DAC 128 AUX_ADC_A2 Auxiliary ADC A Input 2 Differential ((cid:7)) Output 126 AUX_ADC_B1 Auxiliary ADC B Input 1 37–48/50 Tx11/Tx13 12-/14-Bit Transmit DAC Data 125 AUX_ADC_B2 Auxiliary ADC B Input 2 to Tx0 (Interleaved Data when Required) 127 AUX_ADC_REF Auxiliary ADC Reference 51 TxSYNC Synchronization Input for Transmitter 62 MODE/ Configures Default Timing Mode, TxBLANK* Controls Tx Digital Power Down *The logic level of the Mode/TxBLANK pin at power up defines the default timing mode; a logic low configures Normal Operation, logic high configures Alternate Operation Mode. REV. 0 –7–

AD9860/AD9862 DEFINITIONS OF SPECIFICATIONS Aperture Delay Differential Nonlinearity Error (DNL, No Missing Codes) The aperture delay is a measure of the Sample-and-Hold Ampli- An ideal converter exhibits code transitions that are exactly 1LSB fier (SHA) performance and specifies the time delay between the apart. DNL is the deviation from this ideal value. Guaranteed no rising edge of the sampling clock input to when the input signal missing codes to 10-bit resolution indicate that all 1024 codes is held for conversion. respectively, must be present over all operating ranges. Aperture Uncertainty (Jitter) Integral Nonlinearity Error (INL) Aperture jitter is the variation in aperture delay for successive Linearity error refers to the deviation of each individual code from samples and is manifested as noise on the input to the ADC. a line drawn from “negative full scale” through “positive full Input Referred Noise scale.” The point used as “negative full scale” occurs 1/2LSB The rms output noise is measured using histogram techniques. before the first code transition. “Positive full scale” is defined as The ADC output code’s standard deviation is calculated in LSB a level 1 1/2 LSB beyond the last code transition. The deviation and converted to an equivalent voltage. This results in a noise is measured from the middle of each particular code to the true figure that can be referred directly to the input of the AD9860/ straight line. AD9862. Phase Noise Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio Single-sideband phase noise power is specified relative to the S/N+D is the ratio of the rms value of the measured input signal carrier (dBc/Hz) at a given frequency offset (1 kHz) from the to the rms sum of all other spectral components below the Nyquist carrier. Phase noise can be measured directly in Single Tone Trans- frequency, including harmonics but excluding dc. The value for mit Mode with a spectrum analyzer that supports noise marker S/N+D is expressed in decibels. measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number bandwidth (rbw) into account by subtracting 10 log(rbw). It also of bits. Using the following formula: adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. (SINAD–1.76dB) Output Compliance Range N = 6.02 The range of allowable voltage at the output of a current-output it is possible to get a measure of performance expressed as N, DAC. Operation beyond the maximum compliance limits may the effective number of bits. Thus, effective number of bits for cause either output stage saturation or breakdown, resulting in adevice for sine wave inputs at a given input frequency can be nonlinear performance. calculated directly from its measured SINAD. Spurious-Free Dynamic Range (SFDR) Signal-to-Noise Ratio (SNR) The difference, in dB, between the rms amplitude of the DAC’s SNR is the ratio of the rms value of the measured input signal to output signal (or ADC’s input signal) and the peak spurious the rms sum of all other spectral components below the Nyquist signal over the specified bandwidth (Nyquist bandwidth unless frequency, excluding harmonics and dc. The value for SNR is otherwise noted). expressed in decibels. Pipeline Delay (Latency) Total Harmonic Distortion (THD) The number of clock cycles between conversion initiation and THD is the ratio of the rms sum of the first six harmonic the associated output data being made available. components to the rms value of the measured input signal and Offset Error is expressed as a percentage or in decibels. First transition should occur for an analog value 1/2 LSB above Power Supply Rejection –full scale. Offset error is defined as the deviation of the actual Power supply rejection specifies the converter’s maximum full-scale transition from that point. change when the supplies are varied from nominal to minimum Gain Error and maximum specified voltages. The first code transition should occur at an analog value 1/2LSB Channel-to-Channel Isolation (Crosstalk) above –full scale. The last transition should occur for an analog In an ideal multichannel system, the signal in one channel will value 1 1/2 LSB below the nominal full scale. Gain error is the not influence the signal level of another channel. The channel- deviation of the actual difference between first and last code to-channel isolation specification is a measure of the change that transitions and the ideal difference between first and last code occurs to a grounded channel as a full-scale signal is applied to transitions. another channel. –8– REV. 0

Typical Performance Characteristics–AD9860/AD9862 0 0 0 –10 f4D(cid:3)A TIAN T=E 3R2PMOSLPASTION –10 f4D(cid:3)A TIAN T=E 3R2PMOSLPASTION –10 f4D(cid:3)A TIAN T=E 3R2PMOSLPASTION –20 –20 –20 m–30 m–30 m–30 B B B UDE – d––4500 UDE – d––4500 UDE – d––5400 NIT–60 NIT–60 NIT–60 G G G MA–70 MA–70 MA–70 –80 –80 –80 –90 –90 –90 –100 –100 –100 0 20 40 60 80 100 110 120 140 0 20 40 60 80 100 110 120 140 0 20 40 60 80 100 110 120 140 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz TPC 1.AD9862 Tx Output 6 MHz TPC 2.AD9862 Tx Output 6 MHz TPC 3.AD9862 Tx Output 6 MHz Single Tone; CLKIN = 32 MHz; Single Tone; CLKIN = 64 MHz; Single Tone; CLKIN = 128 MHz; DLL 4(cid:1) Setting DLL 2(cid:1) Setting DLL 1(cid:1) Setting 0 0 0 fDATA = 32MSPS fDATA = 32MSPS fDATA = 32MSPS –20 1(cid:3) INTERPOLATION –20 4(cid:3) INTERPOLATION –20 4(cid:3) INTERPOLATION MAGNITUDE – dBm–––468000 MAGNITUDE – dBm–––468000 MAGNITUDE – dBm–––468000 –100 –100 –100 –120 –120 –120 0 20 40 60 80 100 110 120 140 0 20 40 60 80 100 110 120 140 7.907.927.947.967.988.008.028.048.068.08 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz TPC 4.TxDAC Generating an TPC 5.TxDAC Generating an TPC 6.Zoomed in Plot of Four OFDM Signal; CLKIN = 64 MHz, OFDM Signal; CLKIN = 64 MHz, Notched Carriers of OFDM Signal; DLL 2(cid:1) Setting DLL 2(cid:1) Setting CLKIN = 64 MHz, DLL 2(cid:1) Setting –60 T2HndD f2D(cid:3)A TIAN T=E 6R4PMOSLPASTION 74 f2D(cid:3)A TIAN T=E 6R4PMOSLPASTION ––5505 f2D(cid:3)A TIAN T=E 6R4PMOSLPASTION –65 3rd 73 AD9862 –60 –70 72 –65 THD – dBc–75 SNR – dB71 IMD – dBc––7705 –80 70 –80 AD9860 –85 –85 69 AVDD = 3.0V –90 AVDD = 3.3V AVDD = 3.6V –90 68 –95 5 10 15 20 25 30 35 0 5 10 15 20 25 30 5 10 15 20 25 30 fOUT – MHz FREQUENCY – MHz CARRIER FREQUENCY – MHz TPC 7.TxDAC Harmonic TPC 8.Signal-to-Noise Ratio (SNR) TPC 9.Two Tone Intermodulation Distortion vs. fOUT vs. fOUT vs. fOUT1 (fOUT2 = fOUT1 + 1 MHz) REV. 0 –9–

AD9860/AD9862 0 0 0 –20 –20 –20 S S S F F F B B B – d–40 – d–40 – d–40 E E E D D D TU–60 TU–60 TU–60 NI NI NI G G G A A A M–80 M–80 M–80 T T T F F F F F F –100 –100 –100 –120 –120 –120 0 5 10 15 20 25 30 0 5 10 15 20 25 30 0 5 10 15 20 25 30 FFT OUTPUT – MHz FFT OUTPUT – MHz FFT OUTPUT – MHz TPC 10.ADC Dual Tone FFT with TPC 11.ADC Dual Tone FFT without TPC 12.ADC Dual Tone FFT Buffer Tones at 4.5 MHz and 5.5 MHz Buffer Tones at 4.5 MHz and 5.5 MHz (undersampling) without Buffer Tones at 69.5 MHz and 70.5 MHz 68 11.0 70 70 LOW POWER MODE 1, BUFFER BYPASSED, LOW POWER MODE 2, BUFFER BYPASSED, 66 BUFFERED BYPASS 68 2V p-p INPUT, 1(cid:3) RxPGA GAIN 68 2V p-p INPUT, 1(cid:3) RxPGA GAIN 2V INPUT, 1(cid:3) GAIN 10.5 66 BUFFER BYPASSED, 2V p-p, 66 BUFFER BYPASSED, 2V p-p, 64 1(cid:3) RxPGA GAIN 1(cid:3) RxPGA GAIN 64 64 62 10.0 LOW POWER MODE 1, BUFFER LOW POWER MODE 2, BUFFER 60 B1VU FINFPEURTE, D2(cid:3) B YGPAAINSS 9.5 D – dBc6602 E2(cid:3)N ARBxLPEGDA, 1GVA pIN-p INPUT, D – dBc6602 E2(cid:3)N ARBxLPEGDA, 1GVA pIN-p INPUT, 58 A A N58 N58 SI SI 56 9.0 56 56 54 BUFFERED 8.5 54 BUFFER ENABLED, 54 BUFFER ENABLED, 5520 21V(cid:3) IGNAPIUNT , BINUPFUFTE, R 2E(cid:3)D G 1AVIN 8.0 5502 12V(cid:3) pR-xpP IGNPAU GTA,IN 5502 12V(cid:3) pR-xpP IGNPAU GTA,IN 0 50 100 150 200 250 300 0 50 100 150 200 250 300 0 50 100 150 200 250 300 fIN – MHz fIN – MHz fIN – MHz TPC 13.AD9862 Rx SINAD TPC 14.AD9862 Rx SINAD TPC 15.AD9862 Rx SINAD vs. fIN at 64 MSPS vs. fIN at 32 MSPS vs. fIN at 16 MSPS 62 10.0 62 62 LOW POWER MODE 1, BUFFER BYPASSED, LOW POWER MODE 2, BUFFER BYPASSED, 60 60 2V p-p INPUT, 1(cid:3) RxPGA GAIN 60 2V p-p INPUT, 1(cid:3) RxPGA GAIN 58 B1VU FINFPEURTE, D2(cid:3) B YGPAAINSS 9.5 58 B1(cid:3)U FRFxEPRG BAY GPAAISNSED, 2V p-p, 58 B1(cid:3)U FRFxEPRG BAY GPAAISNSED, 2V p-p, 56 9.0 56 56 c c B B 54 8.5 D – d54 D – d54 52 A52 A52 BUFFERED 1V N N 50 BUFFERED 2V INPUTB, U 2F(cid:3)F EGRAEIND BYPASS 8.0 SI50 SI50 48 INPUT, 1(cid:3) GAIN 2V INPUT, 1(cid:3) GAIN 7.5 48 LMBOUOWFDF EPE O1R,W EENRABLED, B1VU FpF-pE RIN EPNUAT,BLED, 48 LMBOUOWFDF EPE O2R,W EENRABLED, B1VU FpF-pE RIN EPNUAT,BLED, 46 46 1V p-p INPUT, 2(cid:3) RxPGA GAIN 46 1V p-p INPUT, 2(cid:3) RxPGA GAIN 44 7.0 44 2(cid:3) RxPGA GAIN 44 2(cid:3) RxPGA GAIN 0 50 100 150 200 250 300 0 50 100 150 200 250 300 0 50 100 150 200 250 300 fIN – MHz fIN – MHz fIN – MHz TPC 16.AD9860 Rx SINAD TPC 17.AD9860 Rx SINAD TPC 18.AD9860 Rx SINAD vs. fIN at 64 MSPS vs. fIN at 32 MSPS vs. fIN at 16 MSPS –10– REV. 0

AD9860/AD9862 –50 –50 AD9860 LOW POWER AD9862 LOW POWER –50 AD9860 LOW POWER AD9862 –55 B2VU FINFPEURTE, D1(cid:3) B YGPAAINSS –55 MENOADBEL 1E, DB,UFFER MODE E1N, BAUBFLFEEDR, –55 MENOADBEL 2E, DB,UFFER LOWM POODWEE 2R, –60 BINUPFUFTE, R 1E(cid:3)D G 2AVIN –60 12V(cid:3) pR-xpP IGNPAU GTA,IN 2(cid:3)1 RVx pP-GpA IN GPAUITN, –60 12V(cid:3) pR-xpP IGNPAU GTA,IN ENBAUBFLFEEDR, –65 1V p-p INPUT, –65 –65 2(cid:3) RxPGA GAIN Bc–70 Bc Bc D – d–75 D – d–70 D – d–70 TH–80 BUFFERED 1V TH–75 ABUDF98F6E0R L BOYWP APSOSWEEDR, 2 MVO pD-pE I N1,PUT, TH–75 ABUDF98F6E0R L BOYWP APSOSWEEDR, 2 MVOp-DpE IN 2P,UT, –85 INPUT, 2(cid:3) GAIN 1(cid:3) RxPGA GAIN 1(cid:3) RxPGA GAIN BUFFERED BYPASS –80 –80 –90 1V INPUT, 2(cid:3) GAIN AD9862 LOW POWER MODE 1, AD9862 LOW POWER MODE 2, –85 BUFFER BYPASSED, 2V p-p INPUT, –85 BUFFER BYPASSED, 2V p-p INPUT, –95 1(cid:3) RxPGA GAIN 1(cid:3) RxPGA GAIN –100 –90 –90 0 10 100 1000 0 50 100 150 200 250 300 0 50 100 150 200 250 300 INPUT FREQUENCY – MHz fIN – MHz fIN – MHz TPC 19.Rx THD vs. f , TPC 20.Rx THD vs. f , TPC 21.Rx THD vs. f , IN IN IN FADC = 64 MSPS FADC = 32 MSPS FADC = 16 MSPS –50 –50 –50 AD9862 LOW POWER MODE 1, AD9860 LOW POWER MODE 2, –55 –55 BUFFER ENABLED, 1V p-p AD9860 –55 BUFFER BYPASSED, 1V p-p INPUT, 2(cid:3) RxPGA GAIN LOW POWER INPUT, 2(cid:3) RxPGA GAIN –60 –60 AD9860 BUFFER BYPMAOSDSEE D1,, –60 AD9860 –65 BUFFERED BYPASS –65 LBOUWFF PEORW EENRA BMLOEDDE, 1, 1(cid:3)2 RVx pP-GpA IN GPAUITN, –65 LBOUWFF PEORW EENRA BMLOEDDE, 2, DR – dBc––7705 B2VU FINFPEURTE, D1(cid:3)1 BV Y GINPAAPINSUST, 2(cid:3) GAIN DR – dBc––7750 12V(cid:3) pR-xpP IGNPAU GTA,IN DR – dBc––7750 12V(cid:3) pR-xpP IGNPAU GTA,IN SF–80 SF–80 SF–80 MODE 2,A BDU9F8F6E2R L OBWYP PAOSWSEEDR, –85 2V p-p INPUT, 1(cid:3) RxPGA GAIN –85 –85 –90 BUFFERED 1V AD9862 LOW POWER MODE 1, AD9862 LOW POWER MODE 2, –95 BUFFERED 2V INPUT, 2(cid:3) GAIN –90 BUFFER BYPASSED, 2V p-p INPUT, –90 BUFFER ENABLED, 1V p-p INPUT, INPUT, 1(cid:3) GAIN 1(cid:3) RxPGA GAIN 2(cid:3) RxPGA GAIN –100 –95 –95 0 10 100 1000 0 50 100 150 200 250 300 0 50 100 150 200 250 300 INPUT FREQUENCY – MHz fIN – MHz fIN – MHz TPC 22.Rx SFDR @ 64 MSPS TPC 23.Rx SFDR @ 32 MSPS TPC 24.Rx SFDR @ 16 MSPS 1 280 800 0 270 700 NOMINAL dB 260 W RELATIVE ATTENUATION – –––––41235 NBUOF BFU 1FVF (cid:3)2V2 (cid:3)1 (cid:5)INPUT IMPEDANCE – 222222154321090000000 Rx ANALOG POWER – m 321456000000000000 16MSP3S2 MLPS PMSO LDPE MODE BUFF 2V (cid:3)1 –6 180 0 1 10 100 1000 0 20 40 60 80 100 0 10 20 30 40 50 60 70 INPUT FREQUENCY – MHz fIN – MHz fADC – MSPS TPC 25.Rx Input Attenuation TPC 26.Rx Input Buffer TPC 27.Rx Analog Power Impedance vs. f Consumption IN REV. 0 –11–

AD9860/AD9862 REGISTER MAP (0x00–0x3F)1 Register Name Address2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Purpose General 0 SDIO BiDir LSB First Soft Reset SPI Setup Rx Power Down 1 V (diff) V Rx Digital Rx Channel B Rx Channel A Buffer B Buffer A All Rx REF REF Rx A 2 Byp Buffer A RxPGA A Rx B 3 Byp Buffer B RxPGA B Receive Path Rx Misc 4 HS Duty Cycle Shared Ref Clk Duty Setup Rx I/F 5 Three State Rx Retime Twos Inv RxSync Mux Out Complement Rx Digital 6 2 Channel Keep –ve Hilbert Decimate RSV 7 Reserved for Future Use Tx Power Down 8 Alt Timing TxOff Enable Tx Digital Tx Analog Power Down [2:0] Mode RSV 9 Reserved for Future Use Tx A Offset 10 DAC A Offset [1:0] DAC A Offset Direction Tx A Offset 11 DAC A Offset [9:2] Tx B Offset 12 DAC B Offset [1:0] DAC B Offset Direction Transmit Tx B Offset 13 DAC B Offset [9:2] Path Tx A Gain 14 DAC A Coarse Gain DAC A Fine Gain Setup Tx B Gain 15 DAC B Coarse Gain DAC B Fine Gain Tx PGA Gain 16 Tx PGA Gain Tx Misc 17 Slave Enable Tx PGA Fast Tx I/F 18 Tx Retime Q/I Order Inv TxSync Twos Inverse 2 Edges Interleaved Complement Sample Tx Digital 19 2 Data Paths Keep–ve Hilbert Interpolation Control Tx Modulator 20 Neg. Fine Tune Fine Mode Real Mix Neg. Coarse Tune Coarse Modulation NCO Tuning 21 FTW [7:0] Word NCO Tuning 22 FTW [15:8] NCO Word Setup NCO Tuning 23 FTW [23:16] Word DLL 24 Reserved Input Control ADC Div 2 DLL Multiplier DLL DLL Clock Clock Power Down FAST Setup CLKOUT 25 CLKOUT2 Divide Factor Inv2 Dis2 Inv1 Dis1 Aux ADC A2 26 Aux ADC A2 Data [1:0] Aux ADC A2 27 Aux ADC A2 Data [9:2] Aux ADC A1 28 Aux ADC A1 Data [1:0] Aux ADC A1 29 Aux ADC A1 Data [9:2] Auxiliary Aux ADC B2 30 Aux ADC B2 Data [1:0] ADC Data Aux ADC B2 31 Aux ADC B2 Data [9:2] and Setup Aux ADC B1 32 Aux ADC B1 Data [1:0] Aux ADC B1 33 Aux ADC B1 Data [9:2] Aux ADC Control 34 Aux SPI SelBnot A Refsel B Select B Start B Refsel A Select A Start A Aux ADC Clock 35 CLK/4 Aux DAC A 36 Aux DAC A Aux DAC B 37 Aux DAC B Auxiliary Aux DAC C 38 Aux DAC C DAC Data Aux DAC 39 Slave Enable Update C Update B Update A and Setup Update Aux DAC 40 Power Down C Power Down BPower Down A DAC Control 41 Inv C Inv B Inv A SigDelt 42 Sigma-Delta Control Word [3:0] Flag Sigma- Delta Data SigDelt 43 Sigma-Delta Control Word [11:4] and Setup ADC Low Power 49, 50 Low Power Register for Rx Path Operation below 32 MSPS Rx Low Power RSV 44–62 Reserved for Future Use Reserved 63 Chip Rev ID Chip ID NOTES 1When writing to a register with unassigned register bit(s), a logic low must be written to the unassigned bit(s). By default, after power up or RESET, all registers are set low, except for the bits in the shaded boxes, which are set high. 2Decimal –12– REV. 0

AD9860/AD9862 REGISTER BIT DEFINITIONS high speed applications when clock duty cycle affects noise and REGISTER 0: GENERAL distortion performance the most. This bit should be set high in conjunction with Clk Dut Enable register bit. BIT 7: SDIO BiDir (Bidirectional) Default setting is low, which indicates SPI serial port uses dedi- BIT 1: Shared Ref cated input and output lines (i.e., 4-wire interface), SDIO and Setting this bit high forces the dual receive ADCs into a mode SDO Pins, respectively. Setting this bit high configures the to share their differential references to provide superior gain serial port to use the SDIO Pin as a bidirectional data pin. matching. When this option is enabled, the REFT of ChannelA and Channel B should be connected together off-chip and the BIT 6: LSB First REFB of both channels should be connected. Default setting is low, which indicates MSB first SPI Port Access Mode. Setting this bit high configures the SPI port access to BIT 0: Clk Duty LSB first mode. Setting this bit high enables an on-chip duty cycle stabilizer (DCS) circuit to generate the internal clock for the Rx block. This option BIT 5: Soft Reset is useful for adjusting for high speed input clocks with skewed Writing a high to this register resets all the registers to their duty cycle. The DCS Mode can be used with ADC sampling default values and forces the DLL to relock to the input clock. frequencies over 40 MHz. The Soft Reset Bit is a one shot register and is cleared immediately after the register write is completed. REGISTER 5: Rx I/F (INTERFACE) REGISTER 1: Rx PWRDWN BIT 4: Three-state Setting this bit high will force both Rx data output buses, including BIT 7: V , diff (Power-Down) REF the RxSYNC Pin, into a three-state mode. Setting this bit high will power down the ADC’s differential references (i.e., REFT and REFB). BIT 3: Rx Retime The Rx path can use either of the clock outputs, CLKOUT1 or BIT 6: V (Power-Down) REF CLKOUT2, to latch the Rx output data. Since CLKOUT1 and Setting this register bit high will power down the ADC reference CLKOUT2 have slight phase offsets, this provides some timing circuit (i.e., V ). REF flexibility with the interface. By default, this bit is low and the BIT 5: Rx Digital (Power-Down) Rx output latches use CLKOUT1. Setting this bit will force the Setting this bit high will power down the digital section of the Rx output latches to use CLKOUT2. receive path of the chip. Typically, any unused digital blocks are BIT 2: Twos Complement automatically powered down. Default data format for the Rx data is straight binary. Setting this BIT 4/3: Rx Channel B/Rx Channel A (Power-Down) bit high will generate two’s complement data. Either ADC or both ADCs can be powered down by setting the BIT 1: Inv RxSync appropriate register bit high. The entire Rx channel is powered When the receive data is multiplexed onto one data port (i.e., Mux down, including the differential references, input buffer, and the Mode Enabled), the RxSYNC Pin can be used to decode which internal digital block. The bandgap reference remains active for channel generated the current output data at the active port. quick recovery. Default condition is that RxSYNC is high when ChannelA is at BIT 2/1: Buffer B/Buffer A (Power-Down) the output and is low when ChannelB is at the output. Setting Setting either of these bits high will power down the input buffer this bit high reverses this synchronization. circuits for the respective channel. The input buffer should be BIT 0: Mux Out powered down when bypassed. By default, these bits are low and Setting this bit high enables the Rx Mux Mode. Default setting the input buffers are enabled. is low, which is Dual Port Mode, (i.e., non Rx Mux Mode). When in BIT 0: All Rx (Power-Down) Rx Mux Mode, both Rx channels share the same output data bus, Setting this bit high powers down all circuits related to the pins D0A to D9A (for AD9860) or D0A to D11A (for AD9862). receive path. The other Rx output bus (pins D0B to D9B or D0B to D11B) REGISTER 2/3: Rx A/Rx B outputs a low logic. BIT 7: Bypass Buffer A/Bypass Buffer B REGISTER 6: Rx Digital Setting either of these bits high will bypass the respective input buf- BIT 3: 2 Channel fer circuit. When the buffer is bypassed, the input signal is routed Setting this bit low disables the Rx B output data port (pins D0B directly to the switched capacitor SHA input of the RxPGA. When to D9B or D11B), forcing the output pins to zero. By default, the operating with buffer bypassed, it should be powered down. bit is high and both data paths are active. BIT 0–4: RxPGA A/RxPGA B BIT 2: Keep –ve These 5-bit straight binary registers (Bit 0 is the LSB, Bit 4 is the This bit selects whether the receive Hilbert filter will filter positive MSB) provide control for the programmable gain amplifiers in or negative frequencies, assuming the filter is enabled. By default the dual receive paths. A 0 dB to 20 dB gain range is accom- this bit is low, which passes positive frequencies. Setting this bit plished through a switched capacitor network with fast settling high will configure the filter to pass negative frequencies. of a few clock cycles. The step size is approximately 1 dB. The BIT 1: Hilbert register default setting is minimum gain or hex00. The maximum This bit enables or disables the Hilbert filter in the receive path. setting for these registers is hex14. By default, this bit is low, which disables the receive Hilbert filter. REGISTER 4: Rx MISC Setting this bit high enables the receive Hilbert filter. BIT 2: HS (High Speed) Duty Cycle BIT 0: Decimate Setting this bit high optimizes duty cycle of the internal ADC This register enables or disables the decimation filters. By default, sampling clock. It is recommended that this bit be set high in the register setting is low and the decimation filter is disabled. REV. 0 –13–

AD9860/AD9862 Setting this bit high enables the decimation filters and decimates DAC A/DAC B Offset Direction the receive data by two. This bit determines to which of the differential output pins for the selected channel the offset current will be applied. Setting this REGISTER 8: Tx PWRDWN bit low will apply the offset to the negative differential pin. Setting BIT 5: Alt Timing Mode this bit high will apply the offset to the positive differential pin. The timing section in the data sheet describes two timing modes, the “Normal Operation” and the “Alternate Operation” modes. REGISTER 14/15: DAC GAIN A/B At power up, the default configuration is established from the BIT 6, 7: DAC A/DAC B Coarse Gain Control logic level of the Mode/TxBlank pin. If Mode/TxBlank is logic These register bits will scale the full-scale output current (I ) OUTFS low, the Normal Operation mode is the default; if the Mode/ of either Tx channel independently. I of the Tx channels is a OUT TxBlank pin is held at a logic high, the Alternative Operation function of the R resistor, the TxPGA setting, and the Coarse SET mode is configured at power-up (the DLL is forced to multiply Gain Control setting. by 4 at power-up by default in this mode). After power up, the MSB, LSB Tx Channel Current Scaling operation mode can be configured so that the Mode/TxBlank pin 10 or 11 Does not scale output current can be used for other functions. To allow this, set this bit high. 01 Scales output current by 1/2 BIT 4: TxOff Enable 00 Scales output current by 1/11 By default, the Mode/TxBlank pin is not used for any transmit BIT 5–0: DAC A/DAC B Fine Gain synchronization. The Mode/TxBlank pin input can be used to The DAC output curve can be adjusted fractionally through the serve two functions, blanking the DAC outputs and slaving the Gain Trim Control. Gain trim of up to –4% can be achieved on TxPGA gain control. When this bit is set high, a logic high on the each channel individually. The Gain Trim register bits are a twos Mode/TxBlank pin forces the Tx digital block to stop clocking. In complement attention control word. this mode, the Tx outputs will be static, holding their last update MSB, LSB values. To slave the TxPGA gain control to the Mode/TxBlank 100000 Maximum positive gain adjustment pin input, register Slave Enable (Register 17, Bit 1) needs to also 111111 Minimum positive gain adjustment be programmed. See that register for more information. 000000 No adjustment (default) BIT 3: Tx Digital (Power-Down) 000001 Minimum negative gain adjustment By default this bit is low, enabling the transmit path digital to 011111 Maximum negative gain adjustment operate as programmed through other registers. By setting this bit high, the digital blocks are not clocked to reduce power con- REGISTER 16: TxPGA GAIN sumption. When enabled, the Tx outputs will be static, holding BIT 0–7: TxPGA Gain their last update values. This 8 bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) reg- BIT 0-2: Tx Analog (Power-Down) ister controls for the Tx programmable gain amplifier (TxPGA). Three options are available to reduce analog power consumption The TxPGA provides a 20 dB continuous gain range with 0.1 dB for the Tx channels. The first two options disable the analog output steps (linear in dB) simultaneously to both Tx channels. By from Tx channel A or B independently, and the third option default, this register setting is hex00. disables the output of both channels and reduces the power MSB, LSB consumption of some of the additional analog support circuitry 000000 Minimum gain scaling –20 dB for maximum power savings. With all three options, the DAC bias 111111 Maximum gain scaling 0 dB current is not powered down so recovery times are fast (typically REGISTER 17: Tx MISC a few clock cycles). The list below explains the different modes and settings used to configure them. BIT 1: Slave Enable The TxPGA Gain is controlled through register TxPGA Gain Tx Analog setting and by default is updated immediately after the register Power-Down write. If this bit is set, the TxPGA Gain update is synchronized Power-Down Option Bits Setting [2:0] with the rising edge of a signal applied to the Mode/TxBlank Power-Down Tx B Channel Analog Output [1 0 0] pin. Setting TxOff enable in Register 8 is also required. Power-Down Tx A Channel Analog Output [0 1 0] BIT 0: TxPGA Fast (Update Mode) Power-Down Tx A and Tx B Analog Outputs [1 1 1] The TxPGA Fast bit controls the update speed of the TxPGA. REGISTER 10/11/12/13: DAC OFFSET A/B When Fast Update mode is enabled, the TxPGA provides fast gain settling within a few clock cycles. Default setting for this bit DAC A/DAC B Offset These 10-bit, twos complement registers control a dc current islow, which indicates Normal Update mode. Fast mode is offset that is combined with the TxA or TxB output signal. An enabled when this bit is set high. offset current of up to –12% IOUTFS (2.4 mA for a 20 mA full- REGISTER 18: Tx IF (INTERFACE) scale output) can be applied to either differential pin on each BIT 6: Tx Retime channel. The offset current can be used to compensate for offsets The Tx path can use either of the clock outputs, CLKOUT1 or that are present in an external mixer stage, reducing LO leakage CLKOUT2, to latch the Tx input data. Since CLKOUT1 and at its output. Default setting is hex00, no offset current. The CLKOUT2 have slight phase offsets, this provides some timing offset current magnitude is set using the lower nine bits. Setting flexibility with the interface. By default, this bit is high and the the MSB high will add the offset current to the selected differen- Tx input latches use CLKOUT1. Setting this bit low will force tial pin, while an MSB low setting will subtract the offset value. the Tx latches to use CLKOUT2. –14– REV. 0

AD9860/AD9862 BIT 5: Q/I Order BIT 3: Real Mix Mode This register indicates the order of received complex transmit This bit determines if the coarse modulation (controlled by register data. By default this bit is low, representing I data preceding Coarse Modulation, will perform a separate real mix on each Qdata. Alternatively, if this bit is set high, the data format is channel or a complex mix using the dual channel data. By default, defined as Q data preceding I data. this bit is set low and a complex mix will be performed. Setting BIT 4: Inv TxSync this bit high will enable the Real Mix mode. Note, the Fine This register identifies how the first and second data sets are Modulator Block only performs complex mixing. identified in a complex data set using the TxSYNC bit. By default BIT 2: Negative Coarse Tune this bit is low, and TxSYNC low indicates the first data set is at When this bit is low (default), the coarse modulator provides the Tx port; TxSYNC high indicates the second data set is at the positive shifts in frequency. Setting this bit high will shift the coarse Tx port. Setting this bit high inverts the TxSYNC bit. TxSYNC modulator processed data negative in frequency. high indicates the first of the data set, and TxSYNC low indicates BIT 1,0: Coarse Modulation the second of the data set. These bits control what coarse modulation processing will be BIT 3: Twos Complement performed on the transmit data. A setting of binary 00 (default) The default data format for Tx data is straight binary. Set this bit will bypass the modulation block, a setting of binary 01 will shift high when providing twos complement Tx data. the transmit data by f /4, and a setting of binary 10 will shift DAC BIT 2: Inverse Sample the transmit data by fDAC/8. By default, the transmit data is sampled on the rising edge of the REGISTER 21/22/23: NCO TUNING WORD CLKOUT. Setting this bit high will change this, and the transmit FTW [23:0] data will be sampled on the falling edge. These three registers set the 24-bit frequency tuning word (FTW) BIT 1: 2 Edges for the NCO in the fine modulator stage of the Tx path. The If the CLKOUT rate is running at half the interleaved data rate, NCO full-scale tuning word is straight binary and produces both edges of the CLKOUT must latch transmit data. Setting afrequency equivalent to f /4 with a resolution of f /226. DAC DAC this bit high allows this clocking configuration. REGISTER 24: DLL BIT 0: Interleaved BIT 6: Input Clock Control By default, the AD9860/AD9862 powers up in single DAC This bit defines what type of clock will be driving the AD9860/ operation. If dual transmit data is to be used, the interleaved data AD9862. The default state is low, which allows either crystal con- option needs to be enabled by setting this bit high. nected to OSC1 and OSC2 or single-ended reference clock driving REGISTER 19: Tx DIGITAL OSC1 to drive the internal timing circuits. If a crystal will not be BIT 4: 2 Data Paths used, the internal oscillator should be disabled after power-up Setting this bit high enables both transmit digital paths. By default, by setting this bit high. this bit is low and the transmit path utilizes only a single channel. BIT 5: ADC Div2 BIT 3: Keep –ve By default, the ADC is driven directly by the input clock in Normal This bit configures the Tx Hilbert filter for either positive or nega- Timing Operation mode or the DLL output in the Alternative tive frequencies passband, assuming it is enabled. By default Timing Operation mode. Setting this bit high will clock the ADC this bit is low, which selects the positive frequencies. Setting this at one half the previous clock rate. This is described further in bit high will setup the Hilbert filter to pass negative frequencies. the timing section. BIT 2: Hilbert BIT 4,3: DLL Multiplier This bit enables or disables the Hilbert filter in the transmit path. These bits control the DLL multiplication factor. A setting of By default, this bit is low, which disables the transmit Hilbert binary 00 will bypass the DLL, a setting of binary 01 will multiply filter. Setting this bit high enables the transmit Hilbert filter. the input clock by 2, and a setting of binary 10 will multiply the BIT 1,0: Interpolation Control input clock by 4. Default mode is defined by Mode/TxBlank These register bits control the interpolation rate of the transmit logic level at power-up or RESET, which configures either Normal path. Default settings are both bits low, indicating that both inter- Operation Timing mode or Alternative Timing mode. In Alter- polation filters are bypassed. The MSB and LSB are address D19, native Timing mode, the DLL will lock to 4(cid:1) multiplication Bits 1 and 0, respectively. Setting binary 01 provides an interpo- factor (the DLL FAST register remains low by default). If the lation rate of 2(cid:1); binary 10 provides an interpolation rate of 4(cid:1). Mode/TxBlank pin is low, by default the DLL will be bypassed and a 1(cid:1) clock is used internally. REGISTER 20: Tx MODULATOR BIT 2: DLL Power-Down BIT 5: Negative Fine Tune Setting this register bit high forces the CLK IN multiplier to a When this bit is low (default), the Numerically Controlled Oscil- power-down state. This mode can be used to conserve power or lator (NCO) provides positive shifts in frequency, assuming fine to bypass the internal DLL. To operate the AD9860/AD9862 modulation is enabled. Setting this bit high will use a negative when the DLL is bypassed, an external clock equal to the fastest frequency shift in the Fine Complex Modulator. on-chip clock is supplied to the OSC pin(s). BIT 4: Fine Mode BIT 0: DLL FAST By default, the NCO and fine modulation stage are bypassed. Setting The DLL can be used to generate output frequencies between this bit high will enable the use of the digital complex modulator, 32 MHz to 128 MHz. Because of the large range of locking fre- enabling tuning with the NCO. quencies allowed, the DLL is separated into two output frequency ranges, a “slow” range between 32 MHz to 64 MHz and a “fast” range starting at frequencies above 64 MHz to 128MHz. By REV. 0 –15–

AD9860/AD9862 default, this bit is low, setting up the DLL in “slow” mode. This the Auxiliary ADCs with a clock that is 1/4 of the receive ADC bit must be set high for DLL output frequencies over 64MHz. conversion rate. The conversion rate of the auxiliary ADCs should be less than 20 MHz. REGISTER 25: CLKOUT BIT 7, 6: CLKOUT2 Divide Factor REGISTER 36, 37, 38: AUX DAC A/B/C These bits control what rate the CLKOUT2 Pin will operate at Auxiliary DAC A, B, and C Output Control Word relative to the DLL output rate. The DLL output rate can be Three 8-bit, straight binary words are used to control the output output directly or divided by 2, 4, or 8. Bit 7 is the MSB and of three on-chip auxiliary DACs. The auxiliary DAC output Bit 6 is the LSB. changes take effect immediately after any of the serial write is completed. The DAC output control words have default values MSB, LSB Relative CLKOUT2 Frequency of 0. The smaller programmed output controlled words corre- 00 (Default) Equals DLL output rate spond to lower DAC output levels. 01 Equals DLL output rate divided by 2 10 Equals DLL output rate divided by 4 REGISTER 39: AUX DAC UPDATE 11 Equals DLL output rate divided by 8 BIT 7: Slave Enable BIT 5, 1: Inv 2/Inv 1 A low setting (default) updates the auxiliary DACs after the respec- The output clocks from CLKOUT1 and CLKOUT2 can be tive register is written to. To synchronize the auxiliary DAC outputs inverted by setting the appropriate one of these bits high. to each other, a slave mode can be enabled by setting this bit BIT 4, 0: Dis 2/Dis 1 high and then setting a high to the appropriate update registers. The output clocks from CLKOUT1 and CLKOUT2 can be BIT 2/1/0: Update C, B, and A disabled and a logic low output is forced by setting the appro- Setting a high bit to any of these registers initiates an update of the priate one of these bits high. respective Auxiliary DAC, A, B, or C, when Slave mode is enabled using the Slave Enable register. The register bit is a one shot REGISTER 26–33: AUXILIARY ADC A2/A1/B2/B1 and always reads back a low. Note: be sure to keep the Slave Enable AUX ADC A2, A1, B2, B1 Data bit high when using the auxiliary DAC synchronization option. These registers are read only registers that are used for read back of the 10-bit auxiliary ADC. The 10 bits are broken into a REGISTER 40: AUX DAC POWER-DOWN two registers, one containing the upper eight bits and the other BIT 2/1/0: Power Down C, B, and A containing the lower two bits. Setting any of these bits high will power down the appropriate auxiliary DAC. By default, these bits are low and the auxiliary REGISTER 34: AUX ADC CONTROL DACs are enabled. BIT 7: Aux SPI (Enable) One of the Auxiliary ADCs can be controlled through an dedi- REGISTER 41: AUX DAC CONTROL cated Auxiliary Serial Port. Setting this bit high enables this mode. BIT 4, 2, 0: Inv C, B, and A BIT 6: Sel BnotA Setting any of these bits high will invert the appropriate Auxiliary If the auxiliary Serial port is used, this bit selects which Auxiliary DAC control word setting. By default, these bits are low and the ADC, A or B, will be using the dedicated Auxiliary Serial port. output control word is decoded as noninverted, straight binary. The Auxiliary Serial port by default (low setting) controls Auxil- REGISTER 42/43: SIGDELT (SIGMA-DELTA) iary ADC A. Setting this bit high will allow the Auxiliary Serial Sigma-Delta Output Control Word Port to control Auxiliary ADC B. A 12-bit straight binary word is used to control the output of an BIT 5, 2: Refsel B/A on-chip sigma-delta converter. The sigma-delta output changes By default, the auxiliary ADCs use an external reference applied to take effect immediately after any serial write is completed. The the AUX_REF pin. This voltage will act as the full-scale reference sigma-delta output control words have default values of 0. The for the selected auxiliary ADC. Either auxiliary ADC can use an smaller programmed output controlled words correspond to lower internally generated reference, which is a buffered version of the integrated sigma-delta output levels. analog supply voltage. To enable use of the internal reference for REGISTER 49,50 : RX LOW POWER MODE either of the auxiliary ADCs, the respective Refsel register should Setting these bits will scale down the bias current to the ADC be set high. analog block when the device is operated at lower speeds. By BIT 4, 1: Select B/A default, these bits are low and the bias is at a nominal setting. These bits select which of the two inputs will be connected to the respective auxiliary ADC. By default (setting low), the AUX_ADC_A2 For ADC operation at or below 32 MSPS, Register 49 can be set pin is connected to Auxiliary ADC A and AUX_ADC_B2 pin is to 0x03 and Register 50 can be set to 0xEC; this will reduce Rx connected to Auxiliary ADC B. Setting the respective bit high AVDD power consumption by about 30% relative to nominal. will connect the AUX_ADC_A1 pin to Auxiliary ADC A and/or For ADC operation at or below 16 MSPS, Register 49 can be set AUX_ADC_B1 pin to Auxiliary ADC B. to 0x03 and Register 50 can be set to 0x9E; this will reduce Rx BIT 3, 0: Start B/A AVDD power consumption by about 60% relative to nominal. Setting a high bit to either of these registers initiates a conversion REGISTER 63: CHIP ID of the respective auxiliary ADC, A or B. The register bit always BIT 7–0: Rev ID reads back a low. This read only register indicates the revision of the AD9860/AD9862. REGISTER 35: AUX ADC CLOCK Reserved Registers BIT 0: CLK/4 Reserved registers are held for future development and should By default (setting low), the auxiliary ADCs are run at the receive never be written to. ADC conversion rate divided by 2. Setting this bit high will run –16– REV. 0

AD9860/AD9862 Blank Registers SDO is a serial output pin used for read back operations in 4-wire mode Blank registers, i.e., the registers with 0 settings and no indicated and is three-stated when SDIO is configured for bidirectional operation. function, are placeholders used throughout the register map for Instruction Header spacing the AD9860/AD9862 control bits in a logic fashion and, Each SPI read or write consists of an instruction header and potentially can be used for future development. A low should data. The instruction header is made up of an 8-bit word and is always be written to these registers if a write needs to take place. used to set up the register data transfer. The 8-bit word consists of a read/not write bit, R/nW (the MSB), followed by a double/ SERIAL PORT INTERFACE not single bit (2/n1) and the 6-bit register address. The Serial Port Interface (SPI) is used to write to and read from the AD9860/AD9862 internal programmable registers. The serial Write Operations The SPI write operation uses the instruction header to configure interface uses four pins: SEN, SCLK, SDIO, and SDO by default. a one or two register write using the 2/n1 bit. The instruction SEN is a serial port enable pin, SCLK is the serial clock pin, SDIO is a bidirectional data line and SDO is a serial output pin. byte followed by the register data, is written serially into the device through the SDIO pin on rising edges of the interface SEN is an active low control gating read and write cycles. When clock at SCLK. The data can be transferred MSB first or LSB first SEN is high, SDO and SDIO are three-stated. depending on the setting of the LSB First register. SCLK is used to synchronize SPI read and writes at a maximum Figure 1 includes a few examples of writing data into the device. bit rate of 16 MHz. Input data is registered on the rising edge and Figure 1a shows a write using 1 Byte and MSB First mode set; output data transitions on the falling edge. During write opera- Figure 1b shows an MSB first, 2 Byte write; and Figure 1c tions, the registers are updated after the 16th rising clock edge shows an LSB first, 2 Byte write. Note the differences between (and 24th rising clock edge for the dual byte case). Incomplete LSB and MSB First modes: instruction header and data are write operations are ignored. reversed, and in 2 Byte writes, the first data byte is written to SDIO is an input only by default. Optionally, a 3-pin interface may the address in the header, N and the second data byte is written be configured using the SDIO for both input and output opera- to the n–1 address. In LSB First mode, the first data byte is still tions and three-stating the SDO pin (see SDIO BiDir register). written to the address in the instruction header, but the second data byte is written to the N+1 address. tS tDH tLO tCLK tH tDS tHI SEN SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/nW 2/n1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE INSTRUCTION HEADER REGISTER DATA tDH tLO tCLK tS tH tDS tHI SEN SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/nW 2/n1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE INSTRUCTION HEADER (REGISTER N) REGISTER (N) DATA REGISTER (N–1) DATA tDH tLO tCLK tS tH tDS tHI SEN SCLK DON’T CARE SDIO A0 A1 A2 A3 A4 A5 2/n1R/nW D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON’T CARE INSTRUCTION HEADER (REGISTER N) REGISTER (N) DATA REGISTER (N+1) DATA Figure 1.SPI Write Examples a. (top) 1 Byte, MSB First Mode; b. (middle) 2 Byte, MSB First Mode; c. (bottom) 2 Byte, LSB First Mode REV. 0 –17–

AD9860/AD9862 tDH tLO tCLK tS tH tDS tHI tDV SEN SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/nW 2/n1 A5 A4 A3 A2 A1 A0 DON’T CARE INSTRUCTION HEADER (REGISTER N) SDO DON’T CARE D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE OUTPUT REGISTER DATA tDH tLO tCLK tS tH tDS tHI tDV SEN SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/nW 2/n1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE INSTRUCTION HEADER OUTPUT REGISTER DATA tDH tLO tCLK tS tH tDS tHI tDV SEN SCLK DON’T CARE DON’T CARE SDIO DON’T CARE A0 A1 A2 A3 A4 A5 2/n1 R/nW DON’T CARE INSTRUCTION HEADER SDO DON’T CARE D0 D1 D2 D3 D4 D5 D6 D7 DON’T CARE OUTPUT REGISTER DATA Figure 2.SPI Read Examples a. (top) 4-Wire Interface, MSB first; b. (middle) 3-Wire Interface, MSB first; c. (bottom) 4-Wire Interface, LSB first Read Operation features include two auxiliary ADCs, a programmable sigma-delta The read back of registers is a single data byte operation. The output, three auxiliary DACs, integrated clock circuitry to generate readback can be configured to use three pins or four pins and can all internal clocks, and buffered output clocks from a single input be formatted as MSB first or LSB first. The instruction header reference. is written to the device either MSB or LSB first (depending on The AD9860/AD9862 system functionality is described in the the mode) followed by the 8-bit output data (appropriately MSB following four sections: the Transmit Block, Receive Block, Timing or LSB justified). By default, the output data is sent to the dedicated Generation Block, and the Auxiliary Function Block. The following output pin (SDO). 3-wire operation can be configured by set- sections provide a brief description of the blocks and applications ting the SDIO BiDir register. In 3-wire mode, the SDIO pin for the four sections. will become an output pin after receiving the 8-bit instruction header with a read back request. TRANSMIT SECTION COMPONENTS Figure 2a shows an MSB first, 4-pin SPI read; Figure 2b shows an The transmit block (Tx) accepts and can process real or complex MSB first, 3-pin read; and Figure 2c shows an LSB first, 4-pin read. data. The Tx interface is configurable for a variety of data formats and has special processing options such as interpolation and Hilbert SYSTEM BLOCK DESCRIPTION filters. A detailed block diagram of the AD9860/AD9862 transmit The AD9860/AD9862 integrates transmit and receive paths with path is shown in Figure 3. The transmit block diagram is broken digital signal processing blocks and auxiliary features. The auxiliary into these stages: DAC (BlockA), Coarse Modulation (Block B), –18– REV. 0

AD9860/AD9862 BLOCK A BLOCK B BLOCK C BLOCK D BLOCK E BYPASSABLE BYPASSABLE BYPASSABLE DIGITAL LOW-PASS DIGITAL HILBERT DAC QUADRATURE INTERPOLATION QUADRATURE FILTER MIXER FILTER MIXER IOUT+A PGA TxDAC IOUT–A I HILBERT TxDATA FILTER [0:13] IOUT+B Q PGA TxDAC IOUT–B fS/4, DDS fS/8 Figure 3.Transmit Section Block Diagram Interpolation Stage (BlockC), Fine Modulation Stage (Block D), Fine Gain controls and dc offset controls can be used to compen- Hilbert filter (BlockE), and the Latch/Demultiplexing circuitry. sate for mismatches (for system level calibration), allowing improved matching characteristics of the two Tx channels and aiding in suppres- DAC sing LO feedthrough. This is especially useful in image rejection The DAC stage of the AD9860/AD9862 integrates a high perfor- architectures. The 10-bit dc offset control of each DAC can be used mance TxDAC core, a programmable gain control through a Programmable Gain Amplifier (TxPGA), coarse gain control, and independently to provide a –12% IOUTFSMAX of offset to either differential pin, thus allowing calibration of any system offsets. The offset adjustment and fine gain control to compensate for system fine gain control with 5-bit resolution allows the I of each mismatches. OUTFSMAX DAC to be varied over a –4% range, thus allowing compensation The TxDAC core of the AD9860/AD9862 provides dual, differen- of any DAC or system gain mismatches. Fine gain control is set tial, complementary current outputs generated from the 12-/14-bit through the DAC A/B Fine Gain registers and the offset control data. The 12-/14-bit Dual DACs support update rates up to of each DAC is accomplished using DAC A/B Offset registers. 128MSPS. The differential outputs (i.e., IOUT+ and IOUT–) A power-down option allows the user to power down the analog of each dual DAC are complementary, meaning they always sum supply current to both DACs or either DAC, individually. A digital to the full-scale current output of the DAC, I . Optimum OUTFS power-down is also possible through either the Tx PwrDwn acperformance is achieved with the differential current interface register or the Mode/TxBlank pin. drives balanced loads or a transformer. Coarse Modulator The maximum full-scale output current, I , is set by the OUTFSMAX A digital coarse modulator is available in the transmit path to external resistor (R ), which sets the DAC reference current. The R resistor is ScEoTnnected between the FSADJ Pin to ground. shift the spectrum of the input data by –fDAC/4 or –fDAC/8. If the SET input data consists of complex data, the modulator can be con- The relationship between I and R is: OUTFSMAX SET figured to perform a complex modulation of the input spectrum. If the data in the transmit path is not complex, a real mix can be ˚1.23V(cid:136) IOUTFSMAX ~67¥` R (cid:152) performed separately on each channel thereby frequency shifting ¸ SET fl the real data and images by f /4 or f /8. Real or complex DAC DAC Typically, RSET is 4 kW, which sets IOUTFSMAX to 20 mA, the mixing is configured by setting the Real Mix register. optimal dynamic setting for the TxDACs. Increasing RSET by a By default, the coarse modulator is bypassed. It can be configured factor of 2 will proportionally decrease IOUTFSMAX by a factor of using Coarse Modulation and Neg Coarse Tune registers. 2. I of each DAC can be re-scaled either simulta- OUTFSMAX Interpolation Stage neously with the TxPGA Gain register or independently with Interpolation filters are available for use in the AD9860/AD9862 DAC A/B Coarse Gain registers. transmit path, providing 1(cid:1) (bypassed), 2(cid:1), or 4(cid:1) interpolation. The TxPGA function provides 20 dB of simultaneous gain The interpolation filters effectively increase the Tx data rate while range for both DACs and is controlled by writing to SPI register suppressing the original images. The interpolation filters digitally TxPGA Gain for a programmable full-scale output of 10% to shift the worst case image further away from the desired signal, 100% I . The gain curve is linear in dB, with steps of OUTFSMAX thus reducing the requirements on the analog output reconstruc- about 0.1dB. Internally, the gain is controlled by changing the tion filter. main DAC bias currents with an internal TxPGA DAC whose There are two 2(cid:1) interpolation filters available in the Tx path. output is heavily filtered via an on-chip R-C filter to provide An interpolation rate of 4(cid:1) is achieved using both interpolation continuous gain transitions. Note, the settling time and band- filters; an interpolation rate of 2(cid:1) is achieved by enabling only width of the TxPGA DAC can be improved by a factor of 2 by the first 2(cid:1) interpolation filter. writing to the TxPGA Fast register. The first interpolation filter provides 2(cid:1) interpolation using a Each DAC has independent coarse gain control. Coarse gain 39tap filter. It suppresses out-of-band signals by 60 dB or more control can be used to accommodate different I from the OUTFS and has a flat passband response (less than 0.1 dB ripple) extend- dual DACs. The coarse full-scale output control can be adjusted ing to 38% of the AD9860/AD9862 input Tx data rate (19% of using the DAC A/B Coarse Gain registers to 1/2 or 1/11th of the DAC update rate, f ). The maximum input data rate is the nominal full scale current. DAC 64MSPS per channel when using 2(cid:1) interpolation. REV. 0 –19–

AD9860/AD9862 The second interpolation filter will provide an additional 2(cid:1) inter- Hilbert Filter polation for an overall 4(cid:1) interpolation. The second filter is a The Hilbert filter is available to provide a Hilbert transform of 15tap filter. It suppresses out-of-band signals by 60 dB or more. “real” input data at a low intermediate frequency (IF) between The flat passband response (less than 0.1 dB attenuation) is 38% 12.5% to 38% of the input data rate. The Hilbert filter essentially of the Tx input data rate (9.5% of f ). The maximum input transforms this “real,” single channel input data into a complex DAC data rate per channel is 32 MSPS per channel when using representation (i.e., I and Q components) that can be used as 4(cid:1)interpolation. part of an image rejection architecture. The complex data can than The 2(cid:1) and 4(cid:1) Interpolation Filter Transfer function plots are be processed further using the on-chip digital complex modulators. The Hilbert filter requires 4(cid:1) interpolation to be enabled and shown in Figure 4a and 4b, respectively. accepts data at a maximum 32 MSPS. Figure 5 shows a spectral plot of the Hilbert filter impulse response. 10 0 INTERPOLATION FILTER 100 –10 80 –20 B INCLUDUNG SIN (X)/X 60 d –30 DE – –40 40 U NIT –50 20 MAG –60 dB 0 –70 –20 –80 –40 –90 –60 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 –80 NORMALIZED – fS –100 –20 –15 –10 –5 0 5 10 15 20 FREQUENCY – MHz 10 Figure 5.Tx Hilbert Filter, Keeping Positive 0 Frequencies Spectral Plot –10 INTERPOLATION FILTER Latch/Demultiplexer –20 The AD9860/AD9862 Tx path accepts dual or single channel B d –30 data. The dual channel data can represent two independent real – DE –40 signals or a complex signal. Various input data latching schemes NITU –50 INCLUDUNG SIN (X)/X relative to one of the output clocks, CLKOUT1 or CLKOUT2, G are allowed, including using any combination of rising and falling A –60 M clock edges. –70 Associated Tx timing is discussed in detail in the Clock Overview –80 section of the data sheet. –90 –100 TRANSMIT APPLICATIONS SECTION 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED – fS The AD9860/AD9862 transmit path (Tx) includes two, high speed, high performance, 12-/14-bit TxDACs. Figure 3 shows a detailed Figure 4.Spectral Response of 2(cid:1) Interpolation Filter block diagram of the transmit data path and can be referred to (top) and 4(cid:1) Interpolation Filter (bottom) throughout the explanation of the various modes of operation. Fine Modulation Stage The various Tx modes of operation are broken into three parts, A digital fine modulation stage is available in the transmit path to determined by the format of the input data. They are: shift the complex Tx output spectrum using a 24-bit numerically 1. Single Channel DAC Data controlled oscillator (NCO). To utilize the Fine Modulation Block, 4(cid:1) interpolation is required. Therefore, the maximum 2. Two Independent Real Signal DAC Data (diversity or dual channel input date rate is 32 MSPS per channel, which generates a DAC update rate, f , of 128 MSPS. The NCO can tune up to 1/4of 3. Dual Channel Complex DAC Data (I and Q or Single Sideband) DAC f , providing a step resolution of f /226. Since the Fine DAC DAC Single Channel DAC Data Modulation Stage precedes the Interpolation Filters, care must In this mode, 12-/14-bit single channel Tx data is provided to be taken to ensure the entire desired signal is placed within the theAD9860/AD9862 and latched using either CLKOUT1 or pass band ofthe Interpolation Filter. CLKOUT2 edges as defined in the Clock Overview section of By default, the Fine Modulation Block is bypassed. To enable it the data sheet. All Tx digital signal processing blocks can be to perform a complex mix of the Tx I and Q data, Register 2’s data utilized to address reconstruction filtering at the DAC output paths, Fine Mod and Fine, should be configured. The NCO and aid in frequency tuning. frequency tuning word is set in the three FTW registers. –20– REV. 0

AD9860/AD9862 In most systems, the DAC (and each up-converter stage) requires independently. The Tx digital processing blocks available in this analog filtering to meet spectral mask and out-of-band spurious mode are the Interpolation Filters (Block C) and the Coarse emissions requirements. Digital interpolation (Block C) and Modulator (Block D). Hilbert filtering (Block E) can be used to relax some of the system As mentioned previously, the interpolation filters can be used to analog filtering. relax requirements on the external analog filters. The maximum Digital 2(cid:1) interpolation with input data rates of up to 64 MSPS or rate of the Tx interface is 128 MSPS, i.e., 64 MSPS/channel 4(cid:1) interpolation with input data rates of 32 MSPS is available with interleaved data. Therefore to fully take advantage of the in this mode (or interpolation filters can be bypassed to achieve DACs maximum update rate of 128 MSPS, 2(cid:1) interpolation is a 128 MSPS input data rate). The data bandwidth with 2(cid:1) or required. The 4(cid:1) interpolation filter is recommended for input 4(cid:1) interpolation enabled is up to 38% of the input data rate. If data rates equal to or less than 32 MSPS/channel (64 MSPS no interpolation is enabled, the data bandwidth will be the full interleaved). The data bandwidth with 2(cid:1) or 4(cid:1) interpolation Nyquist band with Sinc (cid:1) limitations. The interpolation filters enabled is up to 37.5% of the channel input data rate. If no are configured through the Interpolation Serial register. interpolation is enabled, the data bandwidth will be the full Nyquist band with Sinc (cid:1) limitations. The interpolation filters The Hilbert filter can be enabled in this mode to suppress the are configured through the Interpolation Serial register. positive or negative image that naturally occurs with real data. The single sideband signal when combined with a quadrature The coarse modulation will perform a real mix of each channel, modulator can upconvert the desired signal and suppressed image, independently, with either f /4 or f /8. DAC DAC forming a Hartley Image Rejection Architecture (both Tx paths Dual Channel Complex DAC Data need to be enabled to produce the Image Rejection Architecture). The Dual Channel Complex DAC Data (also known as Single The Hilbert filter will provide over 50 dB image suppression for Sideband Data) is used to generate complex Tx signals (i.e., I and signals between 12.5% to 38% of the input data rate. The Hil- Q). In this mode, 12-/14-bit, interleaved I and Q data is provided bert filter can be enabled and configured using the Hilbert and to the AD9860/AD9862 and latched using either CLKOUT1 or Keep –ve Serial registers. CLKOUT2 edges as defined in the Clock Overview section of Digital frequency tuning the Tx output is also possible in this the data sheet. Both Tx paths are enabled and the two signals mode using the coarse modulation block. The coarse modulation will be processed as a complex waveform. The Tx digital pro- block can be used to frequency shift the Tx signal either –f /4, cessing blocks available in this mode are the Fine Modulator DAC –f /8, +f /8 or +f /4. The coarse modulator does not (Block B), the Interpolation Filters (Block C), and the Coarse DAC DAC DAC require the Hilbert filter to be enabled, in which case the real Modulator (Block D). signal and image will shift. If the Hilbert filter is enabled, a As mentioned previously, the interpolation filters can be used to complex mix can be performed on the single sideband signal by relax requirements on the external analog filters. The maximum the coarse modulator (Note: the Hilbert filter does not need to rate of the Tx interface is 128 MSPS, i.e., 64 MSPS/channel with be enabled if single sideband data is provided externally). interleaved data (as is the case in this mode). Therefore, to fully The fine modulator can be used to accurately place the output take advantage of the DAC’s maximum update rate of 128MSPS, signal shifting the Tx data spectrum in the positive or negative 2(cid:1) interpolation is required. The 4(cid:1) interpolation is recommended direction with a resolution of f /226. The fine modulator for input data rates equal to or less than 32MSPS/channel DAC requires both 4(cid:1) interpolation and the Hilbert filter enabled to (64MSPS interleaved). The data bandwidth with 2(cid:1) or 4(cid:1) be used in this mode. The coarse modulator and fine modulator interpolation enabled is up to 37.5% of the channel input data can both be used and provide a tuning range between –68% of rate. If no interpolation is enabled, the data bandwidth will be the DAC Nyquist frequency. the full Nyquist band with Sinc (cid:1) limitations. The interpolation filters are configured through the Interpolation Serial register. If all Tx DSP blocks are bypassed, the AD9860/AD9862 oper- ates similar to a standard TxDAC. In Single Channel DAC Data A complex mix can be performed on the single sideband signal mode, only the Channel A DAC is used; Channel B is powered by the coarse and/or fine modulator. The coarse modulation down to reduce power consumption. block can be used to frequency shift the Tx signal either –f /4, DAC –f /8, +f /8 or + f /4. The fine modulator can be used to Two Independent Real Signal DAC Data DAC DAC DAC accurately place the output signal shifting the Tx data spectrum The Dual Channel Real DAC Data mode is used to transmit in the positive or negative direction with a resolution of 1/226 of diversity or dual channel signals. In this mode, 12-/14-bit, dual the DAC update rate. The fine modulator requires 4(cid:1) interpola- channel, interleaved Tx data is provided to the AD9860/AD9862 tion to be enabled. The coarse modulator and fine modulator and latched using either CLKOUT1 or CLKOUT2 edges as defined in the Clock Overview section of the data sheet. Both can both be used and provide a tuning range between –70% of the DAC Nyquist frequency. Tx paths are enabled and the two signals will be processed REV. 0 –21–

AD9860/AD9862 BLOCK A BLOCK B BLOCK C BLOCK D BLOCK E LOW-PASS DECIMATION FILTER VIN+A 1(cid:3) PGA ADC RxA DATA VIN–A [0:11] HILBERT FILTER VIN+B 1(cid:3) PGA ADC VIN–B RxB DATA [0:11] Figure 6.Receive Section Block Diagram RECEIVE SECTION COMPONENTS RxPGA The receive block is configurable to process input signals of dif- The RxPGA stage has a Programmable Gain Amplifier that can be ferent formats and has special features such as an input buffer, used to amplify the input signal to utilize the entire input range gain stage, and decimation filters. The AD9860/AD9862 receive of the ADC. The RxPGA stage provides a 0dB to 20dB gain path block diagram is shown in Figure 6. The block diagram can range in steps of about 1 dB. The Rx channel independent gain be broken into the following stages: Input Buffer (Block A), control is accomplished through two 5-bit SPI programmable RxPGA (Block B), dual, 10-/12-bit, 64 MSPS ADC (Block C), RxPGA A/B registers. The gain curve is linear in dB with a minimum Decimation filter (Block D), Digital Hilbert Block (Block E), gain setting (0 dB, nominally) of hex00 and a maximum gain and a Data Output Multiplexer. The function of each stage is setting (20 dB, nominally) of hex14. explained in the following paragraphs. The RxPGA stage can provide up to a 2 V p-p signal to the Input Buffer Stage ADC input. The input buffer stage buffers the input signal on-chip for both Analog-to-Digital (A/D) Converter receive paths. The buffer stage has two main benefits, providing The analog-to-digital converter (ADC) stage consists of two a constant input impedance and reducing any “kick-back” noise high performance 10-/12-bit, 64 MSPS analog-to-digital (A/D) that might be generated on-chip, affecting the analog input signal. converters. The dual A/D converter paths are fully independent, The Rx path sampling mode can be split into two categories, except for a shared internal bandgap reference source, V . Each REF depending on the frequency of the input signal. When sampling of the A/D converter’s paths consists of a front-end sample and input signals up to Nyquist of the ADC, the sampling is referred to hold amplifier followed by a pipelined, switched capacitor, A/D as Nyquist sampling. When sampling at rates above ADC Nyquist converter. The pipelined A/D converter is divided into three sections, rate, the sampling is referred to as IF sampling or undersampling. consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct For Nyquist sampling, the input buffer provides a constant 200W for flash errors in the preceding stages. The quantized outputs impedance over the entire input signal range. The constant input from each stage are combined into a final 12-bit result through impedance accommodates matching networks to ensure proper a digital correction logic block. The pipelined architecture permits transfer of signal to the input of the device. The input buffer is the first stage to operate on a new input sample while the remain- self-biased to ~ 2 V, and therefore the input signal should be ing stages operate on preceding samples. Sampling occurs on the ac-coupled to the Rx differential input or have a common-mode rising clock edge. voltage of about 2 V. If an external buffer is present, the internal input buffer can be bypassed and powered down to reduce power Each stage of the pipeline, excluding the last, consists of a low consumption. The input buffer accepts up to a 2 V p-p input resolution flash A/D connected to a switched capacitor DAC and signal for maximum SNR performance. Optimal THD perfor- interstage residue amplifier (MDAC). The residue amplifier magni- mance occurs with 1V p-p input signal. fies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy For IF sampling, the input buffer can be used with input signals is used in each one of the stages to facilitate digital correction of up to about 100 MHz, the 3 dB bandwidth of the buffer. When flash errors. The last stage simply consists of a flash A/D. undersampling the input signal, the output spectrum will contain an aliased version of the original, higher frequency signal. As was A stable and accurate 1.0 V bandgap voltage reference is built into the case with Nyquist sampling, the input signal should be the AD9860/AD9862 and is used to set a 2V p-p differential input ac-coupled to the Rx differential input or have a common-mode range. The internally generated reference should be decoupled voltage of ~ 2V. For input signals over 100MHz to about 250MHz, at the VREF pin using a 10 mF and a 0.1 mF capacitor in parallel the input buffer needs to be bypassed and an external input to ground. Separate top and bottom references, V and V , RT RB buffer is required. In the case that the input buffer is bypassed, for each converter are generated from V and should also be REF the input circuit is a switched capacitor network. The switching decoupled. Recommended decoupling for the top and bottom input impedance during the sample phase is about 1/(2((cid:3))FC), references consists of using 10 mF and 0.1 mF capacitors in parallel where F is the input frequency and C is the input capacitance between the differential reference pins, and a 0.1 mF capacitor (about 4 pF). During hold mode, the input impedance is > 1MW. –22– REV. 0

AD9860/AD9862 from each to ground. The internal references can also be disabled The output data from the dual ADCs can be multiplexed onto (powered down) and driven externally to provide a different input asingle 10-/12-bit output bus. The multiplexing is synchronized voltage range or low drift reference. If an external V reference using the RxSYNC output pin that indicates which channel data REF is used, it should not exceed 1.0V. is on the output bus. A Shared Reference mode allows the user to connect the differen- RECEIVE APPLICATIONS SECTION tial references from both ADCs together externally for superior The AD9860/AD9862 receive path (Rx) includes two high speed, gain matching performance. If the ADCs are to function inde- high performance, 10-/12-bit ADCs. Figure 6 shows a detailed pendently, then the reference can be left separate and will provide block diagram of the Rx data path and can be referred to through- superior isolation between the dual channels. Shared Reference out the explanation of the various modes of operation. The various mode can be enabled through the Shared Ref register. Rx modes of operation are broken into three parts determined by A power-down option allows the user to power down both ADCs the type of input signal: (sleep mode) or either ADC individually to reduce power 1. Single Channel ADC Signal consumption. 2. Dual Channel Real ADC Signal (diversity or dual channel) Decimation Stage 3. Dual Channel Complex ADC Signal (I and Q or Single For signals with maximum frequencies less than or equal to 3/16 the Sideband). ADC sampling rate, f , the decimate by 2 filter (or half-band ADC filter) can be used to provide on-chip suppression of out-of- band Each one of these parts is further divided into two cases, sampling images and noise. When data is present in frequencies greater input signals up to Nyquist of the ADC (Nyquist sampling) and than 1/4 f , the decimate by 2 filter can be disabled by switching sampling at rates above ADC Nyquist rate (IF sampling or ADC the filter out of the circuit. The decimation filter allows the ADC undersampling). to oversample the input while decreasing the output data rate by The AD9860/AD9862 uses oversampling and decimation filters to half. The two main benefits are a simplification of the input anti- ease requirements on external filtering components. The decima- aliasing filter and a slower data interface rate with the external tion filters (for both receive paths) can be used or bypassed so as digital ASIC. The decimation filter is an 11 tap filter and suppresses to accommodate different signal bandwidths and provide different out of band noise by 38dB. output data rates to allow easy integration with several different Hilbert Block data processing schemes. The Hilbert filter is available to provide a Hilbert Transform of the Nonbaseband data can be used in an effort to avoid the dc offsets data from the ADC in Channel B. The Digital Hilbert Transform, in the receive signal path that can cause errors. By receiving in combination with an external complex downconverter, enables nonbaseband data, the requirements of external filtering may be a receive image rejection architecture (similar to Hartley image greatly reduced. rejection architecture). The Hilbert filter pass-band (<0.1dB In each of the different receive modes, the input buffer, Program- ripple) is between 25% to 75% of the Nyquist rate of its input data mable Gain Amplifier (RxPGA), and output multiplexer remain rate. The maximum data rate of the Rx Hilbert filter is 32MSPS. within the receive path. At ADC rates higher than this, the decimation filters should be enabled. The Hilbert filter transfer function plots are shown in Single Channel ADC Signal Figure 7. In this mode, a single input signal to be digitized is connected to the differential input pins, VIN+A and VIN–A. The 10-/12-bit 0 output Rx data is latched using either CLKOUT1 or CLKOUT2 edges as defined in the Clock Overview section. The Rx path available options include bypassing the input buffer, Rx PGA control and using the Decimation Filter. By default, both Rx paths are enabled and the unused one should be powered down using B –40 – d the appropriate bit in the Rx Power-Down register, d1. E UD The input buffer description above explains the conditions under T NI which the buffer should be bypassed. G A M –80 If the input signal, or the undersampled alias signal for the IFsampling case, falls below 40% of the ADC Nyquist rate, the decimation filter can be enabled to suppress out-of-band noise and spurious signals by 40 dB or more. With the decimation filter enabled, the SNR of the Rx path improves by about 2.3dB. –120 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 Dual Channel Real ADC Signal NORMALIZED – fS The Dual Channel Real ADC Signal mode is used to receive Figure 7. Rx Hilbert Filter, Keeping Positive Frequencies diversity signals or dual independent channel signals that will be Response processed independent of each other. In this mode, the two input signals to be digitized are connected to the differential input pins Data Output Multiplexer Stage The Rx data output format can be configured for either twos of the AD9860/AD9862, VIN+A, VIN–A, VIN+B, and VIN–B. complement or offset binary. This is controlled by the Rx Twos The two 10-/12-bit Rx outputs can be either interleaved onto a Complement register. single 10-/12-bit bus or output in parallel on two 10-/12-bit buses. REV. 0 –23–

AD9860/AD9862 The output will be latched using some configuration of CLKOUT1 An internal Delay Lock Loop (DLL) based clock multiplier pro- or CLKOUT2 edges as defined in the Clock Overview section of vides a low noise, 2(cid:1) or 4(cid:1) multiplication of the input clock over the data sheet. The Rx path available options include bypassing an output frequency range of 32 MHz to 128 MHz. The DLL the input buffer, RxPGA control and using the decimation filter. Fast register should be used to optimize the DLL performance. The input buffer description above explains the conditions under For DLL output frequencies between 32 MHz and 64MHz, this which the buffer should be bypassed. bit should be set low. For output frequencies between 64 MHz to 128MHz, the Fast bit should be set high (for a 64MHz out- If the input signal, or the undersampled alias signal for the put frequency, the register can be set either high or low). The DLL IFsampling case, falls below 40% of the ADC Nyquist rate, the can be bypassed by setting a 1(cid:1) multiplication factor in the DLL decimation filter can be enabled to suppress out-of-band noise Multiplier register. The DLL can be powered down when it is and spurious signals by 40dB or more. With the decimation bypassed for power savings by setting the DLL PwrDwn register. filter enabled the SNR of the Rx path improves by about 2.3dB. For applications where an external crystal is desired, the AD9860/ Dual Channel Complex ADC Signal AD9862 internal oscillator circuit and the DLL clock multiplier The Dual Channel Complex ADC Signal mode is used to receive enable a low frequency, lower cost quartz crystal to be used to baseband I and Q signals or a single sideband signal at some IF. generate the input reference clock. The quartz crystal would be In this mode, a complex input signal is generated from an external connected between the OSC1 and OSC2 pins with parallel quadrature demodulator. The in-phase channel (Ichannel) is resonant load capacitors as specified by the crystal manufacturer. connected to VIN+A and VIN–A, and the Quadrature Data (Qchannel) is connected to the VIN+B and VIN–B differential An internal Duty Cycle Stabilizer (DCS) can be enabled on the pins. The Rx path available options include bypassing the input AD9860 by setting the Clk Duty register. This provides a stable buffer, RxPGA control, the decimation filter, and using the digital 50% duty cycle to the ADC for high speed clock rates between Hilbert filter. Shared Reference mode is also discussed below. 40 MSPS to 64 MSPS when proper duty cycle is more critical. The RxPGA provides 0 dB to 20 dB gain control for both chan- System Clock Distribution Circuitry nels. The input buffer description above explains the conditions There are many variables involved in the timing distribution. under which the buffer should be bypassed. External variables include CLKIN, CLKOUT1, CLKOUT2, Rx Data Rate, Tx Data Rate. Internal variables include ADC If the input signal, or the undersampled alias signal for the IFsam- conversion rate, DAC update rate, interpolation rate, decimation pling case, falls below 40% of the ADC Nyquist rate, the decimation rate, Rx data multiplexing and Tx data demultiplexing. Many of filter can be enabled to suppress out-of-band noise and spurious these parameters are interrelated and based on CLKIN. Optimal signals by 40 dB or more. With the decimation filter enabled, power versus performance and ease of integration options can the SNR of the Rx path improves by about 2.3dB. be chosen to suit a particular application. A digital Hilbert filter can be enabled to provide a receive image rejection architecture on-chip. The digital Hilbert filter combines NO DECIMATION, 2 DATA the I data and a phase shifted version of the Q data to produce a ADC MUX Rx DATA single combined Rx signal. The filter can provide 50dB image AND [0:23] LATCH suppression in the pass band (less than 0.1 dB ripple). The pass DECIMATE: band of the filter is from 25% to 75% of Nyquist rate of the data REG D6 B0 MUX OUT: entering the Hilbert filter. Note, the Hilbert filter’s maximum REG D5 B0 NO INVERSION, Rx RETIME: input data rate is 32 MSPS, at ADC rates above 32 MSPS. The 1(cid:3), 1/2(cid:3) INVERT REG D5 B3 decimation filter is required to reduce the data rate. With the DIV INV CLKOUT1 decimation filter also enabled, the pass band of the Hilbert filter will be 12.5% to 37.5% of the ADC Nyquist rate (still 25% to 75% CLKSEL INV1: REG D25 B1 of the Nyquist rate of the data entering the Hilbert filter). NO INVERSION, 1(cid:3), 1/2(cid:3) 1(cid:3), 2(cid:3), 4(cid:3) 1(cid:3), 1/2(cid:3), 1/4(cid:3) INVERT An optional Shared Reference mode allows the user to connect the CLKIN DIV DLL DIV INV CLKOUT2 differential references from the dual ADC together externally for superior gain matching performance. To enable the Shared Ref- ADC DIV2: DLL MULTIPLIER: CLKOUT2 INV2: REG D24 B5 REG D24 B3, 4 DIV FACTOR: REG D25 B5 erence mode, the Shared Ref register (d4, b1) should be set high. REG 25 B6, 7 NO INTERP TIMING GENERATION BLOCK 2, 4 DATA The AD9860/AD9862 Timing Generation block uses a single DAC LATCH Tx DATA AND [0:13] external clock reference to derive all internal clocks to operate DEMUX the transmit and receive channels. The input clock reference INTERPOLATION: REG D19 B0, 1 can consist of either an external single ended clock applied to CLOCK PATH 2 DATA PATHS: REG D19 B4 the OSC1 pin, with the OSC2 pin left floating or an external DATA PATH Q/I ORDER: REG D18 B5 Tx RETIME: REG D18 B6 crystal connected between the clock input pins (OSC1 and OSC2). Figure 8.Normal Operation Timing Block Diagram By default, the AD9860/AD9862 can accept either an external reference clock or a crystal to generate the input clock. The One of two possible timing operation modes can be selected. The internal oscillator, if not used, should be disabled by setting the typical timing mode is called Normal Operation mode; a block Input Control Clock register. The OSC1 input impedance is a diagram is shown in Figure 8. The other mode is called Alterna- relatively high resistive impedance (typically, about 500 kW). tive Operation mode, and a block diagram is shown in Figure12. –24– REV. 0

AD9860/AD9862 Table I. Rx Data Timing Table Table Ia. CLKSEL Set Logic Low Table Ib. CLKSEL Set Logic High ADC See Figure 8 for ADC See Figure 8 for CLKSEL Div 2 Decimate Multiplex Relative Timing CLKSEL Div 2 Decimate Multiplex Relative Timing Timing No. 4 Timing No. 3 No Mux Rx Data = 2 (cid:1) CLKOUT1 No Mux Rx Data = CLKOUT1 CLKOUT1=1⁄2 (cid:1) CLKIN CLKOUT1=CLKIN No No Decimation Decimation Timing No. 4 Mux Not Allowed Mux Rx Data(MUXED) = 2 (cid:1) CLKOUT1 CLKOUT1=CLKIN No No Timing No. 3 Timing No. 2 Div Div No Mux Rx Data = 2 (cid:1) CLKOUT1 No Mux Rx Data = 1⁄2 (cid:1) CLKOUT1 CLKOUT1=1⁄2 (cid:1) CLKIN CLKOUT1= CLKIN Decimation Decimation Timing No. 4 Timing No. 3 Mux Rx Data(MUXED) = 2 (cid:1) CLKOUT1 Mux Rx Data(MUXED) = CLKOUT1 CLKOUT1=1⁄2 (cid:1) CLKIN CLKOUT1= CLKIN Low High Timing No. 3 Timing No. 2 No Mux Rx Data = CLKOUT1 No Mux Rx Data = 1⁄2 (cid:1) CLKOUT1 CLKOUT1=1⁄2 (cid:1) CLKIN CLKOUT1=CLKIN No No Decimation Timing No. 4 Decimation Timing No. 3 Mux Rx Data(MUXED) = 2 (cid:1) CLKOUT1 Mux Rx Data(MUXED) = CLKOUT1 CLOUT1=1⁄2 (cid:1) CLKIN CLOUT1=CLKIN Div Div Timing No. 2 Timing No. 1 No Mux Rx Data = 1⁄2 (cid:1) CLKOUT1 No Mux Rx Data = 1⁄4 (cid:1) CLKOUT1 CLOUT1=1⁄2 (cid:1) CLKIN CLOUT1=CLKIN Decimation Decimation Timing No. 3 Timing No. 2 Mux Rx Data(MUXED) = CLKOUT1 Mux Rx Data(MUXED) = 1⁄2 (cid:1) CLKOUT1 CLKOUT1=1⁄2 (cid:1) CLKIN CLKOUT1=CLKIN f CLKOUT1 Rx DATA TIMING No. 1 fRx = CLKOUT(cid:8)4 Rx DATA TIMING No. 2 fRx = CLKOUT(cid:8)2 Rx DATA TIMING No. 3 fRx = CLKOUT Rx DATA TIMING No. 4 fRx = 2(cid:3)CLKOUT tR(cid:3)1 tR(cid:3)3 tR(cid:3)2 tR(cid:3)1 Figure 9.Rx Timing Diagram ADC DIV2 DLL MULT CLKOUT2 DIV INTERP A B C D E 00: C = B 00: D = C 00: E = D TxDAC UPDATE RATE CLKIN 0: B = A 01: C = B/2 01: D = C/2 01: E = 2 (cid:3) D SINGLE CHANNEL 1: B = A/2 10: C = B/4 10: D = C/4 10: E = 4 (cid:3) D (CANNOT EXCEED DLL OUTPUT RATE) ADC SAMPLE RATE DLL OUTPUT RATE CLKOUT2 INPUT Tx DATA RATE (NOT TO EXCEED 64MHz) (NOT TO EXCEED 128MHz) (SINGLE CHANNEL) Figure 10.Single Tx Timing Block Diagram, Alternative Operation REV. 0 –25–

AD9860/AD9862 For the Normal Operation mode, the Tx timing is based on The Rx data (unless re-timed using the Rx Retime register) is aclock derived from the DLL output, while the Rx clock is timed relative to the CLKOUT1 pin output. The Rx output data unaffected by the DLL setting. can be decimated (halving the data rate) or both channels can be multiplexed onto the channel A data bus (doubling the data rate). The Alternative Operation mode, timing utilizes the output of the DLL to generate both Rx and Tx clocks. It also sets default Decimation enables oversampling while maintaining a slower operation of the DLL to 4(cid:1) mode. external data transfer rate and provides superior suppression of out of band signals and noise. Multiplexing enables fewer digital Normal Operation is typically recommended because the RxADC output bits to be used to transfer data from the Rx path to the is more sensitive to the jitter and noise that the DLL may gener- digital ASIC collecting the data. ate, so its performance may degrade. The Mode/TxBlank pin logic level at power up or RESET defines in which mode the When Mux Mode is enabled with an output data rate equal to device powers up. If Mode/TxBlank is low at power up, the CLKOUT1 (Timing No. 3 in Figure 9) then the RxSync pin is Normal Operation mode is configured. Otherwise, the Alternative required to identify which channel’s output data is on the output Operation mode is configured. data bus. RxSync output is aligned with the output data, and by default a logic low indicates data from Rx Channel B is currently Rx Path (Normal Operation) on the output data bus. If RxSync is logic high, then data from The ADC sampling rate, the Rx data output rate, and the rate of RxChannel A is currently on the output data bus. The Inv RxSync CLKOUT1 (clock used to latch output data) are the parameters register can be used to switch this notation. of interest for the receive path data. These parameters in addition to the data bandwidth are related to CLKIN by decimation filters, The CLKOUT1 pin outputs a clock at the frequency of CLKIN or divide by two circuits, data multiplexer logic and retiming latches. CLKIN/2 depending on the voltage level applied to the CLKSEL The Rx path timing can be broken into two separate relation- pin. If a logic low is applied to CLKSEL, CLKOUT1 will run ships: the ADC sample rate relative to the input clock, CLKIN at half the CLKIN rate, if CLKSEL is set to logic high CLKOUT1 and the output data rate relative to CLKOUT1. outputs a clock equal to CLKIN. The ADCs sample rate relative to CLKIN is controlled by the This timing flexibility along with the invert option for CLKOUT1, ADC Div2 register and the sample rate can be equal to or one half controlled by the Inv 1 register allow for various methods of latch- of the input clock rate. ing data from the Rx path to the digital ASIC, which will process the data. These options are shown in Table Ia and Ib along with The output data relative to CLKOUT1 has many configurations a timing diagram in Figure 9. Not shown is the option to invert providing a flexible interface. The different options are shown in CLKOUT1, controlled by the Inv 1 register. For this mode, relative Figure 8. Table Ia and Ib describe the setup required to obtain timing remains the same except the opposite edges of CLKOUT1 the desired data timing. RxSync is available when the Rx data is would be used. decimated and multiplexed to identify which channel data is present at the output bus. DUAL CHANNEL ADC DIV2 DLL MULT CLKOUT2 DIV 2 EDGES FACTOR INTERP A B C D E F G CLKIN 01:: BB == AA/2 001010::: CCC === B24 (cid:3)(cid:3) BB 001010::: DDD === CCC//24 01:: EE == D2 (cid:3) D F = E/2 001010::: GGG === F24 (cid:3)(cid:3) FF TE(CxAADCNAHCN C OUHTPA EDNXANTCEEEL ERDATE DLL OUTPUT RATE) ADC SAMPLE RATE DLL OUTPUT RATE CLKOUT2 INPUT INPUT Tx DATA RATE (NOT TO EXCEED 64MHz) (NOT TO EXCEED 128MHz) Tx DATA RATE EACH CHANNEL Figure 11.Dual Tx Timing Block Diagram, Alternative Operation f CLKOUT2 Tx DATA TIMING No. 1 fTx = CLKOUT2 Tx DATA TIMING No. 2 fTx = 2(cid:3)CLKOUT2 fT(cid:3)1 fT(cid:3)3 fT(cid:3)2 fT(cid:3)4 Figure 12.Tx Timing Diagram –26– REV. 0

AD9860/AD9862 Tx Path (Normal Operation) Table II. CLKOUT2 Timing Relative to CLKIN The DAC update rate, the Tx input data rate, and the rate of for Normal Operation Mode CLKOUT2 (clock used to latch Tx input data) are the parameters DLL CLKOUT2 of interest for the transmit path data. These parameters, in addition CLK DIV2 Mult Div Factor CLKOUT2 to the output signal bandwidth, are related to CLKIN by the settings of the ADC Div2, the DLL multiplier, the CLKOUT2 Div, the (cid:4)1 CLKIN two edges, and the interpolation registers. 1(cid:1) (cid:4)2 CLKIN/2 The Tx data is timed relative to the CLKOUT2 pin (unless it is (cid:4)4 CLKIN/4 retimed relative to CLKOUT1 by setting Tx Retime register) and (cid:4)1 2(cid:1)CLKIN the input Tx data is latched on either each rising edge, each No Div 2(cid:1) (cid:4)2 CLKIN falling edge or both edges (controlled through the Inverse Sample (cid:4)4 CLKIN/2 and two edges registers). The timing diagrams for these cases are shown in Figure12. (cid:4)1 4(cid:1)CLKIN 4(cid:1) (cid:4)2 2(cid:1)CLKIN The Dual Tx data is multiplexed onto a single bus so that fewer (cid:4)4 CLKIN digital bits are necessary to transfer data. Throughout this discus- sion of Tx path timing, Tx digital processing options other than (cid:4)1 CLKIN/2 interpolation are ignored because they do not change data timing; 1(cid:1) (cid:4)2 CLKIN/4 Tx data timing reflects whether single or dual channel data is (cid:4)4 CLKIN/8 latched into the AD9860/AD9862. (cid:4)1 CLKIN The rates of CLKOUT2 (and the input data rate) are related Div by 2 2(cid:1) (cid:4)2 CLKIN/2 toCLKIN by the DLL Multiplier Register, the setting of the (cid:4)4 CLKIN/4 CLKOUT2 Divide Factor Register and the register ADC Div2. (cid:4)1 2(cid:1)CLKIN These relationships are shown in Table II. 4(cid:1) (cid:4)2 CLKIN (cid:4)4 CLKIN/2 NO DECIMATION, 2 ADC DATA MUX Rx DATA 1(cid:3), 1/2(cid:3) AND [0:23] LATCH DIV DECIMATE: REG D6 B0 MUX OUT: REG D5 B0 ADC DIV2: Rx RETIME: REG D5 B3 REG D24 B5 1(cid:3), 1/2(cid:3) NO INVERSION, INVERT DIV INV CLKOUT1 1(cid:3), 2(cid:3), 4(cid:3) CLKIN DLL CLKSEL INV1: REG D25 B1 DLL MULTIPLIER: 1(cid:3), 1/2(cid:3), 1/4(cid:3) NO INVERSION, INVERT REG D24 B3, 4 DIV INV CLKOUT2 CLKOUT2 DIV FACTOR: INV2: REG D25 B5 REG 25 B6, 7 NO INTERP, 2, 4 DATA LATCH DAC AND Tx DATA DEMUX [0:13] INTERPOLATION: 2 DATA PATHS: REG D19 B4 CLOCK PATH REG D19 B0, 1 Q/I ORDER: REG D18 B5 DATA PATH Tx RETIME: REG D18 B6 Figure 13.Alternative Operation Timing Block Diagram REV. 0 –27–

AD9860/AD9862 The timing block diagrams in Figures 10 and 11 show how the pin. If a logic low is applied to CLKSEL, CLKOUT1 will run at various clocks of the single and dual Tx path are affected by the half the CLKIN rate; if CLKSEL is set to logic high, CLKOUT1 various register settings. outputs a clock equal to CLKIN. For dual Tx data, an option to redirect demultiplexed data to This timing flexibility, along with the invert option for CLKOUT1 either path is available. For example, the AD9860/AD9862 can controlled by the Inv 1 Register, allows for various methods of accept complex data in the form of I then Q data or Q then I data, latching data from the Rx path to the digital ASIC, which will pro- controlled through QI Order register. cess the data. These options are shown in Table Ia and Ib along with a timing diagram in Figure 9. Not shown is the option to For the dual Tx data cases, the Tx_SYNC Pin input logic level invert CLKOUT1, controlled by the Inv 1 register. For this defines what data is currently on the Tx data bus. By default, when mode, relative timing remains the same except the opposite edges Tx_SYNC is low, Channel A data (first of the set) should be on of CLKOUT1 would be used. the data bus; if TxSYNC is high, ChannelB data (or the second of the set) should be on the Tx bus. This can be reversed be setting Overall, relative timing can be found by using the Alternative the Inv TxSYNC register. Operation Mode Master Timing Guide in Table V and using Rx timing shown in Figure 9. Rx Path (Alternative Timing Operation) The ADC sampling rate, the Rx data output rate and the rate of Tx Path (Alternative Timing Operation) CLKOUT1 (clock used to latch output data) are the parameters of The DAC update rate, the Tx input data rate and the rate of interest for the receive path data. These parameters, in addition CLKOUT2 (clock used to latch Tx input data) are the parameters to the data bandwidth, are related to CLKIN by decimation filters, of interest for the transmit path data. These parameters in addi- divide by two circuits, data multiplexer logic retiming latches and tion to the output signal bandwidth are related to CLKIN by the also the DLL multiplication setting (which is not the case for settings of the DLL multiplier, the CLKOUT2 Div, the two edge Normal Operation mode). This mode can be configured by and the Interpolation registers (in this mode, the ADC Div2 default by forcing the Tx_Blank_In pin to a logic high level during register does not affect Tx timing). power up. The Tx data is timed relative to the CLKOUT2 pin (unless it is The Rx path timing can be broken into two separate relationships: retimed relative to CLKOUT1 by setting Tx Retime register) and the ADC sample rate relative to the input clock, CLKIN and remains the same as it does in Normal Operation Mode. The input the output data rate relative to CLKOUT1. Tx data is latched on each rising edge, each falling edge or both edges (controlled through the Inverse Sample and two edge regis- The ADCs sample rate relative to CLKIN is controlled by the ADC ters). The timing diagrams for these cases are shown in Figure12. Div2 register and the DLL Multiplier register. The sample rate can be equal to or one half of the DLL output clock rate. The Dual Tx data is multiplexed onto a single bus so that fewer digital bits are necessary to transfer data. Throughout this discus- The output data rate relative to CLKOUT1 for the Alternative sion of Tx path timing, Tx digital processing options other than Operation Mode has the same configuration options as in the interpolation are ignored because they do not change data timing; Normal Operation Mode. The different options are shown in Tx data timing reflects whether single or dual channel data is Figure9. Table Ia. and Ib. describe the setup required to obtain latched into the AD9860/AD9862. the desired data timing. The rates of CLKOUT2 (and the input data rate) are related to The Rx data (unless retimed using the Rx Retime register) is CLKIN by the DLL Multiplier register and the setting of the timed relative to the CLKOUT1 pin output. The Rx output data CLKOUT2 Divide Factor register. These relationships are shown can be decimated (halving the data rate) or both channels can be in Table III. multiplexed onto the ChannelA data bus (doubling the data rate). Decimation enables oversampling while maintaining a slower Table III. CLKOUT2 Timing Relative to CLKIN external data transfer rate and provides superior suppression of In Alternative Operation Mode out of band signals and noise. Multiplexing enables fewer digital output bits to be used to transfer data from the Rx path to the DLL CLKOUT2 digital ASIC collecting the data. Mult Div Factor CLKOUT2 When Multiplexing mode is enabled with an output data rate equal 1(cid:1) (cid:4)1 CLKIN to CLKOUT1 (Timing No. 3 in Figure 9), then the RxSync pin (cid:4)2 CLKIN/2 is required to identify which channel’s output data is on the (cid:4)4 CLKIN/4 output data bus. RxSync output is aligned with the output data 2(cid:1) (cid:4)1 2(cid:1)CLKIN and by default, a logic low indicates data from Rx ChannelB is (cid:4)2 CLKIN currently on the output data bus. If RxSync is logic high, then data (cid:4)4 CLKIN/2 from Rx ChannelA is currently on the output data bus. The Inv RxSync register can be used to switch this notation. 4(cid:1) (cid:4)1 4(cid:1)CLKIN (cid:4)2 2(cid:1)CLKIN The CLKOUT1 pin outputs a clock at a frequency of CLKIN or (cid:4)4 CLKIN CLKIN/2 depending on the voltage level applied to the CLKSEL –28– REV. 0

AD9860/AD9862 Table IV. Normal Operation Mode Master Timing Guide ADCDataRate1(MSPS) DualDACDataRate2 (MSPS) CLKOUT1 2CLKOUT2 ADC DAC DLL ADC2 Clock Update Mult Rate Rate Non-MUXMode MeUXMode 1(cid:1) 2(cid:1) 4(cid:1) CLKSEL CLKSEL CLKDIV CLKDIVCLKDIV NoDeci Deciby2 NoDeci Deciby2 Interp Interp Interp =Low =High =1(cid:1) =1⁄2(cid:1) =1⁄4(cid:1) 0 1(cid:1) 2(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN (cid:5)2 (cid:5)2 (cid:5)4 0 2(cid:1) CLKIN CLKIN CLKIN 2(cid:1) CLKIN 2(cid:1) 4(cid:1) 2(cid:1) 2(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN (cid:5)2 (cid:5)2 CLKIN 0 4(cid:1) 4(cid:1) 8(cid:1) 4(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN 1 1(cid:1) CLKIN CLKIN CLKIN CLKIN (cid:5)2 CLKIN CLKIN CLKIN (cid:5)2 (cid:5)4 (cid:5)8 (cid:5)2 (cid:5)2 (cid:5)4 1 2(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN 2(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN (cid:5)2 (cid:5)4 (cid:5)2 (cid:5)2 (cid:5)4 (cid:5)2 (cid:5)2 1 4(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 2(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN (cid:5)2 NOTES 1100 MHz rate max. 2 Single DAC data rate = 1⁄2 dual DAC data rate. Table V. Alternative Operation Mode Master Timing Guide ADCDataRate1(MSPS) DualDACDataRate2 (MSPS) CLKOUT1 2CLKOUT2 ADC DAC DLL ADC2 Clock Update Mult Rate Rate Non-MUXMode MUXMode (twobuses) (onebus) 1(cid:1) 2(cid:1) 4(cid:1) CLKSEL CLKSEL CLKDIV CLKDIVCLKDIV NoDeci Deciby2 NoDeci Deciby2 Interp Interp Interp =Low =High =1(cid:1) =1⁄2(cid:1) =1⁄4(cid:1) 0 1(cid:1) CLKIN CLKIN CLKIN 2(cid:1) CLKIN CLKIN 2(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN (cid:5)2 CLKIN CLKIN (cid:5)2 (cid:5)2 (cid:5)2 (cid:5)4 2(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 2(cid:1) 2(cid:1) CLKIN 0 2(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN (cid:5)2 4(cid:1) 4(cid:1) 2(cid:1) 8(cid:1) 4(cid:1) 4(cid:1) 8(cid:1) 4(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 0 4(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN 2(cid:1) 1 1(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN (cid:5)2 (cid:5)2 (cid:5)4 (cid:5)2 (cid:5)2 (cid:5)2 (cid:5)2 (cid:5)4 CLKIN 2(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 2(cid:1) 2(cid:1) CLKIN 1 2(cid:1) CLKIN CLKIN (cid:5)2 CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN (cid:5)2 2(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 4(cid:1) 8(cid:1) 4(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 4(cid:1) 2(cid:1) 1 4(cid:1) CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN NOTES 1100 MHz rate max. 2 Single DAC data rate = 1⁄2 dual DAC data rate. REV. 0 –29–

AD9860/AD9862 The timing block diagrams in Figures 14 and 15 show how the The AUX ADC A multiplexer controls whether pin AUX_ADC_A1 various clocks of the single and dual Tx path are affected by the or pin AUX_ADC_A2 is connected to the input of Auxiliary various register settings. ADC A. The multiplexer is programmed through Register D34 For dual Tx data, an option to redirect demultiplexed data to B1, SelectA. By default, the register is low, which connects the either path is available. For example, the AD9860/AD9862 can AUX_ADC_A2 Pin to the input. Similarly, AUX ADC B has a accept complex data in the form of I then Q data or Q then I data, multiplexed input controlled by Register D34 B4, SelectB. The controlled through QI Order register. default setting for SelectB is low, which connects the AUX_ADC_B2 input pin to AUX ADC B. If the SelectA or SelectB register bit For the dual Tx data cases, the Tx_SYNC pin input logic level is set high, then the AUX_ADC_A1 Pin or the AUX_ADC_B1 defines what data is currently on the Tx data bus. By default, when pin is connected to the respective AUX ADC input. Tx_SYNC is low, Channel A data (first of the set) should be on the data bus. If TxSYNC is high, Channel B data (or the second of An internal reference buffer provides a full-scale reference for the set) should be on the Tx bus. This can be reversed by setting both of the auxiliary ADCs that is equal to the supply voltage for the Inv TxSYNC register. the auxiliary ADCs. An external full-scale reference can be applied to either or both of the AUX ADCs by setting the appropriate ADDITIONAL FEATURES bit(s), RefselB for the AUX ADC B and Refsel A for the AUX In addition to the features mentioned above in the transmit, ADC B in the Register Map. Setting either or both of these bits receive and clock paths, the AD9860/AD9862 also integrates high will disconnect the internal reference buffer and enable the components typically required in communication systems. These externally applied reference from the AUX_REF Pin to the components include auxiliary analog-to-digital converters (AUX respective channel(s). ADC), auxiliary digital-to-analog converters (AUX DAC), and Timing for the auxiliary ADCs is generated from a divided down a sigma-delta output. Rx ADC clock. The divide down ratio is controlled by register Auxiliary ADC D35 B0, CLK/4 and is used to maintain a maximum clock rate of Two auxiliary 10-bit SAR ADCs are available for various external 20MHz. By default, CLK/4 is set low dividing the Rx ADC clock signals throughout the system, such as a Receive Signal Strength by 2; this is acceptable when running the Rx ADC at rate of Indicator (RSSI) function or Temperature Indicator. The auxil- 40MHz or less. At Rx ADC rate greater than 40MHz, the CLK/4 iary ADCs can convert at rates up to 1.25 MSPS and have a register bit should be set high and will divide the Rx ADC clock bandwidth of around 200 kHz. The two auxiliary ADCs (AUX by 4 to derive the auxiliary ADC Clock. The conversion time, ADC A and AUX ADC B) have multiplexed inputs, so that up including setup, takes 16 clock cycles (16 Rx ADC clock cycles); to four system signals can be monitored. when CLK/4 is set low, divide by 2 mode, or 32 clock cycles when CLK/4 is set high. DLL MULT CLKOUT2 DIV INTERP A B C D 00: B = A 00: C = B 00: D = C TxDAC UPDATE RATE CLKIN 01: B = 2 (cid:3) A 01: C = B/2 01: D = 2 (cid:3) C SINGLE CHANNEL 10: B = 4 (cid:3) A 10: C = B/4 10: D = 4 (cid:3) C (CANNOT EXCEED DLL OUTPUT RATE) ADC SAMPLE RATE DLL OUTPUT RATE CLKOUT2 INPUT Tx DATA RATE (NOT TO EXCEED 64MHz) (NOT TO EXCEED 128MHz) (SINGLE CHANNEL) Figure 14.Single Tx Timing Block Diagram, Alternative Operation DUAL CHANNEL DLL MULT CLKOUT2 DIV 2 EDGES FACTOR INTERP A B C D E F 00: B = A 00: C = B 00: F = G TxDAC UPDATE RATE CLKIN 0110:: BB == 24 (cid:3)(cid:3) AA 0110:: CC == BB//24 01:: DD == C2 (cid:3) C E = D/2 0110:: FF == 24 (cid:3)(cid:3) GG E(CAACNHN COHTA ENXNCEELED DLL OUTPUT RATE) ADC SAMPLE RATE DLL OUTPUT RATE CLKOUT2 INPUT INPUT Tx DATA RATE (NOT TO EXCEED 64MHz) (NOT TO EXCEED 128MHz) Tx DATA RATE EACH CHANNEL Figure 15.Dual Tx Timing Block Diagram, Alternative Operation –30– REV. 0

AD9860/AD9862 Conversion is initiated by writing a logic high to one or both of AUX DAC the Start register bits, Register D34 B0 (StartA) and D34 B3 The AD9860/AD9862 has three 8-bit voltage output auxiliary (StartB). When the conversion is complete, the straight binary, DACs, AUX DACs. The AUX DACs are available for supplying 10-bit output data of the AUX ADC is written to one of four various control voltages throughout the system such as a VCXO reserved locations in the register map depending on which auxil- voltage control or external VGA gain control and can typically iary ADC and which multiplexed input is selected. Because the sink or source up to 1 mA. auxiliary ADCs output 10 bits, two register addresses are needed An internal voltage reference buffer provides a full-scale voltage for each data location. reference for both of the AUX DACs equal to the supply voltage Initiating a conversion or retrieving data can also be accomplished for the AUX DACs. The straight binary input codes are written either through the standard Serial Port Interface by reading and to the appropriate registers. If the Slave Mode register bit is writing to the appropriate registers or through a dedicated high, slave mode enabled, the AUX DAC(s) update will occur Auxiliary Serial Port Interface (AUX SPI). The AUX SPI can when the appropriate update register is written to. Otherwise, be configured to allow fast access and control of either one of the the update will occur at the conclusion of the data being written auxiliary ADCs and is available so that the SPI is not tied up to the register. Typical maximum settling time for the auxiliary retrieving auxiliary ADC data. DAC is around 6 ms. The AUX SPI can be enabled and configured by setting register Other optional controls include an invert register control and a AUX ADC CTRL. Setting register use pins high enables the power down option. The invert register control, i.e., instead of AUX SPI port. Setting register Sel BnotA low connects auxiliary hexFF being high and hex00 being low, hex00 is high, and hexFF ADC A to the AUX SPI port, while setting it high connects will be minimum setting. auxiliary ADC B to the AUX SPI port. As mentioned above, Sigma-Delta setting the appropriate Select bit selects which of the multiplexed A 12-bit sigma-delta (SD) output is available to provide an input is connected to the auxiliary ADC. additional control voltage. The SD control word is written to The AUX SPI consists of a chip select pin (AUX_SPI_csb), Registers D42, 43; SD [11:4] are the 8 MSBs and SD [3:0] are aclock pin (AUX_SPI_clk), and a data output pin (AUX_SPI_do). the 4LSBs. The 12-bit word is processed by a sigma-delta A conversion is initiated by pulsing the AUX_SPI_csb pin low. modulator and produces 1-bit data at an oversampled rate equal When the conversion is complete, the data pin, AUX_SPI_do, to 1/8 of the receive ADC’s sampling rate (up to 8 MSPS). The previously a logic low, will go high. At this point, the user supplies 1-bit data then feeds a 1-bit DAC. The 1-bit DAC exhibits an external clock, previously tied low, no data is present on the perfect linearity. An external low-pass filter at the output should first rising edge. The data output bit is updated on the falling be used to low-pass filter the pulse modulated data to produce a edge of the clock pulse and is settled and can be latched on the linear output control voltage. next clock rising edge. The data arrives serially, MSB first. The AUX SPI runs up to a rate of 16 MHz. REV. 0 –31–

AD9860/AD9862 OUTLINE DIMENSIONS 128-Lead Plastic Quad Flatpack [LQFP] (ST-128B) Dimensions shown in millimeters 16.00 BSC 0) 00..7650 M1 .A60X 14.00 BSC 1/02( 0.45 1 128 103 – 1 102 –0 0 SEATING 7 PLANE 9 2 0 C 20.00 BSC TOP VIEW (PINS DOWN) 22.00 BSC 10(cid:6) 1.45 6(cid:6) 1.40 2(cid:6) 0.20 0.09 1.35 VIEW A 7(cid:6) 0(cid:6) 38 65 SEATING 0.08 MAX 39 64 PLANE COPLANARITY 0.50 0.27 VIEW A BSC 0.22 ROTATED 90(cid:6) CCW 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BHB A. S. U. N D I E T N RI P –32– REV. 0