a 12-Bit, 125 MSPS TxDAC® D/A Converter AD9762 FEATURES FUNCTIONAL BLOCK DIAGRAM Member of Pin-Compatible TxDAC Product Family +5V 125 MSPS Update Rate 0.1(cid:1)F 12-Bit Resolution Excellent Spurious Free Dynamic Range Performance REFLO COMP1 AVDD ACOM SFDR to Nyquist @ 5 MHz Output: 70 dBc +1.20V REF AD9762 Differential Current Outputs: 2 mA to 20 mA 0.1(cid:1)F 50pF Power Dissipation: 175 mW @ 5V to 45mW @ 3V REFIO CURRENT COMP2 0.1(cid:1)F FS ADJ SOURCE Power-Down Mode: 25 mW @ 5V ARRAY On-Chip 1.20 V Reference RSET +5V DVDD Single +5 V or +3 V Supply Operation IOUTA SEGMENTED LSB Package: 28-Lead SOIC and TSSOP DCOM SWITCHES SWITCHES IOUTB Edge-Triggered Latches CLOCK CLOCK LATCHES SLEEP APPLICATIONS Communication Transmit Channel: DIGITAL DATA INPUTS (DB11–DB0) Basestations (Single/Multichannel Applications) ADSL/HFC Modems Differential current outputs are provided to support single- Direct Digital Synthesis (DDS) ended or differential applications. Matching between the two Instrumentation current outputs ensures enhanced dynamic performance in a differential output configuration. The current outputs may be PRODUCT DESCRIPTION tied directly to an output resistor to provide two complemen- The AD9762 is the 12-bit resolution member of the TxDAC tary, single-ended voltage outputs or fed directly into a trans- series of high performance, low power CMOS digital-to-analog former. The output voltage compliance range is 1.25V. converters (DACs). The TxDAC family which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs is specifically opti- The on-chip reference and control amplifier are configured for mized for the transmit signal path of communication systems. maximum accuracy and flexibility. The AD9762 can be driven All of the devices share the same interface options, small outline by the on-chip reference or by a variety of external reference package and pinout, thus providing an upward or downward voltages. The internal control amplifier which provides a wide component selection path based on performance, resolution and (>10:1) adjustment span allows the AD9762 full-scale current cost. The AD9762 offers exceptional ac and dc performance to be adjusted over a 2mA to 20 mA range while maintaining while supporting update rates up to 125 MSPS. excellent dynamic performance. Thus, the AD9762 may oper- ate at reduced power levels or be adjusted over a 20dB range to The AD9762’s flexible single-supply operating range of 2.7 V to provide additional gain ranging capabilities. 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further The AD9762 is available in 28-lead SOIC and TSSOP pack- reduced to a mere 45 mW without a significant degradation in ages. It is specified for operation over the industrial tempera- performance by lowering the full-scale current output. Also, a ture range. power-down mode reduces the standby power dissipation to PRODUCT HIGHLIGHTS approximately 25 mW. 1.The AD9762 is a member of the TxDAC product family which The AD9762 is manufactured on an advanced CMOS process. provides an upward or downward component selection path A segmented current source architecture is combined with a based on resolution (8 to 14 bits), performance and cost. proprietary switching technique to reduce spurious components 2.Manufactured on a CMOS process, the AD9762 uses a pro- and enhance dynamic performance. Edge-triggered input prietary switching technique that enhances dynamic perfor- latches and a 1.2 V temperature compensated bandgap refer- mance beyond what was previously attainable by higher ence have been integrated to provide a complete monolithic power/cost bipolar or BiCMOS devices. DAC solution. Flexible supply options support +3 V and +5 V 3.On-chip, edge-triggered input CMOS latches interface readily CMOS logic families. to +3 V and +5 V CMOS logic families. The AD9762 can The AD9762 is a current-output DAC with a nominal full-scale support update rates up to 125 MSPS. output current of 20 mA and > 100 kΩ output impedance. 4.A flexible single-supply operating range of 2.7V to 5.5 V and TxDAC is a registered trademark of Analog Devices, Inc. a wide full-scale current adjustment span of 2mA to 20 mA allow the AD9762 to operate at reduced power levels. REV.B 5.The current output(s) of the AD9762 can be easily config- Information furnished by Analog Devices is believed to be accurate and ured for various single-ended or differential circuit topologies. reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD9762–SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 12 Bits DC ACCURACY1 Integral Linearity Error (INL) T = +25°C –2.5 ±0.75 +2.5 LSB A T to T –4.0 ±1.0 +4.0 LSB MIN MAX Differential Nonlinearity (DNL) T = +25°C –1.5 ±0.5 +1.5 LSB A T to T –2.0 ±0.75 +2.0 LSB MIN MAX ANALOG OUTPUT Offset Error –0.025 +0.025 % of FSR Gain Error (Without Internal Reference) –10 ±2 +10 % of FSR Gain Error (With Internal Reference) –10 ±1 +10 % of FSR Full-Scale Output Current2 2.0 20.0 mA Output Compliance Range –1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.08 1.20 1.32 V Reference Output Current3 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MΩ Small Signal Bandwidth (w/o C )4 1.4 MHz COMP1 TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD5 2.7 5.0 5.5 V DVDD 2.7 5.0 5.5 V Analog Supply Current (I ) 25 30 mA AVDD Digital Supply Current (I )6 1.5 2 mA DVDD Supply Current Sleep Mode (I ) 8.5 mA AVDD Power Dissipation6 (5 V, I = 20 mA) 133 160 mW OUTFS Power Dissipation7 (5 V, I = 20 mA) 190 mW OUTFS Power Dissipation7 (3 V, I = 2 mA) 45 mW OUTFS Power Supply Rejection Ratio—AVDD –0.4 +0.4 % of FSR/V Power Supply Rejection Ratio—DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1Measured at IOUTA, driving a virtual ground. 2Nominal full-scale current, I , is 32 × the I current. OUTFS REF 3Use an external buffer amplifier to drive any external load. 4Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41. 5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6Measured at f = 25 MSPS and f = 1.0 MHz. CLOCK OUT 7Measured as unbuffered voltage output into 50Ω R at IOUTA and IOUTB, f = 100 MSPS and f = 40 MHz. LOAD CLOCK OUT Specifications subject to change without notice. –2– REV. B

AD9762 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, Differential Transformer Coupled Output, DYNAMIC SPECIFICATIONS MIN MAX OUTFS 50(cid:2) Doubly Terminated, unless otherwise noted) Parameter Min Typ Max Units DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 125 MSPS CLOCK Output Settling Time (t ) (to 0.1%)1 35 ns ST Output Propagation Delay (t ) 1 ns PD Glitch Impulse 5 pV-s Output Rise Time (10% to 90%)1 2.5 ns Output Fall Time (10% to 90%)1 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C 75 79 dBc A T to T 73 dBc MIN MAX f = 50 MSPS; f = 1.00 MHz 79 dBc CLOCK OUT f = 50 MSPS; f = 2.51 MHz 74 dBc CLOCK OUT f = 50 MSPS; f = 5.02 MHz 70 dBc CLOCK OUT f = 50 MSPS; f = 20.2 MHz 57 dBc CLOCK OUT f = 100 MSPS; f = 2.51 MHz 73 dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz 67 dBc CLOCK OUT f = 100 MSPS; f = 20.2 MHz 57 dBc CLOCK OUT f = 100 MSPS; f = 40.4 MHz 53 dBc CLOCK OUT Spurious-Free Dynamic Range within a Window f = 25 MSPS; f =1.00 MHz; 2 MHz Span CLOCK OUT T = +25°C 78 86 dBc A T to T 76 dBc MIN MAX f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 84 dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz; 4 MHz Span 84 dBc CLOCK OUT Total Harmonic Distortion f = 25 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C –78 –74 dBc A T to T –72 dBc MIN MAX f = 50 MHz; f = 2.00 MHz –75 dBc CLOCK OUT f = 100 MHz; f = 2.00 MHz –75 dBc CLOCK OUT Multitone Power Ratio (8 Tones at 110 kHz Spacing) f = 20 MSPS; f = 2.00 MHz to 2.99 MHz 73 dBc CLOCK OUT NOTES 1Measured single ended into 50Ω load. Specifications subject to change without notice. REV. B –3–

AD9762 DIGITAL SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V Logic “0” Voltage @ DVDD = +5 V 0 1.3 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10 µA Logic “0” Current –10 +10 µA Input Capacitance 5 pF Input Setup Time (t ) 2.0 ns S Input Hold Time (t ) 1.5 ns H Latch Pulsewidth (t ) 3.5 ns LPW Specifications subject to change without notice. DB0–DB11 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE With Temperature Package Package Parameter Respect to Min Max Units Model Range Description Option* AVDD ACOM –0.3 +6.5 V AD9762AR –40°C to +85°C 28-Lead 300 mil SOIC R-28 DVDD DCOM –0.3 +6.5 V AD9762ARU –40°C to +85°C 28-Lead TSSOP RU-28 ACOM DCOM –0.3 +0.3 V AD9762-EB Evaluation Board AVDD DVDD –6.5 +6.5 V CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V *R = SOIC, RU = TSSOP. Digital Inputs DCOM –0.3 DVDD + 0.3 V IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V THERMAL CHARACTERISTICS COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V Thermal Resistance REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V 28-Lead 300 mil SOIC REFLO ACOM –0.3 +0.3 V θJA = 71.4°C/W Junction Temperature +150 °C θJC = 23°C/W Storage Temperature –65 +150 °C 28-Lead TSSOP Lead Temperature θJA = 97.9°C/W (10 sec) +300 °C θJC = 14.0°C/W *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9762 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE –4– REV. B

AD9762 PIN CONFIGURATION (MSB) DB11 1 28 CLOCK DB10 2 27 DVDD DB9 3 26 DCOM DB8 4 25 NC DB7 5 24 AVDD AD9762 DB6 6 TOP VIEW 23 COMP2 DB5 7 (Not to Scale)22 IOUTA DB4 8 21 IOUTB DB3 9 20 ACOM DB2 10 19 COMP1 DB1 11 18 FS ADJ DB0 12 17 REFIO NC 13 16 REFLO NC 14 15 SLEEP NC = NO CONNECT PIN DESCRIPTIONS Pin No. Name Description 1 DB11 Most Significant Data Bit (MSB). 2–11 DB10–DB1 Data Bits 1–10. 12 DB0 Least Significant Data Bit (LSB). 13,14,25 NC No Internal Connection. 15 SLEEP Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. 16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1µF capacitor to ACOM when internal reference activated. 18 FS ADJ Full-Scale Current Output Adjust. 19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance. 20 ACOM Analog Common. 21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. 24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V). 26 DCOM Digital Common. 27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V). 28 CLOCK Clock Input. Data latched on positive edge of clock. REV. B –5–

AD9762 DEFINITIONS OF SPECIFICATIONS Power Supply Rejection Linearity Error (Also Called Integral Nonlinearity or INL) The maximum change in the full-scale output as the supplies Linearity error is defined as the maximum deviation of the are varied from nominal to minimum and maximum specified actual analog output from the ideal output, determined by a voltages. straight line drawn from zero to full scale. Settling Time Differential Nonlinearity (or DNL) The time required for the output to reach and remain within a DNL is the measure of the variation in analog value, normalized specified error band about its final value, measured from the to full scale, associated with a 1 LSB change in digital input start of the output transition. code. Glitch Impulse Monotonicity Asymmetrical switching times in a DAC give rise to undesired A D/A converter is monotonic if the output either increases or output transients that are quantified by a glitch impulse. It is remains constant as the digital input increases. specified as the net area of the glitch in pV-s. Offset Error Spurious-Free Dynamic Range The deviation of the output current from the ideal of zero is The difference, in dB, between the rms amplitude of the output called offset error. For IOUTA, 0 mA output is expected when the signal and the peak spurious signal over the specified bandwidth. inputs are all 0s. For I , 0 mA output is expected when all OUTB Total Harmonic Distortion inputs are set to 1s. THD is the ratio of the rms sum of the first six harmonic Gain Error components to the rms value of the measured output signal. It is The difference between the actual and ideal output span. The expressed as a percentage or in decibels (dB). actual span is determined by the output when all inputs are set Multitone Power Ratio to 1s minus the output when all inputs are set to 0s. The spurious-free dynamic range for an output containing mul- Output Compliance Range tiple carrier tones of equal amplitude. It is measured as the The range of allowable voltage at the output of a current-output difference between the rms amplitude of a carrier tone to the DAC. Operation beyond the maximum compliance limits may peak spurious signal in the region of a removed tone. cause either output stage saturation or breakdown resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either T or T . For MIN MAX offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. +5V 0.1(cid:1)F REFLO COMP1 AVDD ACOM +1.20V REF AD9762 0.1(cid:1)F 50pF REFIO PMOS 0.1(cid:1)F FS ADJ CURRENT SOURCE COMP2 ARRAY MINI-CIRCUITS RSET T1-1T 2k(cid:2) +5V DVDD TO HP3589A IOUTA SPECTRUM/ DCOM SEGMFOERN TDEBD1 1S–WDIBTC3HES SWILTSCBHES IOUTB 100(cid:2) NAENTAWLYOZREKR 50(cid:2) INPUT CLOCK LATCHES DDCVODMD 50(cid:2) SLEEP 50(cid:2) 20pF RETIMED 50(cid:2) CLOCK DIGITAL 20pF OUTPUT* CLOCK DATA * AWG2021 CLOCK RETIMED LECROY 9210 OUTPUT TEKTRONIX SUCH THAT DIGITAL DATA PULSE GENERATOR AWG-2021 TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 2.Basic AC Characterization Test Set-Up –6– REV. B

AD9762 Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = +5 V, I = 20 mA, 50(cid:2) Doubly Terminated Load, Differential Output, T = +25(cid:3)C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 90 85 85 –6dBFS –6dBFS 80 80 0dBFS –12dBFS 80 5MSPS 25MSPS 75 –12dBFS 75 Bc Bc Bc R – d70 50MSPS R – d70 R – d70 0dBFS SFD SFD65 SFD65 100MSPS 60 60 60 125MSPS 55 55 50 50 50 0.1 1 10 100 0.00 0.50 1.00 1.50 2.00 2.50 0.00 2.00 4.00 6.00 8.00 10.00 12.00 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 3.SFDR vs. f @ 0 dBFS Figure 4.SFDR vs. f @ 5MSPS Figure 5.SFDR vs. f @ 25 MSPS OUT OUT OUT 85 85 85 80 80 80 –6dBFS 75 75 75 Bc –12dBFS Bc Bc R – d70 R – d70 –6dBFS R – d70 SFD65 SFD65 –12dBFS SFD65 –6dBFS –12dBFS 0dBFS 60 60 60 0dBFS 55 55 55 0dBFS 50 50 50 0.00 5.00 10.00 15.00 20.00 25.00 0.00 10.00 20.00 30.00 40.00 50.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 6.SFDR vs. f @ 50 MSPS Figure 7.SFDR vs. f @100 MSPS Figure 8.SFDR vs. f @ 125 MSPS OUT OUT OUT 85 85 455kHz 1MHz 0.675/0.725MHz @ 5MSPS @ 5MSPS 80 @ 5MSPS 75 @ 22.52M7MSPHSz 4.55MHz 75 @ 2 55.M0MSPHSz 10MHz 3.3@8/ 32.56M3MSPHSz Bc @ 50MSPS Bc @ 50MSPS Bc70 d d d R – 65 R – 65 R – D D D60 SF 9.1MHz SF SF 13.5/14.5MHz @ 100MSPS @ 100MSPS 55 11.37MHz 55 20MHz 16.9/18.1MHz @ 125MSPS 25MHz @ 100MSPS 50 6.75/7.25MHz @ 125MSPS @ 125MSPS @ 50MSPS 45 45 40 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 AOUT – dBFS AOUT – dBFS AOUT – dBFS Figure 9.Single-Tone SFDR vs. A Figure 10.Single-Tone SFDR vs. Figure 11.Dual-Tone SFDR vs. A OUT OUT @ f = f /11 A @ f = f /5 @ f = f /7 OUT CLOCK OUT OUT CLOCK OUT CLOCK REV. B –7–

AD9762 –70 80 75 75 2.5MHz IDIFF @ 0dBFS –75 70 70 10MHz IDIFF @ –6dBFS 2ND 65 –80 HARMONIC Bc 60 22.2MHz Bc 65 dBc–85 HARMO 3NRICD SFDR – d 5505 40MHz SFDR – d 60 IOUTA @ 0dBFS 55 45 IOUTA @ –6dBFS –90 40 50 4TH HARMONIC 35 –95 30 45 0 20 40 60 80 100 120 140 2 4 6 8 10 12 14 16 18 20 1 10 100 FREQUENCY – MSPS IOUTFS – mA OUTPUT FREQUENCY – MHz Figure 12. THD vs. f @ Figure 13.SFDR vs. f and I Figure 14.Differential vs. Single- CLOCK OUT OUTFS f = 2MHz @ 100 MSPS, 0 dBFS Ended SFDR vs. f @ 100 MSPS OUT OUT 1.25 1 80 1.00 0.75 0.8 75 2.5MHz 0.50 0.6 OR – LSB 0.250 OR – LSB 00..24 R – dBc 7605 10MHz RR–0.25 RR FD E–0.50 E 0 S 60 –0.75 –0.2 55 –1.00 40MHz –0.4 –1.25 50 0 1000 2000 3000 4000 0 1000 2000 3000 4000 –40 –20 0 20 40 60 80 CODE CODE TEMPERATURE – (cid:3)C Figure 15.Typical INL Figure 16.Typical DNL Figure 17.SFDR vs. Temperature @ 100 MSPS, 0 dBFS 0 0 –10 ffSACOFMLUDOPTRC L=K I =T2 = U.74 21D1d0EM0B H =cM z0SdPBSFS fffSCOOFLUUDOTTRC12 K === = 116 3421..d0550BMM cMHHzzSPS ffffCOOOLUUUOTTTC123 K=== =667 ...52720555 MMMMHHHSzzzPS AMPLITUDE = 0dBFS fOUT4 = 7.75MHz SFDR = 71dBc Div Div Div AMPLITUDE = 0dBFS B – B – B – 10d 10d 10d –100 –100 –110 START: 0.3 MHz STOP: 50.0 MHz START: 0.3 MHz STOP: 50.0 MHz START: 0.3 MHz STOP: 25.0 MHz Figure 18.Single-Tone SFDR Figure 19.Dual-Tone SFDR Figure 20.Four-Tone SFDR –8– REV. B

AD9762 Typical AC Characterization Curves @ +3 V Supplies (AVDD = +3 V, DVDD = +3 V, I = 20 mA, 50Ω Doubly Terminated Load, Differential Output, T = +25(cid:3)C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 90 85 85 0dBFS 80 –6dBFS 80 80 5MSPS –12dBFS 75 75 Bc 25MSPS Bc –12dBFS Bc R – d70 50MSPS R – d 70 R – d70 –6dBFS SFD 100MSPS SFD 65 SFD65 0dBFS 60 60 60 125MSPS 55 55 50 50 50 0.1 1 10 100 0.00 0.50 1.00 1.50 2.00 2.50 0 2 4 6 8 10 12 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 21.SFDR vs. f @ 0 dBFS Figure 22.SFDR vs. f @ 5 MSPS Figure 23.SFDR vs. f @ 25 MSPS OUT OUT OUT 85 85 85 80 80 80 75 –6dBFS 75 75 c –12dBFS c B c B FDR – d7605 DR – dB7605 –6dB–1F2SdBFS FDR – d 7605 0dBFS S SF S –12dBFS 0dBFS 60 60 60 –6dBFS 55 55 0dBFS 55 50 50 50 0 5 10 15 20 25 0 10 20 30 40 50 0 10 20 30 40 50 60 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 24.SFDR vs. f @ 50 MSPS Figure 25.SFDR vs. f @ 100 MSPS Figure 26.SFDR vs. f @ 125 MSPS OUT OUT OUT 90 90 90 455kHz @ 5MSPS 1MHz 0.675/0.725MHz 4.55MHz @ 5MSPS @ 5MSPS 80 @ 50MSPS 80 80 2.27MHz 5.0MHz 3.38/3.63MHz @ 25MSPS @ 25MSPS @ 25MSPS Bc70 Bc70 Bc70 6.75/7.25MHz d d d @ 50MSPS – – 10MHz – R R @ 50MSPS R SFD60 @ 10 90.M1MSPHSz SFD60 SFD60 16.9/18.1MHz 11.37MHz 20MHz @ 125MSPS 50 @ 125MSPS 50 @ 100MSPS 50 25MHz @ 125MSPS 13.5/14.5MHz @ 100MSPS 40 40 40 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 AOUT – dBFS AOUT – dBFS AOUT – dBFS Figure 27.Single-Tone SFDR vs. A Figure 28.Single-Tone SFDR vs. Figure 29.Dual-Tone SFDR vs. A OUT OUT @ f = f /11 A @ f = f /5 @ f = f /7 OUT CLOCK OUT OUT CLOCK OUT CLOCK REV. B –9–

AD9762 –70 80 75 2.5MHz 75 –75 70 70 IDIFF @ 2ND –6dBFS HARMONIC 65 10MHz 3RD 65 dBc––8805 HARMONIC SFDR – dBc 655005 4202M.2HMzHz SFDR – dBc 6505 IOUTA @ ID0dIFBFF @S 45 –6dBFS –90 4TH 40 HARMONIC 50 IOUTA @ 35 0dBFS –95 30 45 0 20 40 60 80 100 120 140 2 4 6 8 10 12 14 16 18 20 1 10 100 FREQUENCY – MSPS IOUTFS – mA OUTPUT FREQUENCY – MHz Figure 30.THD vs. f @ f = Figure 31.SFDR vs. f and I Figure 32.Differential vs. Single CLOCK OUT OUT OUTFS 2MHz @ 100 MSPS, 0 dBFS Ended SFDR vs. f @ 100 MSPS OUT 1.25 1 80 1.00 0.8 75 0.75 2.5MHz 0.6 0.50 B B 70 S 0.25 S 0.4 c L L B OR – 0 OR – 0.2 R – d 65 ERR–0.25 ERR 0 SFD 60 10MHz –0.50 –0.75 –0.2 55 –1.00 28.6MHz –0.4 –1.25 50 0 1000 2000 3000 4000 0 1000 2000 3000 4000 –40 –20 0 20 40 60 80 CODE CODE TEMPERATURE – (cid:3)C Figure 33.Typical INL Figure 34.Typical DNL Figure 35.SFDR vs. Temperature @ 100 MSPS, 0 dBFS 0 0 –10 fCLOCK = 100 MSPS fCLOCK = 100 MSPS fCLOCK = 50 MSPS fOUT = 2.41MHz fOUT1 = 13.5MHz fOUT1 = 6.25MHz SFDR = 72dBc fOUT2 = 14.5MHz fOUT2 = 6.75MHz AMPLITUDE = 0dBFS SFDR = 59.0dBc fOUT3 = 7.25MHz AMPLITUDE = 0dBFS fOUT4 = 7.75MHz Div Div Div SFDR = 71dBc – – – AMPLITUDE = 0dBFS B B B d d d 0 0 0 1 1 1 –100 –100 –110 START: 0.3 MHz STOP: 50.0 MHz START: 0.3 MHz STOP: 50.0 MHz START: 0.3 MHz STOP: 25.0 MHz Figure 36.Single-Tone SFDR Figure 37.Dual-Tone SFDR Figure 38.Four-Tone SFDR –10– REV. B

AD9762 FUNCTIONAL DESCRIPTION I = (DAC CODE/4096) × I (1) OUTA OUTFS Figure 39 shows a simplified block diagram of the AD9762. I = (4095 – DAC CODE)/4096 × I (2) The AD9762 consists of a large PMOS current source array OUTB OUTFS that is capable of providing up to 20mA of total current. The where DAC CODE = 0 to 4095 (i.e., Decimal Representation). array is divided into 31 equal currents that make up the 5 As mentioned previously, I is a function of the reference OUTFS most significant bits (MSBs). The next 4 bits or middle bits current I , which is nominally set by a reference voltage REF consist of 15 equal current sources whose value is 1/16th of an V and external resistor R . It can be expressed as: REFIO SET MSB current source. The remaining LSBs are binary weighted I = 32 × I (3) fractions of the middle-bits current sources. Implementing OUTFS REF the middle and lower bits with current sources, instead of an where I = V /R (4) REF REFIO SET R-2R ladder, enhances its dynamic performance for multitone The two current outputs will typically drive a resistive load or low amplitude signals and helps maintain the DAC’s high directly or via a transformer. If dc coupling is required, I output impedance (i.e., >100kΩ). OUTA and I should be directly connected to matching resistive OUTB All of these current sources are switched to one or the other loads, R , which are tied to analog common, ACOM. Note, LOAD of the two output nodes (i.e., I or I ) via PMOS differen- R may represent the equivalent load resistance seen by OUTA OUTB LOAD tial current switches. The switches are based on a new archi- I or I as would be the case in a doubly terminated OUTA OUTB tecture that drastically improves distortion performance. This new 50Ω or 75Ω cable. The single-ended voltage output appearing switch architecture reduces various timing errors and provides at the I and I nodes is simply : OUTA OUTB matching complementary drive signals to the inputs of the V = I × R (5) OUTA OUTA LOAD differential current switches. V = I × R (6) OUTB OUTB LOAD The analog and digital sections of the AD9762 have separate Note the full-scale value of V and V should not exceed power supply inputs (i.e., AVDD and DVDD) that can operate OUTA OUTB the specified output compliance range to maintain specified independently over a 2.7 volt to 5.5 volt range. The digital distortion and linearity performance. section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding The differential voltage, V , appearing across I and DIFF OUTA logic circuitry. The analog section includes the PMOS current I is: OUTB sources, the associated differential switches, a 1.20 V bandgap V = (I – I ) × R (7) voltage reference and a reference control amplifier. DIFF OUTA OUTB LOAD Substituting the values of I , I , and I ; V can be The full-scale output current is regulated by the reference OUTA OUTB REF DIFF expressed as: control amplifier and can be set from 2 mA to 20 mA via an ewxittehr nbaolt hre tshiset orre,f eRrSeEnTc. eT choen etxrotel ranmalp rleisfiiestro ar,n idn vcoolmtabgien aretifoenr- V(3D2I FRF L=O A{D(/2R DSEAT)C × C VORDEFEIO – 4095)/4096} × (8) ence VREFIO, sets the reference current IREF, which is mirrored These last two equations highlight some of the advantages of over to the segmented current sources with the proper scaling operating the AD9762 differentially. First, the differential factor. The full-scale current, IOUTFS, is thirty-two times the value operation will help cancel common-mode error sources associated of IREF. with IOUTA and IOUTB such as noise, distortion and dc offsets. Second, the differential code dependent current and subsequent DAC TRANSFER FUNCTION voltage, V , is twice the value of the single-ended voltage DIFF The AD9762 provides complementary current outputs, IOUTA output (i.e., VOUTA or VOUTB), thus providing twice the signal and IOUTB. IOUTA will provide a near full-scale current output, power to the load. I , when all bits are high (i.e., DAC CODE = 4095) while OUTFS Note, the gain drift temperature performance for a single-ended I , the complementary output, provides no current. The OUTB (V and V ) or differential output (V ) of the AD9762 current output appearing at I and I is a function of OUTA OUTB DIFF OUTA OUTB can be enhanced by selecting temperature tracking resistors for both the input code and I and can be expressed as: OUTFS R and R due to their ratiometric relationship as shown LOAD SET in Equation 8. +5V 0.1(cid:1)F REFLO COMP1 AVDD ACOM +1.20V REF AD9762 50pF VREFIO REFIO PMOS 0.1(cid:1)F 0.1(cid:1)F IREF FS ADJ CURREANRTR ASOYURCE COMP2 RSET VDIFF = VOUTA – VOUTB 2k(cid:2) +5V DVDD IOUTA IOUTA DCOM SEGMFOERN TDEBD1 1S–WDIBTC3HES SWILTSCBHES IOUTB IOUTB VOUTB VROLOUATAD CLOCK CLOCK LATCHES RLOAD 50(cid:2) SLEEP 50(cid:2) DIGITAL DATA INPUTS (DB11–DB0) Figure 39.Functional Block Diagram REV. B –11–

AD9762 REFERENCE OPERATION The control amplifier allows a wide (10:1) adjustment span of The AD9762 contains an internal 1.20 V bandgap reference I over a 2mA to 20 mA range by setting IREF between OUTFS that can be easily disabled and overridden by an external refer- 62.5µA and 625µA. The wide adjustment span of I OUTFS ence. REFIO serves as either an input or output depending on provides several application benefits. The first benefit relates whether the internal or an external reference is selected. If directly to the power dissipation of the AD9762, which is REFLO is tied to ACOM, as shown in Figure 40, the internal proportional to I (refer to the Power Dissipation section). OUTFS reference is activated and REFIO provides a 1.20V output. In The second benefit relates to the 20dB adjustment, which is this case, the internal reference must be compensated externally useful for system gain control purposes. with a ceramic chip capacitor of 0.1µF or greater from REFIO The small signal bandwidth of the reference control amplifier is to REFLO. Also, REFIO should be buffered with an external approximately 1.4 MHz and can be reduced by connecting an amplifier having an input bias current less than 100nA if any external capacitor between COMP1 and AVDD. The output of additional loading is required. the control amplifier, COMP1, is internally compensated via a 50 pF capacitor that limits the control amplifier small-signal +5V bandwidth and reduces its output impedance. Any additional 0.1(cid:1)F OPTIONAL external capacitance further limits the bandwidth and acts as a EXTERNAL filter to reduce the noise contribution from the reference ampli- REF BUFFER REFLO COMP1 AVDD fier. Figure 42 shows the relationship between the external +1.2V REF capacitor and the small signal –3dB bandwidth of the 50pF REFIO CURRENT ADDITIOLONAADL 0.1(cid:1)F FS ADJ SAORURRACYE 1000 2k(cid:2) AD9762 Figure 40.Internal Reference Configuration Hz The internal reference can be disabled by connecting REFLO to – k AVDD. In this case, an external reference may then be applied DTH 10 to REFIO as shown in Figure 41. The external reference may WI D provide either a fixed reference voltage to enhance accuracy and N A drift performance or a varying reference voltage for gain control. B Note that the 0.1µF compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the external reference. 0 0.1 1 10 100 1000 COMP1 CAPACITOR – nF AVDD Figure 42.External COMP1 Capacitor vs. –3dB Bandwidth 0.1(cid:1)F reference amplifier. Since the –3dB bandwidth corresponds to the dominant pole, and hence the time constant, the settling AVDD REFLO COMP1 AVDD time of the control amplifier to a stepped reference input response can be approximated. +1.2V REF 50pF EXTREERFNAL VREFIO RFSE FAIODJ CSUORURRECNET Twahvee ofoprtmim ius mob dtaisitnoerdti owni tphe ar f0o.r1mµaFn ceex tfeorrn aanl yc arpecaocintsotrr uincstteadlled. ARRAY Thus, if I is fixed for an application, a 0.1µF ceramic chip RSET IREF = capacitor RisE Frecommended. Also, since the control amplifier is VREFIO/RSET AD9762 RCEOFNETRREONLCE optimized for low power operation, multiplying applications AMPLIFIER requiring large signal swings should consider using an external control amplifier to enhance the application’s overall large signal Figure 41.External Reference Configuration multiplying bandwidth and/or distortion performance. REFERENCE CONTROL AMPLIFIER There are two methods in which IREF can be varied for a fixed The AD9762 also contains an internal control amplifier that is RSET. The first method is suitable for a single-supply system in used to regulate the DAC’s full-scale output current, I . which the internal reference is disabled, and the common-mode OUTFS The control amplifier is configured as a V-I converter as shown voltage of REFIO is varied over its compliance range of 1.25 V in Figure 41, such that its current output, I , is determined by to 0.10 V. REFIO can be driven by a single-supply amplifier or REF the ratio of the VREFIO and an external resistor, RSET, as stated DAC, thus allowing IREF to be varied for a fixed RSET. Since the in Equation 4. I is copied over to the segmented current input impedance of REFIO is approximately 1 MΩ, a simple, REF sources with the proper scaling factor to set I as stated in low cost R-2R ladder DAC configured in the voltage mode OUTFS Equation 3. topology may be used to control the gain. This circuit is shown in Figure 43 using the AD7524 and an external 1.2 V reference, the AD1580. –12– REV. B

AD9762 AVDD AVDD OPTIONAL BANDLIMITING CAPACITOR REFLO COMP1 AVDD RFB VDD +1.2V REF 50pF 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 VREF CURRENT AD1580 OUT2 FS ADJ SOURCE ARRAY AGND RSET IREF = AD9762 VREF/RSET DB7–DB0 Figure 43.Single-Supply Gain Control Circuit The second method may be used in a dual-supply system in ANALOG OUTPUTS which the common-mode voltage of REFIO is fixed and I is The AD9762 produces two complementary current outputs, REF varied by an external voltage, V , applied to R via an ampli- I and I , which may be configured for single-ended or GC SET OUTA OUTB fier. An example of this method is shown in Figure 44 in which differential operation. I and I can be converted into OUTA OUTB the internal reference is used to set the common-mode voltage complementary single-ended voltage outputs, V and V , OUTA OUTB of the control amplifier to 1.20V. The external voltage, V , is via a load resistor, R , as described in the DAC Transfer GC LOAD referenced to ACOM and should not exceed 1.2 V. The value Function section by Equations 5 through 8. The differential of R is such that I and I do not exceed 62.5µA voltage, V , existing between V and V can also be SET REFMAX REFMIN DIFF OUTA OUTB and 625µA, respectively. The associated equations in Figure 44 converted to a single-ended voltage via a transformer or differ- can be used to determine the value of R . ential amplifier configuration. The ac performance of the SET AD9762 is optimum and specified using a differential trans- AVDD former coupled output in which the voltage swing at I and OPTIONAL OUTA BANDLIMITING I is limited to ±0.5V. If a single-ended unipolar output is CAPACITOR OUTB desirable, I should be selected. OUTA REFLO COMP1AVDD The distortion and noise performance of the AD9762 can be +1.2V REF enhanced when the AD9762 is configured for differential opera- 50pF REFIO CURRENT tion. The common-mode error sources of both IOUTA and IOUTB 1(cid:1)F FS ADJ SOURCE can be significantly reduced by the common-mode rejection of a ARRAY RSET IREF AD9762 transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. IREF = (1.2–VGC)/RSET The enhancement in distortion performance becomes more VGC WITH VGC < VREFIO AND 62.5(cid:1)A (cid:1) IREF (cid:1) 625A significant as the frequency content of the reconstructed wave- form increases. This is due to the first order cancellation of Figure 44.Dual-Supply Gain Control Circuit various dynamic common-mode distortion mechanisms, digital In some applications, the user may elect to use an external con- feedthrough and noise. trol amplifier to enhance the multiplying bandwidth, distortion Performing a differential-to-single-ended conversion via a performance, and/or settling time. External amplifiers capable transformer also provides the ability to deliver twice the recon- of driving a 50 pF load such as the AD817 are suitable for this structed signal power to the load (i.e., assuming no source purpose. It is configured in such a way that it is in parallel with the weaker internal reference amplifier as shown in Figure 45. termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differen- In this case, the external amplifier simply overdrives the weaker reference control amplifier. Also, since the internal control tially. A properly selected transformer will allow the AD9762 to amplifier has a limited current output, it will sustain no damage provide the required power and voltage levels to different loads. if overdriven. Refer to Applying the AD9762 section for examples of various output configurations. EXTERNAL The output impedance of I and I is determined by the CONTROL AMPLIFIER OUTA OUTB AVDD equivalent parallel combination of the PMOS switches associ- VREF ated with the current sources and is typically 100kΩ in parallel INPUT with 5 pF. It is also slightly dependent on the output voltage REFLO COMP1 AVDD (i.e., V and V ) due to the nature of a PMOS device. +1.2V REF OUTA OUTB 50pF As a result, maintaining I and/or I at a virtual ground REFIO OUTA OUTB CURRENT via an I-V op amp configuration will result in the optimum dc FS ADJ SOURCE ARRAY linearity. Note, the INL/DNL specifications for the AD9762 RSET AD9762 are measured with I maintained at a virtual ground via an OUTA op amp. Figure 45.Configuring an External Reference Control Amplifier REV. B –13–

AD9762 I and I also have a negative and positive voltage Since the AD9762 is capable of being updated up to 125 MSPS, OUTA OUTB compliance range that must be adhered to in order to achieve the quality of the clock and data input signals are important optimum performance. The negative output compliance range in achieving the optimum performance. The drivers of the of –1.0V is set by the breakdown limits of the CMOS process. digital data interface circuitry should be specified to meet the Operation beyond this maximum limit may result in a break- minimum set-up and hold times of the AD9762 as well as its down of the output stage and affect the reliability of the AD9762. required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above The positive output compliance range is slightly dependent conditions will result in the lowest data feedthrough and noise. on the full-scale output current, I . It degrades slightly OUTFS from its nominal 1.25 V for an I = 20 mA to 1.00 V for an Digital signal paths should be kept short and run lengths OUTFS I = 2 mA. The optimum distortion performance for a matched to avoid propagation delay mismatch. The insertion of OUTFS single-ended or differential output is achieved when the maximum a low value resistor network (i.e., 20Ω to 100Ω) between the full-scale signal at I and I does not exceed 0.5 V. AD9762 digital inputs and driver outputs may be helpful in OUTA OUTB Applications requiring the AD9762’s output (i.e., V and/ reducing any overshooting and ringing at the digital inputs that OUTA or V ) to extend its output compliance range should size contribute to data feedthrough. For longer run lengths and high OUTB R accordingly. Operation beyond this compliance range data update rates, strip line techniques with proper termination LOAD will adversely affect the AD9762’s linearity performance and resistors should be considered to maintain “clean” digital subsequently degrade its distortion performance. inputs. Also, operating the AD9762 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce DIGITAL INPUTS data feedthrough. The AD9762’s digital input consists of 12 data input pins and a The external clock driver circuitry should provide the AD9762 clock input pin. The 12-bit parallel data inputs follow standard with a low jitter clock input meeting the min/max logic levels positive binary coding where DB11 is the most significant bit while providing fast edges. Fast clock edges will help minimize (MSB) and DB0 is the least significant bit (LSB). I produces OUTA any jitter that will manifest itself as phase noise on a recon- a full-scale output current when all data bits are at Logic 1. structed waveform. Thus, the clock input should be driven by I produces a complementary output with the full-scale current OUTB the fastest logic family suitable for the application. split between the two outputs as a function of the input code. Note, the clock input could also be driven via a sine wave, The digital interface is implemented using an edge-triggered which is centered around the digital threshold (i.e., DVDD/2), master slave latch. The DAC output is updated following the and meets the min/max logic threshold. This will typically result rising edge of the clock as shown in Figure 1 and is designed in a slight degradation in the phase noise, which becomes more to support a clock rate as high as 125 MSPS. The clock can noticeable at higher sampling rates and output frequencies. be operated at any duty cycle that meets the specified latch Also, at higher sampling rates, the 20% tolerance of the digital pulsewidth. The set-up and hold times can also be varied within logic threshold should be considered since it will affect the the clock cycle as long as the specified minimum times are met; effective clock duty cycle and subsequently cut into the required although the location of these transition edges may affect digital data set-up and hold times. feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge SLEEP MODE OPERATION of a 50% duty cycle clock. The AD9762 has a power-down function which turns off the The digital inputs are CMOS compatible with logic thresholds, output current and reduces the supply current to less than V set to approximately half the digital positive supply 8.5mA over the specified supply range of 2.7V to 5.5 V and THRESHOLD (DVDD) or temperature range. This mode can be activated by applying V = DVDD/2 (±20%) a logic level “1” to the SLEEP pin. This digital input also THRESHOLD contains an active pull-down circuit that ensures the AD9762 The internal digital circuitry of the AD9762 is capable of operating remains enabled if this input is left disconnected. The SLEEP over a digital supply range of 2.7V to 5.5 V. As a result, the input with active pull-down requires <40µA of drive current. digital inputs can also accommodate TTL levels when DVDD is The power-up and power-down characteristics of the AD9762 set to accommodate the maximum high level voltage of the TTL are dependent upon the value of the compensation capacitor drivers V . A DVDD of 3V to 3.3V will typically ensure OH(MAX) connected to COMP1. With a nominal value of 0.1µF, the proper compatibility with most TTL logic families. Figure 46 AD9762 takes less than 5µs to power down and approximately shows the equivalent digital input circuit for the data and clock 3.25ms to power back up. Note, the SLEEP MODE should not inputs. The sleep mode input is similar with the exception that be used when the external control amplifier is used as shown in it contains an active pull-down circuit, thus ensuring that the Figure 45. AD9762 remains enabled if this input is left disconnected. DVDD POWER DISSIPATION The power dissipation, P , of the AD9762 is dependent on D several factors which include: (1) AVDD and DVDD, the power DIGITAL supply voltages; (2) I , the full-scale current output; (3) INPUT OUTFS f , the update rate; (4) and the reconstructed digital input CLOCK waveform. The power dissipation is directly proportional to the analog supply current, I , and the digital supply current, I . AVDD DVDD Figure 46.Equivalent Digital Input IAVDD is directly proportional to IOUTFS as shown in Figure 47 and is insensitive to f . CLOCK –14– REV. B

AD9762 30 APPLYING THE AD9762 OUTPUT CONFIGURATIONS 25 The following sections illustrate some typical output configura- tions for the AD9762. Unless otherwise noted, it is assumed that I is set to a nominal 20 mA. For applications requir- 20 OUTFS A ing the optimum dynamic performance, a differential output m – configuration is suggested. A differential output configuration D15 D may consist of either an RF transformer or a differential op amp V A I configuration. The transformer configuration provides the 10 optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op 5 amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. 0 2 4 6 8 10 12 14 16 18 20 A single-ended output is suitable for applications requiring a IOUTFS – mA unipolar voltage output. A positive unipolar output voltage will Figure 47.IAVDD vs. IOUTFS result if IOUTA and/or IOUTB is connected to an appropriately Conversely, I is dependent on both the digital input wave- sized load resistor, R , referred to ACOM. This configura- DVDD LOAD form, f , and digital supply DVDD. Figures 48 and 49 tion may be more suitable for a single-supply system requiring CLOCK show I as a function of full-scale sine wave output ratios a dc coupled, ground referred output voltage. Alternatively, an DVDD (f /f ) for various update rates with DVDD = 5 V and amplifier could be configured as an I-V converter thus converting OUT CLOCK DVDD = 3 V, respectively. Note, how I is reduced by more I or I into a negative unipolar voltage. This configura- DVDD OUTA OUTB than a factor of 2 when DVDD is reduced from 5 V to 3V. tion provides the best dc linearity since I or I is OUTA OUTB maintained at a virtual ground. Note, I provides slightly OUTA 18 better performance than I . OUTB 125MSPS 16 DIFFERENTIAL COUPLING USING A TRANSFORMER 14 An RF transformer can be used to perform a differential-to- 100MSPS single-ended signal conversion as shown in Figure 50. A 12 A differentially coupled transformer output provides the optimum – m 10 distortion performance for output signals whose spectral content D VD 8 lies within the transformer’s passband. An RF transformer such ID 50MSPS as the Mini-Circuits T1-1T provides excellent rejection of 6 common-mode distortion (i.e., even-order harmonics) and noise 4 25MSPS over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Trans- 2 5MSPS formers with different impedance ratios may also be used for 0 0.01 0.1 1 impedance matching purposes. Note that the transformer RATIO (fOUT/fCLK) provides ac coupling only. Figure 48.I vs. Ratio @ DVDD = 5 V DVDD MINI-CIRCUITS T1-1T IOUTA 22 8 125MSPS AD9762 RLOAD IOUTB 21 6 100MSPS OPTIONAL RDIFF Figure 50.Differential Output Using a Transformer A m – D4 The center tap on the primary side of the transformer must be VD connected to ACOM to provide the necessary dc current path D I 50MSPS for both I and I . The complementary voltages appear- OUTA OUTB ing at I and I (i.e., V and V ) swing symmetri- 2 OUTA OUTB OUTA OUTB 25MSPS cally around ACOM and should be maintained with the specified output compliance range of the AD9762. A differential resistor, 5MSPS R , may be inserted in applications in which the output of 0 DIFF 0.01 0.1 1 the transformer is connected to the load, RLOAD, via a passive RATIO (fOUT/fCLK) reconstruction filter or cable. R is determined by the DIFF Figure 49.I vs. Ratio @ DVDD = 3 V transformer’s impedance ratio and provides the proper source DVDD termination which results in a low VSWR. Note that approxi- mately half the signal power will be dissipated across R . DIFF REV. B –15–

AD9762 DIFFERENTIAL USING AN OP AMP this mode is the integral nonlinearity (INL) as discussed in the An op amp can also be used to perform a differential to single- Analog Output section of this data sheet. For optimum INL ended conversion as shown in Figure 51. The AD9762 is performance, the single-ended, buffered voltage output configu- configured with two equal load resistors, R , of 25 Ω. ration is suggested. LOAD The differential voltage developed across I and I is OUTA OUTB converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across AD9762 IOUTFS = 20mA VOUTA = 0 TO +0.5V I and I forming a real pole in a low-pass filter. The IOUTA 22 OUTA OUTB addition of this capacitor also enhances the op amps distortion 50(cid:2) 50(cid:2) performance by preventing the DACs high slewing output from IOUTB 21 overloading the op amp’s input. 25(cid:2) 500(cid:2) Figure 53.0V to +0.5 V Unbuffered Voltage Output AD9762 225(cid:2) IOUTA 22 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT AD8047 CONFIGURATION 225(cid:2) IOUTB 21 Figure 54 shows a buffered single-ended output configuration COPT in which the op amp U1 performs an I-V conversion on the 500(cid:2) AD9762 output current. U1 maintains I (or I ) at a 25(cid:2) 25(cid:2) OUTA OUTB virtual ground, thus minimizing the nonlinear output imped- ance effect on the DAC’s INL performance as discussed in Figure 51.DC Differential Coupling Using an Op Amp the Analog Output section. Although this single-ended configu- The common-mode rejection of this configuration is typically ration typically provides the best dc linearity performance, its ac determined by the resistor matching. In this circuit, the differ- distortion performance at higher DAC update rates may be ential op amp circuit using the AD8047 is configured to provide limited by U1’s slewing capabilities. U1 provides a negative some additional signal gain. The op amp must operate off of a unipolar output voltage and its full-scale output voltage is sim- dual supply since its output is approximately ±1.0V. A high ply the product of RFB and IOUTFS. The full-scale output should speed amplifier capable of preserving the differential perfor- be set within U1’s voltage output swing capabilities by scaling mance of the AD9762 while meeting other system level objec- IOUTFS and/or RFB. An improvement in ac distortion perfor- tives (i.e., cost, power) should be selected. The op amps mance may result with a reduced IOUTFS since the signal current differential gain, its gain setting resistor values, and full-scale U1 will be required to sink will be subsequently reduced. output swing capabilities should all be considered when opti- mizing this circuit. COPT The differential circuit shown in Figure 52 provides the neces- RFB sary level-shifting required in a single supply system. In this 200(cid:2) case, AVDD which is the positive analog supply for both the AD9762 IOUTFS = 10mA AD9762 and the op amp is also used to level-shift the differ- IOUTA 22 ential output of the AD9762 to midsupply (i.e., AVDD/2). The U1 VOUT = IOUTFS (cid:4) RFB AD8041 is a suitable op amp for this application. IOUTB 21 200(cid:2) 500(cid:2) AD9762 225(cid:2) Figure 54.Unipolar Buffered Voltage Output IOUTA 22 225(cid:2) AD8041 POWER AND GROUNDING CONSIDERATIONS IOUTB 21 In systems seeking to simultaneously achieve high speed and COPT 1k(cid:2) AVDD high performance, the implementation and construction of the 25(cid:2) 25(cid:2) 1k(cid:2) printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection; placement and routing; and supply bypassing and grounding. Figure 52.Single-Supply DC Differential Coupled Circuit Figures 60–65 illustrate the recommended printed circuit board ground, power and signal plane layouts which are implemented SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT on the AD9762 evaluation board. Figure 53 shows the AD9762 configured to provide a unipolar output range of approximately 0V to +0.5 V for a doubly termi- Proper grounding and decoupling should be a primary objective nated 50Ω cable since the nominal full-scale current, I , of in any high speed, high resolution system. The AD9762 features OUTFS 20 mA flows through the equivalent R of 25Ω. In this separate analog and digital supply and ground pins to optimize LOAD case, R represents the equivalent load resistance seen by the management of analog and digital ground currents in a LOAD I or I . The unused output (I or I ) can be system. In general, AVDD, the analog supply, should be decoupled OUTA OUTB OUTA OUTB connected to ACOM directly or via a matching R . Different to ACOM, the analog common, as close to the chip as physi- LOAD values of I and R can be selected as long as the positive cally possible. Similarly, DVDD, the digital supply, should be OUTFS LOAD compliance range is adhered to. One additional consideration in decoupled to DCOM as close as physically as possible. –16– REV. B

AD9762 For those applications that require a single +5V or +3 V supply APPLICATIONS for both the analog and digital supply, a clean analog supply Using the AD9762 for QAM Modulation may be generated using the circuit shown in Figure 55. The QAM is one of the most widely used digital modulation schemes circuit consists of a differential LC filter with separate power in digital communication systems. This modulation technique supply and return lines. Lower noise can be attained using low can be found in both FDM as well as spreadspectrum (i.e., ESR type electrolytic and tantalum capacitors. CDMA) based systems. A QAM signal is a carrier frequency which is both modulated in amplitude (i.e., AM modulation) FERRITE and in phase (i.e., PM modulation). It can be generated by BEADS independently modulating two carriers of identical frequency TTLLO/CGMICOS 100(cid:1)F 10-22(cid:1)F 0.1(cid:1)F AVDD but with a 90° phase difference. This results in an in-phase (I) CIRCUITS ELECT. TANT. CER. carrier component and a quadrature (Q) carrier component at a ACOM 90° phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. +5V OR +3V A common and traditional implementation of a QAM modu- POWER SUPPLY lator is shown in Figure 56. The modulation is performed in the Figure 55.Differential LC Filter for Single +5V or +3 V analog domain in which two DACs are used to generate the Applications baseband I and Q components, respectively. Each component is Maintaining low noise on power supplies and ground is critical then typically applied to a Nyquist filter before being applied to to obtaining optimum results from the AD9762. If properly a quadrature mixer. The matching Nyquist filters shape and implemented, ground planes can perform a host of functions on limit each component’s spectral envelope while minimizing high speed circuit boards: bypassing, shielding, current trans- intersymbol interference. The DAC is typically updated at the port, etc. In mixed signal design, the analog and digital portions QAM symbol rate or possibly a multiple of it if an interpolating of the board should be distinct from each other, with the analog filter precedes the DAC. The use of an interpolating filter typi- ground plane confined to the areas covering the analog signal cally eases the implementation and complexity of the analog traces, and the digital ground plane confined to areas covering filter, which can be a significant contributor to mismatches in the digital interconnects. gain and phase between the two baseband channels. A quadra- ture mixer modulates the I and Q components with in-phase All analog ground pins of the DAC, reference and other analog and quadrature phase carrier frequency and then sums the two components should be tied directly to the analog ground plane. outputs to provide the QAM signal. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to 12 maintain optimum performance. Care should be taken to ensure AD9762 that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running DOSRP CARRIER 0 Σ TO to the DAC as well as any clock signals. On the analog side, this ASIC FREQUENCY 90 MIXER 12 includes the DAC output signal, reference signal and the supply AD9762 feeders. NYQUIST QUADRATURE The use of wide runs or planes in the routing of power lines is FILTERS MODULATOR also recommended. This serves the dual role of providing a low Figure 56.Typical Analog QAM Architecture series impedance power supply to the part, as well as providing In this implementation, it is much more difficult to maintain some “free” capacitive decoupling to the appropriate ground proper gain and phase matching between the I and Q channels. plane. It is essential that care be taken in the layout of signal The circuit implementation shown in Figure 57 helps improve and power ground interconnects to avoid inducing extraneous upon the matching and temperature stability characteristics voltage drops in the signal ground paths. It is recommended that between the I and Q channels. Using a single voltage reference all connections be short, direct and as physically close to the derived from U1 to set the gain for both the I and Q channels package as possible in order to minimize the sharing of conduc- will improve the gain matching and stability. Further enhance- tion paths between different currents. When runs exceed an inch ments in gain matching and stability are achieved by using in length, strip line techniques with proper termination resistor separate matching resistor networks for both R and R . SET LOAD should be considered. The necessity and value of this resistor Additional trim capability via R and R can be added to CAL1 CAL2 will be dependent upon the logic family used. compensate for any initial mismatch in gain between the two For a more detailed discussion of the implementation and channels. This may be attributed to any mismatch between U1 construction of high speed, mixed signal printed circuit boards, and U2’s gain setting resistor, (R ); effective load resistance, SET refer to Analog Devices’ application notes AN-280 and AN-333. (R ); and/or voltage offset of each DAC’s control amplifier. LOAD The differential voltage outputs of U1 and U2 are fed into their respective differential inputs of a quadrature mixer via matching 50Ω filter networks. REV. B –17–

AD9762 AD9762 EVALUATION BOARD General Description REFLO The AD9762-EB is an evaluation board for the AD9762 12-bit REFIO IOUTA TO U1 NYQUIST D/A converter. Careful attention to layout and circuit design I-CHANNEL FILTER FS ADJ IOUTB AND MIXER combined with a prototyping area allow the user to easily and 2RkS(cid:2)ET* CLOCK 5R0L(cid:2)OA**D 5R0L(cid:2)OA**D effectively evaluate the AD9762 in any application where high RCAL1 CLOCK resolution, high speed conversion is required. 50(cid:2) AVDD This board allows the user the flexibility to operate the AD9762 in various configurations. Possible output configurations include REFLO CLOCK REFIO U2 IOUTA TNOYQUIST transformer coupled, resistor terminated, inverting/noninverting 0.1(cid:1)F Q-CHANNEL FILTER and differential amplifier outputs. The digital inputs are designed FS ADJ IOUTB AND MIXER RSET 50(cid:2)** 50(cid:2)** to be driven directly from various word generators, with the 2k(cid:2)* RLOAD RLOAD on-board option to add a resistor network for proper load RCAL2 * OHMTEK ORNA1001F 100(cid:2) ** OHMTEK TOMC1603-50F termination. Provisions are also made to operate the AD9762 with either the internal or external reference, or to exercise Figure 57.Baseband QAM Implementation Using Two the power-down feature. AD9762s Refer to the application note AN-420 “Using the AD9760/ It is also possible to generate a QAM signal completely in the AD9762/AD9764-EB Evaluation Board” for a thorough digital domain via a DSP or ASIC, in which case only a single description and operating instructions for the AD9762 DAC of sufficient resolution and performance is required to evaluation board. reconstruct the QAM signal. Also available from several vendors are Digital ASICs which implement other digital modulation schemes such as PSK and FSK. This digital implementation has the benefit of generating perfectly matched I and Q components in terms of gain and phase, which is essential in maintaining optimum performance in a communication system. In this implementation, the reconstruction DAC must be operating at a sufficiently high clock rate to accommodate the highest specified QAM carrier frequency. Figure 58 shows a block diagram of such an implementation using the AD9762. 12 12 I DATA 12 STEQLA-1M130 LPF TMOIXER Q DATA AD9762 50(cid:2) 50(cid:2) 12 12 SIN COS CARRIER 12 STEL-1177 FREQUENCY NCO CLOCK Figure 58.Digital QAM Architecture –18– REV. B

AD9762 P13 T B A 3 2 1 JP3 VEE TP8C9(cid:1)0.1F A OUT 1OUT 2 TP9 C10(cid:1)0.1F AVDD AVCC C17(cid:1)0.1F U6A376AD804724AJP5 123A C15(cid:1)0.1FR46(cid:2)A1k AVDDC8(cid:1)0.1F TP10 R16(cid:2)2kC11TP14(cid:1)0.1F JP4 AA R42(cid:2)1k6 R43(cid:2)5kCW A C14R45(cid:1)1F(cid:2)1k C7(cid:1)1F AVDD TP11 AVDD 1 2 3JP2NA U7 REF432VINVOUT GND 4A XTREFINJ5 R44(cid:2)50AA B 3 A PDIJ2 C C16(cid:1)1F E CLKTP1JP1A 21R15(cid:2)49.9 U1 AD976x28B13CLOCK27B12DVDD26B11DCOM25B10NC24B9AVDD23B8COMP222B7IOUTA21B6IOUTB20B5ACOM19COMP1B418B3FS ADJ17B2REFIO16B1REFLO15B0SLEEP CT1 A TP12 R17(cid:2)49.9 AVC C18(cid:1)0.1F A DDDDDDDDDDDDDD J1 101234567891011121314 1 DVDD J6 A EXTCLK 9876 432 C22(cid:1)1F R37(cid:2)49.9 C24(cid:1)1F C B6 TP7 C6A(cid:1)10F DVDD R7 1 10543298 21098765 1 R8 AVCC C21(cid:1)0.1FU437A6AD804724 R36(cid:2)1k C23(cid:1)0.1F AAVEE C 7 3 AV 654 654 R18(cid:2)1k JP8 B A R35(cid:2)1k B5 TP6 C5A(cid:1)10F R3 1 32 10987 R4 A P7A B R10(cid:2)1kA A B A AVEE B4 TP19TP18 TP5 16 PINDIPRES PK 11621514341312511671098 16 PINDIPRES PK 161152143134125116107 JP7BJ B A R9(cid:2)1k JP9 AGNDAVDD B3B2 TP4TP2 C4A(cid:1)10F DVDD R5 1 101098765432C19C1C2C25C26C27C28C29 C30C31C32C33C34C35C36 1098765432 11 R6DVDD JP6A J7R12OPENT1C2030A JP6B1 R13OPENA A GND 98 2 4 5 A 6 D 7 3 DVDD B1 TP3 C3(cid:1)10F R1 1P16543213579111315171921232527293133353739 98765410 R2 J3OUT1 C12R20(cid:2)22pF49.9 AAR140 J4OUT2 C13R38(cid:2)22pF49.9 AA 246810121416182022242628303234363840 Figure 59.AD9762 Evaluation Board Schematic REV. B –19–

AD9762 Figure 60.Silkscreen Layer—Top Figure 61.Component Side PCB Layout (Layer 1) –20– REV. B

AD9762 Figure 62.Ground Plane PCB Layout (Layer 2) Figure 63.Power Plane PCB Layout (Layer 3) REV. B –21–

AD9762 Figure 64.Solder Side PCB Layout (Layer 4) Figure 65.Silkscreen Layer—Bottom –22– REV. B

AD9762 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) B) 0.6969 (17.70) v. e 28 15 00 (r 0.2992 (7.60) 3/ 0.2914 (7.40) 1– – 0.4193 (10.65) b 1 14 0.3937 (10.00) 01 2 2 C PIN 1 0.1043 (2.65) 0.0291 (0.74) 0.0926 (2.35) 0.0098 (0.25)(cid:4) 45(cid:3) 8(cid:3) 00..00101480 ((00..3100)) 0(B.10.S52C070) 00..00119328 ((00..4395)) SPELAANTIENG 00..00102951 ((00..3223)) 0(cid:3) 00..00510507 ((10..2470)) 28-Lead, TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.0433 (1.10) 0.002 (0.05) MAX 8(cid:3) SEPALTAINNGE 0.02B56S C(0.65) 00..00101785 ((00..3109)) 00.0.0003759 ( (00.0.2900))0(cid:3) 00..002280 ((00..7500)) A. S. U. N D I E T N RI P REV. B –23–

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9762-EBZ AD9762ARUZ AD9762AR AD9762ARU AD9762ARZ AD9762ARRL AD9762ARURL7 AD9762ARUZRL7 AD9762ARZRL