a 10-Bit, 125 MSPS TxDAC® D/A Converter AD9760 FEATURES FUNCTIONAL BLOCK DIAGRAM Member of Pin-Compatible TxDAC Product Family +5V 125 MSPS Update Rate 0.1(cid:1)F 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance REFLO COMP1 AVDD ACOM SFDR to Nyquist @ 40 MHz Output: 52 dBc +1.20V REF AD9760 Differential Current Outputs: 2 mA to 20 mA 0.1(cid:1)F 50pF REFIO 0.1(cid:1)F Power Dissipation: 175 mW @ 5V to 45mW @ 3V CURRENT COMP2 FS ADJ SOURCE Power-Down Mode: 25 mW @ 5V ARRAY On-Chip 1.20 V Reference RSET +5V DVDD Single +5 V or +3 V Supply Operation SEGMENTED LSB IOUTA Packages: 28-Lead SOIC and TSSOP DCOM SWITCHES SWITCHES IOUTB Edge-Triggered Latches CLOCK CLOCK LATCHES SLEEP APPLICATIONS Communication Transmit Channel: DIGITAL DATA INPUTS (DB9–DB0) Basestations The AD9760 is a current-output DAC with a nominal full-scale Set Top Boxes output current of 20 mA and > 100 kΩ output impedance. Digital Radio Link Differential current outputs are provided to support single- Direct Digital Synthesis (DDS) ended or differential applications. Matching between the two Instrumentation current outputs ensures enhanced dynamic performance in a PRODUCT DESCRIPTION differential output configuration. The current outputs may be The AD9760 and AD9760-50 are the 10-bit resolution members tied directly to an output resistor to provide two complemen- of the TxDAC series of high performance, low power CMOS tary, single-ended voltage outputs or fed directly into a trans- digital-to-analog converters (DACs). The AD9760-50 is a lower former. The output voltage compliance range is 1.25V. performance option that is guaranteed and specified for 50 MSPS operation. The TxDAC family that consists of pin compatible 8-, The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD9760 can be driven 10-, 12- and 14-bit DACs is specifically optimized for the trans- by the on-chip reference or by a variety of external reference mit signal path of communication systems. All of the devices voltages. The internal control amplifier that provides a wide share the same interface options, small outline package and (>10:1) adjustment span allows the AD9760 full-scale current pinout, thus providing an upward or downward component to be adjusted over a 2mA to 20 mA range while maintaining selection path based on performance, resolution and cost. Both excellent dynamic performance. Thus, the AD9760 may oper- the AD9760 and AD9760-50 offer exceptional ac and dc ate at reduced power levels or be adjusted over a 20dB range to performance while supporting update rates up to 125 MSPS provide additional gain ranging capabilities. and 60 MSPS respectively. The AD9760 is available in a 28-lead SOIC and TSSOP packages. The AD9760’s flexible single-supply operating range of 2.7 V to It is specified for operation over the industrial temperature range. 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further PRODUCT HIGHLIGHTS reduced to a mere 45 mW without a significant degradation in 1.The AD9760 is a member of the TxDAC product family that performance by lowering the full-scale current output. Also, a provides an upward or downward component selection path power-down mode reduces the standby power dissipation to based on resolution (8 to 14 bits), performance and cost. approximately 25 mW. 2.Manufactured on a CMOS process, the AD9760 uses a pro- The AD9760 is manufactured on an advanced CMOS process. A prietary switching technique that enhances dynamic perfor- segmented current source architecture is combined with a propri- mance beyond what was previously attainable by higher etary switching technique to reduce spurious components and power/cost bipolar or BiCMOS devices. enhance dynamic performance. Edge-triggered input latches and a 3.On-chip, edge-triggered input CMOS latches interface readily 1.2 V temperature compensated bandgap reference have been inte- to +3 V and +5 V CMOS logic families. The AD9760 can grated to provide a complete monolithic DAC solution. Flexible support update rates up to 125 MSPS. supply options support +3 V and +5 V CMOS logic families. 4.A flexible single-supply operating range of 2.7V to 5.5 V and TxDAC is a registered trademark of Analog Devices, Inc. a wide full-scale current adjustment span of 2mA to 20 mA allow the AD9760 to operate at reduced power levels. REV.B 5.The current output(s) of the AD9760 can be easily config- Information furnished by Analog Devices is believed to be accurate and ured for various single-ended or differential circuit topologies. reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD9760/AD9760-50–SPECIFICATIONS DC SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units RESOLUTION 10 Bits DC ACCURACY1 Integral Linearity Error (INL) –1.0 ±0.5 +1.0 LSB Differential Nonlinearity (DNL) –0.5 ±0.25 +0.5 LSB MONOTONICITY Guaranteed Over Specified Temperature Range ANALOG OUTPUT Offset Error –0.025 +0.025 % of FSR Gain Error (Without Internal Reference) –10 ±2 +10 % of FSR Gain Error (With Internal Reference) –10 ±1 +10 % of FSR Full-Scale Output Current2 2.0 20.0 mA Output Compliance Range –1.0 1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.08 1.20 1.32 V Reference Output Current3 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MΩ Small Signal Bandwidth (w/o C )4 1.4 MHz COMP1 TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD5 2.7 5.0 5.5 V DVDD 2.7 5.0 5.5 V Analog Supply Current (I ) 25 30 mA AVDD Digital Supply Current (I )6 3 5 mA DVDD Supply Current Sleep Mode (I ) 8.5 mA AVDD Power Dissipation6 (5 V, I = 20 mA) 140 175 mW OUTFS Power Dissipation7 (5 V, I = 20 mA) 190 mW OUTFS Power Dissipation7 (3 V, I = 2 mA) 45 mW OUTFS Power Supply Rejection Ratio—AVDD –0.04 +0.04 % of FSR/V Power Supply Rejection Ratio—DVDD –0.025 +0.025 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1Measured at I , driving a virtual ground. OUTA 2Nominal full-scale current, I , is 32 × the I current. OUTFS REF 3Use an external buffer amplifier to drive any external load. 4Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41. 5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6Measured at f = 50 MSPS and f = 1.0 MHz. CLOCK OUT 7Measured as unbuffered voltage output into 50Ω R at I and I , f = 100 MSPS and f = 40 MHz. LOAD OUTA OUTB CLOCK OUT Specifications subject to change without notice. –2– REV. B

AD9760 (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA, Differential Transformer Coupled Output, DYNAMIC SPECIFICATIONS MIN MAX OUTFS 50(cid:2) Doubly Terminated, unless otherwise noted) Model AD9760 AD9760-50 Parameter Min Typ Max Min Typ Max Units DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 125 50 60 MSPS CLOCK Output Settling Time (t ) (to 0.1%)1 35 35 ns ST Output Propagation Delay (t ) 1 1 ns PD Glitch Impulse 5 5 pV-s Output Rise Time (10% to 90%)1 2.5 2.5 ns Output Fall Time (10% to 90%)1 2.5 2.5 ns Output Noise (I = 20 mA) 50 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 50 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C 70 73 68 73 dBc A T to T 68 66 dBc MIN MAX f = 50 MSPS; f = 2.51 MHz 73 73 dBc CLOCK OUT f = 50 MSPS; f = 5.02 MHz 68 68 dBc CLOCK OUT f = 50 MSPS; f = 20.2 MHz 55 55 dBc CLOCK OUT f = 100 MSPS; f = 2.51 MHz 74 N/A dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz 68 N/A dBc CLOCK OUT f = 100 MSPS; f = 20.2 MHz 60 N/A dBc CLOCK OUT f = 100 MSPS; f = 40.4 MHz 52 N/A dBc CLOCK OUT Spurious-Free Dynamic Range within a Window f = 50 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C 74 78 72 78 dBc A T to T 72 70 dBc MIN MAX f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 76 76 dBc CLOCK OUT f = 100 MSPS; f = 5.04 MHz; 4 MHz Span 76 N/A dBc CLOCK OUT Total Harmonic Distortion f = 50 MSPS; f = 1.00 MHz CLOCK OUT T = +25°C –76 –73 –76 –70 dBc A T to T –71 –68 dBc MIN MAX f = 50 MHz; f = 2.00 MHz –71 –71 dBc CLOCK OUT f = 100 MHz; f = 2.00 MHz –71 N/A dBc CLOCK OUT NOTES 1Measured single ended into 50Ω load. Specifications subject to change without notice. REV. B –3–

AD9760 DIGITAL SPECIFICATIONS (T to T , AVDD = +5 V, DVDD = +5 V, I = 20 mA unless otherwise noted) MIN MAX OUTFS Parameter Min Typ Max Units DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V 3.5 5 V Logic “1” Voltage @ DVDD = +3 V 2.1 3 V Logic “0” Voltage @ DVDD = +5 V 0 1.3 V Logic “0” Voltage @ DVDD = +3 V 0 0.9 V Logic “1” Current –10 +10 µA Logic “0” Current –10 +10 µA Input Capacitance 5 pF Input Setup Time (t ) 2.0 ns S Input Hold Time (t ) 1.5 ns H Latch Pulsewidth (t ) 3.5 ns LPW Specification subject to change without notice. DB0–DB9 tS tH CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% Figure 1. Timing Diagram ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS* With Temperature Package Package Parameter Respect to Min Max Units Model Range Descriptions Options AVDD ACOM –0.3 +6.5 V AD9760AR –40°C to +85°C 28-Lead 300 mil R-28 DVDD DCOM –0.3 +6.5 V SOIC ACOM DCOM –0.3 +0.3 V AD9760ARU –40°C to +85°C 28-Lead 170 mil RU-28 AVDD DVDD –6.5 +6.5 V TSSOP CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V AD9760AR50 –40°C to +85°C 28-Lead 300 mil R-28 Digital Inputs DCOM –0.3 DVDD + 0.3 V SOIC I , I ACOM –1.0 AVDD + 0.3 V AD9760ARU50 –40°C to +85°C 28-Lead 170 mil RU-28 OUTA OUTB COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V TSSOP REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V AD9760-EB Evaluation Board REFLO ACOM –0.3 +0.3 V Junction Temperature +150 °C THERMAL CHARACTERISTICS Storage Temperature –65 +150 °C Thermal Resistance Lead Temperature 28-Lead 300 mil (7.5 mm) SOIC (10 sec) +300 °C θ = 71.4°C/W JA *Stresses above those listed under Absolute Maximum Ratings may cause perma- θ = 23°C/W JC nent damage to the device. This is a stress rating only; functional operation of the 28-Lead 170 mil (4.4 mm) TSSOP device at these or any other conditions above those indicated in the operational θ = 97.9°C/W sections of this specification is not implied. Exposure to absolute maximum JA θ = 14.0°C/W ratings for extended periods may effect device reliability. JC CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD9760 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE –4– REV. B

AD9760 PIN CONFIGURATION (MSB) DB9 1 28CLOCK DB8 2 27DVDD DB7 3 26 DCOM DB6 4 25 NC DB5 5 AD9760 24 AVDD DB4 6 TOP VIEW 23 COMP2 DB3 7 (Not to Scale) 22 IOUTA DB2 8 21 IOUTB DB1 9 20ACOM DB0 10 19 COMP1 NC 11 18 FS ADJ NC 12 17 REFIO NC 13 16 REFLO NC 14 15 SLEEP NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 DB9 Most Significant Data Bit (MSB). 2–9 DB8–DB1 Data Bits 1–8. 10 DB0 Least Significant Data Bit (LSB). 11–14,25 NC No Internal Connection. 15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. 16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1µF capacitor to ACOM when internal reference activated. 18 FS ADJ Full-Scale Current Output Adjust. 19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance. 20 ACOM Analog Common. 21 I Complementary DAC Current Output. Full-scale current when all data bits are 0s. OUTB 22 I DAC Current Output. Full-scale current when all data bits are 1s. OUTA 23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. 24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V). 26 DCOM Digital Common. 27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V). 28 CLOCK Clock Input. Data latched on positive edge of clock. REV. B –5–

AD9760 DEFINITIONS OF SPECIFICATIONS Temperature Drift Linearity Error (Also Called Integral Nonlinearity or INL) Temperature drift is specified as the maximum change from the Linearity error is defined as the maximum deviation of the ambient (+25°C) value to the value at either T or T . For MIN MAX actual analog output from the ideal output, determined by a offset and gain drift, the drift is reported in ppm of full-scale straight line drawn from zero to full scale. range (FSR) per degree C. For reference drift, the drift is Differential Nonlinearity (or DNL) reported in ppm per degree C. DNL is the measure of the variation in analog value, normalized Power Supply Rejection to full scale, associated with a 1 LSB change in digital input The maximum change in the full-scale output as the supplies code. are varied from nominal to minimum and maximum specified Monotonicity voltages. A D/A converter is monotonic if the output either increases or Settling Time remains constant as the digital input increases. The time required for the output to reach and remain within a Offset Error specified error band about its final value, measured from the The deviation of the output current from the ideal of zero is start of the output transition. called offset error. For IOUTA, 0 mA output is expected when the Glitch Impulse inputs are all 0s. For IOUTB, 0 mA output is expected when all Asymmetrical switching times in a DAC give rise to undesired inputs are set to 1s. output transients that are quantified by a glitch impulse. It is Gain Error specified as the net area of the glitch in pV-s. The difference between the actual and ideal output span. The Spurious-Free Dynamic Range actual span is determined by the output when all inputs are set The difference, in dB, between the rms amplitude of the output to 1s minus the output when all inputs are set to 0s. signal and the peak spurious signal over the specified bandwidth. Output Compliance Range Total Harmonic Distortion The range of allowable voltage at the output of a current-output THD is the ratio of the rms sum of the first six harmonic DAC. Operation beyond the maximum compliance limits may components to the rms value of the measured output signal. It is cause either output stage saturation or breakdown resulting in expressed as a percentage or in decibels (dB). nonlinear performance. +5V 0.1(cid:1)F REFLO COMP1 AVDD ACOM +1.20V REF AD9760 0.1(cid:1)F 50pF REFIO PMOS 0.1(cid:1)F FS ADJ CURRENT SOURCE COMP2 ARRAY MINI-CIRCUITS RSET T1-1T 2k(cid:2) +5V DVDD TO HP3589A IOUTA SPECTRUM/ DCOM SEGMFOERN TDEBD1 1S–WDIBTC3HES SWILTSCBHES IOUTB 100(cid:2) NETWORK ANALYZER CLOCK 50(cid:2) INPUT LATCHES DDCVDODM 50(cid:2) SLEEP 50(cid:2) 20pF RETIMED 50(cid:2) CLOCK DIGITAL 20pF OUTPUT* CLOCK DATA * AWG2021 CLOCK RETIMED LECROY 9210 OUTPUT TEKTRONIX SUCH THAT DIGITAL DATA PULSE GENERATOR AWG-2021 TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 2.Basic AC Characterization Test Setup –6– REV. B

AD9760 Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = +5 V, I = 20 mA, 50(cid:2) Doubly Terminated Load, Differential Output, T = +25(cid:3)C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 90 85 85 0dBFS 5MSPS 80 80 –6dBFS 80 25MSPS 75 75 –6dBFS DR – dBc70 50MSPS FDR – dBc7605 –12dBFS FDR – dBc7605 0dBFS –12dBFS F S S S 100MSPS 60 60 60 125MSPS 55 55 50 50 50 0.1 1 10 100 0.00 0.50 1.00 1.50 2.00 2.50 0.00 2.00 4.00 6.00 8.00 10.00 12.00 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 3.SFDR vs. f @ 0 dBFS Figure 4.SFDR vs. f @ 5MSPS Figure 5.SFDR vs. f @ 25 MSPS OUT OUT OUT 85 85 85 80 80 80 –6dBFS 75 75 75 SFDR – dBc7605 –12dBFS SFDR – dBc7605 –6dBFS –12dBFS SFDR – dBc7605 –6dBFS 0dBFS 60 60 0dBFS 60 –12dBFS 55 55 55 0dBFS 50 50 50 0.00 5.00 10.00 15.00 20.00 25.00 0.00 10.00 20.00 30.00 40.00 50.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 6.SFDR vs. f @ 50 MSPS Figure 7.SFDR vs. f @100 MSPS Figure 8.SFDR vs. f @ 125 MSPS OUT OUT OUT 85 85 85 455kHz 6.75/7.25MHz @ 5MSPS 1MHz 0.675/0.725MHz @ 50MSPS 4.55MHz @ 5MSPS @ 5MSPS 75 @ 50MSPS 75 2.5MHz 75 3.38/3.63MHz DR – dBc65 @ 22.52M7MSPHSz DR – dBc65 @ 12@52M 52MS5PMHSzSPS DR – dBc65 @ 25MSPS SF 9.1MHz SF SF 13.5/14.5MHz @ 100MSPS @ 100MSPS 55 @ 1112.53M7MSPHSz 55 @ 501M0MSPHSz 55 16.9/18.1MHz 20MHz @ 125MSPS @ 100MSPS 45 45 45 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 AOUT – dBFS AOUT – dBFS AOUT – dBFS Figure 9.Single-Tone SFDR vs. A Figure 10.Single-Tone SFDR vs. Figure 11.Dual-Tone SFDR vs. A OUT OUT @ f = f /11 A @ f = f /5 @ f = f /7 OUT CLOCK OUT OUT CLOCK OUT CLOCK REV. B –7–

AD9760 –70 80 75 IDIFF @ 0dBFS 75 2.5MHz 70 IDIFF @ –6dBFS –75 70 2ND –80 HARMONIC Bc65 10MHz Bc 65 IOUTA @ 0dBFS dBc HARMO 3NRIDC DR – d60 28.6MHz DR – d 60 –85 SF55 SF 55 IOUTA @ –6dBFS 4TH 50 40MHz –90 HARMONIC 50 45 –95 40 45 0 20 40 60 80 100 120 140 2 4 6 8 10 12 14 16 18 20 1 10 100 FREQUENCY – MSPS IOUTFS – mA OUTPUT FREQUENCY – MHz Figure 12. THD vs. f @ Figure 13.SFDR vs. f and I Figure 14.Differential vs. Single- CLOCK OUT OUTFS f = 2MHz @ 100 MSPS, 0dBFS Ended SFDR vs. f @ 100 MSPS OUT OUT 0.5 0.5 80 0.4 0.4 0.3 75 2.5MHz 0.3 0.2 B B 70 S 0.1 S0.2 c L L B OR – 0 OR – 0.1 R – d 65 10MHz RR–0.1 RR FD E E 0 S 60 –0.2 –0.3 –0.1 55 –0.4 40MHz –0.2 –0.5 50 0 125 250 375 500 625 750 875 1000 0 125 250 375 500 625 750 8751000 –40 –20 0 20 40 60 80 CODE CODE TEMPERATURE – (cid:3)C Figure 15.Typical INL Figure 16.Typical DNL Figure 17.SFDR vs. Temperature @ 100 MSPS, 0dBFS 0 0 –10 fCLOCK = 125MSPS fCLOCK = 100MSPS fOUT = 9.95MHz fOUT1 = 13.5MHz fCLOCK = 50MSPS SFDR = 62dBc fOUT2 = 14.5MHz fOUT1 = 6.25MHz AMPLITUDE = 0dBFS SFDR = 61dBc fOUT2 = 6.75MHz AMPLITUDE = 0dBFS fOUT3 = 7.25MHz Div Div Div fSOFUDTR4 == 77.07d5BMcHz B – B – B – AMPLITUDE = 0dBFS 10d 10d 10d –100 –100 –110 START: 0.3MHz STOP: 62.5MHz START: 0.3MHz STOP: 50.0MHz START: 0.3MHz STOP: 25.0MHz Figure 18.Single-Tone SFDR Figure 19.Dual-Tone SFDR Figure 20.Four-Tone SFDR –8– REV. B

AD9760 Typical AC Characterization Curves @ +3 V Supplies (AVDD = +3 V, DVDD = +3 V, I = 20 mA, 50(cid:2) Doubly Terminated Load, Differential Output, T = +25(cid:3)C, SFDR up to Nyquist, unless otherwise noted) OUTFS A 90 85 85 0dBFS 5MSPS 80 80 –6dBFS 80 –6dBFS 75 75 R – dBc70 25MSPS DR – dBc70 –12dBFS DR – dBc70 –12dBFS D F65 F65 0dBFS SF 100MSPS S S 50MSPS 60 60 60 125MSPS 55 55 50 50 50 0.1 1 10 100 0.00 0.50 1.00 1.50 2.00 2.50 0.00 2.00 4.00 6.00 8.00 10.00 12.00 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 21.SFDR vs. f @ 0 dBFS Figure 22.SFDR vs. f @ 5 MSPS Figure 23.SFDR vs. f @ 25 MSPS OUT OUT OUT 85 85 85 80 80 80 75 –6dBFS 75 75 SFDR – dBc7605 –12dBFS SFDR – dBc7605 –6dBFS –12dBFS SFDR – dBc7605 –6dBFS –12dBFS 0dBFS 60 60 60 0dBFS 55 55 55 0dBFS 50 50 50 0.00 5.00 10.00 15.00 20.00 25.00 0.00 10.00 20.00 30.00 40.00 50.00 0.00 10.00 20.00 30.00 40.00 50.0060.00 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 24.SFDR vs. fOUT @ 50 MSPS Figure 25.SFDR vs. fOUT @ 100 MSPS Figure 26.SFDR vs. fOUT @ 125 MSPS 90 90 90 2.27MHz 3.38/3.63MHz @ 25MSPS 1MHz @ 25MSPS 80 4.55MHz 80 @ 5MSPS 80 0.675 /@0.7 52M5MSPHSz @ 50MSPS SFDR – dBc6700 @ 455M5SkPHSz @ 10 90.M1MSPHSz SFDR – dBc6700 2@0 M10@H0z M225S.MP5MSSPHSz @ 501M0MSPHSz SFDR – dBc7600 6@.7 550/7M.2S5PMSHz 11.37MHz 25MHz 13.5/14.5MHz @ 125MSPS @ 125MSPS @ 100MSPS 50 50 50 16.9/18.1MHz @ 125MSPS 40 40 40 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 –30 –25 –20 –15 –10 –5 0 AOUT – dBFS AOUT – dBFS AOUT – dBFS Figure 27.Single-Tone SFDR vs. A Figure 28.Single-Tone SFDR vs. Figure 29.Dual-Tone SFDR vs. A OUT OUT @ f = f /11 A @ f = f /5 @ f = f /7 OUT CLOCK OUT OUT CLOCK OUT CLOCK REV. B –9–

AD9760 –70 80 75 2.5MHz IOUTA @ 75 –6dBFS –75 70 2ND 70 HARMONIC 10MHz IDIFF @ dBc––8805 H3RADRMONIC SFDR – dBc665055 22.4MHz SFDR – dBc6605 –6dBFSID0dIFBFF @S 28.6MHz 55 50 –90 50 H4TAHRMONIC 45 I0OdUBTFAS @ –95 40 45 0 20 40 60 80 100 120 140 2 4 6 8 10 12 14 16 18 20 1 10 100 FREQUENCY – MSPS IREF – mA OUTPUT FREQUENCY – MHz Figure 30.THD vs. f Figure 31.SFDR vs. f and I Figure 32.Differential vs. Single CLOCK OUT OUTFS f = 2MHz @ 100 MSPS, 0dBFS Ended SFDR vs. f @ 100 MSPS OUT OUT 0.5 0.5 80 0.4 0.4 75 2.5MHz 0.3 0.3 70 0.2 ERROR – LSB–00..110 ERROR – LSB00..102 SFDR – dBc 665505 10M2H8z.6MHz –0.2 50 –0.3 –0.1 45 –0.4 –0.2 –0.5 40 0 125 250 375 500 625 750 8751000 0 125 250 375 500 625 750 8751000 –40 –20 0 20 40 60 80 CODE CODE TEMPERATURE – (cid:3)C Figure 33.Typical INL Figure 34.Typical DNL Figure 35.SFDR vs. Temperature @ 100 MSPS, 0dBFS 0 0 –10 fCLOCK = 125MSPS fCLOCK = 100MSPS fCLOCK = 50MSPS fOUT = 9.95MHz fOUT1 = 13.5MHz fOUT1 = 6.25MHz SFDR = 62dBc fOUT2 = 14.5MHz fOUT2 = 6.75MHz AMPLITUDE = 0dBFS SFDR = 59.0dBc fOUT3 = 7.25MHz AMPLITUDE = 0dBFS fOUT4 = 7.75MHz SFDR = 71dBc Div Div Div AMPLITUDE = 0dBFS B – B – B – 10d 10d 10d –100 –100 –110 START: 0.3MHz STOP: 62.5MHz START: 0.3MHz STOP: 50.0MHz START: 0.3MHz STOP: 25.0MHz Figure 36.Single-Tone SFDR Figure 37.Dual-Tone SFDR Figure 38.Four-Tone SFDR –10– REV. B

AD9760 FUNCTIONAL DESCRIPTION DAC TRANSFER FUNCTION Figure 39 shows a simplified block diagram of the AD9760. The AD9760 provides complementary current outputs, I OUTA The AD9760 consists of a large PMOS current source array that and I . I will provide a near full-scale current output, OUTB OUTA is capable of providing up to 20mA of total current. The array I , when all bits are high (i.e., DAC CODE = 1023) while OUTFS is divided into 31 equal currents that make up the 5 most sig- I , the complementary output, provides no current. The OUTB nificant bits (MSBs). The next 4 bits or middle bits consist current output appearing at I and I is a function of OUTA OUTB of 15 equal current sources whose value is 1/16th of an MSB both the input code and I and can be expressed as: OUTFS current source. The remaining LSBs is a binary weighted frac- I = (DAC CODE/1024) × I (1) tion of the middle-bits current sources. Implementing the OUTA OUTFS middle and lower bits with current sources, instead of an R-2R IOUTB = (1023 – DAC CODE)/1024 × IOUTFS (2) ladder, enhances its dynamic performance for multitone or low where DAC CODE = 0 to 1023 (i.e., Decimal Representation). amplitude signals and helps maintain the DAC’s high output impedance (i.e., >100kΩ). As mentioned previously, IOUTFS is a function of the reference current I , which is nominally set by a reference voltage, REF All of these current sources are switched to one or the other of V and external resistor R . It can be expressed as: REFIO SET the two output nodes (i.e., I or I ) via PMOS differen- OUTA OUTB I = 32 × I (3) tial current switches. The switches are based on a new architec- OUTFS REF ture that drastically improves distortion performance. This new where I = V /R (4) REF REFIO SET switch architecture reduces various timing errors and provides The two current outputs will typically drive a resistive load matching complementary drive signals to the inputs of the dif- directly or via a transformer. If dc coupling is required, I OUTA ferential current switches. and I should be directly connected to matching resistive OUTB The analog and digital sections of the AD9760 have separate loads, R , that are tied to analog common, ACOM. Note, LOAD power supply inputs (i.e., AVDD and DVDD) that can operate R may represent the equivalent load resistance seen by LOAD independently over a 2.7 volt to 5.5 volt range. The digital I or I as would be the case in a doubly terminated OUTA OUTB section, which is capable of operating up to a 125 MSPS clock 50Ω or 75Ω cable. The single-ended voltage output appearing rate, consists of edge-triggered latches and segment decoding at the I and I nodes is simply: OUTA OUTB logic circuitry. The analog section includes the PMOS current V = I × R (5) OUTA OUTA LOAD sources, the associated differential switches, a 1.20 V bandgap V = I × R (6) voltage reference and a reference control amplifier. OUTB OUTB LOAD Note the full-scale value of V and V should not exceed The full-scale output current is regulated by the reference con- OUTA OUTB the specified output compliance range to maintain specified trol amplifier and can be set from 2 mA to 20 mA via an exter- distortion and linearity performance. nal resistor, R . The external resistor, in combination with SET both the reference control amplifier and voltage reference V , sets the reference current I , which is mirrored over to REFIO REF the segmented current sources with the proper scaling factor. The full-scale current, I , is thirty-two times the value of I . OUTFS REF +5V 0.1(cid:1)F REFLO COMP1 AVDD ACOM +1.20V REF AD9760 50pF 0.1(cid:1)F VREFIO IREF RFSE FAIODJ CURREPNMTO SSOURCE COMP2 0.1(cid:1)F ARRAY RSET VDIFF = VOUTA – VOUTB 2k(cid:2) +5V DVDD DCOM SEGMFEONRT DEBD9 S–WDBIT1CHES SWLSITBCH IIOOUUTTBA IOUTB IOUTA VOUTB VROLOUATAD CLOCK CLOCK LATCHES RLOAD 50(cid:2) SLEEP 50(cid:2) DIGITAL DATA INPUTS (DB9–DB0) Figure 39.Functional Block Diagram REV. B –11–

AD9760 The differential voltage, V , appearing across I and REFERENCE CONTROL AMPLIFIER DIFF OUTA I is: The AD9760 also contains an internal control amplifier that is OUTB V = (I – I ) × R (7) used to regulate the DAC’s full-scale output current, IOUTFS. DIFF OUTA OUTB LOAD The control amplifier is configured as a V-I converter as shown Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be in Figure 41, so that its current output, IREF, is determined by expressed as: the ratio of the V and an external resistor, R , as stated REFIO SET V = {(2 DAC CODE – 1023)/1024} × in Equation 4. I is copied over to the segmented current DIFF REF (32 R /R ) × V (8) sources with the proper scaling factor to set I as stated in LOAD SET REFIO OUTFS Equation 3. These last two equations highlight some of the advantages of AVDD operating the AD9760 differentially. First, the differential op- eration will help cancel common-mode error sources associated 0.1(cid:1)F with I and I such as noise, distortion and dc offsets. OUTA OUTB Second, the differential code dependent current and subsequent voltage, V , is twice the value of the single-ended voltage AVDD REFLO COMP1 AVDD DIFF +1.2V REF output (i.e., VOUTA or VOUTB), thus providing twice the signal 50pF power to the load. EXTERNAL VREFIO REFIO CURRENT REF FS ADJ SOURCE Note, the gain drift temperature performance for a single-ended ARRAY (VOUTA and VOUTB) or differential output (VDIFF) of the AD9760 RSET IREF = can be enhanced by selecting temperature tracking resistors for VREFIO/RSET REFERENCE AD9760 CONTROL R and R due to their ratiometric relationship as shown AMPLIFIER LOAD SET in Equation 8. Figure 41.External Reference Configuration REFERENCE OPERATION The control amplifier allows a wide (10:1) adjustment span of The AD9760 contains an internal 1.20 V bandgap reference I over a 2mA to 20 mA range by setting IREF between OUTFS that can be easily disabled and overridden by an external refer- 62.5µA and 625µA. The wide adjustment span of I pro- OUTFS ence. REFIO serves as either an input or output depending on vides several application benefits. The first benefit relates whether the internal or an external reference is selected. If directly to the power dissipation of the AD9760, which is REFLO is tied to ACOM, as shown in Figure 40, the internal proportional to I (refer to the Power Dissipation section). OUTFS reference is activated and REFIO provides a 1.20V output. In The second benefit relates to the 20dB adjustment, which is this case, the internal reference must be compensated externally useful for system gain control purposes. with a ceramic chip capacitor of 0.1µF or greater from REFIO The small signal bandwidth of the reference control amplifier is to REFLO. Also, REFIO should be buffered with an external approximately 1.4 MHz and can be reduced by connecting an amplifier having an input bias current less than 100nA if any external capacitor between COMP1 and AVDD. The output of additional loading is required. the control amplifier, COMP1, is internally compensated via a +5V 50 pF capacitor that limits the control amplifier small-signal 0.1(cid:1)F bandwidth and reduces its output impedance. Any additional OPTIONAL EXTERNAL external capacitance further limits the bandwidth and acts as a REF BUFFER REFLO COMP1 AVDD filter to reduce the noise contribution from the reference ampli- +1.2V REF fier. Figure 42 shows the relationship between the external 50pF capacitor and the small signal –3dB bandwidth of the refer- REFIO CURRENT ence amplifier. Since the –3dB bandwidth corresponds to the ADDITIOLONAADL 0.1(cid:1)F FS ADJ SAORURRACYE dominant pole, and hence the time constant, the settling time of 2k(cid:2) AD9760 the control amplifier to a stepped reference input response can be approximated. Figure 40.Internal Reference Configuration 1000 The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may be applied to REFIO as shown in Figure 41. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Hz k Note that the 0.1µF compensation capacitor is not required H – since the internal reference is disabled, and the high input im- DT 10 pedance (i.e., 1 MΩ) of REFIO minimizes any loading of the DWI N external reference. A B 0.1 0.1 1 10 100 1000 COMP1 CAPACITOR – nF Figure 42.External COMP1 Capacitor vs. –3dB Bandwidth –12– REV. B

AD9760 AVDD AVDD OPTIONAL BANDLIMITING CAPACITOR REFLO COMP1 AVDD RFB VDD +1.2V REF 50pF 1.2V OUT1 0.1V TO 1.2V REFIO AD7524 VREF CURRENT AD1580 OUT2 FS ADJ SOURCE ARRAY AGND RSET IREF = AD9760 VREF/RSET DB7–DB0 Figure 43.Single-Supply Gain Control Circuit The optimum distortion performance for any reconstructed In some applications, the user may elect to use an external con- waveform is obtained with a 0.1µF external capacitor installed. trol amplifier to enhance the multiplying bandwidth, distortion Thus, if I is fixed for an application, a 0.1µF ceramic chip performance and/or settling time. External amplifiers capable of REF capacitor is recommended. Also, since the control amplifier is driving a 50 pF load such as the AD817 are suitable for this optimized for low power operation, multiplying applications purpose. It is configured in such a way that it is in parallel with requiring large signal swings should consider using an external the weaker internal reference amplifier as shown in Figure 45. control amplifier to enhance the application’s overall large signal In this case, the external amplifier simply overdrives the weaker multiplying bandwidth and/or distortion performance. reference control amplifier. Also, since the internal control amplifier has a limited current output, it will sustain no damage There are two methods in which I can be varied for a fixed REF if overdriven. R . The first method is suitable for a single-supply system in SET which the internal reference is disabled, and the common-mode voltage of REFIO is varied over its compliance range of 1.25 V EXTERNAL CONTROL AMPLIFIER AVDD to 0.10 V. REFIO can be driven by a single-supply amplifier or DAC, allowing I to be varied for a fixed R . Since the VREF REF SET INPUT input impedance of REFIO is approximately 1 MΩ, a simple, REFLO 50pF COMP1 AVDD low cost R-2R ladder DAC configured in the voltage mode +1.2V REF topology may be used to control the gain. This circuit is shown REFIO CURRENT in Figure 43 using the AD7524 and an external 1.2 V reference, FS ADJ SOURCE the AD1580. ARRAY RSET AD9760 The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed and IREF is Figure 45.Configuring an External Reference Control varied by an external voltage, VGC, applied to RSET via an ampli- Amplifier fier. An example of this method is shown in Figure 44 where the internal reference is used to set the common-mode voltage ANALOG OUTPUTS of the control amplifier to 1.20V. The external voltage, V , is The AD9760 produces two complementary current outputs, GC referenced to ACOM and should not exceed 1.2 V. The value I and I , which may be configured for single-ended or OUTA OUTB of R is such that I and I do not exceed 62.5µA differential operation. I and I can be converted into SET REFMAX REFMIN OUTA OUTB and 625µA, respectively. The associated equations in Figure 44 complementary single-ended voltage outputs, V and V , OUTA OUTB can be used to determine the value of R . via a load resistor, R , as described in the DAC Transfer SET LOAD Function section by Equations 5 through 8. The differential OPTIONAL AVDD voltage, VDIFF, existing between VOUTA and VOUTB can also be BANDLIMITING converted to a single-ended voltage via a transformer or differ- CAPACITOR ential amplifier configuration. The ac performance of the AD9760 is optimum and specified using a differential transformer REFLO COMP1 AVDD coupled output in which the voltage swing at I and I is +1.2V REF OUTA OUTB 50pF limited to ±0.5V. If a single-ended unipolar output is desirable, REFIO CURRENT I should be selected. 1(cid:1)F FS ADJ SOURCE OUTA ARRAY RSET IREF AD9760 The distortion and noise performance of the AD9760 can be enhanced when the AD9760 is configured for differential opera- IREF = (1.2 – VGC)/RSET tion. The common-mode error sources of both IOUTA and IOUTB VGC WITH VGC < VREFIO AND 62.5(cid:1)A IREF 625A can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode Figure 44.Dual-Supply Gain Control Circuit error sources include even-order distortion products and noise. REV. B –13–

AD9760 The enhancement in distortion performance becomes more clock cycle as long as the specified minimum times are met significant as the frequency content of the reconstructed wave- although the location of these transition edges may affect digital form increases. This is due to the first order cancellation of feedthrough and distortion performance. Best performance is various dynamic common-mode distortion mechanisms, digi- typically achieved when the input data transitions on the falling edge tal feedthrough and noise. of a 50% duty cycle clock. Performing a differential-to-single-ended conversion via a The digital inputs are CMOS compatible with logic thresholds, transformer also provides the ability to deliver twice the re- V set to approximately half the digital positive supply THRESHOLD constructed signal power to the load (i.e., assuming no source (DVDD) or termination). Since the output currents of I and I are OUTA OUTB V = DVDD/2 (±20%) complementary, they become additive when processed differ- THRESHOLD entially. A properly selected transformer will allow the AD9760 The internal digital circuitry of the AD9760 is capable of oper- to provide the required power and voltage levels to different ating over a digital supply range of 2.7V to 5.5 V. As a result, loads. Refer to Applying the AD9760 section for examples of the digital inputs can also accommodate TTL levels when various output configurations. DVDD is set to accommodate the maximum high level voltage V . A DVDD of 3V to 3.3V will typically ensure proper The output impedance of I and I is determined by the OH(MAX) OUTA OUTB compatibility with most TTL logic families. Figure 46 shows the equivalent parallel combination of the PMOS switches associ- equivalent digital input circuit for the data and clock inputs. ated with the current sources and is typically 100kΩ in parallel The sleep mode input is similar with the exception that it con- with 5 pF. It is also slightly dependent on the output voltage tains an active pull-down circuit, ensuring that the AD9760 (i.e., V and V ) due to the nature of a PMOS device. OUTA OUTB remains enabled if this input is left disconnected. As a result, maintaining I and/or I at a virtual ground OUTA OUTB via an I-V op amp configuration will result in the optimum dc DVDD linearity. Note the INL/DNL specifications for the AD9760 are measured with I maintained at a virtual ground via an OUTA op amp. DIGITAL I and I also have a negative and positive voltage com- INPUT OUTA OUTB pliance range that must be adhered to in order to achieve opti- mum performance. The negative output compliance range of –1.0V is set by the breakdown limits of the CMOS process. Figure 46.Equivalent Digital Input Operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9760. Since the AD9760 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in The positive output compliance range is slightly dependent on achieving the optimum performance. The drivers of the digital the full-scale output current, I . It degrades slightly from OUTFS data interface circuitry should be specified to meet the mini- its nominal 1.25 V for an I = 20 mA to 1.00 V for an OUTFS mum setup and hold times of the AD9760 as well as its required I = 2 mA. The optimum distortion performance for a OUTFS min/max input logic level thresholds. Typically, the selection of single-ended or differential output is achieved when the maximum the slowest logic family that satisfies the above conditions will full-scale signal at I and I does not exceed 0.5 V. Ap- OUTA OUTB result in the lowest data feedthrough and noise. plications requiring the AD9760’s output (i.e., V and/or OUTA V ) to extend its output compliance range should size R Digital signal paths should be kept short and run lengths OUTB LOAD accordingly. Operation beyond this compliance range will ad- matched to avoid propagation delay mismatch. The insertion of versely affect the AD9760’s linearity performance and subse- a low value resistor network (i.e., 20Ω to 100Ω) between the quently degrade its distortion performance. AD9760 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that DIGITAL INPUTS contribute to data feedthrough. For longer run lengths and high The AD9760’s digital input consists of 10 data input pins and a data update rates, strip line techniques with proper termination clock input pin. The 10-bit parallel data inputs follow standard resistors should be considered to maintain “clean” digital in- positive binary coding where DB9 is the most significant bit puts. Also, operating the AD9760 with reduced logic swings and (MSB) and DB0 is the least significant bit (LSB). I pro- a corresponding digital supply (DVDD) will also reduce data OUTA duces a full-scale output current when all data bits are at feedthrough. Logic 1. IOUTB produces a complementary output with the full- The external clock driver circuitry should provide the AD9760 scale current split between the two outputs as a function of the with a low jitter clock input meeting the min/max logic levels input code. while providing fast edges. Fast clock edges will help minimize The digital interface is implemented using an edge-triggered any jitter that will manifest itself as phase noise on a recon- master slave latch. The DAC output is updated following the structed waveform. Thus, the clock input should be driven by rising edge of the clock as shown in Figure 1 and is designed to the fastest logic family suitable for the application. support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse- width. The setup and hold times can also be varied within the –14– REV. B

AD9760 Note, the clock input could also be driven via a sine wave that is Conversely, I is dependent on both the digital input wave- DVDD centered around the digital threshold (i.e., DVDD/2), and form, f , and digital supply DVDD. Figures 48 and 49 CLOCK meets the min/max logic threshold. This will typically result in a show I as a function of full-scale sine wave output ratios DVDD slight degradation in the phase noise, that becomes more notice- (f /f ) for various update rates with DVDD = 5 V and OUT CLOCK able at higher sampling rates and output frequencies. Also, at DVDD = 3 V, respectively. Note how I is reduced by more DVDD higher sampling rates, the 20% tolerance of the digital logic than a factor of 2 when DVDD is reduced from 5 V to 3V. threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data 18 setup and hold times. 125MSPS 16 SLEEP MODE OPERATION 14 100MSPS The AD9760 has a power-down function that turns off the out- 12 put current and reduces the supply current to less than 8.5 mA A m over the specified supply range of 2.7V to 5.5 V and tempera- – 10 D ture range. This mode can be activated by applying a logic level VD 8 D “1” to the SLEEP pin. This digital input also contains an active I 50MSPS 6 pull-down circuit that ensures that the AD9760 remains enabled if this input is left disconnected. The SLEEP input with active 4 25MSPS pull-down requires <40 µA of drive current. 2 The power-up and power-down characteristics of the AD9760 5MSPS 0 are dependent upon the value of the compensation capacitor 0.01 0.1 1 connected to COMP1. With a nominal value of 0.1µF, the RATIO (fOUT/fCLK) AD9760 takes less than 5µs to power down and approximately Figure 48.IDVDD vs. Ratio @ DVDD = 5 V 3.25ms to power back up. Note, the SLEEP MODE should not be used when the external control amplifier is used as shown in 8 125MSPS Figure 45. POWER DISSIPATION 6 100MSPS The power dissipation, P , of the AD9760 is dependent on D several factors that include: (1) AVDD and DVDD, the power A m supply voltages; (2) IOUTFS, the full-scale current output; (3) – D4 D f , the update rate; (4) and the reconstructed digital input V CLOCK D waveform. The power dissipation is directly proportional to the I 50MSPS analog supply current, I , and the digital supply current, AVDD 2 IDVDD. IAVDD is directly proportional to IOUTFS as shown in Fig- 25MSPS ure 47 and is insensitive to f . CLOCK 5MSPS 0 30 0.01 0.1 1 RATIO (fOUT/fCLK) 25 Figure 49.I vs. Ratio @ DVDD = 3 V DVDD 20 A m – D15 D V A I 10 5 0 2 4 6 8 10 12 14 16 18 20 IOUTFS – mA Figure 47.I vs. I AVDD OUTFS REV. B –15–

AD9760 APPLYING THE AD9760 DIFFERENTIAL USING AN OP AMP OUTPUT CONFIGURATIONS An op amp can also be used to perform a differential to single- The following sections illustrate some typical output configura- ended conversion as shown in Figure 51. The AD9760 is con- tions for the AD9760. Unless otherwise noted, it is assumed figured with two equal load resistors, R , of 25 Ω. The LOAD that I is set to a nominal 20 mA. For applications requir- differential voltage developed across I and I is con- OUTFS OUTA OUTB ing the optimum dynamic performance, a differential output verted to a single-ended signal via the differential op amp con- configuration is suggested. A differential output configuration figuration. An optional capacitor can be installed across I OUTA may consist of either an RF transformer or a differential op amp and I , forming a real pole in a low-pass filter. The addition OUTB configuration. The transformer configuration provides the opti- of this capacitor also enhances the op amps distortion perfor- mum high frequency performance and is recommended for any mance by preventing the DACs high slewing output from over- application allowing for ac coupling. The differential op amp loading the op amp’s input. configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. 500(cid:2) A single-ended output is suitable for applications requiring a AD9760 225(cid:2) unipolar voltage output. A positive unipolar output voltage will IOUTA 22 result if I and/or I is connected to an appropriately AD8047 OUTA OUTB 225(cid:2) stiiozend m loaayd b ree smistoorre, sRuLiOtaAbDl,e r efoferr rae dsi ntog lAe-CsuOpMpl.y T shysist ecmon rfeigquurirai-ng IOUTB 21 COPT 500(cid:2) a dc coupled, ground referred output voltage. Alternatively, an 25(cid:2) 25(cid:2) amplifier could be configured as an I-V converter, thus convert- ing I or I into a negative unipolar voltage. This con- OUTA OUTB figuration provides the best dc linearity since I or I is Figure 51.DC Differential Coupling Using an Op Amp OUTA OUTB maintained at a virtual ground. Note that IOUTA provides slightly The common-mode rejection of this configuration is typically better performance than IOUTB. determined by the resistor matching. In this circuit, the differ- ential op amp circuit using the AD8047 is configured to provide DIFFERENTIAL COUPLING USING A TRANSFORMER some additional signal gain. The op amp must operate off of a An RF transformer can be used to perform a differential-to- dual supply since its output is approximately ±1.0V. A high single-ended signal conversion as shown in Figure 50. A speed amplifier capable of preserving the differential perfor- differentially coupled transformer output provides the optimum mance of the AD9760 while meeting other system level objec- distortion performance for output signals whose spectral content tives (i.e., cost, power) should be selected. The op amps lies within the transformer’s passband. An RF transformer such differential gain, its gain setting resistor values, and full-scale as the Mini-Circuits T1-1T provides excellent rejection of com- output swing capabilities should all be considered when opti- mon-mode distortion (i.e., even-order harmonics) and noise mizing this circuit. over a wide frequency range. It also provides electrical isolation The differential circuit shown in Figure 52 provides the neces- and the ability to deliver twice the power to the load. Trans- sary level-shifting required in a single supply system. In this formers with different impedance ratios may also be used for case, AVDD which is the positive analog supply for both the impedance matching purposes. Note that the transformer AD9760 and the op amp is also used to level-shift the differ- provides ac coupling only. ential output of the AD9760 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. MINI-CIRCUITS T1-1T IOUTA 22 500(cid:2) AD9760 RLOAD AD9760 225(cid:2) IOUTB 21 IOUTA 22 OPTIONAL RDIFF 225(cid:2) AD8041 Figure 50.Differential Output Using a Transformer IOUTB 21 COPT 1k(cid:2) AVDD The center tap on the primary side of the transformer must be 25(cid:2) 25(cid:2) 1k(cid:2) connected to ACOM to provide the necessary dc current path for both I and I . The complementary voltages appear- OUTA OUTB Figure 52.Single-Supply DC Differential Coupled Circuit ing at I and I (i.e., V and V ) swing symmetri- OUTA OUTB OUTA OUTB cally around ACOM and should be maintained with the specified SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT output compliance range of the AD9760. A differential resistor, Figure 53 shows the AD9760 configured to provide a unipolar R , may be inserted in applications where the output of the DIFF output range of approximately 0V to +0.5 V for a doubly termi- transformer is connected to the load, R , via a passive re- LOAD nated 50Ω cable since the nominal full-scale current, I , of construction filter or cable. R is determined by the OUTFS DIFF 20 mA flows through the equivalent R of 25Ω. In this case, transformer’s impedance ratio and provides the proper source LOAD R represents the equivalent load resistance seen by I or termination that results in a low VSWR. Note that approxi- LOAD OUTA I . The unused output (I or I ) can be connected mately half the signal power will be dissipated across R . OUTB OUTA OUTB DIFF to ACOM directly or via a matching R . Different values of LOAD –16– REV. B

AD9760 I and R can be selected as long as the positive compli- the management of analog and digital ground currents in a OUTFS LOAD ance range is adhered to. One additional consideration in this system. In general, AVDD, the analog supply, should be de- mode is the integral nonlinearity (INL) as discussed in the Ana- coupled to ACOM, the analog common, as close to the chip as log Output section of this data sheet. For optimum INL perfor- physically possible. Similarly, DVDD, the digital supply, should mance, the single-ended, buffered voltage output configuration be decoupled to DCOM as close as physically possible. is suggested. For those applications that require a single +5V or +3 V supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 55. The AD9760 IOUTFS = 20mA VOUTA = 0 TO +0.5V circuit consists of a differential LC filter with separate power IOUTA 22 supply and return lines. Lower noise can be attained using low 50(cid:2) 50(cid:2) ESR type electrolytic and tantalum capacitors. IOUTB 21 25(cid:2) FERRITE BEADS TTL/CMOS AVDD Figure 53.0V to +0.5 V Unbuffered Voltage Output LOGIC 100(cid:1)F 10-22(cid:1)F 0.1(cid:1)F CIRCUITS ELECT. TANT. CER. SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT ACOM CONFIGURATION Figure 54 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the +5V OR +3V AD9760 output current. U1 maintains I (or I ) at a POWER SUPPLY OUTA OUTB virtual ground, thus minimizing the nonlinear output impedance Figure 55.Differential LC Filter for Single +5V or +3 V effect on the DAC’s INL performance as discussed in the Ana- Applications log Output section. Although this single-ended configuration Maintaining low noise on power supplies and ground is critical typically provides the best dc linearity performance, its ac distor- to obtain optimum results from the AD9760. If properly imple- tion performance at higher DAC update rates may be limited by mented, ground planes can perform a host of functions on high U1’s slewing capabilities. U1 provides a negative unipolar out- speed circuit boards: bypassing, shielding, current transport, put voltage and its full-scale output voltage is simply the product etc. In mixed signal design, the analog and digital portions of of R and I . The full-scale output should be set within FB OUTFS the board should be distinct from each other, with the analog U1’s voltage output swing capabilities by scaling I and/or OUTFS ground plane confined to the areas covering the analog signal R . An improvement in ac distortion performance may result FB traces, and the digital ground plane confined areas covering the with a reduced I since the signal current U1 will be required OUTFS digital interconnects. to sink will be subsequently reduced. All analog ground pins of the DAC, reference and other analog COPT components should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to RFB 1/4 inch wide underneath or within 1/2 inch of the DAC to 200(cid:2) maintain optimum performance. Care should be taken to ensure AD9760 IOUTFS = 10mA that the ground plane is uninterrupted over crucial signal paths. IOUTA 22 On the digital side, this includes the digital input lines running U1 VOUT = IOUTFS (cid:4) RFB to the DAC as well as any clock signals. On the analog side, this IOUTB 21 includes the DAC output signal, reference signal and the supply 200(cid:2) feeders. The use of wide runs or planes in the routing of power lines is Figure 54.Unipolar Buffered Voltage Output also recommended. This serves the dual role of providing a low series impedance power supply to the part and providing some POWER AND GROUNDING CONSIDERATIONS “free” capacitive decoupling to the appropriate ground plane. It In systems seeking to simultaneously achieve high speed and is essential that care be taken in the layout of signal and power high performance, the implementation and construction of the ground interconnects to avoid inducing extraneous voltage printed circuit board design is often as important as the circuit drops in the signal ground paths. It is recommended that all design. Proper RF techniques must be used in device selection, connections be short, direct and as physically close to the pack- placement and routing, and supply bypassing and grounding. age as possible to minimize the sharing of conduction paths The evaluation board for the AD9760, which uses a four-layer between different currents. When runs exceed an inch in length, PC board, serves as a good example for the above-mentioned strip line techniques with proper termination resistor should be considerations. Figures 60–65 illustrate the recommended considered. The necessity and value of this resistor will be de- printed circuit board ground, power and signal plane layouts pendent upon the logic family used. that are implemented on the AD9760 evaluation board. For a more detailed discussion of the implementation and con- Proper grounding and decoupling should be a primary objective struction of high speed, mixed signal printed circuit boards, in any high speed, high resolution system. The AD9760 features refer to Analog Devices’ application notes AN-280 and AN-333. separate analog and digital supply and ground pins to optimize REV. B –17–

AD9760 APPLICATIONS Using the AD9760 for QAM Modulation QinA dMigi tisa lo cnoem omf tuhnei cmatoiostn w siydsetelym uss. eTdh disig mitaold muloadtiuolna ttieocnh sncihqeumees REFIO REFLOU1 IOUTA TNOYQUIST I-CHANNEL FILTER can be found in both FDM spreadspectrum (i.e., CDMA) based FS ADJ IOUTB AND MIXER systems. A QAM signal is a carrier frequency that is both 2RkS(cid:2)ET* CLOCK 5R0L(cid:2)OA**D 5R0L(cid:2)OA**D modulated in amplitude (i.e., AM modulation) and in phase RCAL1 CLOCK (i.e., PM modulation). It can be generated by independently 50(cid:2) AVDD modulating two carriers of identical frequency but with a 90° pnhenast ea nddif fae rqeunacde.r aTtuhrise r(eQsu) lctas rirnie arn c oinm-pphoanseen (tI a) tc aa r9r0ie°r pchoamsepo- 0.1(cid:1)F REFIO RQE-FCLHOUA2NCNLEOLCKIOUTA TNFIOYLQTEURIST shift with respect to the I component. The I and Q components RSET FS ADJ IOUTB 50(cid:2)** 50(cid:2)** AND MIXER are then summed to provide a QAM signal at the specified car- 2k(cid:2)* RLOAD RLOAD rier frequency. RCAL2 * OHMTEK ORNA1001F 100(cid:2) ** OHMTEK TOMC1603-50F A common and traditional implementation of a QAM modu- lator is shown in Figure 56. The modulation is performed in the Figure 57.Baseband QAM Implementation Using Two analog domain in which two DACs are used to generate the AD9760s baseband I and Q components, respectively. Each component is are Digital ASICs which implement other digital modulation then typically applied to a Nyquist filter before being applied to schemes such as PSK and FSK. This digital implementation has a quadrature mixer. The matching Nyquist filters shape and the benefit of generating perfectly matched I and Q components limit each component’s spectral envelope while minimizing in terms of gain and phase, which is essential in maintaining intersymbol interference. The DAC is typically updated at the optimum performance in a communication system. In this QAM symbol rate or possibly a multiple of it if an interpolating implementation, the reconstruction DAC must be operating at a filter precedes the DAC. The use of an interpolating filter typi- sufficiently high clock rate to accommodate the highest specified cally eases the implementation and complexity of the analog QAM carrier frequency. Figure 58 shows a block diagram of filter, which can be a significant contributor to mismatches in such an implementation using the AD9760. gain and phase between the two baseband channels. A quadra- ture mixer modulates the I and Q components with in-phase and quadrature phase carrier frequency and sums the two out- 12 10 I DATA puts to provide the QAM signal. 12 STEQLA-1M130 LPF TMOIXER Q DATA AD9760 50(cid:2) 50(cid:2) 10 AD9760 12 12 SIN COS ADOSSRIPC FRECQAURERNIECRY 0 90 Σ TMOIXER FRECQAURERNIECRY 12 STENLC-1O177 10 AD9760 CLOCK NYQUIST QUADRATURE FILTERS MODULATOR Figure 58.Digital QAM Architecture Figure 56.Typical Analog QAM Architecture AD9760 EVALUATION BOARD In this implementation, it is much more difficult to maintain General Description proper gain and phase matching between the I and Q channels. The AD9760-EB is an evaluation board for the AD9760 10-bit The circuit implementation shown in Figure 57 helps improve D/A converter. Careful attention to layout and circuit design, on the matching and temperature stability characteristics be- combined with a prototyping area, allow the user to easily and tween the I and Q channels. Using a single voltage reference effectively evaluate the AD9760 in any application where high derived from U1 to set the gain for both the I and Q channels resolution, high speed conversion is required. will improve the gain matching and stability. Further enhance- ments in gain matching and stability are achieved by using sepa- This board allows the user the flexibility to operate the AD9760 rate matching resistor networks for both R and R . in various configurations. Possible output configurations include SET LOAD Additional trim capability via R and R can be added to transformer coupled, resistor terminated, inverting/noninverting CAL1 CAL2 compensate for any initial mismatch in gain between the two and differential amplifier outputs. The digital inputs are designed channels. This may be attributed to any mismatch between U1 to be driven directly from various word generators with the on- and U2’s gain setting resistor (R ), effective load resistance, board option to add a resistor network for proper load termina- SET (R ), and/or voltage offset of each DAC’s control amplifier. tion. Provisions are also made to operate the AD9760 with LOAD The differential voltage outputs of U1 and U2 are fed into their either the internal or external reference or to exercise the power- respective differential inputs of a quadrature mixer via matching down feature. 50Ω filter networks. Refer to the application note AN-420, “Using the AD9760/ It is also possible to generate a QAM signal completely in the AD9760/AD9764-EB Evaluation Board,” for a thorough digital domain via a DSP or ASIC, in which case only a single description and operating instructions for the AD9760 evalua- DAC of sufficient resolution and performance is required to tion board. reconstruct the QAM signal. Also available from several vendors –18– REV. B

AD9760 Figure 59.Evaluation Board Schematic REV. B –19–

AD9760 Figure 60.Silkscreen Layer—Top Figure 61.Component Side PCB Layout (Layer 1) –20– REV. B

AD9760 Figure 62.Ground Plane PCB Layout (Layer 2) Figure 63.Power Plane PCB Layout (Layer 3) REV. B –21–

AD9760 Figure 64.Solder Side PCB Layout (Layer 4) Figure 65.Silkscreen Layer—Bottom –22– REV. B

AD9760 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) B) v. 28 15 0.2992 (7.60) 0 (re 0 0.2914 (7.40) 3/ – 0.4193 (10.65) 1 – 0.3937 (10.00) b 1 14 0 0 2 2 C PIN 1 00..10094236 ((22..6355)) 00..00209918 ((00..7245))(cid:4) 45(cid:3) 8(cid:3) 0.0500 (1.27) 0.0118 (0.30) 0.0500 0.0192 (0.49) 0(cid:3) 0.0157 (0.40) 0.0040 (0.10) (B1.S2C7) 0.0138 (0.35) SEPALTAINNGE 00..00102951 ((00..3223)) 28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50)0.169 (4.30) 0.256 (6.50)0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 8(cid:3) 0.028 (0.70) 0.0256 (0.65) 0.0118 (0.30) 0(cid:3) 0.020 (0.50) SEPALTAINNGE BSC 0.0075 (0.19) 00.0.0003759 ( (00.0.2900)) A. S. U. N D I E T N RI P REV. B –23–

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9760-EBZ AD9760AR50 AD9760AR AD9760ARZ50 AD9760ARZ AD9760ARU AD9760ARUZ50 AD9760ARU50 AD9760ARUZ AD9760ARU50RL7 AD9760ARUZ50RL7 AD9760ARUZRL7 AD9760ARZ50RL AD9760ARZRL