a 14-Bit, 300 MSPS High Speed TxDAC+® D/A Converter AD9755 FEATURES FUNCTIONAL BLOCK DIAGRAM 14-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate DVDD DCOM AVDD ACOM Excellent SFDR and IMD Performance SInFtDerRn atol CNloyqcku iDsto @ub l2i5n gM PHLzL Output: 71 dB PORT1 LATCH TCH IOUTA A MUX L DAC Differential or Single-Ended Clock Input C On-Chip 1.2 V Reference PORT2 LATCH DA IOUTB Single 3.3 V Supply Operation CLK+ Power Dissipation: 155mW @ 3.3 V REFIO CLK– PLL REFERENCE 48-Lead LQFP CLKVDD CLOCK FSADJ PLLVDD MULTIPLIER APPLICATIONS CLKCOM AD9755 Communications: LMDS, LMCS, MMDS RESET LPF DIV0 DIV1 PLLLOCK Base Stations Digital Synthesis QAM and OFDM PRODUCT DESCRIPTION The DAC utilizes a segmented current source architecture com- The AD9755 is a dual, muxed port, ultrahigh speed, single- bined with a proprietary switching technique to reduce glitch channel, 14-bit CMOS DAC. It integrates a high quality 14-bit energy and maximize dynamic accuracy. Differential current TxDAC+ core, a voltage reference, and digital interface circuitry outputs support single-ended or differential applications. The into a small 48-lead LQFP package. The AD9755 offers excep- differential outputs each provide a nominal full-scale current tional ac and dc performance while supporting update rates up from 2mA to 20 mA. to 300MSPS. The AD9755 is manufactured on an advanced low cost 0.35µm The AD9755 has been optimized for ultrahigh speed applica- CMOS process. It operates from a single supply of 3.0 V to 3.6V tions up to 300 MSPS where data rates exceed those possible on and consumes 155 mW of power. a single data interface port DAC. The digital interface consists of two buffered latches as well as control logic. These latches PRODUCT HIGHLIGHTS can be time multiplexed to the high speed DAC in several ways. 1. The AD9755 is a member of a pin compatible family of high This PLL drives the DAC latch at twice the speed of the exter- speed TxDAC+s providing 10-, 12-, and 14-bit resolution. nally applied clock and is able to interleave the data from the 2. Ultrahigh Speed 300 MSPS Conversion Rate. two input channels. The resulting output data rate is twice that of the two input channels. With the PLL disabled, an external 3. Dual 14-Bit Latched, Multiplexed Input Ports. The AD9755 2× clock may be supplied and divided by two internally. features a flexible digital interface allowing high speed data conversion through either a single or dual port input. The CLK inputs (CLK+/CLK–) can be driven either differentially or single-ended, with a signal swing as low as 1 V p-p. 4. Low Power. Complete CMOS DAC function operates on 155 mW from a 3.0 V to 3.6 V single supply. The DAC full- scale current can be reduced for lower power operation. 5. On-Chip Voltage Reference. The AD9755 includes a 1.20V temperature compensated band gap voltage reference. REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.

AD9755–SPECIFICATIONS (T to T , AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless DC SPECIFICATIONS MIN MAX OUTFS otherwise noted.) Parameter Min Typ Max Unit RESOLUTION 14 Bits DC ACCURACY1 Integral Linearity Error (INL) –5 ±2.5 +5 LSB Differential Nonlinearity (DNL) –3 ±1.5 +3 LSB ANALOG OUTPUT Offset Error –0.025 ±0.01 +0.025 % of FSR Gain Error (Without Internal Reference) –2 ±0.5 +2 % of FSR Gain Error (With Internal Reference) –2 ±0.25 +2 % of FSR Full-Scale Output Current2 2.0 20.0 mA Output Compliance Range –1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V Reference Output Current3 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance 1 MΩ TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 3.0 3.3 3.6 V DVDD 3.0 3.3 3.6 V PLLVDD 3.0 3.3 3.6 V CLKVDD 3.0 3.3 3.6 V Analog Supply Current (I )4 33 36 mA AVDD Digital Supply Current (I )4 3.5 4.5 mA DVDD PLL Supply Current (I )4 4.5 5.1 mA PLLVDD Clock Supply Current (I )4 10.0 11.5 mA CLKVDD Power Dissipation4 (3 V, I = 20 mA) 155 165 mW OUTFS Power Dissipation5 (3 V, I = 20 mA) 216 mW OUTFS Power Supply Rejection Ratio6—AVDD –1 +1 % of FSR/V Power Supply Rejection Ratio6—DVDD –0.04 +0.04 % of FSR/V OPERATING RANGE –40 +85 °C NOTES 1Measured at I , driving a virtual ground. OUTA 2Nominal full-scale current, I , is 32× the I current. OUTFS REF 3An external buffer amplifier is recommended to drive any external load. 4100 MSPS f with PLL on, f = 100 MHz, all supplies = 3.0 V. DAC OUT 5300 MSPS f . DAC 6±5% power supply variation. Specifications subject to change without notice. –2– REV. B

AD9755 (T to T , AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, CLKVDD = 3.3 V, I = 20 mA, DYNAMIC SPECIFICATIONS MIN MAX OUTFS Differential Transformer-Coupled Output, 50 (cid:1) Doubly Terminated, unless otherwise noted.) Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 300 MSPS DAC Output Settling Time (t ) (to 0.1%)1 11 ns ST Output Propagation Delay (t )1 1 ns PD Glitch Impulse1 5 pV-s Output Rise Time (10% to 90%)1 2.5 ns Output Fall Time (90% to 10%)1 2.5 ns Output Noise (I = 20 mA) 50 pA/√Hz OUTFS Output Noise (I = 2 mA) 30 pA/√Hz OUTFS AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 100 MSPS; f = 1.00 MHz DAC OUT 0 dBFS Output 74 84 dBc –6 dBFS Output 77 dBc –12 dBFS Output 79 dBc f = 65 MSPS; f = 1.1 MHz2 79 dBc DATA OUT f = 65 MSPS; f = 5.1 MHz2 79 dBc DATA OUT f = 65 MSPS; f = 10.1 MHz2 78 dBc DATA OUT f = 65 MSPS; f = 20.1 MHz2 74 dBc DATA OUT f = 65 MSPS; f = 30.1 MHz2 70 dBc DATA OUT f = 160 MSPS; f = 1.1 MHz 80 dBc DAC OUT f = 160 MSPS; f = 11.1 MHz 77 dBc DAC OUT f = 160 MSPS; f = 31.1 MHz 72 dBc DAC OUT f = 160 MSPS; f = 51.1 MHz 72 dBc DAC OUT f = 160 MSPS; f = 71.1 MHz 69 dBc DAC OUT f = 300 MSPS; f = 1.1 MHz 80 dBc DAC OUT f = 300 MSPS; f = 26.1 MHz 71 dBc DAC OUT f = 300 MSPS; f = 51.1 MHz 67 dBc DAC OUT f = 300 MSPS; f = 101.1 MHz 61 dBc DAC OUT f = 300 MSPS; f = 141.1 MHz 60 dBc DAC OUT Spurious-Free Dynamic Range within a Window f = 100 MSPS; f = 1 MHz; 2 MHz Span DAC OUT 0 dBFS Output 83.5 93 dBc f = 65 MSPS; f = 5.02 MHz; 2 MHz Span 85 dBc DAC OUT f = 150 MSPS; f = 5.04 MHz; 4 MHz Span 85 dBc DAC OUT Total Harmonic Distortion f = 100 MSPS; f = 1.00 MHz DAC OUT T = 25°C –83 –73 dBc A T to T –83 –71 dBc MIN MAX f = 65 MHz; f = 2.00 MHz –78 dBc DAC OUT f = 160 MHz; f = 2.00 MHz –78 dBc DAC OUT Multitone Power Ratio (Eight Tones at 110 kHz Spacing) f = 65 MSPS; f = 2.00 MHz to 2.77 MHz DAC OUT 0 dBFS Output 75 dBc –6 dBFS Output 73 dBc –12 dBFS Output 70 dBc NOTES 1Measured single-ended into 50 Ω load. 2Single Port Mode (PLL disabled, DIV0 = 1, DIV1 = 0, data on Port 1). Specifications subject to change without notice. REV. B –3–

AD9755 DIGITAL SPECIFICATIONS (T to T , AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted.) MIN MAX OUTFS Parameter Min Typ Max Unit DIGITAL INPUTS Logic 1 2.1 3 V Logic 0 0 0.9 V Logic 1 Current –10 +10 µA Logic 0 Current –10 +10 µA Input Capacitance 5 pF Input Setup Time (t ), T = 25°C 1.0 0.5 ns S A Input Hold Time (t ), T = 25°C 1.0 0.5 ns H A Latch Pulsewidth (t ), T = 25°C 1.5 ns LPW A Input Setup Time (t PLLVDD = 0 V), T = 25°C –1.0 –1.5 ns S, A Input Hold Time (t PLLVDD = 0 V), T = 25°C 2.5 1.7 ns H, A CLK to PLLLOCK Delay (t , PLLVDD = 0 V), T = 25°C 3.5 4.0 ns D A Latch Pulsewidth (t PLLVDD = 0 V), T = 25°C 1.5 ns LPW A PLLOCK (V ) 3.0 V OH PLLOCK (V ) 0.3 V OL CLK INPUTS Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V Min CLK Frequency* 6.25 MHz *Min CLK Frequency only applies when using internal PLL. When PLL is disabled, there is no minimum CLK frequency. Specifications subject to change without notice. –4– REV. B

AD9755 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect To Min Max Unit AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM –0.3 +3.9 V AVDD, DVDD, CLKVDD, PLLVDD AVDD, DVDD, CLKVDD, PLLVDD –3.9 +3.9 V ACOM, DCOM, CLKCOM, PLLCOM ACOM, DCOM, CLKCOM, PLLCOM –0.3 +0.3 V REFIO, REFLO, FSADJ ACOM –0.3 AVDD + 0.3 V I , I ACOM –1.0 AVDD + 0.3 V OUTA OUTB Digital Data Inputs (DB13 to DB0) DCOM –0.3 DVDD + 0.3 V CLK+/CLK–, PLLLOCK CLKCOM –0.3 CLKVDD + 0.3 V DIV0, DIV1, RESET CLKCOM –0.3 CLKVDD + 0.3 V LPF PLLCOM –0.3 PLLVDD + 0.3 V Junction Temperature 150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) 300 °C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. t t S H PORT 1 DATA X DATA IN ORDERING GUIDE PORT 2 DATA Y Temperature Package Package INPUT CLK Model Range Description Option (PLL ENABLED) AD9755AST –40°C to +85°C 48-Lead LQFP ST-48 tLPW tPD AD9755ASTRL –40°C to +85°C 48-Lead LQFP ST-48 IOUTA OR IOUTB DATA X DATA Y AD9755-EB Evaluation Board t PD THERMAL CHARACTERISTIC Figure 1.I/O Timing Thermal Resistance 48-Lead LQFP θ = 91°C/W JA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9755 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5–

AD9755 PIN CONFIGURATION CLKVDD PLLVDD LPF CLKCOM ACOM IOUTAIOUTBAVDD FSADJ REFIO DIV1 DIV0 48 47 46 45 44 43 42 41 40 39 38 37 RESET 1 36 P2B0–LSB PIN 1 CLK+ 2 IDENTIFIER 35 P2B1 CLK– 3 34 P2B2 DCOM 4 33 P2B3 DVDD 5 32 P2B4 AD9755 PLLLOCK 6 31 P2B5 MSB–P1B13 7 (NToOt Pto V SIEcaWle) 30 P2B6 P1B12 8 29 P2B7 P1B11 9 28 P2B8 P1B10 10 27 P2B9 P1B9 11 26 P2B10 P1B8 12 25 P2B11 13 14 15 16 17 18 19 20 21 22 23 24 7 6 5 4 3 2 1 0 D M 3 2 P1B P1B P1B P1B P1B P1B P1B –P1B DVD DCO P2B1 P2B1 B – S B L S M PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 RESET Internal Clock Divider Reset 2 CLK+ Differential Clock Input 3 CLK– Differential Clock Input 4, 22 DCOM Digital Common 5, 21 DVDD Digital Supply Voltage 6 PLLLOCK Phase-Locked Loop Lock Indicator Output 7–20 P1B13–P1B0 Data Bits P1B13 to P1B0, Port 1 23–36 P2B13–P2B0 Data Bits P2B13 to P2B0, Port 2 37, 38 DIV0, DIV1 Control Inputs for PLL and Input Port Selector Mode; see Tables I and II for details. 39 REFIO Reference Input/Output 40 FSADJ Full-Scale Current Output Adjust 41 AVDD Analog Supply Voltage 42 I Differential DAC Current Output OUTB 43 I Differential DAC Current Output OUTA 44 ACOM Analog Common 45 CLKCOM Clock and Phase-Locked Loop Common 46 LPF Phase-Locked Loop Filter 47 PLLVDD Phase-Locked Loop Supply Voltage 48 CLKVDD Clock Supply Voltage –6– REV. B

AD9755 TERMINOLOGY Power Supply Rejection Linearity Error (Also Called Integral Nonlinearity or INL) The maximum change in the full-scale output as the supplies Linearity error is defined as the maximum deviation of the actual are varied from minimum to maximum specified voltages. analog output from the ideal output, determined by a straight Settling Time line drawn from zero to full scale. The time required for the output to reach and remain within a Differential Nonlinearity (DNL) specified error band around its final value, measured from the DNL is the measure of the variation in analog value, normalized start of the output transition. to full scale, associated with a 1 LSB change in digital input code. Glitch Impulse Monotonicity Asymmetrical switching times in a DAC cause undesired output A D/A converter is monotonic if the output either increases or transients that are quantified by a glitch impulse. It is specified remains constant as the digital input increases. as the net area of the glitch in pV-s. Offset Error Spurious-Free Dynamic Range The deviation of the output current from the ideal of zero is The difference, in dB, between the rms amplitude of the output called offset error. For I , 0 mA output is expected when the signal and the peak spurious signal over the specified bandwidth. OUTA inputs are all 0s. For I , 0 mA output is expected when the OUTB Total Harmonic Distortion (THD) inputs are all 1s. THD is the ratio of the rms sum of the first six harmonic com- Gain Error ponents to the rms value of the measured fundamental. It is The difference between the actual and ideal output span. The expressed as a percentage or in decibels (dB). actual span is determined by the output when all inputs are set Signal-to-Noise Ratio (SNR) to 1s, minus the output when all inputs are set to 0s. SNR is the ratio of the rms value of the measured output signal Output Compliance Range to the rms sum of all other spectral components below the The range of allowable voltage at the output of a current-output Nyquist frequency, excluding the first six harmonics and dc. DAC. Operation beyond the maximum compliance limits may The value for SNR is expressed in decibels. cause either output stage saturation or breakdown, resulting in Adjacent Channel Power Ratio (ACPR) nonlinear performance. A ratio in dBc between the measured power within a channel Temperature Drift relative to its adjacent channel. Specified as the maximum change from the ambient (25°C) value to the value at either T or T . For offset and gain drift, the MIN MAX drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. 3.0V TO 3.6V MINI TO ROHDE & DVDD AVDD CIRCUITS SCHWARZ REF1IO.2V REF SPMOUORSC CEU ARRRREANYT SDSWBEITG0C MTHOEE NDSTB FE1OD3R DAC IIOOUUTTAB 50(cid:1) T1-1T FSASPNEEAACL3TY0RZEURM 0.1(cid:2)F FSADJ PLLVDD R2SkE(cid:1)T DAC LATCH PLL CRELKSVEDTD 50(cid:1) 2–1 MUX CIRCUITRY LPF AD9755 CLKCOM DCOM DIV0 PORT 1 LATCH PORT 2 LATCH DIV1 ACOM DB0 – DB13 DB0 – DB13 CLK+ CLK– PLLLOCK DIGITAL DATA INPUTS 1k(cid:1) 3.0V TO 3.6V TEKTRONIX DG2020 MINI 1k(cid:1) OR CIRCUITS AWG2021 w/OPTION 4 T1-1T LECROY 9210 PLL ENABLED HSIPG8N6A44L PULSE GENERATOR PLL DISABLED GENERATOR (FOR DATA RETIMING) Figure 2.Basic AC Characterization Test Setup REV. B –7–

AD9755–Typical Performance Characteristics 90 90 90 0dBmFS 80 80 0dBmFS 80 –6dBmFS Bc) 70 Bc) 70 –6dBmFS Bc) 70 R (d R (d R (d –6dBmFS D –12dBmFS D D SF 60 SF 60 SF 60 –12dBmFS –12dBmFS 0dBmFS 50 50 50 40 40 40 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 fOUT (MHz) fOUT (MHz) fOUT (MHz) TPC 1.Single-Tone SFDR vs. f @ TPC 2.Single-Tone SFDR vs. f @ TPC 3.Single-Tone SFDR vs. f @ OUT OUT OUT f = 65 MSPS; Single Port Mode f = 200 MSPS f = 300 MSPS DAC DAC DAC 90 90 90 SFDR NEAR CARRIERS 65MSPS (2F1-F2, 2F2-F1) SFDR CLOSE TO CARRIERS 80 80 80 (2F1-F2, 2F2-F1) 200MSPS Bc) 70 Bc) 70 Bc) 70 R (d R (d R (d D D SFDR OVER D SF 60 SF 60 NYQUIST BAND SF 60 50 300MSPS 50 50 SFDR OVER NYQUIST BAND 40 40 40 0 20 40 60 80 100 120 140 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 fOUT (MHz) fOUT (MHz) fOUT (MHz) TPC 4.SFDR vs. f @ 0 dBFS TPC 5.Two-Tone IMD vs. f @ TPC 6.Two-Tone IMD vs. f @ OUT OUT OUT f = 200 MSPS, 1 MHz Spacing f = 300 MSPS, 1 MHz Spacing DAC DAC between Tones, 0 dBFS between Tones, 0 dBFS 90 90 90 11.82MHz @ 130MSPS 26MHz @ 130MSPS 11.82/12.82MHz 80 80 80 @ 130MSPS Bc) 70 18.18MHz @ 200MSPS Bc) 70 Bc) 70 R (d R (d 40MHz @ 200MSPS R (d 18.18/19.18MHz SFD 60 SFD 60 SFD 60 27.27/28.27MHz @ 200MSPS @ 300MSPS 27.27MHz @ 300MSPS 50 50 50 60MHz @ 300MSPS 40 40 40 –16 –14 –12 –10 –8 –6 –4 –2 0 –16 –14 –12 –10 –8 –6 –4 –2 0 –20–18–16–14–12 –10 –8 –6 –4 –2 0 AOUT (dB) AOUT (dBm) AOUT (dBm) TPC 7.Single-Tone SFDR vs. A TPC 8.Single-Tone SFDR vs. A TPC 9.Two-Tone IMD (Third Order OUT OUT @ fOUT = fDAC/11 @ fOUT = fDAC/5 Products) vs. AOUT @ fOUT = fDAC/11 –8– REV. B

AD9755 90 90 90 40MHz/41MHz 11.82MHz/12.82MHz @ 200MSPS @ 130MSPS 80 80 2@6M 1H3z0/M27SMPHSz 80 2@6M 1H3z0/M27SMPHSz Bc) 70 Bc) 70 Bc) 70 R (d 18.1@8M 2H0z0/M19S.1P8SMHz R (d 60MHz/61MHz R (d SFD 60 SFD 60 @ 300MSPS SFD 60 40MHz/41MHz @ 200MSPS 27.27MHz/28.27MHz 50 @ 300MSPS 50 50 60MHz/61MHz @ 300MSPS 40 40 40 –20–18–16–14–12 –10 –8 –6 –4 –2 0 –20–18–16–14–12 –10 –8 –6 –4 –2 0 –20–18–16–14–12 –10 –8 –6 –4 –2 0 AOUT (dBm) AOUT (dBm) AOUT (dBm) TPC 10. Two-Tone IMD (to Nyquist) TPC 11.Two-Tone IMD (Third Order TPC 12.Two-Tone IMD (to Nyquist) vs. AOUT @ fOUT = fDAC/11 Products) vs. AOUT @ fOUT = fDAC/5 vs. AOUT @ fOUT = fDAC/5 90 75 80 85 70 75 80 70 65 10MHz IOUTFS = 20mA SINAD (dBm) 776055 SFDR (dBc) 6505 IOUTFS = 10mA SFDR (dBc) 665505 40MHz 80MHz 50 60 50 IOUTFS = 5mA 55 45 45 120MHz 50 40 40 50 100 150 200 250 300 0 20 40 60 80 100 120 140 160 –50 –30 –10 10 30 50 70 90 fDAC (MHz) fOUT (MHz) TEMPERATURE ((cid:3)C) TPC 13.SINAD vs. f @ f = TPC 14.SFDR vs. I , f = TPC 15.SFDR vs. Temperature, DAC OUT OUTFS DAC 10 MHz, 0 dBFS 300 MSPS @ 0 dBFS fDAC = 300 MSPS @ 0 dBFS 2.0 2 0 1.5 –10 ffDOAUCT1 = = 3 2040MMHSzPS 1.0 –20 fOUT2 = 25MHz INL (LSB)–00..550 DNL (LSB) 1 MPLITUDE (dBm) ––––34560000 ffffffOOOOOOUUUUUUTTTTTT345678 ====== 222233678901MMMMMMHHHHHHzzzzzz 0 A –70 SFDR = 58dBc –1.0 MAGNITUDE = 0dBFS –80 –1.5 –90 –2.0 –1 –100 0 20484096 6144819210240122881433616383 0 2048 6144 10240 14336 0 20 40 60 80 100 120 140 CODE 4096 8192 12288 16383 FREQUENCY (MHz) CODE TPC 16.Typical INL TPC 17.Typical DNL TPC 18.Eight-Tone SFDR @ fOUT ≈ f /11, f = 300 MSPS DAC DAC REV. B –9–

AD9755 FUNCTIONAL DESCRIPTION REFERENCE OPERATION Figure 3 shows a simplified block diagram of the AD9755. The The AD9755 contains an internal 1.20 V band gap reference. AD9755 consists of a PMOS current source array capable of This can easily be overdriven by an external reference with no providing up to 20 mA of full-scale current, I . The array is effect on performance. REFIO serves as either an input or output, OUTFS divided into 31 equal sources that make up the five most significant depending on whether the internal or an external reference is used. bits (MSBs). The next four bits, or middle bits, consist of 15 equal To use the internal reference, simply decouple the REFIO current sources whose value is 1/16th of an MSB current source. pin to ACOM with a 0.1 µF capacitor. The internal reference The remaining LSBs are a binary weighted fraction of the middle voltage will be present at REFIO. If the voltage at REFIO is bit current sources. Implementing the middle and lower bits to be used elsewhere in the circuit, an external buffer amplifier with current sources, instead of an R-2R ladder, enhances dynamic with an input bias current less than 100 nA should be used. An performance for multitone or low amplitude signals and helps example of the use of the internal reference is given in Figure 4. maintain the DAC’s high output impedance (i.e., >100 kΩ). A low impedance external reference can be applied to REFIO, as All of the current sources are switched to one or the other of the shown in Figure 5. The external reference may provide either a two outputs (i.e., I or I ) via PMOS differential current fixed reference voltage to enhance accuracy and drift performance OUTA OUTB switches. The switches are based on a new architecture that or a varying reference voltage for gain control. Note that the 0.1µF significantly improves distortion performance. This new switch compensation capacitor is not required since the internal reference architecture reduces various timing errors and provides matching is overdriven, and the relatively high input impedance of REFIO complementary drive signals to the inputs of the differential minimizes any loading of the external reference. current switches. The analog and digital sections of the AD9755 have separate REFERENCE CONTROL AMPLIFIER The AD9755 also contains an internal control amplifier that is power supply inputs (i.e., AVDD and DVDD) that can operate used to regulate the DAC’s full-scale output current, I . independently over a 3.0 V to 3.6 V range. The digital section, OUTFS The control amplifier is configured as a voltage-to-current con- which is capable of operating at a 300 MSPS clock rate, consists verter as shown in Figure 4, so that its current output, I , is of edge-triggered latches and segment decoding logic circuitry. REF determined by the ratio of V and an external resistor, R , The analog section includes the PMOS current sources, the REFIO SET as stated in Equation 4. I is applied to the segmented current associated differential switches, a 1.20 V band gap voltage REF sources with the proper scaling factor to set I , as stated in reference, and a reference control amplifier. OUTFS Equation 3. The full-scale output current is regulated by the reference The control amplifier allows a wide (10:1) adjustment span of control amplifier and can be set from 2 mA to 20 mA via an I over a 2mA to 20 mA range by setting I between external resistor, R . The external resistor, in combination OUTFS REF SET 62.5µA and 625µA. The wide adjustment span of I provides with both the reference control amplifier and voltage reference OUTFS several application benefits. The first benefit relates directly to V , sets the reference current I , which is replicated to the REFIO REF the power dissipation of the AD9755, which is proportional to segmented current sources with the proper scaling factor. The I (refer to the Power Dissipation section). The second full-scale current, I , is 32 times the value of I . OUTFS OUTFS REF benefit relates to the 20dB adjustment, which is useful for sys- tem gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency, small signal multiplying applications. 3.0V TO 3.6V VDIFF = VOUTA – VOUTB DVDD AVDD REF1IO.2V REF SPMOUORSC CEU ARRRREANYT SDSWBEITG0C MTHOEE NDSTB FE1OD3R DAC IIOOUUTTAB VOUTB RVOLOUATAD 0.1(cid:2)F R2SkE(cid:1)T FSADJ DAC LATCH PLL PCCLLLLKKVV+DDDD 5R0L(cid:1)OAD 50(cid:1) 2–1 MUX CIRCUITRY CLK– AD9755 CLKCOM DCOM RESET PORT 1 LATCH PORT 2 LATCH LPF ACOM DB0 – DB13 DB0 – DB13 DIV0DIV1PLLLOCK DIGITAL DATA INPUTS Figure 3.Simplified Block Diagram –10– REV. B

AD9755 EOXPTTEIORNNAALL AD9755 AVDD tS tH REFERENCE REFERENCE BUFFER SECTION PORT 1 DATA X 1.2V REF DATA IN REFIO ADEXDTITEIORNNAALL 0.1(cid:2)F FSADJ CSUORURRECNET PORT 2 DATA Y LOAD ARRAY IREF 2k(cid:1) CLK tLPW tPD Figure 4.Internal Reference Configuration IOUTA OR IOUTB DATA X DATA Y AD9755 AVDD 1/2 CYCLE + tPD REFERENCE Figure 7a.DAC Input Timing Requirements AVDD SECTION with PLL Active, Single Clock Cycle 1.2V REF EXTERNAL REFIO CURRENT REFERENCE FSADJ SOURCE PORT 1 DATA W DATA Y ARRAY IREF 2k(cid:1) DATA IN PORT 2 DATA X DATA Z Figure 5.External Reference Configuration CLK PLL CLOCK MULTIPLIER OPERATION The Phase-Locked Loop (PLL) is intrinsic to the operation of the XXX AD9755 in that it produces the necessary internally synchronized IOUTA OR IOUTB DATA W DATA X 2× clock for the edge-triggered latches, multiplexer, and DAC. DATA Y DATA Z With PLLVDD connected to its supply voltage, the AD9755 is in Figure 7b.DAC Input Timing Requirements PLL active mode. Figure 6 shows a functional block diagram of with PLL Active, Multiple Clock Cycles the AD9755 clock control circuitry with PLL active. The Typically, the VCO can generate outputs of 100 MHz to 400MHz. circuitry consists of a phase detector, charge pump, voltage The range control is used to keep the VCO operating within its controlled oscillator (VCO), input data rate range control, clock logic circuitry, and control input/outputs. The ÷2 logic in the designed range while allowing input clocks as low as 6.25MHz. feedback loop allows the PLL to generate the 2× clock needed for With the PLL active, logic levels at DIV0 and DIV1 determine the divide (prescaler) ratio of the range controller. Table I gives the DAC output latch. the frequency range of the input clock for the different states of Figure 7 defines the input and output timing for the AD9755 DIV0 and DIV1. with the PLL active. CLK in Figure 7 represents the clock that is generated external to the AD9755. The input data at both Table I. CLK Rates for DIV0, DIV1 Levels with PLL Active Ports 1 and 2 is latched on the same CLK rising edge. CLK may be applied as a single ended signal by tying CLK– to mid supply CLK Frequency DIV1 DIV0 Range Controller and applying CLK to CLK+, or as a differential signal applied 50 MHz–150 MHz 0 0 ÷1 to CLK+ and CLK–. 25 MHz–100 MHz 0 1 ÷2 RESET has no purpose when using the internal PLL and should 12.5 MHz–50 MHz 1 0 ÷4 be grounded. When the AD9755 is in PLL active mode, 6.25 MHz–25 MHz 1 1 ÷8 PLLLOCK is the output of the internal phase detector. When A 392 Ω resistor and 1.0 µF capacitor connected in series from locked, the lock output in this mode is Logic 1. LPF to PLLVDD are required to optimize the phase noise versus settling/acquisition time characteristics of the PLL. To obtain 392(cid:1) 1.0(cid:2)F 3.0V TO optimum noise and distortion performance, PLLVDD should be CLKVDD 3.6V (3.0V TO 3.6V) PLLLOCK LPF PLLVDD set to a voltage level similar to DVDD and CLKVDD. In general, the best phase noise performance for any PLL range DIFFE RTEON-TIAL- DEPTHEACSTEOR CHPUAMRGPE VCO control setting is achieved with the VCO operating near its SINGLE-ENDED maximum output frequency of 400MHz. AMP RANGE DIV0 CLK+ CONTROL As stated earlier, applications requiring input data rates below CLK– ((cid:4)1, 2, 4, 8) DIV1 6.25 MSPS must disable the PLL clock multiplier and provide TLOA T ICNHPUEST (cid:4)2 an external 2× reference clock. At higher data rates however, TO DAC applications already containing a low phase noise (i.e., jitter) AD9755 LATCH CLKCOM reference clock that is twice the input data rate should consider disabling the PLL clock multiplier to achieve the best SNR Figure 6.Clock Circuitry with PLL Active performance from the AD9755. Note that the SFDR performance of the AD9755 remains unaffected with or without the PLL clock multiplier enabled. REV. B –11–

AD9755 The effects of phase noise on the AD9755’s SNR performance DAC TIMING WITH PLL ACTIVE become more noticeable at higher reconstructed output frequen- As described in Figure 7, in PLL ACTIVE mode, Port 1 and cies and signal levels. Figure 8 compares the phase noise of a Port 2 input latches are updated on the rising edge of CLK. On full-scale sine wave at exactly f /4 at different data rates the same rising edge, data previously present in the input Port 2 DATA (thus carrier frequency) with the optimum DIV1, DIV0 setting. latch is written to the DAC output latch. The DAC output will update after a short propagation delay (t ). PD Following the rising edge of CLK, at a time equal to half of its 0 period, the data in the Port 1 latch will be written to the DAC output latch, again with a corresponding change in the DAC –10 output. Due to the internal PLL, the time at which the data in –20 the Port 1 and Port 2 input latches is written to the DAC latch Hz) –30 is independent of the duty cycle of CLK. When using the PLL, Bm/ –40 the external clock can be operated at any duty cycle that d Y ( –50 meets the specified input pulsewidth. T NSI –60 On the next rising edge of CLK, the cycle begins again with the E E D –70 PLL ON, fDATA = 150MSPS two input port latches being updated and the DAC output latch S being updated with the current data in the Port 2 input latch. OI –80 N –90 PLL DISABLED MODE –100 When PLLVDD is grounded, the PLL is disabled. An external PLL OFF, fDATA = 50MSPS clock must now drive the CLK inputs at the desired DAC output –110 0 1 2 3 4 5 update rate. The speed and timing of the data present at input FREQUENCY OFFSET (MHz) Ports 1 and 2 are now dependent on whether or not the AD9755 Figure 8.Phase Noise of PLL Clock Multiplier at is interleaving the digital input data, or only responding to data f = f /4 at Different f Settings with DIV0/DIV1 on a single port. Figure 10 is a functional block diagram of the OUT DATA DATA Optimized, Using R&S FSEA30 Spectrum Analyzer AD9755 clock control circuitry with the PLL disabled. SNR is partly a function of the jitter generated by the clock circuitry. As a result, any noise on PLLVDD or CLKVDD may PLLLOCK decrease the SNR at the output of the DAC. To minimize this TO DAC AD9755 LATCH potential problem, PLLVDD and CLKVDD can be connected to DVDD using an LC filter network similar to the one shown CLKIN+ CLOCK TO INPUT LOGIC in Figure 9. CLKIN– ((cid:4)1 OR (cid:4)2) LATCHES DIFFERENTIAL- TO- TO SINGLE-ENDED INTERNAL FERRITE AMP MUX BEADS PLLVDD CLKVDD 100(cid:2)F 10(cid:2)F–22(cid:2)F 0.1(cid:2)F RESET DIV0 DIV1 TTL/CMOS ELECT. TANT. CER. LOGIC CIRCUITS PLLVDD Figure 10.Clock Circuitry with PLL Disabled DIV0 and DIV1 no longer control the PLL, but are used to set CLKCOM the control on the input mux for either interleaving or non- interleaving the input data. The different modes for states of 3.3V POWER SUPPLY DIV0 and DIV1 are given in Table II. Figure 9.LC Network for Power Filtering Table II. Input Mode for DIV0, DIV1 Levels with PLL Disabled Input Mode DIV1 DIV0 Interleaved (2×) 0 0 Noninterleaved Port 1 Selected 0 1 Port 2 Selected 1 0 Not Allowed 1 1 –12– REV. B

AD9755 INTERLEAVED (2(cid:5)) MODE WITH PLL DISABLED NONINTERLEAVED MODE WITH PLL DISABLED The relationship between the internal and external clocks in this If the data at only one port is required, the AD9755 interface mode is shown in Figure 11. A clock at the output update data can operate as a simple double buffered latch with no interleaving. rate (2× the input data rate) must be applied to the CLK inputs. On the rising edge of the 1× clock, input latch 1 or 2 is updated Internal dividers then create the internal 1× clock necessary for with the present input data (depending on the state of DIV0/ the input latches. Although the input latches are updated on the DIV1). On the next rising edge, the DAC latch is updated and a rising edge of the delayed internal 1× clock, the setup-and-hold time t later, the DAC output reflects this change. Figure 13 PD times given in the Digital Specifications table are with respect to represents the AD9755 timing in this mode. the rising edge of the external 2× clock. With the PLL disabled, a load-dependent delayed version of the 1× clock is present at t t S H the PLLLOCK pin. This signal can be used to synchronize the external data. DATA IN PORT 1 OR PORT 2 t t S H 1(cid:5) CLOCK PORT 1 DATA X DATA ENTERS tLPW t DATA IN INPUT LATCHES PD ON THIS EDGE PORT 2 DATA Y IOUTA OR IOUTB XX DPOATRAT O1 UOTR EXTERNAL PORT 2 2(cid:5) CLK tLPW tPD tPD Figure 13.Timing Requirements, Noninterleaved Mode DELAYED with PLL Disabled INTERNAL 1(cid:5) CLK t D EXTERNAL DAC TRANSFER FUNCTION 1(cid:5) CLK @ PLLLOCK The AD9755 provides complementary current outputs, IOUTA and I . I provides a near full-scale current output, I , IOUTA OR IOUTB DATA X DATA Y wOhUeTnB alOl UbTitAs are high (i.e., DAC CODE = 16383) whilOeU ITFS , OUTB Figure 11.Timing Requirements, Interleaved (2×) Mode the complementary output, provides no current. The current output appearing at I and I is a function of both the with PLL Disabled OUTA OUTB input code and I , and can be expressed as OUTFS Updates to the data at input Ports 1 and 2 should be synchro- ( ) nized to the specific rising edge of the external 2× clock that I = DAC CODE 16383 ×I (1) OUTA OUTFS corresponds to the rising edge of the 1× internal clock, as shown I =(16383−DAC CODE) 16384×I (2) in Figure 11. To ensure synchronization, a Logic 1 must be OUTB OUTFS momentarily applied to the RESET pin. Doing this and return- where DAC CODE = 0 to 16383 (i.e., decimal representation). ing RESET to Logic 0 brings the 1× clock at PLLLOCK to a As mentioned previously, I is a function of the reference Logic 1. On the next rising edge of the 2× clock, the 1× clock current, I , which is nomOinUaTlFlSy set by a reference voltage, will go to Logic 0. On the second rising edge of the 2× clock, the V , anRdEF external resistor R . It can be expressed as 1× clock (PLLLOCK) will again go to Logic 1, as well as update REFIO SET I =32×I (3) the data in both of the input latches. The details of this are OUTFS REF shown in Figure 12. whereI =V R (4) REF REFIO SET The two current outputs typically drive a resistive load directly DATA ENTERS INPUT LATCHES or via a transformer. If dc coupling is required, I and I ON THESE EDGES OUTA OUTB should be directly connected to matching resistive loads, R , LOAD RESET that are tied to analog common, ACOM. Note that R may LOAD represent the equivalent load resistance seen by I or I OUTA OUTB PLLLOCK as would be the case in a doubly terminated 50Ω or 75 Ω cable. The single-ended voltage output appearing at the I and OUTA EXTERNAL I nodes is simply 2(cid:5) CLOCK OUTB V =I ×R (5) tRS = 0.2ns tRH = 1.2ns V OOUUTTAB =IOOUUTTAB ×RLLOOAADD (6) Note that the full-scale value of V and V should not Figure 12.Reset Function Timing with PLL Disabled OUTA OUTB exceed the specified output compliance range to maintain specified For proper synchronization, sufficient delay must be present distortion and linearity performance. between the time RESET goes low and the rising edge of the 2× ( ) V = I −I ×R (7) clock. RESET going low must occur either at least t ns before DIFF OUTA OUTB LOAD RS the rising edge of the 2× clock, or tRH ns afterwards. In the first Substituting the values of IOUTA, IOUTB, and IREF, VDIFF can be case, the immediately occurring CLK rising edge will cause expressed as {( ) } PLLLOCK to go low. In the second case, the next CLK rising V = 2DAC CODE −16383 16384 × DIFF edge will toggle PLLLOCK. ( ) (8) 32R R ×V LOAD SET REFIO REV. B –13–

AD9755 Equations 7 and 8 highlight some of the advantages of operating I and I also have a negative and positive voltage OUTA OUTB the AD9755 differentially. First, the differential operation will compliance range that must be adhered to in order to achieve help cancel common-mode error sources associated with I optimum performance. The negative output compliance range OUTA and I such as noise, distortion, and dc offsets. Second, the of –1.0V is set by the breakdown limits of the CMOS process. OUTB differential code-dependent current and subsequent voltage, V , Operation beyond this maximum limit may result in a breakdown DIFF is twice the value of the single-ended voltage output (i.e., V of the output stage and affect the reliability of the AD9755. OUTA or V ), thus providing twice the signal power to the load. OUTB The positive output compliance range is slightly dependent on Note that the gain drift temperature performance for a single- the full-scale output current, I . It degrades slightly from its OUTFS ended (V and V ) or differential output (V ) of the nominal 1.25 V for an I = 20 mA to 1.00 V for an I = OUTA OUTB DIFF OUTFS OUTFS AD9755 can be enhanced by selecting temperature tracking 2 mA. The optimum distortion performance for a single-ended resistors for R and R due to their ratiometric relation- or differential output is achieved when the maximum full-scale LOAD SET ship, as shown in Equation 8. signal at I and I does not exceed 0.5 V. Applications OUTA OUTB requiring the AD9755’s output (i.e., V and/or V ) to OUTA OUTB ANALOG OUTPUTS extend its output compliance range should size R accordingly. LOAD The AD9755 produces two complementary current outputs, Operation beyond this compliance range will adversely affect the I and I , that may be configured for single-ended or AD9755’s linearity performance and subsequently degrade its OUTA OUTB differential operation. I and I can be converted into distortion performance. OUTA OUTB complementary single-ended voltage outputs, V and V , OUTA OUTB via a load resistor, R , as described by Equations 5 through DIGITAL INPUTS LOAD 8 in the DAC Transfer Function section. The differential volt- The AD9755’s digital inputs consist of two channels of 14 data age, V , existing between V and V , can also be input pins each and a pair of differential clock input pins. The DIFF OUTA OUTB converted to a single-ended voltage via a transformer or differen- 14-bit parallel data inputs follow standard straight binary coding tial amplifier configuration. The ac performance of the AD9755 where DB13 is the most significant bit (MSB) and DB0 is the is optimum and is specified using a differential transformer- least significant bit (LSB). I produces a full-scale output OUTA coupled output in which the voltage swing at I and I is current when all data bits are at Logic 1. I produces a comple- OUTA OUTB OUTB limited to ±0.5V. If a single-ended unipolar output is desirable, mentary output with the full-scale current split between the two I should be selected as the output, with I grounded. outputs as a function of the input code. OUTA OUTB The distortion and noise performance of the AD9755 can be The digital interface is implemented using an edge-triggered enhanced when it is configured for differential operation. The master slave latch. With the PLL active or disabled, the DAC common-mode error sources of both I and I can be output is updated twice for every input latch rising edge, as OUTA OUTB significantly reduced by the common-mode rejection of a trans- shown in Figures 7 and 11. The AD9755 is designed to support former or differential amplifier. These common-mode error an input data rate as high as 150 MSPS, giving a DAC output sources include even-order distortion products and noise. The update rate of 300 MSPS. The setup-and-hold times can also be enhancement in distortion performance becomes more significant varied within the clock cycle as long as the specified minimum as the frequency content of the reconstructed waveform increases. times are met. Best performance is typically achieved when the This is due to the first order cancellation of various dynamic input data transitions on the falling edge of a 50% duty cycle clock. common-mode distortion mechanisms, digital feedthrough, The digital inputs are CMOS compatible with logic thresholds, and noise. V , set to approximately half the digital positive THRESHOLD Performing a differential-to-single-ended conversion via a supply (DVDD) or transformer also provides the ability to deliver twice the recon- V =DVDD 2(±20%) structed signal power to the load (i.e., assuming no source THRESHOLD termination). Since the output currents of I and I are The internal digital circuitry of the AD9755 is capable of oper- OUTA OUTB complementary, they become additive when processed differen- ating over a digital supply range of 3.0 V to 3.6 V. As a result, tially. A properly selected transformer will allow the AD9755 to the digital inputs can also accommodate TTL levels when DVDD provide the required power and voltage levels to different loads. is set to accommodate the maximum high level voltage of the Refer to Applying the AD9755 section for examples of various TTL drivers V (max). A DVDD of 3.0 V to 3.6 V typically OH output configurations. ensures proper compatibility with most TTL logic families. Figure 14 shows the equivalent digital input circuit for the data The output impedance of I and I is determined by the OUTA OUTB and clock inputs. equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100kΩ in parallel with DVDD 5 pF. It is also slightly dependent on the output voltage (i.e., V and V ) due to the nature of a PMOS device. As a OUTA OUTB result, maintaining I and/or I at a virtual ground via an OUTA OUTB DIGITAL I-V op amp configuration will result in the optimum dc linearity. INPUT Note that the INL/DNL specifications for the AD9755 are measured with I and I maintained at virtual ground via OUTA OUTB an op amp. Figure 14.Equivalent Digital Input –14– REV. B

AD9755 The AD9755 features a flexible differential clock input operating INPUT CLOCK AND DATA TIMING RELATIONSHIP from separate supplies (i.e., CLKVDD, CLKCOM) to achieve SNR in a DAC is dependent on the relationship between the optimum jitter performance. The two clock inputs, CLK+ and position of the clock edges and the point in time at which the CLK–, can be driven from a single-ended or differential clock input data changes. The AD9755 is rising edge triggered, and so source. For single-ended operation, CLK+ should be driven by exhibits SNR sensitivity when the data transition is close to this a logic source while CLK– should be set to the threshold voltage edge. In general, the goal when applying the AD9755 is to make of the logic source. This can be done via a resistor divider/ the data transition close to the falling clock edge. This becomes capacitor network, as shown in Figure 15a. For differential opera- more important as the sample rate increases. Figure 16 shows tion, both CLK+ and CLK– should be biased to CLKVDD/2 the relationship of SNR to clock placement with different sample via a resistor divider network, as shown in Figure 15b. rates. Note that the setup-and-hold times implied in Figure 16 appear to violate the maximums stated in the Digital Specifica- Because the output of the AD9755 can be updated at up to tions table. The variation in Figure 16 is due to the skew present 300 MSPS, the quality of the clock and data input signals are between data bits inherent in the digital data generator used to important in achieving the optimum performance. The drivers perform these tests. Figure 16 is presented to show the effects of of the digital data interface circuitry should be specified to violating setup-and-hold times, and to show the insensitivity of the meet the minimum setup-and-hold times of the AD9755 as AD9755 to clock placement when data transitions fall outside of well as its required min/max input logic level thresholds. the so-called “bad window.” The setup-and-hold times stated in Digital signal paths should be kept short and run lengths matched the Digital Specifications table were measured on a bit-by-bit basis, to avoid propagation delay mismatch. Inserting a low value therefore eliminating the skew present in the digital data generator. resistor network (i.e., 20Ω to 100Ω) between the AD9755 digi- At higher data rates, it becomes very important to account for the tal inputs and driver outputs may be helpful in reducing any skew in the input digital data when defining timing specifications. overshooting and ringing at the digital inputs that contribute to data feedthrough. For longer run lengths and high data update 80 rates, strip line techniques with proper termination resistors should be considered to maintain “clean” digital inputs. 70 The external clock driver circuitry should provide the AD9755 60 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges help minimize any c) 50 jwitatveer ftohramt .m Tahnuisfe, stthse ictsloeclfk a isn ppuhta sseh onuolids eb eo nd raiv reenc obny stthreu cfatesdtest NR (dB 40 S logic family suitable for the application. 30 Note that the clock input could also be driven via a sine wave 20 that is centered around the digital threshold (i.e., DVDD/2) and meets the min/max logic threshold. This typically results in a 10 slight degradation in the phase noise, which becomes more 0 noticeable at higher sampling rates and output frequencies. Also, –3 –2 –1 0 1 2 3 at higher sampling rates, the 20% tolerance of the digital logic TIME OF DATA TRANSITION RELATIVE TO PLACEMENT OF threshold should be considered since it affects the effective clock CLK RISING EDGE (ns), fOUT = 10MHz, fDAC = 300MHz duty cycle and, subsequently, cuts into the required data setup- Figure 16.SNR vs. Time of Data Transition Relative to and-hold times. Clock Rising Edge RSERIES AD9755 POWER DISSIPATION CLK+ The power dissipation, PD, of the AD9755 is dependent on sev- eral factors that include the power supply voltages (AVDD and CLKVDD DVDD), the full-scale current output I , the update rate OUTFS f , and the reconstructed digital input waveform. The power 0.1(cid:2)F CLK– CLOCK dissipation is directly proportional to the analog supply current, VTHRESHOLD CLKCOM IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to I , as shown in Figure 17, and is insensitive OUTFS to f . Conversely, I is dependent on both the digital Figure 15a.Single-Ended Clock Interface CLOCK DVDD input waveform, f , and digital supply DVDD. Figure 18 CLOCK shows I as a function of the ratio (f /f ) for various DVDD OUT DAC 0.1(cid:2)F AD9755 update rates. In addition, Figure 19 shows the effect that the speed of f has on the PLLVDD current, given the PLL CLK+ DAC 0.1(cid:2)F divider ratio. CLKVDD 0.1(cid:2)F CLK– CLKCOM Figure 15b.Differential Clock Interface REV. B –15–

AD9755 APPLYING THE AD9755 40 OUTPUT CONFIGURATIONS 35 The following sections illustrate some typical output configurations for the AD9755. Unless otherwise noted, it is assumed that I 30 OUTFS is set to a nominal 20 mA. For applications requiring the optimum 25 dynamic performance, a differential output configuration is mA) suggested. A differential output configuration may consist of (D 20 either an RF transformer or a differential op amp configuration. D AV The transformer configuration provides the optimum high I 15 frequency performance and is recommended for any application 10 allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, 5 signal gain, and/or level-shifting within the bandwidth of the chosen op amp. 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 A single-ended output is suitable for applications requiring a IOUTFS (mA) unipolar voltage output. A positive unipolar output voltage will Figure 17.I vs. I AVDD OUTFS result if I and/or I are connected to an appropriately OUTA OUTB sized load resistor, R , referred to ACOM. This configuration LOAD 20 may be more suitable for a single-supply system requiring a dc- 18 coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting I or 16 OUTA I into a negative unipolar voltage. This configuration provides OUTB 14 the best dc linearity since I or I is maintained at a virtual 300MSPS OUTA OUTB A) 12 ground. Note that IOUTA provides slightly better performance m (D10 than IOUTB. VD 200MSPS ID 8 DIFFERENTIAL COUPLING USING A TRANSFORMER 6 100MSPS An RF transformer can be used to perform a differential-to- 50MSPS single-ended signal conversion, as shown in Figure 20. A 4 25MSPS differentially-coupled transformer output provides the optimum 2 distortion performance for output signals whose spectral content 0 lies within the transformer’s pass band. An RF transformer such 0.001 0.01 0.1 1 as the Mini-Circuits T1–1T provides excellent rejection of RATIO (fOUT/fDAC) common-mode distortion (i.e., even-order harmonics) and Figure 18.I vs. f /f Ratio DVDD OUT DAC noise over a wide frequency range. When I and I are OUTA OUTB terminated to ground with 50 Ω, this configuration provides 10 0dBm power to a 50 Ω load on the secondary with a DAC full- DIV SETTING 11 9 scale current of 20 mA. A 2:1 transformer such as the Coilcraft DIV SETTING 10 8 WB2040-PC can also be used in a configuration in which IOUTA DIV SETTING 01 and I are terminated to ground with 75 Ω. This configuration 7 OUTB improves load matching and increases power to 2 dBm into a mA) 6 50 Ω load on the secondary. Transformers with different imped- (DD 5 ance ratios may also be used for impedance matching purposes. V LL_ 4 DIV SETTING 00 Note that the transformer provides ac coupling only. P The center tap on the primary side of the transformer must be 3 connected to ACOM to provide the necessary dc current path for 2 both I and I . The complementary voltages appearing OUTA OUTB 1 at I and I (i.e., V and V ) swing symmetrically OUTA OUTB OUTA OUTB around ACOM and should be maintained with the specified 0 0 25 50 75 100 125 150 175 200 225 250 275 300 output compliance range of the AD9755. A differential resistor, fDAC (MHz) R , may be inserted into applications where the output of the DIFF Figure 19.PLLV vs. f transformer is connected to the load, R , via a passive DD DAC LOAD reconstruction filter or cable. R is determined by the DIFF transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. –16– REV. B

AD9755 SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT AD9755 MINI-TC1IR-1CTUITS Figure 23 shows the AD9755 configured to provide a unipolar IOUTA output range of approximately 0V to 0.5 V for a doubly termi- RLOAD nated 50Ω cable since the nominal full-scale current, I , of OUTFS IOUTB 20 mA flows through the equivalent RLOAD of 25Ω. In this case, R represents the equivalent load resistance seen by I or LOAD OUTA I . The unused output (I or I ) can be connected to OUTB OUTA OUTB ACOM directly or via a matching R . Different values of Figure 20.Differential Output Using a Transformer LOAD I and R can be selected as long as the positive compli- OUTFS LOAD ance range is adhered to. One additional consideration in this DIFFERENTIAL COUPLING USING AN OP AMP mode is the integral nonlinearity (INL), as discussed in the An op amp can also be used to perform a differential-to-single- Analog Outputs section. For optimum INL performance, ended conversion, as shown in Figure 21. The AD9755 is the single-ended, buffered voltage output configuration is configured with two equal load resistors, R , of 25 Ω. The LOAD suggested. differential voltage developed across I and I is converted OUTA OUTB to a single-ended signal via the differential op amp configuration. Afonrm opintigo na arle caal ppaoclieto irn c aa nlo bwe- ipnasstsa lflieldte ar.c rToshse IaOdUdTAit iaonnd oIfO UthTiBs, AD9755 IOUTFS = 20mA VOUTA = 0V TO 0.5V IOUTA capacitor also enhances the op amp’s distortion performance by 50(cid:1) 50(cid:1) preventing the DAC’s high slewing output from overloading the IOUTB op amp’s input. 25(cid:1) 500(cid:1) Figure 23.0 V to 0.5 V Unbuffered Voltage Output AD9755 225(cid:1) IOUTA SINGLE-ENDED BUFFERED VOLTAGE OUTPUT AD8047 225(cid:1) Figure 24 shows a buffered single-ended output configuration in IOUTB COPT which the op amp performs an I–V conversion on the AD9755 500(cid:1) output current. The op amp maintains I (or I ) at a OUTA OUTB 25(cid:1) 25(cid:1) virtual ground, thus minimizing the nonlinear output impedance effect on the DAC’s INL performance as discussed in the Analog Outputs section. Although this single-ended configuration Figure 21.DC Differential Coupling Using an Op Amp typically provides the best dc linearity performance, its ac distor- The common-mode rejection of this configuration is typically tion performance at higher DAC update rates may be limited by determined by the resistor matching. In this circuit, the differen- the op amp’s slewing capabilities. The op amp provides a negative tial op amp circuit using the AD8047 is configured to provide unipolar output voltage and its full-scale output voltage is simply some additional signal gain. The op amp must operate from a the product of R and I . The full-scale output should be set FB OUTFS dual supply since its output is approximately ±1.0V. A high within the op amp’s voltage output swing capabilities by scaling speed amplifier capable of preserving the differential performance I and/or R . An improvement in ac distortion performance OUTFS FB of the AD9755, while meeting other system level objectives (i.e., may result with a reduced I , since the signal current the op OUTFS cost, power), should be selected. The op amp’s differential gain, amp will be required to sink will subsequently be reduced. its gain setting resistor values, and full-scale output swing capa- bilities should all be considered when optimizing this circuit. COPT The differential circuit shown in Figure 22 provides the nec- essary level-shifting required in a single supply system. In this 2R0F0B(cid:1) case, AVDD, which is the positive analog supply for both the AD9755 AD9755 and the op amp, is also used to level-shift the differ- IOUTA ential output of the AD9755 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. IOUTB VOUT = IOUTFS (cid:5) RFB 200(cid:1) 500(cid:1) AD9755 225(cid:1) Figure 24.Unipolar Buffered Voltage Output IOUTA AD8041 225(cid:1) IOUTB COPT 1k(cid:1) AVDD 25(cid:1) 25(cid:1) 500(cid:1) Figure 22.Single-Supply DC Differential Coupled Circuit REV. B –17–

AD9755 POWER AND GROUNDING CONSIDERATIONS, POWER mixing effect that can modulate low frequency power supply SUPPLY REJECTION noise to higher frequencies. Worst-case PSRR for either one of Many applications seek high speed and high performance under the differential DAC outputs occurs when the full-scale current is less than ideal operating conditions. In these applications, the directed toward that output. As a result, the PSRR measurement implementation and construction of the printed circuit board is in Figure 25 represents a worst-case condition in which the as important as the circuit design. Proper RF techniques must digital inputs remain static and the full-scale output current of be used for device selection, placement, and routing, as well as 20 mA is directed to the DAC output being measured. power supply bypassing and grounding to ensure optimum An example serves to illustrate the effect of supply noise on the performance. Figures 34 to 41 illustrate the recommended analog supply. Suppose a switching regulator with a switching printed circuit board ground, power, and signal plane layouts frequency of 250 kHz produces 10 mV rms of noise and, for that are implemented on the AD9755 evaluation board. simplicity sake (i.e., ignore harmonics), all of this noise is con- One factor that can measurably affect system performance is the centrated at 250 kHz. To calculate how much of this undesired ability of the DAC output to reject dc variations or ac noise noise will appear as current noise superimposed on the DAC’s superimposed on the analog or digital dc power distribution. full-scale current, I , one must determine the PSRR in dB OUTFS This is referred to as the Power Supply Rejection Ratio. For dc using Figure 25 at 250 kHz. To calculate the PSRR for a given variations of the power supply, the resulting performance of the R , such that the units of PSRR are converted from A/V to LOAD DAC directly corresponds to a gain error associated with the V/V, adjust the curve in Figure 25 by the scaling factor 20 × Log DAC’s full-scale current, I . AC noise on the dc supplies is (R ). For instance, if R is 50 Ω, the PSRR is reduced by OUTFS LOAD LOAD common in applications where the power distribution is generated 34 dB, i.e., PSRR of the DAC at 250 kHz, which is 85 dB in by a switching power supply. Typically, switching power supply Figure 25, becomes 51 dB V /V . OUT IN noise occurs over the spectrum from tens of kHz to several MHz. Proper grounding and decoupling should be a primary objective The PSRR versus frequency of the AD9755 AVDD supply over in any high speed, high resolution system. The AD9755 features this frequency range is shown in Figure 25. separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. 85 In general, AVDD, the analog supply, should be decoupled to 80 ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled 75 to DCOM as close to the chip as physically possible. 70 For those applications that require a single 3.3 V supply for both dB)65 the analog and digital supplies, a clean analog supply may be R ( generated using the circuit shown in Figure 26. The circuit SR60 consists of a differential LC filter with separate power supply and P 55 return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. 50 45 FERRITE BEADS 40 AVDD 0 2 4 6 8 10 12 100(cid:2)F 10(cid:2)F-22(cid:2)F 0.1(cid:2)F FREQUENCY (MHz) TTL/CMOS ELECT. TANT. CER. LOGIC CIRCUITS ACOM Figure 25.Power Supply Rejection Ratio Note that the units in Figure 25 are given in units of (amps out/ volts in). Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. 3.3V The voltage noise on AVDD thus is added in a nonlinear manner POWER SUPPLY to the desired I . Due to the relative different size of these OUT Figure 26.Differential LC Filter for a Single 3.3 V Application switches, PSRR is very code-dependent. This can produce a –18– REV. B

AD9755 APPLICATIONS A figure of merit for wideband signal synthesis is the ratio of signal QAM/PSK Synthesis power in the transmitted band to the power in an adjacent channel. Quadrature modulation (QAM or PSK) consists of two baseband In Figure 28, the adjacent channel power ratio (ACPR) at the PAM (Pulse Amplitude Modulated) data channels. Both channels output of the AD9755 is measured to be 65 dB. The limitation on are modulated by a common frequency carrier. However, the making a measurement of this type is often not the DAC but the carriers for each channel are phase-shifted 90° from each other. noise inherent in creating the digital data record using computer This orthogonality allows twice the spectral efficiency (data for a tools. To find how much this is limiting the perceived DAC given bandwidth) of digital data transmitted via AM. Receivers can performance, the signal amplitude can be reduced, as is shown be designed to selectively choose the “in phase” and “quadrature” in Figure 29. The noise contributed by the DAC will remain carriers, and then recombine the data. The recombination of the constant as the signal amplitude is reduced. When the signal QAM data can be mapped as points representing digital words amplitude is reduced to the level where the noise floor drops in a two-dimensional constellation, as shown in Figure 27. Each below that of the spectrum analyzer, ACPR will fall off at the same point, or symbol, represents the transmission of multiple bits rate that the signal level is being reduced. Under the condi- in one symbol period. tions measured in Figure 28, this point occurs in Figure 29 at –10 dBFS. This shows that the data record is actually degrading the measured ACPR by up to 10 dB. 0100 0101 0001 0000 80 0110 0111 0011 0010 70 1110 1111 1011 1010 B) d R ( 60 P C A 1100 1101 1001 1000 Figure 27.16 QAM Constellation, Gray Coded (Two 4-Level 50 PAM Signals with Orthogonal Carriers) Typically, the I and Q data channels are quadrature-modulated in the digital domain. The high data rate of the AD9755 allows 40 extremely wideband (>10 MHz) quadrature carriers to be syn- –20 –15 –10 –5 0 AMPLITUDE (dBFS) thesized at IFs of over 100 MHz. Figure 28 shows an example of a 25 MSymbol/S QAM signal, raised cosine-like pulse, Figure 29.ACPR vs. Amplitude for QAM Carrier oversampled by 8 at a data rate of 200 MSPS modulated onto a A single-channel active mixer such as the Analog Devices AD8343 25 MHz carrier and reconstructed using the AD9755. can then be used for the hop to the transmit frequency. Figure 30 shows an applications circuit using the AD9755 and the AD8343. –74.25dBm VBW 50kHz The AD8343 is capable of mixing carriers from dc to 2.5 GHz. 9.71442886MHz SWT 12.5s UNIT dBm Figure 31 shows the result of mixing the signal in Figure 28 up to –30 1 [T1] –74.25dBm A a carrier frequency of 800 MHz. ACPR measured at the output –40 9.71442886MHz of the AD8343 is shown in Figure 31 to be 60 dB. CH PWR –77.42dBm –50 ACP UP m) ACP LOW –78.88dBm B –60 –11.83dBm d L ( 1RM E –70 V 1 E E L –80 C EN –90 R E F –100 E R –110 C11 C11 –120 CU1 C0 C0 –130 START 100kHz 12.49MHz/ STOP 125MHz FREQUENCY (MHz) COMMENT A: 25 MSYMBOL, 64 QAM, CARRIER = 25MHz Figure 28.Reconstructed 64-QAM Signal at 25MHz IF REV. B –19–

AD9755 DVDD AVDD CLK+ CLK– PLLLOCK PLL/DIVIDER PORT 1 INPUT 50(cid:1) INDPAUTTA LATCHES S IOUTA 0.1(cid:2)F INPP E CH OUTP DAATC DAC 0.1(cid:2)F OUTM L PIONDRPATUT T2A LAINTPCUHTES IOUTB 50(cid:1) 68(cid:1) 68(cid:1) INPM LOIM AD9755 FSADJ LOIP RSET2 REFIO ACOM1 ACOM DCOM AD8343 ACTIVE MIXER 1.9k(cid:1) 0.1(cid:2)F 0.1(cid:2)F LOINPUT 0.1(cid:2)F M/A-COM ETC-1-1-13 WIDEBAND BALUN Figure 30.QAM Transmitter Architecture Using AD9755 and AD8343 Active Mixer –100.55dBm VBW 10kHz coding) can theoretically be achieved with an energy/symbol- 859.91983968MHz SWT 2.8s UNIT dBm to-noise (E/N ) ratio of 27.8 dB. Due to the loss and interferers –20 O 1 [T1] –100.55dBm A inherent in the wireless path, this signal-to-noise ratio must be –30 859.91983968MHz realized at the receiver to achieve the given bit error rate. CH PWR –66.52dBm –40 ACP UP –60.16dBm m) ACP LOW –6.86dBm Distortion effects on BER are much more difficult to determine B –50 1 [T2] 33.62dBm accurately. Most often in simulation, the energies of the strongest EL (d –60 2 [T2] –49.91983339.6628dMBHmz 2mA distortion components are root-sum-squared with the noise, and ENCE LEV ––7800 2 –49.91983968MHz terhaxteai mor episslu eml ta ubisco htvr ege aroetfea 6dte4 ra Qst hiAfa Mnit t wwheeirt hew aothlrles nt -BocEiassRee. oSTfF h1Daet-R 6b,,e tuihnsegin nsgao tiidhse,e iwEf /tiNlhleO R FE –90 dominate the BER calculation. E R –100 The AD9755 has a worst-case in-band SFDR of 47 dB at the CL1 CL1 –110 CU1 CU1 upper end of its frequency spectrum (see TPCs 2, 3). When C0 C0 used to synthesize high level QAM signals as described above, –120 CENTER 860MHz 11MHz/ SPAN 110MHz noise, as opposed to distortion, will dominate its performance in FREQUENCY (MHz) these applications. COMMENT A: 25 MSYMBOL, 64 QAM, CARRIER = 825MHz Figure 31.Signal of Figure 28 Mixed to Carrier 1E0 Frequency of 800 MHz Effects of Noise and Distortion on Bit Error Rate (BER) 1E–1 Y Textbook analysis of Bit Error Rate (BER) performance is gen- LIT erally stated in terms of E (energy in watts-per-symbol or ABI 1E–2 watts-per-bit) and N (spectral noise density in watts/Hz). For OB 4 QAM 16 QAM 64 QAM O R QAM signals, this performance is shown graphically in Figure 32. R P 1E–3 M represents the number of levels in each quadrature PAM signal RO R (i.e., M = 8 for 64 QAM, M = 16 for 256 QAM). Figure 32 E implies gray coding in the QAM constellation, as well as the use OL 1E–4 B of matched filters at the receiver, which is typical. The YM S horizontal axis of Figure 32 can be converted to units of energy/ 1E–5 symbol by adding to the horizontal axis 10 log of the number of bits in the desired curve. For instance, to achieve a BER of 1e-6 1E–6 with 64 QAM, an energy per bit of 20 dB is necessary. To 0 5 10 15 20 SNR/BIT (dB) calculate energy per symbol, add 10 log(6) or 7.8 dB. Therefore Figure 32.Probability of a Symbol Error for QAM 64 QAM with a BER of 1e-6 (assuming no source or channel –20– REV. B

AD9755 Pseudo Zero Stuffing/IF Mode that either the Mini-Circuits T1-1T (through-hole) or the The excellent dynamic range of the AD9755 allows its use in Coilcraft TTWB-1-B (SMT) be placed in the position of T1 applications where synthesis of multiple carriers is desired. In on the evaluation board. To evaluate the output either single- addition, the AD9755 can be used in a pseudo zero-stuffing ended or direct-coupled, remove the transformer and bridge mode, which improves dynamic range at IF frequencies. In this either BL1 or BL2. mode, data from the two input channels is interleaved to the The digital data to the AD9755 comes from two ribbon cables that DAC, which is running at twice the speed of either of the input interface to the 40-lead IDC connectors P1 and P2. Proper termi- ports. However, the data at Port 2 is held constant at midscale. nation or voltage scaling can be accomplished by installing the The effect of this is shown in Figure 33. The IF signal is the resistor pack networks RN1–RN12. RN1, R4, R7, and R10 are image, with respect to the input data rate, of the fundamental. 22 Ω DIP resistor packs and should be installed as they help reduce Normally, the sinx/x response of the DAC attenuates this image. the digital edge rates and therefore peak current on the inputs. Zero stuffing improves the passband flatness so that the image A single-ended clock can be applied via J3. By setting the SE/DIFF amplitude is closer to that of the fundamental signal. Zero stuffing labeled jumpers J2, J3, J4, and J6, the input clock can be directed can be an especially useful technique in the synthesis of IF signals. to the CLK+/CLK– inputs of the AD9755 in either a single-ended 0 or differential manner. If a differentially applied clock is desired, a Mini-Circuits T1-1T transformer should be used in the position F–10 of T2. Note that with a single-ended square wave clock input, T2 F O must be removed. A clock can also be applied via the ribbon cable LL- AMPLITUDE on Port 1 (P1), Pin 33. By inserting the EDGE jumper (JP1), this O OF IMAGE X R–20 USING clock will be applied to the CLK+ input of the AD9755. JP3 X/ ZERO STUFFING should be set in its SE position in this application to bias CLK– N AMPLITUDE OF SI–30 OWFI TIMHAOGUET to half the supply voltage. T ZERO STUFFING The AD9755’s PLL clock multiplier can be enabled by inserting C E F JP7 in the IN position. As described in the Typical Performance F E–40 Characteristics and Functional Description section, with the PLL enabled, a clock at half the output data rate should be applied as described in the last paragraph. The PLL takes care –50 0 0.5 1.0 1.5 2.0 of the internal 2× frequency multiplication and all internal timing FREQUENCY (Normalized to Input Data Rate) requirements. In this application, the PLLLOCK output indicates Figure 33.Effects of Pseudo Zero Stuffing on Spectrum when lock is achieved on the PLL. With the PLL enabled, the of AD9755 DIV0 and DIV1 jumpers (JP8 and JP9) provide the PLL divider ratio as described in Table I. EVALUATION BOARD The PLL is disabled when JP7 is in the EX setting. In this mode, The AD9755-EB is an evaluation board for the AD9755 TxDAC. a clock at the speed of the output data rate must be applied to the Careful attention to layout and circuit design, combined with clock inputs. Internally, the clock is divided by 2. For data prototyping area, allows the user to easily and effectively evaluate synchronization, a 1× clock is provided on the PLLLOCK pin the AD9755 in different modes of operation. in this application. Care should be taken to read the timing Referring to Figures 34 and 35, the AD9755’s performance requirements described earlier in the data sheet for optimum perfor- can be evaluated differentially or single-ended using either a mance. With the PLL disabled, the DIV0 and DIV1 jumpers transformer, or directly coupling the output. To evaluate the define the mode (interleaved, noninterleaved) as described in output differentially using the transformer, it is recommended Table II. REV. B –21–

AD9755 RN2 RN3 VALUE VALUE RN1 VALUE 1 1 2 P1 P1 1 1B13 1 16 P1B13 2 1B13 2 4 P1 P1 3 1B12 2 15 P1B12 3 1B12 3 6 P1 P1 5 1B11 3 14 P1B11 4 1B11 4 8 P1 P1 7 1B10 4 13 P1B10 5 1B10 5 OUT16 11114206 PPPP1111 PPPP11111119135 1111BBBB00009876 5678 1119210 PPPP1111BBBB00009876 6789 1111BBBB00009876 6789 DGND: 3,4,5J121 DVDD PLACNLEK– EDEGXET2AB 13RJ4P5WHRTESTEPT3 10 10 P1B13 MSB 50(cid:1) P1B12 CLK+ P RN5 RN6 P1B11 RN4 VALUE VALUE P1B10 RESET PLLVDD PLANE VALUE 1 1 P1B09 122802 PPP111 PPP111112791 111BBB000543 123 111654 PPP111BBB000435 234 111BBB000543 234 PPPPP11111BBBBB0000087654 111345 121110 9 8 7 6 5 4 3 2 1 444876 LPFCLKVDD R3C195.1021(cid:2)(cid:1)F NSRCPHL5OO LITNAEVENNLD:EDDDC ACTPR1EL1OD AAU NTRNOEED 24 P1 P123 1B02 4 13 P1B02 5 1B02 5 P1B03 1167 4454 26 P1 P125 1B01 5 12 P1B01 6 1B01 6 PP11BB0012 18 U1 43 IIAB 3208 PP11 PP112279 11OB0107 67 1110 PO1UBT0105 78 1O15 1B00 78 DVDDPP1LBA00N LESB 122901 AD9751/AD9753/AD9755 444210 AVDD PLANE 333264 PPP111 PPP111333531 11OO1156 8 9 OUT16 190 JP10 11OO1176190 PPPM222BSBBB111321 222234 252627282930313233343536 333987 15CR001p3(cid:1)0F ORP10T 51RC002(cid:1)p9F 38 P1 P137 RN8 RN9 P2B10 40 P1 P139 VARLNU7E 1VALUE 1VALUE PP22BB0098 BL1 IOJU5T 24 PP22 PP22 13 22BB1123 12 1165 PP22BB1123 23 22BB1132 23 PPP222BBB000765 3 T1 4 12 6 P2 P2 5 2B11 3 14 P2B11 4 2B11 4 P2B04 2 8 P2 P2 7 2B10 4 13 P2B10 5 2B10 5 PP22BB0032 1 P 6 10 P2 P2 9 2B09 5 12 P2B09 6 2B09 6 P2B01 S 2B08 6 11 P2B08 7 7 P2B00 LSB TP1 12 P2 P211 2B07 7 10 P2B07 8 2B08 8 FSADJ WHT 1.9R11k(cid:1) BL2 14 P2 P213 2B07 16 P2 P215 2B06 8 9 P2B06 190 2B06 190 NOTES REFIOTPW2HT 0C.11(cid:2)2F 1. ALL DIGITAL INPUTS FROM RN1–RN12 MUST BE OF EQUAL LENGTH. 2. ALL DECOUPLING CAPS TO BE LOCATED JP8 RN11 RN12 AS CLOSE AS POSSIBLE TO DUT, 1 3 VALUE VALUE PREFERABLY UNDER DUT ON BOTTOM A B VRANL1U0E 1 1 SIGNAL LAYER. DIV1 2 1280PP22 PP221179 22BB0054 12 1165 PP22BB0045 23 22BB0054 23 3 4 .. CCBDOROIEENTLATNEOTECEMCT RT PS ILGCIGAN BNNDEAEST LC WU LANEAPDEYAENECR RLIT .ADOYURET R WUSIST 2IHN A G0N.0D0 73". 1 AJP9B 3 AVDD_PLANE 22P2 P221 2B03 3 14 P2B03 4 2B03 4 DIV0 2 24P2 P223 2B02 4 13 P2B02 5 2B02 5 26P2 P225 2B01 5 12 P2B01 6 2B01 6 28P2 P227 2B00 6 11 P2B00 7 2B00 7 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP12 30P2 P229 7 10 P2OUT15 8 2OUT15 8 BLK BLK BLK BLK BLK BLK BLK BLK 32P2 P231 8 9 P2OUT16 9 2OUT16 9 34P2 P233 10 10 P 36P2 P235 38P2 P237 40P2 P239 Figure 34.Evaluation Board Circuitry –22– REV. B

AD9755 OUT15 EDGE JP1 SE 1 2A CLK+ JP2 B R508(cid:1) CKLVDD DF 3 T2 3 B2 A 1 R1k9(cid:1) 3 4 JP4 1CLK J3 JP6 P SE 1 2 DF 2 PGND: 3, 4, 5 CLK– DF2AB JP3 R1k7(cid:1) C0.116(cid:2)F 1 S P 6 P P 3 P L1 TP13 DVDD FBEAD J8 1 1 2 RED DVDD PLANE U1 BYPASS CAPS C13 10(cid:2)F TP14 DGND1 10V BLK DVDD PLANE PINS 5, 6 PINS 21, 22 J9 C1 C2 C3 C4 0.1(cid:2)F 1(cid:2)F 0.1(cid:2)F 1(cid:2)F L2 TP15 AVDD FBEAD 1 1 2 RED J10 AVDD PLANE C14 PINS 41, 44 10(cid:2)F TP16 AVDD PLANE J11AGND1 10V BLK C0.51(cid:2)F C1(cid:2)6F L3 TP17 CLKVDD FBEAD 1 1 2 RED PINS 45, 47 J12 1 CLKVDD CLKVDD C101(cid:2)5F TP11 JP7 A 2 PLLVDD PLANE C0.71(cid:2)F C1(cid:2)8F CLKGND 10V B J13 1 BLK 3 P P Figure 35.Evaluation Board Clock Circuitry Figure 36.Evaluation Board, Assembly—Top REV. B –23–

AD9755 Figure 37.Evaluation Board, Assembly—Bottom Figure 38.Evaluation Board—Top Layer –24– REV. B

AD9755 Figure 39.Evaluation Board, Layer 2, Ground Plane Figure 40.Evaluation Board, Layer 3, Power Plane REV. B –25–

AD9755 Figure 41.Evaluation Board, Bottom Layer –26– REV. B

AD9755 OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 1.60 9.00 BSC 0.60 MAX SQ 0.45 48 37 1 36 SEATING PIN 1 10(cid:3) PLANE 1.45 6(cid:3) TOP VIEW 7.00 1.40 2(cid:3) 0.20 (PINS DOWN) BSC SQ 0.09 1.35 7(cid:3) VIEW A 3.5(cid:3) 0.15 0(cid:3) 1213 24 25 0.05 SPELAANTIENG 0C.O08P LMAANXARITY 0.50 0.27 BSC 0.22 VIEW A 0.17 ROTATED 90(cid:3) CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC REV. B –27–

AD9755 Revision History Location Page 6/03—Data Sheet changed from REV. A to REV. B. Changes to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 B) 3( Changes to DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 0 6/ – Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 0 – 2 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 25 2 0 Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 C Changes to FUNCTIONAL DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Changes to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Changes to DIGITAL INPUTS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to Figure 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Changes to Figure 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1/03—Data Sheet changed from REV. 0 to REV. A. Changes to DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Changes to Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 –28– REV. B