10-Bit, 210 MSPS TxDAC® D/A Converter AD9740 FEATURES APPLICATIONS High performance member of pin-compatible Wideband communication transmit channel TxDAC product family Direct IF Excellent spurious-free dynamic range performance Base stations SNR @ 5 MHz output, 125 MSPS: 65 dB Wireless local loops Twos complement or straight binary data format Digital radio links Differential current outputs: 2 mA to 20 mA Direct digital synthesis (DDS) Power dissipation: 135 mW @ 3.3 V Instrumentation Power-down mode: 15 mW @ 3.3 V FUNCTIONAL BLOCK DIAGRAM On-chip 1.2 V Reference 3.3V CMOS-compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP REFLO 150pF AVDD ACOM packages 1.2V REF 0.1μF Edge-triggered latches REFIO CURRENT AD9740 FS ADJ SOURCE ARRAY RSET 3.3V DVDD IOUTA SEGMENTED LSB DCOM SWITCHES SWITCHES IOUTB CLOCK CLOCK LATCHES MODE SLEEP DIGITAL DATA INPUTS (DB9–DB0) 02911-001 Figure 1. GENERAL DESCRIPTION The AD97401 is a 10-bit resolution, wideband, third generation Edge-triggered input latches and a 1.2 V temperature-compensated member of the TxDAC series of high performance, low power band gap reference have been integrated to provide a complete CMOS digital-to-analog converters (DACs). The TxDAC monolithic DAC solution. The digital inputs support 3 V CMOS family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit logic families. DACs, is specifically optimized for the transmit signal path PRODUCT HIGHLIGHTS of communication systems. All of the devices share the same 1. The AD9740 is the 10-bit member of the pin-compatible interface options, small outline package, and pinout, providing TxDAC family, which offers excellent INL and DNL an upward or downward component selection path based performance. on performance, resolution, and cost. The AD9740 offers 2. Data input supports twos complement or straight binary exceptional ac and dc performance while supporting update data coding. rates up to 210 MSPS. 3. High speed, single-ended CMOS clock input supports 210 MSPS conversion rate. The AD9740’s low power dissipation makes it well suited for 4. Low power: Complete CMOS DAC function operates on portable and low power applications. Its power dissipation 135 mW from a 2.7 V to 3.6 V single supply. The DAC full- can be further reduced to 60 mW with a slight degradation in scale current can be reduced for lower power operation, performance by lowering the full-scale current output. In and a sleep mode is provided for low power idle periods. addition, a power-down mode reduces the standby power 5. On-chip voltage reference: The AD9740 includes a 1.2 V dissipation to approximately 15 mW. A segmented current temperature-compensated band gap voltage reference. source architecture is combined with a proprietary switching 6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32- technique to reduce spurious components and enhance lead LFCSP packages. dynamic performance. 1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

AD9740 TABLE OF CONTENTS Features..............................................................................................1 DAC Transfer Function.............................................................14 Applications.......................................................................................1 Analog Outputs..........................................................................14 Functional Block Diagram..............................................................1 Digital Inputs..............................................................................15 General Description.........................................................................1 Clock Input..................................................................................15 Product Highlights...........................................................................1 DAC Timing................................................................................16 Revision History...............................................................................3 Power Dissipation.......................................................................16 Specifications.....................................................................................4 Applying the AD9740................................................................17 DC Specifications.........................................................................4 Differential Coupling Using a Transformer...............................17 Dynamic Specifications...............................................................5 Differential Coupling Using an Op Amp................................18 Digital Specifications...................................................................6 Single-Ended, Unbuffered Voltage Output.............................18 Absolute Maximum Ratings............................................................7 Single-Ended, Buffered Voltage Output Configuration........18 Thermal Characteristics..............................................................7 Power and Grounding Considerations, Power Supply Rejection......................................................................................19 ESD Caution..................................................................................7 Evaluation Board............................................................................20 Pin Configurations and Function Descriptions...........................8 General Description...................................................................20 Terminology......................................................................................9 Outline Dimensions.......................................................................30 Typical Performance Characteristics...........................................10 Ordering Guide..........................................................................31 Functional Description..................................................................13 Reference Operation..................................................................13 Reference Control Amplifier....................................................14 Rev. B | Page 2 of 32

AD9740 REVISION HISTORY 12/05—Rev. A to Rev. B 5/03—Rev. 0 to Rev. A Updated Format..................................................................Universal Added 32-Lead LFCSP Package.......................................Universal Changes to General Description and Product Highlights...........1 Edits to Features................................................................................1 Changes to Table 1............................................................................4 Edits to Product Highlights.............................................................1 Changes to Table 2............................................................................5 Edits to DC Specifications...............................................................2 Changes to Table 5............................................................................8 Edits to Dynamic Specifications.....................................................3 Changes to Figure 6.........................................................................10 Edits to Digital Specifications..........................................................4 Inserted Figure 11; Renumbered Sequentially............................10 Edits to Absolute Maximum Ratings..............................................5 Changes to Figure 12, Figure 13, Figure 14, and Figure 15.......11 Edits to Thermal Characteristics....................................................5 Changes to Functional Description and Reference Edits to Ordering Guide...................................................................5 Operation Sections..........................................................................13 Edits to Pin Configuration...............................................................6 Inserted Figure 23; Renumbered Sequentially............................13 Edits to Pin Function Descriptions................................................6 Changes to DAC Transfer Function Section and Figure 25......14 Edits to Figure 2................................................................................7 Changes to Digital Inputs Section.................................................15 Replaced TPCs 1, 4, 7, and 8............................................................8 Changes to Figure 30 and Figure 31.............................................17 Edits to Figure 3..............................................................................10 Updated Outline Dimensions........................................................30 Edits to Functional Description Section......................................10 Changes to Ordering Guide...........................................................31 Edits to Digital Inputs Section.......................................................12 Added Clock Input Section............................................................12 Added Figure 7................................................................................12 Edits to DAC Timing Section........................................................12 Edits to Sleep Mode Operation Section.......................................13 Edits to Power Dissipation Section...............................................13 Renumbered Figures 8 to 26..........................................................13 Added Figure 11..............................................................................13 Added Figures 27 to 35...................................................................21 Updated Outline Dimensions........................................................26 5/02—Revision 0: Initial Version Rev. B | Page 3 of 32

AD9740 SPECIFICATIONS DC SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 1. Parameter Min Typ Max Unit RESOLUTION 10 Bits DC ACCURACY1 Integral Linearity Error (INL) −0.7 ±0.15 +0.7 LSB Differential Nonlinearity (DNL) −0.5 ±0.12 +0.5 LSB ANALOG OUTPUT Offset Error −0.02 +0.02 % of FSR Gain Error (Without Internal Reference) −2 ±0.1 +2 % of FSR Gain Error (With Internal Reference) −2 ±0.1 +2 % of FSR Full-Scale Output Current2 2 20 mA Output Compliance Range −1 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF REFERENCE OUTPUT Reference Voltage 1.14 1.20 1.26 V Reference Output Current3 100 nA REFERENCE INPUT Input Compliance Range 0.1 1.25 V Reference Input Resistance (External Reference) 7 kΩ Small Signal Bandwidth 0.5 MHz TEMPERATURE COEFFICIENTS Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C POWER SUPPLY Supply Voltages AVDD 2.7 3.3 3.6 V DVDD 2.7 3.3 3.6 V CLKVDD 2.7 3.3 3.6 V Analog Supply Current (I ) 33 36 mA AVDD Digital Supply Current (I )4 8 9 mA DVDD Clock Supply Current (I ) 5 6 mA CLKVDD Supply Current Sleep Mode (I ) 5 6 mA AVDD Power Dissipation4 135 145 mW Power Dissipation5 145 mW Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V Power Supply Rejection Ratio—DVDD6 −0.04 +0.04 % of FSR/V OPERATING RANGE −40 +85 °C 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, IOUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current <100 nA should be used to drive any external load. 4 Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz. 5 Measured as unbuffered voltage output with IOUTFS = 20 mA, 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS, and fOUT = 40 MHz. 6 ±5% power supply variation. Rev. B | Page 4 of 32

AD9740 DYNAMIC SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, differential transformer coupled output, 50 Ω doubly MIN MAX OUTFS terminated, unless otherwise noted. Table 2. Parameter Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) 210 MSPS CLOCK Output Settling Time (t ) (to 0.1%)1 11 ns ST Output Propagation Delay (t ) 1 ns PD Glitch Impulse 5 pV-s Output Rise Time (10% to 90%)1 2.5 ns Output Fall Time (10% to 90%)1 2.5 ns Output Noise (I = 20 mA)2 50 pA/√Hz OUTFS Output Noise (I = 2 mA)2 30 pA/√Hz OUTFS Noise Spectral Density3 −143 dBm/Hz AC LINEARITY Spurious-Free Dynamic Range to Nyquist f = 25 MSPS; f = 1.00 MHz CLOCK OUT 0 dBFS Output 71 79 dBc −6 dBFS Output 75 dBc −12 dBFS Output 67 dBc −18 dBFS Output 61 dBc f = 65 MSPS; f = 1.00 MHz 84 dBc CLOCK OUT f = 65 MSPS; f = 2.51 MHz 80 dBc CLOCK OUT f = 65 MSPS; f = 10 MHz 78 dBc CLOCK OUT f = 65 MSPS; f = 15 MHz 76 dBc CLOCK OUT f = 65 MSPS; f = 25 MHz 75 dBc CLOCK OUT f = 165 MSPS; f = 21 MHz 70 dBc CLOCK OUT f = 165 MSPS; f = 41 MHz 60 dBc CLOCK OUT f = 210 MSPS; f = 40 MHz 67 dBc CLOCK OUT f = 210 MSPS; f = 69 MHz 63 dBc CLOCK OUT Spurious-Free Dynamic Range within a Window f = 25 MSPS; f = 1.00 MHz; 2 MHz Span 80 dBc CLOCK OUT f = 50 MSPS; f = 5.02 MHz; 2 MHz Span 90 dBc CLOCK OUT f = 65 MSPS; f = 5.03 MHz; 2.5 MHz Span 90 dBc CLOCK OUT f = 125 MSPS; f = 5.04 MHz; 4 MHz Span 90 dBc CLOCK OUT Total Harmonic Distortion f = 25 MSPS; f = 1.00 MHz −79 −71 dBc CLOCK OUT f = 50 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT f = 65 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT f = 125 MSPS; f = 2.00 MHz −77 dBc CLOCK OUT Signal-to-Noise Ratio f = 65 MSPS; f = 5 MHz; I = 20 mA 68 dB CLOCK OUT OUTFS f = 65 MSPS; f = 5 MHz; I = 5 mA 64 dB CLOCK OUT OUTFS f = 125 MSPS; f = 5 MHz; I = 20 mA 64 dB CLOCK OUT OUTFS f = 125 MSPS; f = 5 MHz; I = 5 mA 62 dB CLOCK OUT OUTFS f = 165 MSPS; f = 5 MHz; I = 20 mA 64 dB CLOCK OUT OUTFS f = 165 MSPS; f = 5 MHz; I = 5 mA 62 dB CLOCK OUT OUTFS f = 210 MSPS; f = 5 MHz; I = 20 mA 63 dB CLOCK OUT OUTFS f = 210 MSPS; f = 5 MHz; I = 5 mA 60 dB CLOCK OUT OUTFS Rev. B | Page 5 of 32

AD9740 Parameter Min Typ Max Unit Multitone Power Ratio (8 Tones at 400 kHz Spacing) f = 78 MSPS; f = 15.0 MHz to 18.2 MHz CLOCK OUT 0 dBFS Output 65 dBc −6 dBFS Output 66 dBc −12 dBFS Output 60 dBc −18 dBFS Output 55 dBc 1 Measured single-ended into 50 Ω load. 2 Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only. 3 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. DIGITAL SPECIFICATIONS T to T , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I = 20 mA, unless otherwise noted. MIN MAX OUTFS Table 3. Parameter Min Typ Max Unit DIGITAL INPUTS1 Logic 1 Voltage 2.1 3 V Logic 0 Voltage 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF Input Setup Time (t) 2.0 ns S Input Hold Time (t ) 1.5 ns H Latch Pulse Width (t ) 1.5 ns LPW CLK INPUTS2 Input Voltage Range 0 3 V Common-Mode Voltage 0.75 1.5 2.25 V Differential Voltage 0.5 1.5 V 1 Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode. 2 Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode. DB0–DB9 t t S H CLOCK t LPW t PD t ST IOUTA OR 0.1% IOUTB 0.1% 02911-002 Figure 2. Timing Diagram Rev. B | Page 6 of 32

AD9740 ABSOLUTE MAXIMUM RATINGS Table 4. THERMAL CHARACTERISTICS1 With Thermal Resistance Parameter Respect to Min Max Unit 28-Lead 300-Mil SOIC AVDD ACOM −0.3 +3.9 V θ = 55.9°C/W JA DVDD DCOM −0.3 +3.9 V 28-Lead TSSOP CLKVDD CLKCOM −0.3 +3.9 V θ = 67.7°C/W JA ACOM DCOM −0.3 +0.3 V 32-Lead LFCSP ACOM CLKCOM −0.3 +0.3 V θ = 32.5°C/W JA DCOM CLKCOM −0.3 +0.3 V AVDD DVDD −3.9 +3.9 V 1 Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. AVDD CLKVDD −3.9 +3.9 V DVDD CLKVDD −3.9 +3.9 V CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V REFIO, REFLO, FS ADJ ACOM −0.3 AVDD + 0.3 V CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V Junction 150 °C Temperature Storage −65 +150 °C Temperature Range Lead Temperature 300 °C (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 32

AD9740 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS )B (MSB) DB9 1 28 CLOCK SMMP DB8 2 27 DVDD 45678( 9OEE BBBBBBCL DDDDDDDS DB7 3 26 DCOM 21098765 DB6 4 25 MODE 33322222 DB5 5 24 AVDD DB3 1 24 FS ADJ DB4 6 AD9740 23 RESERVED DB2 2 PIN 1 23 REFIO DB3 7 TOP VIEW 22 IOUTA DVDD 3 INDICATOR 22 ACOM (Not to Scale) DB1 4 AD9740 21 IOUTA DB2 8 21 IOUTB DB0 5 TOP VIEW 20 IOUTB DB1 9 20 ACOM NC 6 (Not to Scale) 19 ACOM NC 7 18 AVDD DB0 10 19 NC NC 8 17 AVDD NC 11 18 FS ADJ NC 12 17 REFIO 90123456 1111111 NC 13 16 REFLO CMD+–MEE NODKKODD NC 14NC = NO CONNECT15 SLEEP 02911-003 NCCD = VKLCNOLC CLCONCKLCNOMCECOMT 02911-004 Figure 3. 28-Lead SOIC and TSSOP Pin Configuration Figure 4. 32-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions SOIC/TSSOP LFCSP Pin No. Pin No. Mnemonic Description 1 27 DB9 (MSB) Most Significant Data Bit (MSB). 2 to 9 28 to 32, 1, 2, 4 DB8 to DB1 Data Bits 8 to 1. 10 5 DB0 (LSB) Least Significant Data Bit (LSB). 11 to 14, 19 6 to 9 NC No Internal Connection. 15 25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it can be left unterminated if not used. 16 N/A REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both internal and external reference operation modes. 17 23 REFIO Reference Input/Output. Serves as reference input when using external reference. Serves as 1.2 V reference output when using internal reference. Requires 0.1 μF capacitor to ACOM when using internal reference. 18 24 FS ADJ Full-Scale Current Output Adjust. 20 19, 22 ACOM Analog Common. 21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 N/A RESERVED Reserved. Do Not Connect to Common or Supply. 24 17, 18 AVDD Analog Supply Voltage (3.3 V). 25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. N/A 15 CMODE Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip). 26 10, 26 DCOM Digital Common. 27 3 DVDD Digital Supply Voltage (3.3 V). 28 N/A CLOCK Clock Input. Data latched on positive edge of clock. N/A 12 CLK+ Differential Clock Input. N/A 13 CLK− Differential Clock Input. N/A 11 CLKVDD Clock Supply Voltage (3.3 V). N/A 14 CLKCOM Clock Common. Rev. B | Page 8 of 32

AD9740 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Power Supply Rejection Linearity error is defined as the maximum deviation of the The maximum change in the full-scale output as the supplies actual analog output from the ideal output, determined by a are varied from nominal to minimum and maximum specified straight line drawn from zero to full scale. voltages. Differential Nonlinearity (or DNL) Settling Time The time required for the output to reach and remain within a DNL is the measure of the variation in analog value, normalized specified error band about its final value, measured from the to full scale, associated with a 1 LSB change in digital input code. start of the output transition. Monotonicity Glitch Impulse A DAC is monotonic if the output either increases or remains Asymmetrical switching times in a DAC give rise to undesired constant as the digital input increases. output transients that are quantified by a glitch impulse. It is Offset Error specified as the net area of the glitch in pV-s. The deviation of the output current from the ideal of zero is Spurious-Free Dynamic Range called the offset error. For IOUTA, 0 mA output is expected The difference, in dB, between the rms amplitude of the output when the inputs are all 0s. For IOUTB, 0 mA output is expected signal and the peak spurious signal over the specified bandwidth. when all inputs are set to 1s. Total Harmonic Distortion (THD) Gain Error T THD is the ratio of the rms sum of the first six harmonic The difference between the actual and ideal output span. The components to the rms value of the measured input signal. It is actual span is determined by the output when all inputs are set expressed as a percentage or in decibels (dB). to 1s minus the output when all inputs are set to 0s. Multitone Power Ratio Output Compliance Range The spurious-free dynamic range containing multiple carrier The range of allowable voltage at the output of a current output tones of equal amplitude. It is measured as the difference DAC. Operation beyond the maximum compliance limits can between the rms amplitude of a carrier tone to the peak cause either output stage saturation or breakdown, resulting in spurious signal in the region of a removed tone. nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T or T . For MIN MAX offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. 3.3V REFLO AVDD ACOM 150pF 1.2V REF AD9740 0.1μF REFIO PMOS FS ADJ CURRENT SOURCE ARRAY MINI-CIRCUITS RSET T1-1T 2kΩ 3.3V DVDD ROHDE & SCHWARZ IOUTA FSEA30 DCOM SEGMFEONRT DEBD9 S–WDBIT1CHES SWILTSCBHES IOUTB SAPNEACLTYRZEURM CLOCK MODE LATCHES DVDD SLEEP 50Ω DCOM 50Ω RETIMED 50Ω CLOCK DIGITAL OUTPUT* DATA CLOCK *AWG2021 CLOCK RETIMED PULLSEEC GROENYE 9R2A10TOR OUTPUT TEKWTRITOHN OIXP ATIWOGN -42021 STOROFA 5TN0HS%AI TTDI OTUHNTEYS DCOIYNGC IFTLAAELL CL DLINAOGTC AEKD.GE 02911-005 Figure 5. Basic AC Characterization Test Setup (SOIC/TSSOP Packages) Rev. B | Page 9 of 32

AD9740 TYPICAL PERFORMANCE CHARACTERISTICS 95 95 210MSPS (LFCSP) 90 125MSPS 90 0dBFS 85 85 165MSPS (LFCSP) 80 80 dBc) 75 65MSPS dBc) 75 –6dBFS DR ( 70 125MSPS (LFCSP) DR ( 70 SF 65 SF 65 –12dBFS 60 60 210MSPS 55 55 165MSPS 50 50 450 fOUT1 (0MHz) 100 02911-006 450 10 20 fOUT3 (0MHz) 40 50 60 02911-009 Figure 6. SFDR vs. fOUT @ 0 dBFS Figure 9. SFDR vs. fOUT @ 165 MSPS 95 95 90 90 85 85 80 80 0dBFS 20mA c) 75 c) 75 B B d –6dBFS d 10mA R ( 70 R ( 70 D D F –12dBFS F 5mA S 65 S 65 60 60 55 55 50 50 450 5 10fOUT (MHz)15 20 25 02911-007 450 5 10fOUT (MHz)15 20 25 02911-010 Figure 7. SFDR vs. fOUT @ 65 MSPS Figure 10. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS 95 95 90 90 0dBFS 0dBFS (LFCSP) 85 85 –12dBFS (LFCSP) 80 80 c) 75 c) 75 –6dBFS (LFCSP) B –6dBFS B d d R ( 70 R ( 70 D –12dBFS D 0dBFS F F S 65 S 65 60 60 –12dBFS 55 55 –6dBFS 50 50 450 5 10 15 f2O0UT (MH25z) 30 35 40 45 02911-008 450 10 20 30 fOUT4 (0MHz) 50 60 70 80 02911-054 Figure 8. SFDR vs. fOUT @ 125 MSPS Figure 11. SFDR vs. fOUT @ 210 MSPS Rev. B | Page 10 of 32

AD9740 95 95 90 125MSPS 165MSPS 125MSPS 85 85 165MSPS 65MSPS 80 65MSPS c) 75 c) 75 dB 210MSPS dB R ( 70 (LFCSP) R ( 210MSPS (29, 31) D D SF 65 210MSPS SF 65 210MSPS (29, 31) LFCSP 78MSPS 60 55 55 50 45–25 –20 –1A5OUT (dBFS–1)0 –5 0 02911-011 45–25 –20 –1A5OUT (dBFS–1)0 –5 0 02911-014 Figure 12. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/11 Figure 15. Dual-Tone IMD vs. AOUT @ fOUT = fCLOCK/7 95 0.25 90 85 0.15 65MSPS 125MSPS 80 c) 75 210MSPS (LFCSP) SB) 0.05 B L R (d 70 OR ( D R SF 65 ER –0.05 165MSPS 60 55 210MSPS –0.15 50 45–25 –20 –1A5OUT (dBFS–1)0 –5 0 02911-012 –0.250 256 C5O1D2E 768 1024 02911-015 Figure 13. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5 Figure 16. Typical INL 90 0.25 85 0.15 80 20mA B) 75 20mA (LFCSP) LSB) 0.05 R (d 70 OR ( N R S R –0.05 65 E 60 5mA –0.15 10mA (LFCSP) 5mA (LFCSP) 10mA 55 500 30 60 fC9L0OCK (MS12P0S) 150 180 210 02911-013 –0.250 256 C5O1D2E 768 1024 02911-016 Figure 14. SNR vs. fCLOCK and IOUTFS @ fOUT = 5 MHz and 0 dBFS Figure 17. Typical DNL Rev. B | Page 11 of 32

AD9740 90 0 fCLOCK = 78MSPS 85 –10 fOUT1 = 15.0MHz –20 fOUT2 = 15.4MHz SFDR = 77dBc 80 AMPLITUDE = 0dBFS –30 4MHz m) 75 B R (dBc) 70 UDE (d ––4500 D 19MHz T SF 65 GNI –60 A 34MHz M –70 60 49MHz –80 55 –90 50–40 –20 0TEMPER2A0TURE (°C4)0 60 80 02911-017 –1001 6 11 FRE1Q6UENCY2 (1MHz) 26 31 36 02911-019 Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS Figure 20. Dual-Tone SFDR 0 0 fCLOCK = 78MSPS fCLOCK = 78MSPS –10 fOUT = 15.0MHz –10 fOUT1 = 15.0MHz –20 SAFMDPRL I=T U77DdEB =c 0dBFS –20 ffOOUUTT23 == 1155..48MMHHzz m) –30 m) –30 SfOFUDTR4 == 1762.d2BMcHz B B d –40 d –40 AMPLITUDE = 0dBFS E ( E ( UD –50 UD –50 T T GNI –60 GNI –60 A A M M –70 –70 –80 –80 –90 –90 –1001 6 11 FRE1Q6UENCY2 (1MHz) 26 31 36 02911-018 –1001 6 11 FRE1Q6UENCY2 (1MHz) 26 31 36 02911-020 Figure 19. Single-Tone SFDR Figure 21. Four-Tone SFDR 3.3V REFLO 150pF AVDD ACOM 1.2V REF AD9740 VREFIO REFIO PMOS 0.1μF IREF FS ADJ CURRENT SOURCE ARRAY RSET VDIFF= VOUTA– VOUTB 2kΩ 3.3V DVDD IOUTA IOUTA SEGMENTED SWITCHES LSB VOUTA DCOM FOR DB9–DB1 SWITCHES IOUTB IOUTB VOUTB RLOAD CLOCK CLOCK LATCHES MODE RLOAD 50Ω SLEEP DIGITAL DATA INPUTS (DB9–DB0) 50Ω 02911-021 Figure 22. Simplified Block Diagram (SOIC/TSSOP Packages) Rev. B | Page 12 of 32

AD9740 FUNCTIONAL DESCRIPTION Figure 22 shows a simplified block diagram of the AD9740. The REFERENCE OPERATION AD9740 consists of a DAC, digital control logic, and full-scale The AD9740 contains an internal 1.2 V band gap reference. The output current control. The DAC contains a PMOS current internal reference cannot be disabled, but can be easily overridden source array capable of providing up to 20 mA of full-scale by an external reference with no effect on performance. Figure 23 current (I ). The array is divided into 31 equal currents that OUTFS shows an equivalent circuit of the band gap reference. REFIO make up the five most significant bits (MSBs). The next four serves as either an output or an input depending on whether bits, or middle bits, consist of 15 equal current sources whose the internal or an external reference is used. To use the internal value is 1/16 of an MSB current source. The remaining LSBs are reference, simply decouple the REFIO pin to ACOM with a binary weighted fractions of the middle bits current sources. 0.1 μF capacitor and connect REFLO to ACOM via a resistance Implementing the middle and lower bits with current sources, less than 5 Ω. The internal reference voltage is present at instead of an R-2R ladder, enhances its dynamic performance REFIO. If the voltage at REFIO is to be used anywhere else in for multitone or low amplitude signals and helps maintain the the circuit, then an external buffer amplifier with an input bias DAC’s high output impedance (that is, >100 kΩ). current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 24. All of these current sources are switched to one or the other of the two output nodes (that is, IOUTA or IOUTB) via PMOS AVDD differential current switches. The switches are based on the 84µA architecture that was pioneered in the AD9764 family, with REFIO further refinements to reduce distortion contributed by the 7kΩ switching transient. This switch architecture also reduces vdarrivioeu ssig tnimalisn tgo etrhreo rins pauntds porf otvhied desif mferaetcnhtiianlg c ucorrmenptle smweitncthaersy. REFLO 02911-057 Figure 23. Equivalent Circuit of Internal Reference The analog and digital sections of the AD9740 have separate power supply inputs (that is, AVDD and DVDD) that can 3.3V operate independently over a 2.7 V to 3.6 V range. The digital OPTIONAL EXTERNAL section, which is capable of operating at a clock rate of up to REF BUFFER REFLO 150pF AVDD 210 MSPS, consists of edge-triggered latches and segment 1.2V REF decoding logic circuitry. The analog section includes the PMOS REFIO CURRENT current sources, the associated differential switches, a 1.2 V ADDITILOONAADL 0.1μF FS ADJ SAORURRACYE band gap voltage reference, and a reference control amplifier. 2kΩ The DAC full-scale output current is regulated by the reference AD9740 02911-022 control amplifier and can be set from 2 mA to 20 mA via an Figure 24. Internal Reference Configuration external resistor, R , connected to the full-scale adjust SET An external reference can be applied to REFIO, as shown in (FS ADJ) pin. The external resistor, in combination with both Figure 25. The external reference can provide either a fixed the reference control amplifier and voltage reference, V , sets REFIO reference voltage to enhance accuracy and drift performance the reference current, I , which is replicated to the segmented REF or a varying reference voltage for gain control. Note that the current sources with the proper scaling factor. The full-scale 0.1 μF compensation capacitor is not required because the current, I , is 32 times I . OUTFS REF internal reference is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. Rev. B | Page 13 of 32

AD9740 3.3V The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, then IOUTA and IOUTB should be directly connected to matching resistive REFLO 150pF AVDD loads, RLOAD, that are tied to analog common, ACOM. Note that 1.2V REF RLOAD can represent the equivalent load resistance seen by REFIO IOUTA or IOUTB, as would be the case in a doubly terminated CURRENT FSADJ SOURCE 50 Ω or 75 Ω cable. The single-ended voltage output appearing ARRAY at the IOUTA and IOUTB nodes is simply REFERENCE AD9740 CAOMNPTLRIFOIELR 02911-023 VVOOUUTTAB == IIOOUUTTBA ×× RRLLOOAADD ((56)) Figure 25. External Reference Configuration Note that the full-scale value of V and V should not OUTA OUTB REFERENCE CONTROL AMPLIFIER exceed the specified output compliance range to maintain specified distortion and linearity performance. The AD9740 contains a control amplifier that is used to regulate the full-scale output current, I . The control amplifier is V = (IOUTA − IOUTB) × R (7) OUTFS DIFF LOAD configured as a V-I converter, as shown in Figure 24, so that its Substituting the values of IOUTA, IOUTB, I , and V can be current output, I , is determined by the ratio of the V and REF DIFF REF REFIO expressed as: an external resistor, R , as stated in Equation 4. I is copied SET REF to the segmented current sources with the proper scale factor to V = {(2 × DAC CODE − 1023)/1024} DIFF set I , as stated in Equation 3. (32 × R /R ) × V (8) OUTFS LOAD SET REFIO The control amplifier allows a wide (10:1) adjustment span of Equation 7 and Equation 8 highlight some of the advantages of I over a 2 mA to 20 mA range by setting I between operating the AD9740 differentially. First, the differential OUTFS REF 62.5 μA and 625 μA. The wide adjustment span of I operation helps cancel common-mode error sources associated OUTFS provides several benefits. The first relates directly to the power with IOUTA and IOUTB, such as noise, distortion, and dc dissipation of the AD9740, which is proportional to I (see offsets. Second, the differential code-dependent current and OUTFS the Power Dissipation section). The second relates to a 20 dB subsequent voltage, V , is twice the value of the single-ended DIFF adjustment, which is useful for system gain control purposes. voltage output (that is, V or V ), thus providing twice the OUTA OUTB signal power to the load. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency small Note that the gain drift temperature performance for a single- signal multiplying applications. ended (V and V ) or differential output (V ) of the OUTA OUTBB DIFF AD9740 can be enhanced by selecting temperature tracking DAC TRANSFER FUNCTION resistors for R and R due to their ratiometric relationship, LOAD SET The AD9740 provides complementary current outputs, IOUTA as shown in Equation 8. and IOUTB. IOUTA provides a near full-scale current output, ANALOG OUTPUTS I , when all bits are high (that is, DAC CODE = 1023), while OUTFS IOUTB, the complementary output, provides no current. The The complementary current outputs in each DAC, IOUTA, current output appearing at IOUTA and IOUTB is a function of and IOUTB can be configured for single-ended or differential both the input code and I and can be expressed as: operation. IOUTA and IOUTB can be converted into OUTFS complementary single-ended voltage outputs, V and V , IOUTA = (DAC CODE/1023) × I (1) OUTA OUTB OUTFS via a load resistor, R , as described in the DAC Transfer LOAD IOUTB = (1023 − DAC CODE)/1024 × I (2) OUTFS Function section by Equation 5 through Equation 8. The differential voltage, V , existing between V and V , can where DAC CODE = 0 to 1023 (that is, decimal representation). DIFF OUTA OUTB also be converted to a single-ended voltage via a transformer or As mentioned previously, I is a function of the reference differential amplifier configuration. The ac performance of the OUTFS current I , which is nominally set by a reference voltage, AD9740 is optimum and specified using a differential REF V , and external resistor, R . It can be expressed as: transformer-coupled output in which the voltage swing at REFIO SET IOUTA and IOUTB is limited to ±0.5 V. I = 32 × I (3) OUTFS REF where The distortion and noise performance of the AD9740 can be I = V /R (4) enhanced when it is configured for differential operation. The REF REFIO SET common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a Rev. B | Page 14 of 32

AD9740 transformer or differential amplifier. These common-mode DVDD error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed DIGITAL INPUT waveform increases and/or its amplitude decreases. This is due to the first-order cancellation of various dynamic common- mode distortion mechanisms, digital feedthrough, and noise. 02911-024 Performing a differential-to-single-ended conversion via a Figure 26. Equivalent Digital Input transformer also provides the ability to deliver twice the The digital interface is implemented using an edge-triggered reconstructed signal power to the load (assuming no source master/slave latch. The DAC output updates on the rising edge termination). Because the output currents of IOUTA and of the clock and is designed to support a clock rate as high as IOUTB are complementary, they become additive when 210 MSPS. The clock can be operated at any duty cycle that processed differentially. A properly selected transformer allows meets the specified latch pulse width. The setup and hold times the AD9740 to provide the required power and voltage levels to can also be varied within the clock cycle as long as the specified different loads. minimum times are met, although the location of these transition The output impedance of IOUTA and IOUTB is determined by edges can affect digital feedthrough and distortion performance. the equivalent parallel combination of the PMOS switches Best performance is typically achieved when the input data associated with the current sources and is typically 100 kΩ in transitions on the falling edge of a 50% duty cycle clock. parallel with 5 pF. It is also slightly dependent on the output CLOCK INPUT voltage (that is, V and V ) due to the nature of a PMOS OUTA OUTB SOIC/TSSOP Packages device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration results in the The 28-lead package options have a single-ended clock input optimum dc linearity. Note that the INL/DNL specifications for (CLOCK) that must be driven to rail-to-rail CMOS levels. The the AD9740 are measured with IOUTA maintained at a virtual quality of the DAC output is directly related to the clock quality, ground via an op amp. and jitter is a key concern. Any noise or jitter in the clock translates directly into the DAC output. Optimal performance is IOUTA and IOUTB also have a negative and positive voltage achieved if the CLOCK input has a sharp rising edge, because compliance range that must be adhered to in order to achieve the DAC latches are positive edge triggered. optimum performance. The negative output compliance range of −1 V is set by the breakdown limits of the CMOS process. LFCSP Package Operation beyond this maximum limit can result in a A configurable clock input is available in the LFCSP package, breakdown of the output stage and affect the reliability of the which allows for one single-ended and two differential modes. AD9740. The mode selection is controlled by the CMODE input, as summarized in Table 6. Connecting CMODE to CLKCOM The positive output compliance range is slightly dependent on selects the single-ended clock input. In this mode, the CLK+ the full-scale output current, I . It degrades slightly from its OUTFS input is driven with rail-to-rail swings and the CLK− input is nominal 1.2 V for an I = 20 mA to 1 V for an I = 2 mA. OUTFS OUTFS left floating. If CMODE is connected to CLKVDD, then the The optimum distortion performance for a single-ended or differential receiver mode is selected. In this mode, both inputs differential output is achieved when the maximum full-scale are high impedance. The final mode is selected by floating signal at IOUTA and IOUTB does not exceed 0.5 V. CMODE. This mode is also differential, but internal DIGITAL INPUTS terminations for positive emitter-coupled logic (PECL) are activated. There is no significant performance difference The AD9740 digital section consists of 10 input bit channels between any of the three clock input modes. and a clock input. The 10-bit parallel data inputs follow standard positive binary coding, where DB9 is the most Table 6. Clock Mode Selection significant bit (MSB) and DB0 is the least significant bit (LSB). CMODE Pin Clock Input Mode IOUTA produces a full-scale output current when all data bits CLKCOM Single-ended are at Logic 1. IOUTB produces a complementary output with CLKVDD Differential the full-scale current split between the two outputs as a Float PECL function of the input code. The single-ended input mode operates in the same way as the clock input in the 28-lead packages, as described previously. Rev. B | Page 15 of 32

AD9740 In the differential input mode, the clock input functions as a 75 high impedance differential pair. The common-mode level of 70 the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and the differential voltage can be as low as 0.5 V p-p. This mode 65 can be used to drive the clock with a differential sine wave because the high gain bandwidth of the differential inputs 60 20MHz SFDR converts the sine wave into a single-ended square wave internally. dB 55 The final clock mode allows for a reduced external component 50MHz SFDR count when the DAC clock is distributed on the board using 50 PECL logic. The internal termination configuration is shown in 45 Figure 27. These termination resistors are untrimmed and can vary up to ±20%. However, matching between the resistors 40 should generally be better than ±1%. 50MHz SFDR AD9740 35–3 –2 –1 n0s 1 2 3 02911-026 CLK+ Figure 28. SFDR vs. Clock Placement @ CLK– CRLEOCCEIKVER TO DAC CORE fOUT = 20 MHz and 50 MHz (fCLOCK = 165 MSPS) Sleep Mode Operation 50Ω 50Ω The AD9740 has a power-down function that turns off the output VTT = 1.3V NOM 02911-025 cspuercreifniet da nsudp rpeldyu rcaensg teh eo fs u2.p7p Vly tcou 3rr.6e nVt taon lde stsh teh taenm 6p emraAtu orvee rra tnhgee . Figure 27. Clock Termination in PECL Mode This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω DAC TIMING AVDD. This digital input also contains an active pull-down Input Clock and Data Timing Relationship circuit that ensures that the AD9740 remains enabled if this input is left disconnected. The AD9740 takes less than 50 ns Dynamic performance in a DAC is dependent on the to power down and approximately 5 μs to power back up. relationship between the position of the clock edges and the time at which the input data changes. The AD9740 is rising POWER DISSIPATION edge triggered, and so exhibits dynamic performance sensitivity The power dissipation, P , of the AD9740 is dependent on when the data transition is close to this edge. In general, the D several factors that include: goal when applying the AD9740 is to make the data transition close to the falling clock edge. This becomes more important as • The power supply voltages (AVDD, CLKVDD, and the sample rate increases. Figure 28 shows the relationship of DVDD) SFDR to clock placement with different sample rates. Note that • The full-scale current output (I ) OUTFS at the lower sample rates, more tolerance is allowed in clock • The update rate (f ) CLOCK placement, while at higher rates, more care must be taken. • The reconstructed digital input waveform The power dissipation is directly proportional to the analog supply current, I , and the digital supply current, I . I AVDD DVDD AVDD is directly proportional to I , as shown in Figure 29, and is OUTFS insensitive to f . Conversely, I is dependent on both the CLOCK DVDD digital input waveform, f , and digital supply DVDD. Figure 30 CLOCK shows I as a function of full-scale sine wave output ratios DVDD (f /f ) for various update rates with DVDD = 3.3 V. OUT CLOCK Rev. B | Page 16 of 32

AD9740 35 APPLYING THE AD9740 Output Configurations 30 The following sections illustrate some typical output configurations for the AD9740. Unless otherwise noted, it is 25 A) assumed that IOUTFS is set to a nominal 20 mA. For applications m (D20 requiring the optimum dynamic performance, a differential D V output configuration is suggested. A differential output A I configuration can consist of either an RF transformer or a 15 differential op amp configuration. The transformer configuration provides the optimum high frequency 10 performance and is recommended for any application that allows ac coupling. The differential op amp configuration is 02 4 6 8 IO1U0TFS (m12A) 14 16 18 20 02911-027 suitable for applications requiring dc coupling, bipolar output, signal gain, and/or level shifting within the bandwidth of the Figure 29. IAVDD vs. IOUTFS chosen op amp. 20 A single-ended output is suitable for applications requiring a 18 210MSPS unipolar voltage output. A positive unipolar output voltage 16 results if IOUTA and/or IOUTB is connected to an 14 appropriately sized load resistor, R , referred to ACOM. 165MSPS LOAD A) 12 This configuration can be more suitable for a single-supply m (D10 125MSPS system requiring a dc-coupled, ground referred output voltage. D V Alternatively, an amplifier could be configured as an I-V ID 8 converter, thus converting IOUTA or IOUTB into a negative 6 65MSPS unipolar voltage. This configuration provides the best dc linearity 4 because IOUTA or IOUTB is maintained at a virtual ground. 2 DIFFERENTIAL COUPLING USING A TRANSFORMER 0 0.01 RATIO (fO0.U1T/fCLOCK) 1 02911-055 Asinng RleF- etnradnesdf osrigmnearl ccaonn vbeer suisoend, taos psheorfwonrm in a F digifuferree 3n2ti. aAl- to- Figure 30. IDVDD vs. Ratio @ DVDD = 3.3 V differentially coupled transformer output provides the 11 optimum distortion performance for output signals whose 10 spectral content lies within the transformer’s pass band. An RF transformer, such as the Mini-Circuits® T1–1T, provides 9 DIFF excellent rejection of common-mode distortion (that is, even- 8 order harmonics) and noise over a wide frequency range. It also 7 A) provides electrical isolation and the ability to deliver twice the m (D 6 PECL power to the load. Transformers with different impedance ratios D CLKV 5 SE can also be used for impedance matching purposes. Note that I 4 the transformer provides ac coupling only. 3 MINI-CIRCUITS 2 T1-1T 1 IOUTA 22 00 50 1f0C0LOCK (MSP1S50) 200 250 02911-056 AD9740 RLOAD IOUTB 21 Figure 31. ICLKVDD vs. fCLOCK and Clock Mode OPTIONAL RDIFF 02911-030 Figure 32. Differential Output Using a Transformer Rev. B | Page 17 of 32

AD9740 500Ω The center tap on the primary side of the transformer must be AD9740 connected to ACOM to provide the necessary dc current path 225Ω IOUTA 22 for both IOUTA and IOUTB. The complementary voltages AD8041 appearing at IOUTA and IOUTB (that is, V and V ) 225Ω OUTA OUTBB IOUTB 21 swing symmetrically around ACOM and should be maintained COPT 1kΩ AVDD with the specified output compliance range of the AD9740. A tdhifef eoruetnptuiat lo rfe tshiset otrr,a RnsDfIoFFr, mcaenr bise c ionnsneretcetde din t oa pthpeli cloataido,n Rs whe, re 25Ω 25Ω 1kΩ 02911-032 LOAD Figure 34. Single-Supply DC Differential Coupled Circuit via a passive reconstruction filter or cable. R is determined DIFF by the transformer’s impedance ratio and provides the proper SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT source termination that results in a low VSWR. Note that Figure 35 shows the AD9740 configured to provide a unipolar approximately half the signal power is dissipated across R . DIFF output range of approximately 0 V to 0.5 V for a doubly DIFFERENTIAL COUPLING USING AN OP AMP terminated 50 Ω cable because the nominal full-scale current, I , of 20 mA flows through the equivalent R of 25 Ω. OUTFS LOAD An op amp can also be used to perform a differential-to-single- In this case, R represents the equivalent load resistance seen LOAD ended conversion, as shown in Figure 33. The AD9740 is by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) configured with two equal load resistors, R , of 25 Ω. The LOAD can be connected to ACOM directly or via a matching R . LOAD differential voltage developed across IOUTA and IOUTB is Different values of I and R can be selected as long as OUTFS LOAD converted to a single-ended signal via the differential op amp the positive compliance range is adhered to. One additional configuration. An optional capacitor can be installed across consideration in this mode is the integral nonlinearity (INL), IOUTA and IOUTB, forming a real pole in a low-pass filter. The discussed in the Analog Outputs section. For optimum INL addition of this capacitor also enhances the op amp’s distortion performance, the single-ended, buffered voltage output performance by preventing the DAC’s high slewing output from configuration is suggested. overloading the op amp’s input. 500Ω AD9740 IOUTFS= 20mA AD9740 IOUTA 22 VOUTA= 0V TO 0.5V 225Ω IOUTA 22 50Ω 50Ω AD8047 IOUTB 21 225Ω IOUTB 21 COPT 500Ω 25Ω 02911-033 Figure 35. 0 V to 0.5 V Unbuffered Voltage Output 25Ω 25Ω 02911-031 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT Figure 33. DC Differential Coupling Using an Op Amp CONFIGURATION Figure 36 shows a buffered single-ended output configuration The common-mode rejection of this configuration is typically in which the op amp U1 performs an I-V conversion on the determined by the resistor matching. In this circuit, the AD9740 output current. U1 maintains IOUTA (or IOUTB) at a differential op amp circuit using the AD8047 is configured to virtual ground, minimizing the nonlinear output impedance provide some additional signal gain. The op amp must operate effect on the DAC’s INL performance as described in the Analog off a dual supply because its output is approximately ±1 V. A Outputs section. Although this single-ended configuration high speed amplifier capable of preserving the differential typically provides the best dc linearity performance, its ac performance of the AD9740 while meeting other system level distortion performance at higher DAC update rates can be objectives (that is, cost or power) should be selected. The op limited by U1’s slew rate capabilities. U1 provides a negative amp’s differential gain, gain setting resistor values, and full-scale unipolar output voltage, and its full-scale output voltage is output swing capabilities should all be considered when simply the product of R and I . The full-scale output optimizing this circuit. FB OUTFS should be set within U1’s voltage output swing capabilities by The differential circuit shown in Figure 34 provides the scaling IOUTFS and/or RFB. An improvement in ac distortion necessary level shifting required in a single-supply system. In performance can result with a reduced IOUTFS because U1 is this case, AVDD, which is the positive analog supply for both required to sink less signal current. the AD9740 and the op amp, is also used to level shift the differential output of the AD9740 to midsupply (that is, AVDD/2). The AD8041 is a suitable op amp for this application. Rev. B | Page 18 of 32

AD9740 COPT Note that the ratio in Figure 37 is calculated as amps out/volts RFB in. Noise on the analog power supply has the effect of modulating 200Ω the internal switches, and therefore the output current. The AD9740 IOUTFS= 10mA voltage noise on AVDD, therefore, is added in a nonlinear IOUTA 22 manner to the desired IOUT. Due to the relative different size of U1 VOUT= IOUTFS× RFB these switches, the PSRR is very code dependent. This can produce IOUTB 21 200Ω 02911-034 an omisiex itnog h eifgfhecert tfhreaqt uceannc mieos.d Wuloartest l-ocwas efr PeqSuReRn cfoyr p eoitwheerr sounpep olyf the differential DAC outputs occur when the full-scale current Figure 36. Unipolar Buffered Voltage Output is directed toward that output. POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION As a result, the PSRR measurement in Figure 37 represents a worst-case condition in which the digital inputs remain static Many applications seek high speed and high performance and the full-scale output current of 20 mA is directed to the under less than ideal operating conditions. In these application DAC output being measured. circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF The following illustrates the effect of supply noise on the analog techniques must be used for device selection, placement, and supply. Suppose a switching regulator with a switching frequency routing as well as power supply bypassing and grounding to of 250 kHz produces 10 mV of noise and, for simplicity’s sake ensure optimum performance. Figure 41 to Figure 44 illustrate (ignoring harmonics), all of this noise is concentrated at 250 kHz. the recommended printed circuit board ground, power, and To calculate how much of this undesired noise appears as current signal plane layouts implemented on the AD9740 evaluation noise superimposed on the DAC’s full-scale current, I , users OUTFS board. must determine the PSRR in dB using Figure 37 at 250 kHz. To calculate the PSRR for a given R , such that the units of PSRR LOAD One factor that can measurably affect system performance is are converted from A/V to V/V, adjust the curve in Figure 37 by the ability of the DAC output to reject dc variations or ac noise the scaling factor 20 Ω log (R ). For instance, if R is 50 Ω, LOAD LOAD superimposed on the analog or digital dc power distribution. then the PSRR is reduced by 34 dB (that is, PSRR of the DAC at This is referred to as the power supply rejection ratio (PSRR). 250 kHz, which is 85 dB in Figure 37, becomes 51 dB V /V ). OUT IN For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with Proper grounding and decoupling should be a primary the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies objective in any high speed, high resolution system. The is common in applications where the power distribution is AD9740 features separate analog and digital supplies and generated by a switching power supply. Typically, switching ground pins to optimize the management of analog and digital power supply noise occurs over the spectrum from tens of ground currents in a system. In general, AVDD, the analog kilohertz to several megahertz. The PSRR vs. frequency of the supply, should be decoupled to ACOM, the analog common, as AD9740 AVDD supply over this frequency range is shown in close to the chip as physically possible. Similarly, DVDD, the Figure 37. digital supply, should be decoupled to DCOM as close to the chip as physically possible. 85 80 For those applications that require a single 3.3 V supply for both the analog and digital supplies, a clean analog supply can be 75 generated using the circuit shown in Figure 38. The circuit 70 consists of a differential LC filter with separate power supply dB)65 and return lines. Lower noise can be attained by using low ESR SRR (60 type electrolytic and tantalum capacitors. P FERRITE 55 BEADS 50 TTL/CMOS AVDD LOGIC 100μF 10μF–22μF 0.1μF CIRCUITS ELECT. TANT. CER. 45 ACOM 400 Figu2re 37. Pow4FeRr ESQupUpElNy6C RYe (jeMcHtzio)n8 Ratio (PS1R0R) 12 02911-035 POWE3R. 3SVUPPLY 02911-036 Figure 38. Differential LC Filter for Single 3.3 V Applications Rev. B | Page 19 of 32

AD9740 EVALUATION BOARD GENERAL DESCRIPTION This board allows the user the flexibility to operate the AD9740 in various configurations. Possible output configurations The TxDAC family evaluation boards allow for easy setup and include transformer coupled, resistor terminated, and single testing of any TxDAC product in the SOIC and LFCSP packages. and differential outputs. The digital inputs are designed to be Careful attention to layout and circuit design, combined with a driven from various word generators, with the on-board option prototyping area, allows the user to evaluate the AD9740 easily to add a resistor network for proper load termination. Provisions and effectively in any application where high resolution, high are also made to operate the AD9740 with either the internal or speed conversion is required. external reference or to exercise the power-down feature. J1 2 1 DB13X 4 3 DB12X 6 5 DB11X M M 8 7 O O DB10X C123456789 RP5 C 123456789 RP1 1102 191 DDBB98XX D1R2R3R4R5R6R7R8R9R10 OPT D1R2R3R4R5R6R7R8R9R10 OPT 14 13 16 15 DB7X DB13X 1RP3 22Ω16 DB13 18 17 DB6X DB12X 2RP3 22Ω15 DB12 20 19 DB5X DB11X 3RP3 22Ω14 DB11 22 21 DB4X DB10X 4RP3 22Ω13 DB10 24 23 DB3X DB9X 5RP3 22Ω12 DB9 26 25 DB2X DB8X 6RP3 22Ω11 DB8 28 27 DB1X DB7X 7RP3 22Ω10 DB7 30 29 DB0X DB6X 8RP3 22Ω9 DB6 32 31 DB5X 1RP4 22Ω16 DB5 34 33 JP3 DB4X 2RP4 22Ω15 DB4 36 35 CKEXTX DB3X 3RP4 22Ω14 DB3 38 37 DB2X 4RP4 22Ω13 DB2 40 39 DB1X 5RP4 22Ω12 DB1 DB0X 6RP4 22Ω11 DB0 7RP4 22Ω10 RIBBON CKEXTX 8RP4 22Ω9 CKEXT 1 234567890 1234567890 L2 BEAD REDTP2 DCOMR1R2R3R4R5R6R7R8R91 ORPPT6 DCOMR1R2R3R4R5R6R7R8R91 ORPPT2 TB1 1 DVDD +C4 C7 10μF C6 0.1μF BLK 25V 0.1μF BLK BLK TP4 TP7 TP8 TB1 2 RED L3 BEAD TP5 TB1 3 AVDD +C5 C9 10μF C8 TB1 4 0.1μF BLKTP6 25V 0.1μF BLKTP10 BLKTP9 02911-037 Figure 39. SOIC Evaluation Board—Power Supply and Digital Inputs Rev. B | Page 20 of 32

AD9740 AVDD CUT +C14 C16 C17 UNDER DUT 10μF 0.1μF 0.1μF 16V JP6 DVDD +C15 C18 C19 DVDD JP10 1106μVF 0.1μF 0.1μF R5 IX 1 A2 B 3 OPT S2 CLOCK IOUTA R11 CKEXT S5 10kΩ JP4 CLOCK DVDD TP1 R4 WHT 50Ω DDBB1132 12 DDBB1132 CDLOVDCDK 2287 DVDD 1R02kΩ OCP13T JP8 DB11 3 DB11 DCOM 26 JP2 IOUT 4 25 DB10 DB10 MODE DB9 5 DB9 AVDD 24 AVDD MODE 3 T1 4 6 23 DB8 DB8 RESERVED DDBB76 78 DDBB76 ADU91740 IIOOUUTTAB 2221 OPRT6 2 5 S3 DB5 9 DB5 ACOM 20 1 6 DB4 10 DB4 NC 19 T1-1T DB3 11 DB3 FSADJ 18 REF TP3 DDBB21 1123 DDBB21 RREEFFLIOO 1176 WHT C0.11μF C0.21μF C12 JP9 DB0 14 DB0 SLEEP 15 R1 0C.111μF AVDD OPT 2kΩ 2 AVDD 1 A B 3 SLEEP S1 1R01k0Ω EXT JP5 INT TP11 IOUTB WHT REF R103kΩ IY 1 AJ2P1B1 3 02911-038 Figure 40. SOIC Evaluation Board—Output Signal Conditioning Rev. B | Page 21 of 32

AD9740 02911-039 Figure 41. SOIC Evaluation Board—Primary Side 02911-040 Figure 42. SOIC Evaluation Board—Secondary Side Rev. B | Page 22 of 32

AD9740 02911-041 Figure 43. SOIC Evaluation Board—Ground Plane 02911-042 Figure 44. SOIC Evaluation Board—Power Plane Rev. B | Page 23 of 32

AD9740 02911-043 Figure 45. SOIC Evaluation Board Assembly—Primary Side 02911-044 Figure 46. SOIC Evaluation Board Assembly—Secondary Side Rev. B | Page 24 of 32

AD9740 RED L1BEAD TP12 TB1 1 CVDD 2 1 DB13X 4 3 BLK DB12X C3 C2 C10 6 5 0.1μF TP2 10μF 0.1μF DB11X 6.3V 8 7 DB10X TB1 2 10 D 9 DB9X U 12 O 11 DB8X R RED 14 SH 13 DB7X L2BEAD TP13 16 O 15 DB6X N TB3 1 DVDD 18 E 17 DB5X L 20 A 19 DB4X C7 BLK C4 C6 22 P M 21 DB3X 0.1μF TP4 160.3μVF 0.1μF 24 T U 23 DB2X TB3 2 26 GH 25 DB1X 28 AI 27 DB0X R RED 30 T 29 L3BEAD TP5 32 R S 31 TB4 1 AVDD 34 DE 33 JP3 A CKEXTX C9 BLK C5 C8 36 HE 35 0.1μF 10μF 0.1μF 38 37 TP6 6.3V 40 39 TB4 2 J1 R3 R4 R15 R16 R17 R18 R19 R20 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 1 RP3 22Ω16 DB13X DB13 2 RP3 22Ω15 DB12X DB12 3 RP3 22Ω14 DB11X DB11 4 RP3 22Ω13 DB10X DB10 5 RP3 22Ω12 DB9X DB9 6 RP3 22Ω11 DB8X DB8 7 RP3 22Ω10 DB7X DB7 8 RP3 22Ω 9 DB6X DB6 1 RP4 22Ω16 DB5X DB5 2 RP4 22Ω15 DB4X DB4 3 RP4 22Ω14 DB3X DB3 4 RP4 22Ω13 DB2X DB2 5 RP4 22Ω12 DB1X DB1 6 RP4 22Ω11 DB0X DB0 7 RP4 22Ω10 8 RP4 22Ω 9 CKEXTX CKEXT R21 R24 R25 R26 R27 R28 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 02911-045 Figure 47. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs Rev. B | Page 25 of 32

AD9740 AVDD DVDD CVDD C17 CC1199 C32 0.1μF 0.1μF 0.1μF SLEEP TP11 WHT R29 10kΩ DB7 1 DB7 DB8 32 DB8 DVDDBD6 23 DDVBD6D DDBB190 3301 DDBB910 R501k1Ω DB5 4 DB5 DB11 29 DB11 CD1N3P 5 28 DB4 DB4 DB12 DB12 DB3 6 DB3 DB13 27 DB13 DB2 7 DB2 DCOM1 26 TP3 TP1 JP8 DB1 8 DB1 SLEEP 25 WHT WHT IOUT DB0 9 DB0 FSADJ 24 10 23 11 DCOM U1 REFIO 22 3 T1 4 CVCDLKD 1123 CCLVKDD ACOIMA 2210 2 5 ASG3ND: 3, 4, 5 CLKB CLKB IB 6 14 CCOM ACOM1 19 1 15 CMODE AVDD 18 AVDD C11 T1– 1T CMODE 16 MODE AVDD1 17 0.1μF JP9 AD9740LFCSP DNP C12 TP7 R30 WHT 10kΩ CVDD R10 50Ω R1 2kΩ JP1 0.1% MODE 02911-046 Figure 48. LFCSP Evaluation Board Schematic—Output Signal Conditioning CVDD 1 7 U4 2 C20 C35 10μF 0.1μF AGND: 5 16V CVDD: 8 CVDD R5 120Ω 3 CLKB 6 JP2 U4 4 S5 CKEXT AGND: 3, 4, 5 AGND: 5 C34 CLK CVDD: 8 R2 0.1μF R6 120Ω 50Ω 02911-047 Figure 49. LFCSP Evaluation Board Schematic—Clock Input Rev. B | Page 26 of 32

AD9740 02911-048 Figure 50. LFCSP Evaluation Board Layout—Primary Side 02911-049 Figure 51. LFCSP Evaluation Board Layout—Secondary Side Rev. B | Page 27 of 32

AD9740 02911-050 Figure 52. LFCSP Evaluation Board Layout—Ground Plane 02911-051 Figure 53. LFCSP Evaluation Board Layout—Power Plane Rev. B | Page 28 of 32

AD9740 02911-052 Figure 54. LFCSP Evaluation Board Layout Assembly—Primary Side 02911-053 Figure 55. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev. B | Page 29 of 32

AD9740 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 COPL0A.1N0ARITY 00..3109 SEPALTAINNGE 00..2009 0° 00..6405 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 56. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1 14 10.00 (0.3937) 2.65 (0.1043) 0.75 (0.0295) ×45° 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0039) 8° COPL0A.1N0ARITY 1.27B (0S.C0500) 00..5311 ((00..00210212)) SPELAANTIENG 00..3230 ((00..00103709)) 0° 10..2470 ((00..00510507)) COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 57. 28-Lead Standard Small Outline Package [SOIC] Wide Body (RW-28) Dimensions shown in millimeters and (inches) Rev. B | Page 30 of 32

AD9740 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 PIN 1 24 1 INDICATOR 0.50 TOP 4.75 BSC EXPOSED 3.25 VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP 0.05 MAX 1.00 0.02 NOM 0.85 0.30 COPLANARITY 0.80 SEATING 0.23 0.20 REF 0.08 PLANE 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 58. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9740AR −40°C to +85°C 28-Lead Wide Body SOIC RW-28 AD9740ARRL −40°C to +85°C 28-Lead Wide Body SOIC RW-28 AD9740ARZ1 −40°C to +85°C 28-Lead Wide Body SOIC RW-28 AD9740ARZRL1 −40°C to +85°C 28-Lead Wide Body SOIC RW-28 AD9740ARU −40°C to +85°C 28-Lead TSSOP RU-28 AD9740ARURL7 −40°C to +85°C 28-Lead TSSOP RU-28 AD9740ARUZ1 −40°C to +85°C 28-Lead TSSOP RU-28 AD9740ARUZRL71 −40°C to +85°C 28-Lead TSSOP RU-28 AD9740ACP −40°C to +85°C 32-Lead LFCSP CP-32-2 AD9740ACPRL7 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 AD9740ACPZ1 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 AD9740ACPZRL71 −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2 AD9740-EB Evaluation Board (SOIC) AD9740ACP-PCB Evaluation Board (LFCSP) 1 Z = Pb-free part. Rev. B | Page 31 of 32

AD9740 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02911–0–12/05(B) Rev. B | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9740ACP-PCBZ AD9740ARUZ AD9740ARU AD9740ARZ AD9740ACPZ AD9740ACPZRL7 AD9740ARURL7 AD9740ARUZRL7 AD9740ARZRL AD9740WARUZRL7