Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs Data Sheet AD9523-1 FEATURES FUNCTIONAL BLOCK DIAGRAM Output frequency: <1 MHz to 1 GHz OSC_IN, OSC_IN Start-up frequency accuracy: <±100 ppm (determined by AD9523-1 OUT0, VCXO reference accuracy) OUT0 Zero delay operation RREEFFAA, OUT3, OUT3 Input-to-output edge timing: <150 ps RREEFFBB, PLL1 PLL2 DIV3I,D 4E, -5BY- 8 OUTPUTS OUT10, Dual VCO dividers OUT10 REF_TEST 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS OUT13, 14 dedicated output dividers with jitter-free adjustable delay OUT13 Adjustable delay: 63 resolution steps of ½ period of VCO output divider SCLK/SCL CONTROL OOUUTT44, SDIO/SDA INTERFACE Output-to-output skew: <50 ps SDO (SPIAND I2C) DIV3I,D 4E, -5BY- 6 OUTPUTS OUT9, Duty cycle correction for odd divider settings ZERO OUT9 DELAY Automatic synchronization of all outputs on power-up 14-CLOCK AbIsnotleugtrea otiuotnp ruatn jgitete: r1:2 < k1H50z tfos a2t0 1 M22H.z8 8 MHz EEPROM ZD_IN, ZD_IN DISTRIBUTION 09278-001 Broadband timing jitter: 124 fs Figure 1. Digital lock detect Nonvolatile EEPROM stores configuration settings GENERAL DESCRIPTION SPI- and I²C-compatible serial control port The AD9523-1 provides a low power, multi-output, clock Dual PLL architecture distribution function with low jitter performance, along with an PLL1 on-chip PLL and VCO with two VCO dividers. The on-chip VCO Low bandwidth for reference input clock cleanup with tunes from 2.94 GHz to 3.1 GHz. external VCXO Phase detector rate up to 130 MHz The AD9523-1 is designed to support the clock requirements Redundant reference inputs for long term evolution (LTE) and multicarrier GSM base Automatic and manual reference switchover modes station designs. It relies on an external VCXO to provide the Revertive and nonrevertive switching reference jitter cleanup to achieve the restrictive low phase noise Loss of reference detection with holdover mode requirements necessary for acceptable data converter SNR Low noise LVCMOS output from VCXO used for RF/IF performance. synthesizers The input receivers, oscillator, and zero delay receiver provide PLL2 both single-ended and differential operation. When connected Phase detector rate up to 259 MHz to a recovered system reference clock and a VCXO, the device Integrated low noise VCO generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). APPLICATIONS The frequency and phase of one clock output relative to another LTE and multicarrier GSM base stations clock output can be varied by means of a divider phase select Wireless and broadband infrastructure function that serves as a jitter-free, coarse timing adjustment Medical instrumentation in increments that are equal to half the period of the signal Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs coming out of the VCO. Low jitter, low phase noise clock distribution An in-package EEPROM can be programmed through the serial Clock generation and translation for SONET, 10Ge, 10G FC, interface to store user-defined register settings for power-up and other 10 Gbps protocols and chip reset. Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD9523-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 22 Applications ....................................................................................... 1 Detailed Block Diagram ............................................................ 22 Functional Block Diagram .............................................................. 1 Overview ..................................................................................... 22 General Description ......................................................................... 1 Component Blocks—Input PLL (PLL1) .................................. 23 Revision History ............................................................................... 3 Component Blocks—Output PLL (PLL2) .............................. 24 Specifications ..................................................................................... 4 Clock Distribution ..................................................................... 26 Conditions ..................................................................................... 4 Zero Delay Operation ................................................................ 28 Supply Current .............................................................................. 4 Lock Detect ................................................................................. 28 Power Dissipation ......................................................................... 6 Reset Modes ................................................................................ 28 REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, and ZD_IN, Power-Down Mode .................................................................... 29 ZD_IN Input Characteristics ...................................................... 7 Power Supply Sequencing ......................................................... 29 OSC_CTRL Output Characteristics .......................................... 7 Serial Control Port ......................................................................... 30 REF_TEST Input Characteristics ............................................... 7 SPI/I²C Port Selection ................................................................ 30 PLL1 Output Characteristics ...................................................... 8 I²C Serial Port Operation .......................................................... 30 OUT0, OUT0 to OUT13, OUT13 Distribution Output SPI Serial Port Operation .......................................................... 33 Characteristics .............................................................................. 8 SPI Instruction Word (16 Bits) ................................................. 34 Timing Alignment Characteristics ............................................ 9 SPI MSB/LSB First Transfers .................................................... 34 Jitter and Noise Characteristics ................................................ 10 EEPROM Operations ..................................................................... 37 PLL2 Characteristics .................................................................. 10 Writing to the EEPROM ........................................................... 37 Logic Input Pins—PD, SYNC, RESET, EEPROM_SEL, Reading from the EEPROM ..................................................... 37 REF_SEL ...................................................................................... 10 Programming the EEPROM Buffer Segment ......................... 38 Status Output Pins—STATUS1, STATUS0 ............................. 11 Device Initialization Flowcharts ................................................... 40 Serial Control Port—SPI Mode ................................................ 11 Power Dissipation and Thermal Considerations ....................... 43 Serial Control Port—I²C Mode ................................................ 12 Clock Speed and Driver Mode ................................................. 43 Absolute Maximum Ratings .......................................................... 13 Evaluation of Operating Conditions ........................................ 43 Thermal Resistance .................................................................... 13 Thermally Enhanced Package Mounting Guidelines ............ 44 ESD Caution ................................................................................ 13 Control Registers ............................................................................ 45 Pin Configuration and Function Descriptions ........................... 14 Control Register Map ................................................................ 45 Typical Performance Characteristics ........................................... 17 Control Register Map Bit Descriptions ................................... 50 Input/Output Termination Recommendations .......................... 20 Outline Dimensions ....................................................................... 63 Terminology .................................................................................... 21 Ordering Guide .......................................................................... 63 Rev. C | Page 2 of 63

Data Sheet AD9523-1 REVISION HISTORY 9/15—Rev. B to Rev. C 3/11—Rev. A to Rev. B Changes to Features Section ............................................................ 1 Added Table Summary, Table 8 ....................................................... 7 Added Junction Temperature, T Parameter, Table 1 ................... 4 Changes to Figure 24 ...................................................................... 21 J Changes to Table 7 ............................................................................ 8 Changes to EEPROM Operations Section and Writing to the Changes to Table 11 ........................................................................ 10 EEPROM Section ............................................................................ 35 Changes to Figure 23 ...................................................................... 20 Changes to Addr (Hex) 0x01A, Bits[4:3], Table 30 .................... 40 Changes to Overview Section ........................................................ 22 Changes to Bits[4:3], Table 40 ....................................................... 47 Added OSC_IN Input Section ....................................................... 23 Changes to PLL1 Loop Filter Section ........................................... 23 12/10—Rev. 0 to Rev. A Changed VCXO to OSC_IN, VCO Calibration Section ............ 25 Changes to General Description Section ....................................... 1 Changes to Clock Distribution Synchronization Section .......... 27 Changes to Frequency Range, Table 11 .......................................... 9 Changes to Zero Delay Operation Section .................................. 28 Changes to PLL2 General Description Section ........................... 23 Added Lock Detect Section and Reset Modes Section .............. 28 Changes to Table 47, Address 0x0F3, Bit 1 .................................. 48 Added Power-Down Mode Section and Power Supply Sequencing Section ......................................................................... 29 10/10—Revision 0: Initial Version Changes to Read Section ................................................................ 33 Changes to Writing to the EEPROM Section .............................. 37 Changes to Reading from the EEPROM Section and Programming the EEPROM Buffer Segment Section ................ 38 Added Device Initialization Flowcharts Section, Figure 46, and Figure 47; Renumbered Sequentially ............................................ 40 Changes to Power Dissipation and Thermal Considerations Section and Evaluation of Operating Conditions Section ......... 43 Changes to Example 2 Section....................................................... 44 Changes to Table 39 ........................................................................ 51 Changes to Table 46 ........................................................................ 54 Updated Outline Dimensions ........................................................ 63 Rev. C | Page 3 of 63

AD9523-1 Data Sheet SPECIFICATIONS f = 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, f = 2949.12 MHz, doubler is on, unless otherwise noted. VCXO VCO Typical is given for VDD = 3.3 V ± 5%, and T = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD and A T (−40°C to +85°C) variation, as listed in Table 1. A CONDITIONS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE VDD3_PLL, Supply Voltage for PLL1 and PLL2 3.135 3.3 3.465 V 3.3 V ± 5% VDD3_VCO, Supply Voltage for VCO 3.135 3.3 3.465 V 3.3 V ± 5% VDD3_REF, Supply Voltage Clock Output Drivers Reference 3.135 3.3 3.465 V 3.3 V ± 5% VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 3.135 3.3 3.465 V 3.3 V ± 5% VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers 1.768 1.8 1.832 V 1.8 V ± 5% AMBIENT TEMPERATURE RANGE, T −40 +25 +85 °C A JUNCTION TEMPERATURE, T +115 °C J 1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67, respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively). SUPPLY CURRENT Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS VDD3_PLL, Supply Voltage for PLL1 and PLL2 37 41.9 mA Decreases by 9 mA typical if REFB is turned off VDD3_VCO, Supply Voltage for VCO and VCO Divider M1 70 75.8 mA All outputs use VCO Divider M1 VDD3_REF, Supply Voltage Clock Output Drivers Reference VCO Divider M1 Enabled LVPECL Mode, LVDS Mode 4 5.1 mA Use VCO Divider M1; only one output driver is turned on; for each additional output that is turned on, the current increments by 1.2 mA maximum HSTL Mode, CMOS Mode 3 3.6 mA Use VCO Divider M1; values are independent of the number of outputs turned on VCO Divider M2 Enabled LVPECL Mode, LVDS Mode 26 30.1 mA Use VCO Divider M2; only one output driver is turned on; for each additional output that is turned on, the current increments by 1.2 mA maximum HSTL Mode, CMOS Mode 24.5 28.6 mA Use VCO Divider M2; values are independent of the number of outputs turned on VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers 3.2 5.8 mA Current for each divider: f = 122.88 MHz VDD1.8_OUT[x:y],1 Supply Voltage Clock Dividers 6.4 12 mA Current for each divider: f = 983.04 MHz CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF Channel x control register, Bit 4 = 0 LVDS Mode, 7 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11.5 13.2 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 40 45 mA f = 983.04 MHz LVDS Mode, 3.5 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 6.5 7.5 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 23 26.3 mA f = 983.04 MHz LVPECL Mode VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 13 14.4 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 41 46.5 mA f = 983.04 MHz Rev. C | Page 4 of 63

Data Sheet AD9523-1 Parameter Min Typ Max Unit Test Conditions/Comments HSTL Mode, 16 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 20 24.2 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 50 59.1 mA f = 983.04 MHz HSTL Mode, 8 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 14 16.7 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 42.5 49 mA f = 983.04 MHz CMOS Mode (Single-Ended) VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 2 2.4 mA f = 15.36 MHz, 10 pF Load CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON Channel x control register, Bit 4 = 1 LVDS Mode, 7 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 10 10.8 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 27 29.8 mA f = 983.04 MHz LVDS Mode, 3.5 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 6.5 7.5 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 23 26.3 mA f = 983.04 MHz LVPECL Mode VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11 12.4 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 28 31.2 mA f = 983.04 MHz HSTL Mode, 16 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 20 24.3 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 50 59.1 mA f = 983.04 MHz HSTL Mode, 8 mA VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 11 12.7 mA f = 122.88 MHz VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers 27 31.8 mA f = 983.04 MHz 1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67, respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively). Rev. C | Page 5 of 63

AD9523-1 Data Sheet POWER DISSIPATION Table 3. Parameter Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION Does not include power dissipated in termination resistors Typical Configuration 898 984.7 mW Clock distribution outputs running as follows: 7 LVPECL at 122.88 MHz, 3 LVDS (3.5 mA) at 61.44 MHz, 3 LVDS (3.5 mA) at 245.76 MHz, 1 single- ended CMOS 10 pF load at 122.88 MHz, 1 differential input reference at 30.72 MHz; f = 122.88 MHz, f = 2949.12 MHz, VCO Divider M1 VCXO VCO at 3, and VCO Divider M2 is off; PLL2 BW = 530 kHz PD, Power-Down 74 98.2 mW PD pin pulled low, with typical configuration conditions INCREMENTAL POWER DISSIPATION Base Typical Configuration 393 434.7 mW Absolute total power with clock distribution; 1 LVPECL output (OUT0) running at 122.88 MHz; 1 differential input reference at 30.72 MHz; f = 122.88 MHz, f = 2949.12 MHz, VCO Divider M1 at 3; VCO VCXO VCO Divider M2 is off Switched to One Input, −28.5 −8 mW Running at 30.72 MHz Reference Single-Ended Mode Switched to Two Inputs, 26 44.6 mW Running at 30.72 MHz Reference Differential Mode Switched to Two Inputs, −27.5 −5.1 mW Running at 30.72 MHz Reference Single-Ended Mode VCO Divider M2 76 88.3 mW Incremental power increase VCO Divider M2 (OUT4) from base typical Output Distribution, Driver On Incremental power increase (OUT1) from base typical LVDS Mode 3.5 mA 29 34.8 mW Single 3.5 mA LVDS output at 122.88 MHz 88 105.6 mW Single 3.5 mA LVDS output at 983.04 MHz 7 mA 43 50 mW Single 7 mA LVDS output at 122.88 MHz 141 164 mW Single 7 mA LVDS output at 983.04 MHz LVPECL Mode 46 51 mW Single LVPECL output at 122.88 MHz 144 159 mW Single LVPECL output at 983.04 MHz HSTL Mode 8 mA 44 51 mW Single 8 mA HSTL output at 122.88 MHz 143 165 mW Single 8 mA HSTL output at 983.04 MHz 16 mA 48 55 mW Single 16 mA HSTL output at 122.88 MHz 153 176 mW Single 16 mA HSTL output at 983.04 MHz CMOS Mode 6.6 7.9 mW Single 3.3 V CMOS output at 15.36 MHz 9.9 11.9 mW Dual complementary 3.3 V CMOS output at 15.36 MHz 9.9 11.9 mW Dual in-phase 3.3 V CMOS output at 15.36 MHz Output Distribution, Driver On Lower power mode on, (Channel x control register, Bit 4 = 1) LVDS Mode 3.5 mA 28.5 33.6 mW Single 3.5 mA LVDS output at 122.88 MHz 88 105.6 mW Single 3.5 mA LVDS output at 983.04 MHz 7 mA 37 42.9 mW Single 7 mA LVDS output at 122.88 MHz 98 113.7 mW Single 7 mA LVDS output at 983.04 MHz LVPECL Mode 40.5 46 mW Single LVPECL output at 122.88 MHz 100 110 mW Single LVPECL output at 983.04 MHz HSTL Mode 8 mA 34 39.1 mW Single 8 mA HSTL output at 122.88 MHz 94 108.1 mW Single 8 mA HSTL output at 983.04 MHz 16 mA 48 55.2 mW Single 16 mA HSTL output at 122.88 MHz 153 176 mW Single 16 mA HSTL output at 983.04 MHz Rev. C | Page 6 of 63

Data Sheet AD9523-1 REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments DIFFERENTIAL MODE Input Frequency Range 400 MHz Input Slew Rate (OSC_IN) 400 V/µs Minimum limit imposed for jitter performance Common-Mode Internally 0.6 0.7 0.8 V Generated Input Voltage Input Common-Mode Range 1.025 1.475 V For dc-coupled LVDS (maximum swing) Differential Input Voltage, 100 mV p-p Capacitive coupling required; can Sensitivity Frequency < 250 MHz accommodate single-ended input by ac grounding of unused input; instantaneous voltage on either pin must not exceed the 1.8 V dc supply rails Differential Input Voltage, 200 mV p-p Capacitive coupling required; can Sensitivity Frequency > 250 MHz accommodate single-ended input by ac grounding of unused input; instantaneous voltage on either pin must not exceed the 1.8 V dc supply rails Differential Input Resistance 4.8 kΩ Differential Input Capacitance 1 pF Duty Cycle Duty cycle limits are set by pulse width high and pulse width low Pulse Width Low 1 ns Pulse Width High 1 ns CMOS MODE, SINGLE-ENDED INPUT Input Frequency Range 250 MHz Input High Voltage 2.0 V Input Low Voltage 0.8 V Input Capacitance 1 pF Duty Cycle Duty cycle limits are set by pulse width high and pulse width low Pulse Width Low 1.6 ns Pulse Width High 1.6 ns OSC_CTRL OUTPUT CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT VOLTAGE High VDD3_PLL − 0.15 V R > 20 kΩ LOAD Low 150 mV REF_TEST INPUT CHARACTERISTICS Table 6. Parameter Min Typ Max Unit Test Conditions/Comments REF_TEST INPUT Input Frequency Range 250 MHz Input High Voltage 2.0 V Input Low Voltage 0.8 V Rev. C | Page 7 of 63

AD9523-1 Data Sheet PLL1 OUTPUT CHARACTERISTICS Table 7. Parameter1 Min Typ Max Unit Test Conditions/Comments MAXIMUM OUTPUT FREQUENCY 250 MHz Rise Time/Fall Time (20% to 80%) 387 665 ps 15 pF load Duty Cycle 45 50 55 % f = 250 MHz OUTPUT VOLTAGE HIGH Output driver static VDD3_PLL − 0.25 V Load current = 10 mA VDD3_PLL − 0.1 V Load current = 1 mA OUTPUT VOLTAGE LOW Output driver static 0.2 V Load current = 10 mA 0.1 V Load current = 1 mA MAXIMUM PFD FREQUENCY Antibacklash Pulse Width High is the initial PLL1 antibacklash pulse width setting. The user must program Register 0x019[4] = 1b to enable SPI control of the antibacklash pulse width to the setting defined in Register 0x019[3:2] and Table 39. Minimum 130 MHz Low 90 MHz High 65 MHz Maximum 45 MHz 1 CMOS driver strength: strong (see Table 52). OUT0, OUT0 TO OUT13, OUT13 DISTRIBUTION OUTPUT CHARACTERISTICS Duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (For example, for Channel 0, 0x190[7] = 1 and 0x192[7:2] = 1.) Table 8. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL MODE Maximum Output Frequency 1 GHz Minimum VCO/maximum dividers Rise Time/Fall Time (20% to 80%) 117 147 ps 100 Ω termination across output pair Duty Cycle 47 50 52 % f < 500 MHz 43 48 52 % f = 500 MHz to 800 MHz 40 49 54 % f = 800 MHz to 1 GHz Differential Output Voltage Swing 643 775 924 mV Magnitude of voltage across pins; output driver static Common-Mode Output Voltage VDD – 1.5 VDD − 1.4 VDD − 1.25 V Output driver static SCALED HSTL MODE, 16 mA Maximum Output Frequency 1 GHz Minimum VCO/maximum dividers Rise Time/Fall Time (20% to 80%) 112 141 ps 100 Ω termination across output pair Duty Cycle 47 50 52 % f < 500 MHz 44 48 51 % f = 500 MHz to 800 MHz 40 49 54 % f = 800 MHz to 1 GHz Differential Output Voltage Swing 1.3 1.6 1.7 mV Nominal supply Supply Sensitivity 0.6 mV/ Change in output swing vs. mV VDD3_OUT[x:y] (ΔV /ΔVDD3) OD Common-Mode Output Voltage VDD − 1.76 VDD − 1.6 VDD − 1.42 V Rev. C | Page 8 of 63

Data Sheet AD9523-1 Parameter Min Typ Max Unit Test Conditions/Comments LVDS MODE, 3.5 mA Maximum Output Frequency 1 GHz Rise Time/Fall Time (20% to 80%) 138 161 ps 100 Ω termination across output pair Duty Cycle 48 51 53 % f < 500 MHz 43 49 53 % f = 500 MHz to 800 MHz 41 49 55 % f = 800 MHz to 1 GHz Differential Output Voltage Swing Balanced 247 454 mV Voltage swing between output pins; output driver static Unbalanced 50 mV Absolute difference between voltage swing of normal pin and inverted pin Common-Mode Output Voltage 1.125 1.375 V Output driver static Common-Mode Difference 50 mV Voltage difference between output pins; output driver static Short-Circuit Output Current 3.5 24 mA Output driver static CMOS MODE Maximum Output Frequency 250 MHz Rise Time/Fall Time (20% to 80%) 387 665 ps 15 pF load Duty Cycle 45 50 55 % f = 250 MHz Output Voltage High Output driver static VDD − 0.25 V Load current = 10 mA VDD − 0.1 V Load current = 1 mA Output Voltage Low Output driver static 0.2 V Load current = 10 mA 0.1 V Load current = 1 mA TIMING ALIGNMENT CHARACTERISTICS Table 9. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT TIMING SKEW Delay off on all outputs; maximum deviation between rising edges of outputs; all outputs are on, unless otherwise noted Between Outputs in Same Group1 LVPECL, HSTL, and LVDS Between LVPECL, HSTL, and 30 183 ps LVDS Outputs CMOS Between CMOS Outputs 100 300 ps Single-ended, true phase, high-Z mode Mean Delta Between Groups1 50 Adjustable Delay 0 63 Steps Resolution step; for example, 8 × 0.5/1 GHz Resolution Step 500 ps ½ period of 1 GHz Zero Delay Between Input Clock Edge on 150 500 ps PLL1 settings: PFD = 7.68 MHz, I = 63.5 µA, CP REFA or REFB to ZD_IN Input R = 10 kΩ, antibacklash pulse width is ZERO Clock Edge, External Zero at maximum, BW = 40 Hz, REFA and Delay Mode ZD_IN are set to differential mode 1 There are three groups of outputs. They are as follows: the top outputs group, consisting of OUT0, OUT1, OUT2, and OUT3; the right outputs group, consisting of OUT4, OUT5, OUT6, OUT7, OUT8, and OUT9; and the bottom outputs group, consisting of OUT10, OUT11, OUT12, and OUT13. Rev. C | Page 9 of 63

AD9523-1 Data Sheet JITTER AND NOISE CHARACTERISTICS Table 10. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT ABSOLUTE RMS TIME JITTER Application example based on a typical setup (see Table 3); f = 122.88 MHz LVPECL Mode, HSTL Mode, LVDS Mode 109 fs Integrated BW = 200 kHz to 5 MHz 115 fs Integrated BW = 200 kHz to 10 MHz 150 fs Integrated BW = 12 kHz to 20 MHz 177 fs Integrated BW = 10 kHz to 61 MHz 187 fs Integrated BW = 1 kHz to 61 MHz 124 fs Integrated BW = 1 MHz to 61 MHz PLL2 CHARACTERISTICS Table 11. Parameter Min Typ Max Unit Test Conditions/Comments VCO (ON CHIP) Frequency Range 2940 3100 MHz Gain 45 MHz/V PLL2 FIGURE OF MERIT (FOM) −226 dBc/Hz MAXIMUM PFD FREQUENCY Antibacklash Pulse Width High is the initial PLL2 antibacklash pulse width setting. The user must program Register 0x019[4] = 1b to enable SPI control of the antibacklash pulse width to the setting defined in Register 0x00F2[3:2] and Table 46. Minimum 259 MHz Low 200 MHz High 135 MHz Maximum 80 MHz LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL Table 12. Parameter Min Typ Max Unit Test Conditions/Comments VOLTAGE Input High 2.0 V Input Low 0.8 V INPUT LOW CURRENT ±80 ±250 µA The minus sign indicates that, due to the internal pull-up resistor, current is flowing out of the AD9523-1 CAPACITANCE 3 pF RESET TIMING Pulse Width Low 50 ns Inactive to Start of Register 100 ns Programming SYNC TIMING Pulse Width Low 1.5 ns High speed clock is the CLK input signal Rev. C | Page 10 of 63

Data Sheet AD9523-1 STATUS OUTPUT PINS—STATUS1, STATUS0 Table 13. Parameter Min Typ Max Unit Test Conditions/Comments VOLTAGE Output High 2.94 V Output Low 0.4 V SERIAL CONTROL PORT—SPI MODE Table 14. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 40 kΩ pull-up resistor Voltage Input Logic 1 2.0 V Input Logic 0 0.8 V Current Input Logic 1 30 µA Input Logic 0 −110 µA The minus sign indicates that, due to the internal pull-up resistor, current is flowing out of the AD9523-1 Input Capacitance 2 pF SCLK (INPUT) IN SPI MODE SCLK has an internal 40 kΩ pull-down resistor in SPI mode but not in I2C mode Voltage Input Logic 1 2.0 V Input Logic 0 0.8 V Current Input Logic 1 240 µA Input Logic 0 1 µA Input Capacitance 2 pF SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE) Voltage Input Logic 1 2.0 V Input Logic 0 0.8 V Current Input Logic 1 1 µA Input Logic 0 1 µA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/t ) 25 MHz SCLK Pulse Width High, t 8 ns HIGH Pulse Width Low, t 12 ns LOW SDIO to SCLK Setup, t 3.3 ns DS SCLK to SDIO Hold, t 0 ns DH SCLK to Valid SDIO and SDO, t 14 ns DV CS to SCLK Setup, tS 10 ns CS to SCLK Setup and Hold, tS, tC 0 ns CS Minimum Pulse Width High, tPWH 6 ns Rev. C | Page 11 of 63

AD9523-1 Data Sheet SERIAL CONTROL PORT—I²C MODE VDD = VDD3_REF, unless otherwise noted. Table 15. Parameter Min Typ Max Unit Test Conditions/Comments SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage 0.7 × VDD V Input Logic 0 Voltage 0.3 × VDD V Input Current with an Input Voltage Between −10 +10 µA 0.1 × VDD and 0.9 × VDD Hysteresis of Schmitt Trigger Inputs 0.015 × VDD V Pulse Width of Spikes That Must Be 50 ns Suppressed by the Input Filter, t SPIKE SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current 0.4 V Output Fall Time from VIH to VIL with 20 + 0.1 C1 250 ns MIN MAX B a Bus Capacitance from 10 pF to 400 pF TIMING Note that all I2C timing values are referred to VIH (0.3 × VDD) and VIL levels (0.7 × VDD) MIN MAX Clock Rate (SCL, f ) 400 kHz I2C Bus Free Time Between a Stop and Start 1.3 µs Condition, t IDLE Setup Time for a Repeated Start Condition, 0.6 µs t SET; STR Hold Time (Repeated) Start Condition, t 0.6 µs After this period, the first clock pulse is HLD; STR generated Setup Time for a Stop Condition, t 0.6 µs SET; STP Low Period of the SCL Clock, t 1.3 µs LOW High Period of the SCL Clock, t 0.6 µs HIGH SCL, SDA Rise Time, t 20 + 0.1 C 1 300 ns RISE B SCL, SDA Fall Time, t 20 + 0.1 C 1 300 ns FALL B Data Setup Time, t 100 ns SET; DAT Data Hold Time, t 100 880 ns This is a minor deviation from the original I²C HLD; DAT specification of 0 ns minimum2 Capacitive Load for Each Bus Line, C1 400 pF B 1 CB is the capacitance of one bus line in picofarads (pF). 2 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL falling edge. Rev. C | Page 12 of 63

Data Sheet AD9523-1 ABSOLUTE MAXIMUM RATINGS Table 16. THERMAL RESISTANCE Parameter Rating θ is specified for the worst-case conditions, that is, a device JA VDD3_PLL, VDD3_REF, VDD3_OUT[x:y], −0.3 V to +3.6 V soldered in a circuit board for surface-mount packages. LDO_VCO to GND REFA, REFA, REFB, REFB to GND −0.3 V to +3.6 V Table 17. Thermal Resistance SCLK/SCL, SDIO/SDA, SDO, CS to GND −0.3 V to +3.6 V Airflow OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, −0.3 V to +3.6 V Velocity Package Type (m/sec) θ 1, 2 θ 1, 3 θ 1, 4 Ψ 1, 2 Unit OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, JA JC JB JT OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, 72-Lead LFCSP, 0 21.3 1.7 12.6 0.1 °C/W OUT9, OUT9, OUT10, OUT10, OUT11, 10 mm × 1.0 20.1 0.2 °C/W 10 mm OUT11, OUT12, OUT12, OUT13, OUT13 2.5 18.1 0.3 °C/W to GND 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. SYNC, RESET, PD, REF_SEL to GND −0.3 V to +3.6 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. STATUS0, STATUS1 to GND −0.3 V to +3.6 V 4 Per JEDEC JESD51-8 (still air). SP0, SP1, EEPROM_SEL to GND −0.3 V to +3.6 V VDD1.8_OUT[x:y], LDO_PLL1, LDO_DIV_M1 2 V Additional power dissipation information can be found in the to GND Power Dissipation and Thermal Considerations section. Junction Temperature1 115°C ESD CAUTION Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C 1 See Table 17 for θJA. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 13 of 63

AD9523-1 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1] 3] LL1_OUTD_IND_INDD1.8_OUT[0:UT0UT0DD3_OUT[0:1]UT1UT1DD1.8_OUT[2:UT2UT2DD3_OUT[2:3]UT3UT3EPROM_SELTATUS0/SP0TATUS1/SP1 PZZVOOVOOVOOVOOESS 210987654321098765 777666666666655555 LDO_PLL1 1 PIN 1 54 VDD1.8_OUT[4:5] VDD3_PLL 2 INDICATOR 53 OUT4 REFA 3 52 OUT4 REFA 4 51 VDD3_OUT[4:5] REFB 5 50 OUT5 REFB 6 49 OUT5 LF1_EXT_CAP 7 48 VDD1.8_OUT[6:7] AD9523-1 OSC_CTRL 8 47 OUT6 OSC_IN 9 TOP VIEW 46 OUT6 OSC_IN 10 (Not to Scale) 45 VDD3_OUT[6:7] LF2_EXT_CAP 11 44 OUT7 LDO_VCO 12 43 OUT7 VDD3_VCO 13 42 VDD1.8_OUT[8:9] LDO_DIV_M1 14 41 OUT8 PD 15 40 OUT8 REF_SEL 16 39 VDD3_OUT[8:9] SYNC 17 38 OUT9 VDD3_REF 18 37 OUT9 901234567890123456 122222222223333333 RESETCSSCLK/SCLSDIO/SDASDOREF_TESTOUT13OUT13OUT[12:13]OUT12OUT12OUT[12:13]OUT11OUT11OUT[10:11]OUT10OUT10OUT[10:11] _ _ _ _ 3 8 3 8 DD D1. DD D1. V D V D V V NOTES 1. ATTOHNED T HEHXEEPAAOTN SADELISDOSPGIPA GADTRDIOOLEUN N,I SND O TOHISFE ET G,HARENO DPU CMNBDET CCOHO AENNNNISCEUACRTLEI OS PTNRR OOENPN EGTRHT HEF UBCNEHCNIPTE.I FOITINT MSAU.LSITTY BE SOLDERED 09278-002 Figure 2. Pin Configuration Table 18. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1 LDO_PLL1 P/O 1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 μF decoupling capacitor from this pin to ground. Note that for best performance, the LDO bypass capacitor must be placed in close proximity to the device. 2 VDD3_PLL P 3.3 V Supply PLL1 and PLL2. Use the same supply as VCXO. 3 REFA I Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 4 REFA I Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input. 5 REFB I Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 6 REFB I Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 7 LF1_EXT_CAP O PLL1 External Loop Filter Capacitor. Connect this pin to ground. 8 OSC_CTRL O Oscillator Control Voltage. Connect this pin to the voltage control pin of the external oscillator. 9 OSC_IN I PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 10 OSC_IN I Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. Rev. C | Page 14 of 63

Data Sheet AD9523-1 Pin No. Mnemonic Type1 Description 11 LF2_EXT_CAP O PLL2 External Loop Filter Capacitor Connection. Connect capacitor to this pin and the LDO_VCO pin. 12 LDO_VCO P/O 2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 μF decoupling capacitor from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close proximity to the device. 13 VDD3_VCO P 3.3 V Supply for VCO and VCO M1 Divider. 14 LDO_DIV_M1 P/O 1.8 V LDO Regulator Decoupling Pin for VCO Divider M1. Connect a 0.47 μF decoupling capacitor from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close proximity to the device. 15 PD I Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor. 16 REF_SEL I Reference Input Select. This pin has an internal 40 kΩ pull-down resistor. 17 SYNC I Manual Synchronization. This pin initiates a manual synchronization and has an internal 40 kΩ pull- up resistor. 18 VDD3_REF P 3.3 V Supply for Output Clock Drivers Reference and VCO Divider M2. 19 RESET I Digital Input, Active Low. Resets internal logic to default states. This pin has an internal 40 kΩ pull-up resistor. 20 CS I Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor. 21 SCLK/SCL I Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial program- ming. This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode. 22 SDIO/SDA I/O Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I²C Mode (SDA). 23 SDO O Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There is no internal pull-up/pull-down resistor on this pin. 24 REF_TEST I Test Input to PLL1 Phase Detector. 25 OUT13 O Complementary Square Wave Clocking Output 13. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 26 OUT13 O Square Wave Clocking Output 13. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 27 VDD3_OUT[12:13] P 3.3 V Supply for Output 12 and Output 13 Clock Drivers. 28 OUT12 O Complementary Square Wave Clocking Output 12. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 29 OUT12 O Square Wave Clocking Output 12. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 30 VDD1.8_OUT[12:13] P 1.8 V Supply for Output 12 and Output 13 Clock Dividers. 31 OUT11 O Complementary Square Wave Clocking Output 11. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 32 OUT11 O Square Wave Clocking Output 11. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 33 VDD3_OUT[10:11] P 3.3 V Supply for Output 10 and Output 11 Clock Drivers. 34 OUT10 O Complementary Square Wave Clocking Output 10. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 35 OUT10 O Square Wave Clocking Output 10. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 36 VDD1.8_OUT[10:11] P 1.8 V Supply for Output 10 and Output 11 Clock Dividers. 37 OUT9 O Complementary Square Wave Clocking Output 9. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 38 OUT9 O Square Wave Clocking Output 9. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 39 VDD3_OUT[8:9] P 3.3 V Supply for Output 8 and Output 9 Clock Drivers. 40 OUT8 O Complementary Square Wave Clocking Output 8. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 41 OUT8 O Square Wave Clocking Output 8. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 42 VDD1.8_OUT[8:9] P 1.8 V Supply for Output 8 and Output 9 Clock Dividers. 43 OUT7 O Complementary Square Wave Clocking Output 7. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 44 OUT7 O Square Wave Clocking Output 7. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. Rev. C | Page 15 of 63

AD9523-1 Data Sheet Pin No. Mnemonic Type1 Description 45 VDD3_OUT[6:7] P 3.3 V Supply for Output 6 and Supply Output 7 Clock Drivers. 46 OUT6 O Complementary Square Wave Clocking Output 6. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 47 OUT6 O Square Wave Clocking Output 6. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 48 VDD1.8_OUT[6:7] P 1.8 V Supply for Output 6 and Output 7 Clock Dividers. 49 OUT5 O Complementary Square Wave Clocking Output 5. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 50 OUT5 O Square Wave Clocking Output 5. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 51 VDD3_OUT[4:5] P 3.3 V Supply for Output 4 and Output 5 Clock Drivers. 52 OUT4 O Complementary Square Wave Clocking Output 4. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 53 OUT4 O Square Wave Clocking Output 4. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 54 VDD1.8_OUT[4:5] P 1.8 V Supply for Output 4 and Output 5 Clock Dividers. 55 STATUS1/SP1 I/O Lock Detect and Other Status Signals (STATUS1)/I2C Address (SP1). This pin has an internal 40 kΩ pull- down resistor. 56 STATUS0/SP0 I/O Lock Detect and Other Status Signals (STATUS0)/I2C Address (SP0). This pin has an internal 40 kΩ pull- down resistor. 57 EEPROM_SEL I EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9523-1 to load the hard-coded default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor. 58 OUT3 O Complementary Square Wave Clocking Output 3. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 59 OUT3 O Square Wave Clocking Output 3. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 60 VDD3_OUT[2:3] P 3.3 V Supply for Output 2 and Output 3 Clock Drivers. 61 OUT2 O Complementary Square Wave Clocking Output 2. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 62 OUT2 O Square Wave Clocking Output 2. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 63 VDD1.8_OUT[2:3] P 1.8 V Supply for Output 2 and Output 3 Clock Dividers. 64 OUT1 O Complementary Square Wave Clocking Output 1. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 65 OUT1 O Square Wave Clocking Output 1. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 66 VDD3_OUT[0:1] P 3.3 V Supply for Output 0 and Output 1 Clock Drivers. 67 OUT0 O Complementary Square Wave Clocking Output 0. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a single-ended CMOS output. 68 OUT0 O Square Wave Clocking Output 0. This pin can be configured as one side of a differential LVPECL/ LVDS/HSTL output or as a single-ended CMOS output. 69 VDD1.8_OUT[0:1] P 1.8 V Supply for Output 0 and Output 1 Clock Dividers. 70 ZD_IN I External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 71 ZD_IN I Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 72 PLL1_OUT O Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in Register 0x1BA, Bit 4 (see Table 52). EP EP, GND GND Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1 P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground. Rev. C | Page 16 of 63

Data Sheet AD9523-1 TYPICAL PERFORMANCE CHARACTERISTICS f = 122.88 MHz, REFA differential at 30.72 MHz, f = 2949.12 MHz, and doubler is off, unless otherwise noted. VCXO VCO 60 45 40 50 35 HSTL = 16mA 40 30 A) A) m m CURRENT (2300 HSTL = 8mA CURRENT ( 122505 10 10 5 00 200 400FREQUE6N0C0Y (MHz8)00 1000 1200 09278-003 00 200 400FREQUE6N0C0Y (MHz8)00 1000 1200 09278-005 Figure 3. VDD3_OUT[x:y] Current (Typical) vs. Frequency; Figure 5. VDD3_OUT[x:y] Current (Typical) vs. Frequency, LVPECL Mode HSTL Mode at 16 mA and 8 mA 45 35 40 20pF 30 35 25 30 LVDS = 7mA 10pF mA) mA) 2pF T (25 T ( 20 N N E E RR20 RR 15 U U C C 15 LVDS = 3.5mA 10 10 5 5 0 0 0 200 400FREQUE6N0C0Y (MHz8)00 1000 1200 09278-004 0 100 200FREQUE3N0C0Y (MHz4)00 500 600 09278-006 Figure 4. VDD3_OUT[x:y] Current (Typical) vs. Frequency; Figure 6. VDD3_OUT[x:y] Current (Typical) vs. Frequency; LVDS Mode at 7 mA and 3.5 mA CMOS Mode at 20 pF, 10 pF, and 2 pF Load Rev. C | Page 17 of 63

AD9523-1 Data Sheet 3.5 4.0 2pF 3.0 3.5 HSTL = 16mA p) V p-2.5 3.0 10pF WING (2.0 E (V) 2.5 20pF TIAL S1.5 HSTL = 8mA PLITUD 2.0 EN AM 1.5 R E F1.0 F 1.0 DI 0.5 0.5 0 0 0 200 400FREQUE6N0C0Y (MHz8)00 1000 1200 09278-007 0 100 200FREQUE3N0C0Y (MHz4)00 500 600 09278-010 Figure 7. Differential Voltage Swing vs. Frequency; Figure 10. Amplitude vs. Frequency and Capacitive Load; HSTL Mode at 16 mA and 8 mA CMOS Mode at 2 pF, 10 pF, and 20 pF Load 1.6 1.4 p) p- 1.2 V NG ( 1.0 WI S L 0.8 1 A TI N E 0.6 R E F F 0.4 DI 0.2 00 200 40F0REQUE6N0C0Y (MHz8)00 1000 1200 09278-008 CH1 200mV 4 0 2.0.5GnSs//sDIV A CH1 104mV 09278-013 Figure 8. Differential Voltage Swing vs. Frequency, LVPECL Mode Figure 11. Output Waveform (Differential), LVPECL at 122.88 MHz 1.4 1.2 LVDS = 7mA p) V p- 1.0 G ( N WI 0.8 S L TIA 0.6 LVDS = 3.5mA 1 N E R E F 0.4 F DI 0.2 0 0 200 400FREQUE6N0C0Y (MHz8)00 1000 1200 09278-009 CH1 500mV Ω 4 0 2.0.5GnSs//sDIV A CH1 80mV 09278-049 Figure 9. Differential Voltage Swing vs. Frequency; Figure 12. Output Waveform (Differential), HSTL at 16 mA, 122.88 MHz LVDS Mode at 7 mA and 3.5 mA Rev. C | Page 18 of 63

Data Sheet AD9523-1 –80 –80 1: 1kHz, –120.0dBc/Hz 1: 1kHz, –123.1dBc/Hz 2: 10kHz, –130.6dBc/Hz 2: 10kHz, –133.8dBc/Hz –90 3: 100kHz, –137.4dBc/Hz –90 3: 100kHz, –140.5dBc/Hz 4: 1MHz, –145.7dBc/Hz 4: 1MHz, –149.0Bc/Hz –100 56:: 1400MMHHzz,, ––115690..63ddBBcc//HHzz –100 56:: 1400MMHHzz,, ––116612..51ddBBcc//HHzz 7: 800kHz, –143.7dBc/Hz 7: 800kHz, –146.9dBc/Hz Hz)–110 Hz)–110 c/ c/ B B d–120 d–120 OISE (–130 1 OISE (–130 1 N 2 N SE –140 3 7 SE –140 2 7 A A 3 PH–150 4 PH–150 NOISE: NOISE: 4 –160 ANALYSIS RANGE x: START 10kHz TO STOP 40MHz –160 ANALYSIS RANGE x: START 10kHz TO STOP 40MHz IRNMTSG NNOOIISSEE:: 1–7758..41µdRBAcD/40MHz 5 6 IRNMTSG NNOOIISSEE:: 1–2861..60µdRBAcD/40MHz 5 6 –170 10.0mdeg –170 7.3mdeg RMS JITTER: 151.4fsec RMS JITTER: 164.0fsec RESIDUAL FM: 2.1kHz RESIDUAL FM: 1.7kHz –180100 1k 10FkREQUE1N0C0Yk (Hz) 1M 10M 09278-113 –180100 1k F1R0EkQUENC1Y0 (0Hkz) 1M 10M 09278-014 Figure 13. Phase Noise, Output = 184.32 MHz Figure 15. Phase Noise, Output = 122.88 MHz (VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On (VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On –80 –80 1: 1kHz, –118.3dBc/Hz 1: 1kHz, –122.0Bc/Hz 2: 10kHz, –127.5dBc/Hz 2: 10kHz, –130.7dBc/Hz –90 3: 100kHz, –126.0dBc/Hz –90 3: 100kHz, –129.3dBc/Hz 4: 1MHz, –151.8dBc/Hz 4: 1MHz, –154.9dBc/Hz –100 56:: 1400MMHHzz,, ––115690..63ddBBcc//HHzz –100 56:: 1400MMHHzz,, ––116612..51ddBBcc//HHzz 7: 800kHz, –149.5dBc/Hz 7: 800kHz, –152.7dBc/Hz Hz)–110 Hz)–110 c/ c/ B B d–120 d–120 E ( 1 E ( 1 NOIS–130 2 3 NOIS–130 2 3 E –140 E –140 S S A 7 A PH–150 NOISE: PH–150 NAONAISLEY:SIS RANGE x: START 10kHz 7 ANALYSIS RANGE x: START 10kHz 4 TO STOP 40MHz –160 TO STOP 40MHz –160 INTG NOISE: –76.3dBc/40MHz 4 IRNMTSG NNOOIISSEE:: 3–1723..01µdRBAcD/40MHz 5 6 R M S N O I S E : 2 1172..04µmRdAeDg 5 6 –170 17.9mdeg –170 RMS JITTER: 281.1fsec RMS JITTER: 269.4fsec RESIDUAL FM: 1.6kHz RESIDUAL FM: 2.0kHz –180100 1k 10FkREQUE1N0C0Yk (Hz) 1M 10M 09278-012 –180100 1k F1R0EkQUENC1Y0 (0Hkz) 1M 10M 09278-015 Figure 14. Phase Noise, Output = 184.32 MHz Figure 16. Phase Noise, Output = 122.88 MHz (VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On; (VCXO = 122.88 MHz, Crystek VCXO CVHD-950); Doubler On; Optimized for Low 800 kHz Offset Noise Optimized for Low 800 kHz Offset Noise Rev. C | Page 19 of 63

AD9523-1 Data Sheet INPUT/OUTPUT TERMINATION RECOMMENDATIONS AD9523-1 0.1µF AD9523-1 0.1µF HIGH HIGH LVDS 100Ω IMPEDANCE DOWNSTREAM HSTL 100Ω IMPEDANCE DOWNSTREAM OUTPUT INPUT DEVICE OUTPUT INPUT DEVICE 0.1µF 09278-142 0.1µF 09278-046 Figure 17. AC-Coupled LVDS Output Driver Figure 21. AC-Coupled HSTL Output Driver AD9523-1 AD9523-1 HIGH HIGH LVDS 100Ω IMPEDANCE DOWNSTREAM HSTL 100Ω IMPEDANCE DOWNSTREAM OUTPUT INPUT DEVICE OUTPUT INPUT DEVICE 09278-143 09278-047 Figure 18. DC-Coupled LVDS Output Driver Figure 22. DC-Coupled HSTL Output Driver AD9523-1 0.1µF 0.1µF AD9523-1 LVPECL- HIGH SELF BIASED COMPATIBLE 100Ω IMPEDANCE DOWNSTREAM 100Ω REF, OSC_IN, OUTPUT INPUT DEVICE (OPTIONAL1) ZERO DELAY 0.1µF 09278-044 0.1µF INPUTS 1 RREESQIUSITROERD VTAELRUMEI NDAETPIEONND OSF U SPOOUNRCE. 09278-048 Figure 19. AC-Coupled LVPECL Output Driver Figure 23. REF, OSC_IN, and Zero Delay Input Differential Mode AD9523-1 LVPECL- HIGH COMPATIBLE 100Ω IMPEDANCE DOWNSTREAM OUTPUT INPUT DEVICE 09278-045 Figure 20. DC-Coupled LVPECL Output Driver Rev. C | Page 20 of 63

Data Sheet AD9523-1 TERMINOLOGY Phase Jitter and Phase Noise wave, the time jitter is a displacement of the edges from their An ideal sine wave can be thought of as having a continuous ideal (regular) times of occurrence. In both cases, the variations in and even progression of phase with time from 0° to 360° for timing from the ideal are the time jitter. Because these variations each cycle. Actual signals, however, display a certain amount are random in nature, the time jitter is specified in seconds root of variation from ideal phase progression over time. This mean square (rms) or 1 sigma of the Gaussian distribution. phenomenon is called phase jitter. Although many causes can Time jitter that occurs on a sampling clock for a DAC or an contribute to phase jitter, one major cause is random noise, ADC decreases the signal-to-noise ratio (SNR) and dynamic which is characterized statistically as being Gaussian (normal) range of the converter. A sampling clock with the lowest possible in distribution. jitter provides the highest performance from a given converter. This phase jitter leads to a spreading out of the energy of the Additive Phase Noise sine wave in the frequency domain, producing a continuous Additive phase noise is the amount of phase noise that is power spectrum. This power spectrum is usually reported as attributable to the device or subsystem being measured. a series of values whose units are dBc/Hz at a given offset in The phase noise of any external oscillators or clock sources is frequency from the sine wave (carrier). The value is a ratio subtracted. This makes it possible to predict the degree to which (expressed in decibels) of the power contained within a 1 Hz the device impacts the total system phase noise when used in bandwidth with respect to the power at the carrier frequency. conjunction with the various oscillators and clock sources, each For each measurement, the offset from the carrier frequency is of which contributes its own phase noise to the total. In many also given. cases, the phase noise of one element dominates the system It is meaningful to integrate the total power contained within phase noise. When there are multiple contributors to phase some interval of offset frequencies (for example, 10 kHz to noise, the total is the square root of the sum of squares of the 10 MHz). This is called the integrated phase noise over that individual contributors. frequency offset interval and can be readily related to the time Additive Time Jitter jitter due to the phase noise within that offset frequency interval. Additive time jitter is the amount of time jitter that is attributable to Phase noise has a detrimental effect on the performance of ADCs, the device or subsystem being measured. The time jitter of any DACs, and RF mixers. It lowers the achievable dynamic range of external oscillators or clock sources is subtracted. This makes the converters and mixers, although they are affected in somewhat it possible to predict the degree to which the device impacts the different ways. total system time jitter when used in conjunction with the various Time Jitter oscillators and clock sources, each of which contributes its own Phase noise is a frequency domain phenomenon. In the time time jitter to the total. In many cases, the time jitter of the external domain, the same effect is exhibited as time jitter. When observing oscillators and clock sources dominates the system time jitter. a sine wave, the time of successive zero crossings varies. In a square Rev. C | Page 21 of 63

AD9523-1 Data Sheet THEORY OF OPERATION DETAILED BLOCK DIAGRAM VCXO STATUS0/ STATUS1/ VDD3_PLL LDO_PLL1 LF1_EXT_CAP OSC_CTRL OSC_IN PLL1_OUT SP0 SP1 LF2_EXT_CAP LDO_VCO VDD1.8_OUT[x:y] VDD3_OUT[x:y] ÷D ED∆GtE OUT13 SELECT OUT13 ∆t OUT12 ÷D SEEDLEGCET OUT12 STATUS MONITOR ∆t OUT11 LSOECRKIA DLE PTOERCTT/ ÷D SEEDLEGCET OUT11 ADDRESS ∆t OUT10 REFA LOCK ÷D1 ÷D SEEDLEGCET OUT10 REFR_ESFEAL ÷R1 SWOVITECRH- DETECT LOOP LOCK M1 FANOUT ÷D SEEDL∆∆EGttCET OOOUUUTTT989 ÷R1 CONTROL FILTER DETECT ÷D SEEDLEGCET OUT8 REFB ∆t OUT7 REFB DPF CHPUAMRGPE ÷R2 ×2 DPF CHPUAMRGPE FLILOTOEPR VCO M2 FANOUT ÷D SEEDL∆EGtCET OOUUTT67 REF_TEST ÷R1 H) ÷D SEEDLEGCET OUT6 ÷N1 PLL1 PLL2 ÷N2 (TEST PAT ÷÷DD SEEEDDL∆∆EGGttCEET OOOUUUTTT545 SELECT OUT4 ∆t SDIO/SDA ÷D SEEDLEGCET OOUUTT33 SDO SCLK/SCCLS (SINCDTOIE NARTNFRDAO CI2LEC) ÷D SEEDL∆EGtCET OOUUTT22 RESPEDT ÷D SEEDL∆EGtCET OOUUTT11 ∆t OUT0 ÷D EDGE SELECT OUT0 EEPROM_SEL EEPROM ZD_IN AD9523-1 ZD_IN LDO_DIV_MI VDD3_VCO SYNC 09278-020 Figure 24. Top Level Diagram OVERVIEW A register setting determines what action to take if the failed reference is once again available: either stay on Reference B or The AD9523-1 is a clock generator that employs integer-N-based revert to Reference A. If neither reference is usable, the AD9523-1 phase-locked loops (PLL). The device architecture consists of two supports a holdover mode. A reference select pin (REF_SEL, cascaded PLL stages. The first stage, PLL1, consists of an integer Pin 16) is available to manually select which input reference is division PLL that uses an external voltage-controlled crystal active (see Table 42). The accuracy of the holdover is dependent oscillator (VCXO) from 15 MHz to 250 MHz. PLL1 has a narrow- on the external VCXO frequency stability at half supply voltage. loop bandwidth that provides initial jitter cleanup of the input reference signal. The second stage, PLL2, is a frequency Any of the divider settings are programmable via the serial multiplying PLL that translates the first stage output frequency programming port, enabling a wide range of input/output to a range of 2.94 GHz to 2.96 GHz. PLL2 incorporates an frequency ratios under program control. The dividers also integer-based feedback divider that enables integer frequency include a programmable delay to adjust timing of the output multiplication. Programmable integer dividers (1 to 1024) follow signals, if required. PLL2, establishing a final output frequency of 1 GHz or less. The 14 outputs are compatible with LVPECL, LVDS, HSTL, and The AD9523-1 includes reference signal processing blocks that 3.3 V CMOS logic levels (see the Input/Output Termination enable a smooth switching transition between two reference inputs. Recommendations section. All differential output logic settings This circuitry automatically detects the presence of the reference require a single 100 Ω differential termination. input signals. If only one input is present, the device uses it as The loop filters of each PLL are integrated and programmable. the active reference. If both are present, one becomes the active Only a single external capacitor for each of the two PLL loop reference and the other becomes the backup reference. If the active filters is required. reference fails, the circuitry automatically switches to the backup The AD9523-1 operates over the extended industrial temperature reference (if available), making it the new active reference. range of −40°C to +85°C. Rev. C | Page 22 of 63

Data Sheet AD9523-1 COMPONENT BLOCKS—INPUT PLL (PLL1) the external capacitor depends on the use of an external VCXO PLL1 General Description and the configuration parameters, such as input clock rate and desired bandwidth. Normally, a 0.3 µF capacitor allows the loop Fundamentally, the input PLL (referred to as PLL1) consists of bandwidth to range from 10 Hz to 100 Hz and ensures loop a phase-frequency detector (PFD), charge pump, passive loop filter, stability over the intended operating parameters of the device (see and an external VCXO operating in a closed loop (see Figure 26). Table 43 for R values). The operating loop bandwidth (LBW) ZERO PLL1 has the flexibility to operate with a loop bandwidth of of PLL1 can be used as a metric to estimate the time required for approximately 10 Hz to 100 Hz. This relatively narrow loop the PLL to phase lock. In general, PLL1 is phase locked within bandwidth gives the AD9523-1 the ability to suppress jitter that 10 loop bandwidth time constants, τ , where τ = 1/LBW. LBW LBW appears on the input references (REFA and REFB). The output Therefore, PLL_TO (see Figure 46) equals 10 × τ . LBW of PLL1 then becomes a low jitter phase-locked version of the reference input system clock. LF1_EXT_CAP LDO_PLL1 PLL1 Reference Clock Inputs AD9523-1 The AD9523-1 features two separate differential reference clock inputs, REFA and REFB. These inputs can be configured to RZERO operate in full differential mode or single-ended CMOS mode. CPOLE1 CPOLE2 In differential mode, these pins are internally self biased. If CHARGE OSC_CTRL RREEFFAB) o srh RoEulFdB b ies ddericvoeunp sleindg vleia- ean sdueidta, bthlee c uanpuacseitdo rs itdoe a ( RquEiFeAt , PUMP RPOLE2 BUFFER 1kΩ 0.3µF 09278-022 Figure 25. PLL1 Loop Filter ground. Figure 23 shows the equivalent circuit of REFA or REFB. It is possible to dc couple to these inputs, but the dc operation Table 19. PLL1 Loop Filter Programmable Values point should be set as specified in the Specifications tables. R C R C LF1_EXT_CAP1 ZERO POLE1 POLE2 POLE2 (kΩ) (nF) (kΩ) (nF) (µF) To operate either the REFA input or the REFB input in 3.3 V 883 1.5 fixed 165 fixed 0.337 fixed 0.3 CMOS mode, the user must set Bit 5 or Bit 6, respectively, in 677 Register 0x01A (see Table 40). The single-ended inputs can be 341 driven by either a dc-coupled CMOS level signal or an ac-coupled 135 sine wave or square wave. 10 The differential reference input receiver is powered down when External the differential reference input is not selected, or when the PLL is powered down. The single-ended buffers power down when 1 External loop filter capacitor. the PLL is powered down, when their respective individual power-down registers are set, or when the differential receiver is An external R-C low-pass filter should be used at the OSC_CTRL selected. output. The values shown in Figure 25 add an additional low- pass pole at ~530 Hz. This R-C network filters the noise The REFB R divider uses the same value as the REFA R divider associated with the OSC_CTRL buffer to achieve the best noise unless Bit 7, the enable REFB R divider independent division performance at the 1 kHz offset region. control bit in Register 0x01C, is programmed as shown in Table 42. LF1_EXT_CAP OSC_IN Input The OSC_IN receiver connects to the PLL1 feedback divider REFA DIVIDE-BY- REFA 1, 2, ...1023 and to the PLL2 PFD through an optional doubler. This input SWITCH- RZERO receiver is identical to the PLL1 REFA and REFB receivers. REF_SEL OVER CONTROL CFiognutrreo 2l 3b isths ofowrs t thhies rreecceoimvemr aerned leodc adtiefdfe rinen Rtieagl iisntepru 0t x01A[1:0]. RREEFFBB 1D,I V2,I D..E.1-B02Y3- DPF 0C.75HP µBUAAIMRT LGPSS,EB RPOLE2 OSC_VCCTRXOL termination to the OSC_IN receiver. 3.3V CMOS CPOLE1 CPOLE2 The OSC_IN receiver is powered down when the PLL1 power- DIFFOERR 1E.N8VTIAL down bit is set (Register 0x233[2] = 1b). When using the REF_TEST D1IV, I2D, E..-.B6Y3- 1D,I V2,I D..E.1-B02Y3- OSC_IN AD9523-1 in a mode of operation that bypasses PLL1, the PLL1 1.8V LDO power-down bit must be disabled (Register 0x233[2] = 0b). AD9523-1 PLL1 Loop Filter VDD3_PLL LDO_PLL1 09278-021 The PLL1 loop filter requires the connection of an external Figure 26. Input PLL (PLL1) Block Diagram capacitor from LF1_EXT_CAP (Pin 7) to ground. The value of Rev. C | Page 23 of 63

AD9523-1 Data Sheet PLL1 Input Dividers the charge pump tristates. The device continues operating in this mode until a reference signal becomes available. Then the device Each reference input feeds a dedicated reference divider block. exits holdover mode, and PLL1 resynchronizes with the active The input dividers provide division of the reference frequency reference. In addition to tristate, the charge pump can be forced in integer steps from 1 to 1023. They provide the bulk of the to VCC/2 during holdover (Register 0x01C, Bit 6; see Table 42). frequency prescaling that is necessary to reduce the reference frequency to accommodate the bandwidth that is typically COMPONENT BLOCKS—OUTPUT PLL (PLL2) desired for PLL1. PLL2 General Description PLL1 Reference Switchover The output PLL (referred to as PLL2) consists of an optional The reference monitor verifies the presence/absence of the input reference doubler, reference divider, phase-frequency prescaled REFA and REFB signals (that is, after division by the detector (PFD), a partially integrated analog loop filter (see input dividers). The status of the reference monitor guides the Figure 27), an integrated voltage-controlled oscillator (VCO), activity of the switchover control logic. The AD9523-1 supports and a feedback divider. The VCO produces a nominal 3.0 GHz automatic and manual PLL reference clock switching between signal with an output divider that is capable of division ratios of REFA (the REFA and REFA pins) and REFB (the REFB and 3, 4, and 5. REFB pins). This feature supports networking and infrastructure The PFD of the output PLL drives a charge pump that increases, applications that require redundant references. decreases, or holds constant the charge stored on the loop filter There are several configurable modes of reference switchover. The capacitors (both internal and external). The stored charge results manual switchover is achieved either via a programming register in a voltage that sets the output frequency of the VCO. The setting or by using the REF_SEL pin. The automatic switchover feedback loop of the PLL causes the VCO control voltage to occurs when REFA disappears and there is a reference on REFB. vary in a way that phase locks the PFD input signals. The reference automatic switchover can be set to work as follows: The gain of PLL2 is proportional to the current delivered by the charge pump. The loop filter bandwidth is chosen to reduce • Nonrevertive: stay on REFB. Switch from REFA to REFB noise contributions from PLL sources that could degrade phase when REFA disappears, but do not switch back to REFA noise requirements. if it reappears. If REFB disappears, then go back to REFA. • Revert to REFA. Switch from REFA to REFB when REFA The output PLL has a VCO with multiple bands spanning a range of 2.94 GHz to 3.1 GHz. However, the actual operating frequency disappears. Return to REFA from REFB when REFA returns. within a particular band depends on the control voltage that See Table 42 for the PLL1 miscellaneous control register bit settings. appears on the loop filter capacitor. The control voltage causes PLL1 Holdover the VCO output frequency to vary linearly within the selected band. This frequency variability allows the control loop of the In the absence of both input references, the device enters hold- output PLL to synchronize the VCO output signal with the over mode. Holdover is a secondary function that is provided reference signal applied to the PFD. Typically, the device by PLL1. Because PLL1 has an external VCXO available as a automatically selects the appropriate band as part of its frequency source, it continues to operate in the absence of the calibration process (invoked via the VCO control register input reference signals. When the device switches to holdover, at Address 0x0F3, shown in Table 47). PLL1_OUT VDD3_PLL LF2_EXT_CAP LDO_VCO VDD3_VCO LDO_DIV_M1 PLL CORE LDO LDO 1.9V RZERO DIVIDE-BY- PLL_1.8V 1, 2, 4, 8, 16 CPOLE1 CPOLE2 CHARGE PUMP M1 DIVIDRE2-BY- ×2 PFD 7 BITS, 3.5µA LSB RPOLE2 DIV3I,D 4E, -5B,Y- TO DIST/ 1, 2, 3...31 RESYNC M2 DIVIDE-BY- AD9523-1 3, 4, 5, TO DIST/ A/B DIVIDE-BY-4 RESYNC COUNTERS PRESCALER N DIVIDER 09278-023 VDD3_REF Figure 27. Output PLL (PLL2) Block Diagram Rev. C | Page 24 of 63

Data Sheet AD9523-1 Input 2× Frequency Multiplier VCO Divider M1 and VCO Divider M2 The 2× frequency multiplier provides the option to double the The VCO dividers provide frequency division between the internal frequency at the PLL2 input. This allows the user to take advantage VCO and the clock distribution. Each VCO divider can be set to of a higher frequency at the input to the PLL (PFD) and, thus, divide by 3, 4, or 5. When the AD9523-1 is used without any allows for reduced in-band phase noise and greater separation zero delay feedback (internal or external), the phase relationship between the frequency generated by the PLL and the modulation between the reference inputs and the outputs is a function of spur associated with PFD. However, increased reference spur the phase relationship between the OSC input and the reference separation results in harmonic spurs, introduced by the frequency inputs. Because the VCO divider is not reset by SYNC, there is multiplier, that increase as the duty cycle deviates from 50% at the an additional phase variability of up to x VCO periods, where OSC_IN inputs. As such, beneficial use of the frequency multiplier x = VCO divider setting. is application-specific. Typically, a VCXO with proper interfacing VCO Calibration has a duty cycle that is approximately 50% at the OSC_IN inputs. The AD9523-1 on-chip VCO must be manually calibrated to Note that the maximum output frequency of the 2× frequency ensure proper operation over process and temperature. This is multipliers must not exceed the maximum PFD rate that is accomplished by setting the calibrate VCO bit (Register 0x0F3, specified in Table 11. Bit 1) to 1. (This bit is not self clearing.) The setting can be PLL2 Feedback Divider performed as part of the initial setup before executing the PLL2 has a feedback divider (N divider) that enables it to provide IO_Update bit (Register 0x234, Bit 0 = 1). A readback bit, VCO integer frequency up-conversion. The PLL2 N divider is a com- calibration in progress (Register 0x22D, Bit 0), indicates when bination of a prescaler (P) and two counters, A and B. The total a VCO calibration is in progress by returning a logic true (that is, divider value is Bit 0 = 1). If the EEPROM is in use, setting the calibrate VCO bit to 1 before saving the register settings to the EEPROM ensures N = (P × B) + A that the VCO calibrates automatically after the EEPROM has where P = 4. loaded. After calibration, it is recommended that a sync be initiated The feedback divider is a dual modulus prescaler architecture, with (see the Clock Distribution Synchronization section). a nonprogrammable P that is equal to 4. The value of the B counter Note that the calibrate VCO bit defaults to 0. This bit must can be from 3 to 63, and the value of the A counter can be from 0 to 3. change from 0 to 1 to initiate a calibration sequence. Therefore, However, due to the architecture of the divider, there are constraints, any subsequent calibrations require the following sequence: as listed in Table 45. 1. Register 0x0F3, Bit 1 (calibrate VCO bit) = 0 PLL2 Loop Filter 2. Register 0x234, Bit 0 (IO_Update bit) = 1 The PLL2 loop filter requires the connection of an external 3. Register 0x0F3, Bit 1 (calibrate VCO bit) = 1 capacitor from LF2_EXT_CAP (Pin 11) to LDO_VCO (Pin 12), 4. Register 0x234, Bit 0 (IO_Update bit) = 1 as illustrated in Figure 27. The value of the external capacitor VCO calibration is controlled by a calibration controller that depends on the operating mode and the desired phase noise runs off the OSC_IN input clock. The calibration requires that performance. For example, a loop bandwidth of approximately PLL2 be set up properly to lock the PLL2 loop and that the 500 kHz produces the lowest integrated jitter. A lower bandwidth OSC_IN clock be present. produces lower phase noise at 1 MHz but increases the total integrated jitter. During power-up or reset, the distribution section is automatically held in sync until the first VCO calibration is finished. Therefore, Table 20. PLL2 Loop Filter Programmable Values no outputs can occur until VCO calibration is complete and PLL2 R C R C LF2_EXT_CAP1 ZERO POLE1 POLE2 POLE2 is locked. (Ω) (pF) (Ω) (pF) (pF) Initiate a VCO calibration under the following conditions: 3250 48 900 Fixed at 16 Typical at 1000 3000 40 450 • After changing any of the PLL2 B counter and A counter 2750 32 300 settings or after a change in the PLL2 reference clock 2500 24 225 frequency. This means that a VCO calibration should be 2250 16 initiated any time that a PLL2 register or reference clock 2100 8 changes such that a different VCO frequency is the result. 2000 0 • Whenever system calibration is desired. The VCO is designed 1850 to operate properly over extremes of temperature even 1 External loop filter capacitor. when it is first calibrated at the opposite extreme. However, a VCO calibration can be initiated at any time, if desired. Rev. C | Page 25 of 63

AD9523-1 Data Sheet CLOCK DISTRIBUTION If the output channel is ac-coupled to the circuit to be clocked, changing the mode varies the voltage swing to determine sensi- The clock distribution block provides an integrated solution for tivity to the drive level. For example, in LVDS mode, a current of generating multiple clock outputs based on frequency dividing 3.5 mA causes a 350 mV peak voltage. Likewise, in LVPECL mode, the PLL2 VCO divider output. OUT4 to OUT9 can use either a current of 8 mA causes an 800 mV peak voltage at the 100 Ω load VCO Divider M1 or VCO Divider M2, selectable via the register resistor. settings. The distribution output consists of 14 channels (OUT0 to OUT13). Each of the output channels has a dedicated divider In addition to the four mode bits, each of the 14 Channel 0 to and output driver, as shown in Figure 29. The AD9523-1 also has Channel 13 control registers includes the following control bits: the capability to route the VCXO output to four of the outputs • Invert divider output. Enables the user to choose between (OUT0 to OUT3). normal polarity and inverted polarity. Normal polarity is the Clock Dividers default state. Inverted polarity reverses the representation of The output clock distribution dividers are referred to as D0 to Logic 0 and Logic 1, regardless of the logic family. D13, corresponding to output channels OUT0 through OUT13, • Ignore sync. Makes the divider ignore the SYNC signal respectively. Each divider is programmable with 10 bits of division from any source. depth that is equal to 1 to 1024. Dividers have duty cycle correction • Power down channel. Powers down the entire channel. to always give 50% duty cycle, even for odd divides. • Lower power mode. Output Power-Down • Driver mode. • Channel divider. Each of the output channels offers independent control of the • Divider phase. power-down functionality via the Channel 0 to Channel 13 control registers (see Table 51). Each output channel has a dedicated VDD3_OUT[x:y] power-down bit for powering down the output driver. However, if all 14 outputs are powered down, the entire distribution output 1.25V LVDS enters a deep sleep mode. Although each channel has a channel VDD – 1.3V LVPECL HSTL 50Ω power-down control signal, it may sometimes be desirable to ENABLED CM power down an output driver while maintaining the divider’s synchronization with the other channel dividers. This is accom- COMMON MODE CIRCUIT plished by placing the output in tristate mode (this works in CMOS mode, as well). P Multimode Output Drivers N CM The user has independent control of the operating mode of each of the fourteen output channels via the Channel 0 to Channel 13 + – control registers (see Table 51). The operating mode control 100Ω LOAD includes the following: N P • Logic family and pin functionality • Output drive strength • Output polarity The four least significant bits (LSBs) of each of the 14 Channel 0 3.5mA/8mA to Channel 13 control registers comprise the driver mode bits. The LVDS/LVPECL 50Ω HENSTALBLED ENABLED mode value selects the desired logic family and pin functionality oalfl oanw so ua tcpoumt cmhoann n1e0l0, aΩs leisxtteedrn inal Traebsilset o5r1 .f oTrh aisll dthriev edri fdfeerseignnt 09278-031 Figure 28. Multimode Driver driver modes of operation that are illustrated in Figure 28. Rev. C | Page 26 of 63

Data Sheet AD9523-1 Clock Distribution Synchronization other when PLL2 is ready. The dividers support programmable phase offsets from 0 to 63 steps, in half periods of the input A block diagram of the clock distribution synchronization clock (for example, the VCO divider output clock). The phase functionality is shown in Figure 29. The synchronization offsets are incorporated into the dividers through a preset for the sequence begins with the primary synchronization signal, first output clock period of each divider. Phase offsets are which ultimately results in delivery of a synchronization strobe supported only by programming the initial phase and divide to the clock distribution logic. value and then issuing a sync to the distribution (automatically As indicated, the primary synchronization signal originates at startup or manually, if desired). from one of the following sources: When using the SYNC pin (Pin 17), there are 11 VCO divider  Direct synchronization source via the sync dividers bit output pipe line delays plus one period of the clock from the (see Table 55, Register 0x232, Bit 0) rising edge of SYNC to the clock output. There is at least one  Device pin, SYNC (Pin 17) extra VCO divider period of uncertainty because the SYNC An automatic synchronization of the divider is initiated the first signal and the VCO divider output are asynchronous. time that PLL2 locks after a power-up or reset event. Subsequent In normal operation, the phase offsets are already programmed lock/unlock events do not initiate a resynchronization of the through the EEPROM or the SPI/I2C port before the AD9523-1 distribution dividers unless they are preceded by a power-down starts to provide outputs. Although the user cannot adjust the or reset of the part. phase offsets while the dividers are operating, it is possible to Both sources of the primary synchronization signal are logic OR’d; adjust the phase of all the outputs together without powering therefore, any one of them can synchronize the clock distribution down PLL1 and PLL2. This is accomplished by programming output at any time. When using the sync dividers bit, the user the new phase offset, using Bits[7:2] in Register 0x192 (see Table 51) and then issuing a divide sync signal by using the first sets and then clears the bit. The synchronization event is the SYNC pin or the sync dividers bit (Register 0x232, Bit 0). clearing operation (that is, the Logic 1 to Logic 0 transition of the bit). The dividers are all automatically synchronized to each OUTx DIVIDE OUT DRIVER DIVIDER PHASE OUTx SYNC VCO OUTPUT DIVIDER FAN OUT SYNC (PIN 17) SYNC SYNC DIVIDERS BIT 09278-025 Figure 29. Clock Distribution Synchronization Block Diagram SYNC VCO DIVIDER OUTPUT CLOCK DIVIDE = 2, PHASE = 0 DIVIDE = 2, PHASE = 6 CONTROL 6 × 0.5 PERIODS 09278-026 Figure 30. Clock Output Synchronization Timing Diagram Rev. C | Page 27 of 63

AD9523-1 Data Sheet All outputs that are not programmed to ignore the sync are Bit 5 in Register 0x01B is used to select the external zero delay disabled temporarily while the sync is active. Note that, if mode. In external zero delay mode, OUT0 must be routed back an output is used for the zero delay path, it also disappears to PLL1 (the N divider) through the ZD_IN and ZD_IN pins. momentarily. However, this is desirable because it ensures PLL1 synchronizes the phase/edge of the feedback output clock that all the synchronized outputs have a deterministic phase with the phase/edge of the reference input. Because the channel relationship with respect to the zero delay output and, therefore, dividers are synchronized to each other, the clock outputs are also with respect to the input. synchronous with the reference input. Both the reference path ZERO DELAY OPERATION delay and the feedback delay from ZD_IN are designed to have the same propagation delay from the output drivers and PLL Zero delay operation aligns the phase of the output clocks with components to minimize the phase offset between the clock the phase of the external PLL reference input. The OUT0 output output and the reference input to achieve zero delay. is designed to be used as the output for zero delay. There are two zero delay modes on the AD9523-1: internal and external LOCK DETECT (see Figure 31). Note that the external delay mode provides The PLL1 and PLL2 lock detectors issue an unlock condition better matching than the internal delay mode because the when the frequency error is greater than the threshold of the output drivers are included in the zero delay path. lock detector. When the PLL is unlocked, there is a random Internal Zero Delay Mode phase between the reference clock and feedback clock. Due to The internal zero delay function of the AD9523-1 is achieved the random phase relationship that exists, the unlock condition by feeding the output of Channel Divider 0 back to the PLL1 can take between 215 × TPFD cycles to 1 × TPFD cycles. A lock N divider. Bit 5 in Register 0x01B is used to select internal zero condition always takes 216 × TPFD to lock, but can potentially delay mode (see Table 41). In the internal zero delay mode, take 231 × TPFD cycles depending on how big the phase jump is the output of Channel Divider 0 is routed back to the PLL1 and when it occurs in relation to the lock detect restart. (N divider) through a mux. PLL1 synchronizes the phase/edge RESET MODES of the output of Channel Divider 0 with the phase/edge of the The AD9523-1 has a power-on reset (POR) and several other ways reference input. to apply a reset condition to the chip. Because the channel dividers are synchronized to each other, Power-On Reset the outputs of the channel divider are synchronous with the reference input. During chip power-up, a power-on reset pulse is issued when the 3.3 V supply reaches ~2.6 V (<2.8 V) and restores the chip External Zero Delay Mode either to the setting stored in EEPROM (EEPROM pin = 1) or The external zero delay function of the AD9523-1 is achieved to the on-chip setting (EEPROM pin = 0). At power-on, the by feeding OUT0 back to the ZD_IN input and, ultimately, back AD9523-1 executes a sync operation, which brings the outputs to the PLL1 N divider. In Figure 31, the change in signal routing into phase alignment according to the default settings. The for external zero delay is external to the AD9523-1. output drivers are held in sync for the duration of the internally generated power-up sync timer (~70 ms). The outputs begin to toggle after this period. ZD_IN ZD_IN OUT0 OUT0 Reset via the RESET Pin RESET, a reset (an asynchronous hard reset is executed by briefly ENB pulling RESET low), restores the chip either to the setting stored in FEEDBACK DELAY EEPROM (EEPROM pin = 1) or to the on-chip setting (EEPROM INTERNAL FB pin = 0). A reset also executes a sync operation, which brings the REFA outputs into phase alignment according to the default settings. REFA When EEPROM is inactive (EEPROM pin = 0), it takes ~2 µs for PFD the outputs to begin toggling after RESET is issued. When REF DELAY EEPROM is active (EEPROM pin = 1), it takes ~40 ms for the AD9523-1 09278-027 outputs to toggle after RESET is brought high. Figure 31. Zero Delay Function Rev. C | Page 28 of 63

Data Sheet AD9523-1 Reset via the Serial Port POWER-DOWN MODE The serial port control register allows for a reset by setting Bit 2 Chip Power-Down via PD and Bit 5 in Register 0x000. When Bit 2 and Bit 5 are set, the chip Place the AD9523-1 into a power-down mode by pulling the enters a reset mode and restores the chip either to the setting PD pin low. Power-down turns off most of the functions and stored in EEPROM (EEPROM pin = 1) or to the on-chip setting currents inside the AD9523-1. The chip remains in this power- (EEPROM pin = 0), except for Register 0x000. Except for the down state until PD is returned to a logic high state. When self clearing bits, Bit 2 and Bit 5, Register 0x000 retains its taken out of power-down mode, the AD9523-1 returns to the previous value prior to reset. During the internal reset, the settings programmed into its registers prior to the power-down, outputs hold static. Bit 2 and Bit 5 are self clearing. However, unless the registers are changed by new programming while the the self clearing operation does not complete until an additional PD pin is held low. serial port SCLK cycle completes, and the AD9523-1 is held in reset until Bit 2 and Bit 5 self clear. POWER SUPPLY SEQUENCING Reset to Settings in EEPROM when EEPROM Pin = 0 via the The AD9523-1 has multiple power supply domains that operate Serial Port with 3.3 V, and the output supply domain that operates on 1.8 V. The serial port control register allows the chip to be reset to settings The 1.8 V supplies should be brought high and stable prior to or in EEPROM when the EEPROM pin = 0 via Register 0xB02[1]. simultaneously with the 3.3 V supplies to ensure proper device This bit is self clearing. This bit does not have any effect when operation. It is recommended to hold the RESETpin low while the EEPROM pin = 1. It takes ~40 ms for the outputs to begin both supply domains settle to ensure that the 3.3 V supplies do toggling after the SOFT_EEPROM register is cleared. not lead the 1.8 V supplies. Rev. C | Page 29 of 63

AD9523-1 Data Sheet SERIAL CONTROL PORT The AD9523-1 serial control port is a flexible, synchronous I2C Bus Characteristics serial communications port that allows an easy interface with Table 22. I2C Bus Definitions many industry-standard microcontrollers and microprocessors. Abbreviation Definition The AD9523-1 serial control port is compatible with most S Start synchronous transfer formats, including Philips I2C, Motorola® Sr Repeated start SPI, and Intel® SSR protocols. The AD9523-1 I2C implementation P Stop deviates from the classic I2C specification in two specifications, A Acknowledge and these deviations are documented in Table 15 of this data sheet. The serial control port allows read/write access to all A No acknowledge registers that configure the AD9523-1. W Write R Read SPI/I²C PORT SELECTION One pulse on the SCL clock line is generated for each data bit The AD9523-1 has two serial interfaces, SPI and I2C. Users can that is transferred. select either the SPI or I2C, depending on the states (logic high, logic low) of the two logic level input pins, SP1 and SP0, when The data on the SDA line must not change during the high period power is applied or after a RESET (each pin has an internal of the clock. The state of the data line can change only when the 40 kΩ pull-down resistor). When both SP1 and SP0 are low, clock on the SCL line is low. the SPI interface is active. Otherwise, I2C is active with three DATA LINE CHANGE STABLE; OF DATA different I2C slave address settings (seven bits wide), as shown DATA VALID ALLOWED in Table 21. The five MSBs of the slave address are hardware SDA coded as 11000, and the two LSBs are determined by the logic lTeavbellse o2f1 .t hSee rSiPal1 P aonrdt MSPo0d pe iSnesl.e ction SCL 09278-160 Figure 32. Valid Bit Transfer SP1 SP0 Address A start condition is a transition from high to low on the SDA Low Low SPI line while SCL is high. The start condition is always generated Low High I2C: 1100000 by the master to initialize the data transfer. High Low I2C: 1100001 High High I2C: 1100010 A stop condition is a transition from low to high on the SDA line while SCL is high. The stop condition is always generated I²C SERIAL PORT OPERATION by the master to end the data transfer. The AD9523-1 I2C port is based on the I2C fast mode standard. The AD9523-1 supports both I2C protocols: standard mode SDA (100 kHz) and fast mode (400 kHz). SCL The AD9523-1 I2C port has a 2-wire interface consisting of a serial S P dthaeta A liDne9 5(S2D3-A1) iasn cdo na nseercitaeld c ltooc kth lein see (rSiaCl Lb)u. sIn ( danat Ia2 Cbu bsu SsD syAs taenmd, COSNTDAIRTITON COSNTDOITPION 09278-161 Figure 33. Start and Stop Conditions clock bus SCL) as a slave device, meaning that no clock is generated by the AD9523-1. The AD9523-1 uses direct 16-bit (two bytes) A byte on the SDA line is always eight bits long. An acknowledge memory addressing instead of traditional 8-bit (one byte) memory bit must follow every byte. Bytes are sent MSB first. addressing. Rev. C | Page 30 of 63

Data Sheet AD9523-1 The acknowledge bit is the ninth bit attached to any 8-bit data Data is then sent over the serial bus in the format of nine clock byte (see Figure 34). An acknowledge bit is always generated by pulses, one data byte (eight bits) from either master (write mode) the receiving device (receiver) to inform the transmitter that the or slave (read mode), followed by an acknowledge bit from the byte has been received. It is accomplished by pulling the SDA receiving device. The number of bytes that can be transmitted per line low during the ninth clock pulse after each 8-bit data byte. transfer is unrestricted. In write mode, the first two data bytes immediately after the slave address byte are the internal memory The no acknowledge bit is the ninth bit attached to any 8-bit (control registers) address bytes with the high address byte first. data byte. A no acknowledge bit is always generated by the This addressing scheme gives a memory address of up to 216 − 1 = receiving device (receiver) to inform the transmitter that the 65,535. The data bytes after these two memory address bytes are byte has not been received. It is accomplished by leaving the SDA register data written into the control registers. In read mode, the line high during the ninth clock pulse after each 8-bit data byte. data bytes after the slave address byte are register data read from Data Transfer Process the control registers. A single I2C transfer can contain multiple data The master initiates data transfer by asserting a start condition. bytes that can be read from or written to control registers whose This indicates that a data stream follows. All I2C slave devices address is automatically incremented starting from the base connected to the serial bus respond to the start condition. memory address. The master then sends an 8-bit address byte over the SDA line, When all data bytes are read or written, stop conditions are consisting of a 7-bit slave address (MSB first), plus an R/W bit. established. In write mode, the master (transmitter) asserts This bit determines the direction of the data transfer, that is, a stop condition to end data transfer during the 10th clock pulse whether data is written to or read from the slave device following the acknowledge bit for the last data byte from the slave (0 = write, 1 = read). device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but The peripheral whose address corresponds to the transmitted does not pull it low during the ninth clock pulse. This is known as a address responds by sending an acknowledge bit. All other devices no acknowledge bit. Upon receiving the no acknowledge bit, the on the bus remain idle while the selected device waits for data slave device knows that the data transfer is finished and releases to be read from or written to it. If the R/W bit is 0, the master the SDA line. The master then takes the data line low during the (transmitter) writes to the slave device (receiver). If the R/W bit is 1, low period before the 10th clock pulse and high during the 10th the master (receiver) reads from the slave device (transmitter). clock pulse to assert a stop condition. The format for these commands is described in the Data Transfer Format section. SDA MSB ACKNOWLEDGE FROM ACKNOWLEDGE FROM SLAVE-RECEIVER SLAVE-RECEIVER SCL S 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 1P0 09278-162 Figure 34. Acknowledge Bit SDA MSB = 0 ACKNOWLEDGE FROM ACKNOWLEDGE FROM SLAVE-RECEIVER SLAVE-RECEIVER SCL S 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 1P0 09278-163 Figure 35. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration) SDA MSB = 1 ACKNOWLEDGE FROM NO ACKNOWLEDGE MASTER-RECEIVER FROM SLAVE-RECEIVER SCL S 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 1P0 09278-164 Figure 36. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration) Rev. C | Page 31 of 63

AD9523-1 Data Sheet A repeated start (Sr) condition can be used in place of a stop follows a write to Register 0x234, thereby ending the I2C transfer. condition. Furthermore, a start or stop condition can occur at For an I2C data read transfer containing multiple data bytes, any time; partially transferred bytes are discarded. the peripheral drives data bytes of 0x00 for subsequent reads that follow a read from Register 0x234. For an I2C data write transfer containing multiple data bytes, the peripheral drives a no acknowledge for the data byte that Data Transfer Format Send byte format. The send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P Write byte format. The write byte protocol is used to write a register address to the RAM, starting from the specified RAM address. RAM Address RAM Address RAM RAM RAM S Slave Address W A High Byte A Low Byte A Data 0 A Data 1 A Data 2 A P Receive byte format. The receive byte protocol is used to read the data byte(s) from the RAM, starting from the current address. S Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A P Read byte format. The combined format of the send byte and the receive byte. Slave RAM Address RAM Address Slave RAM RAM RAM S Address W A High Byte A Low Byte A Sr Address R A Data 0 A Data 1 A Data 2 A P I²C Serial Port Timing SDA tFALL tSET; DAT tFALL tHLD; STR tSPIKE tRISE tIDLE t t LOW RISE SCL S tHLD; STR tHLD; DAT tHIGH tSET; STR Sr tSET; STP P S 09278-165 Figure 37. I²C Serial Port Timing Table 23. I2C Timing Definitions Parameter Description f I²C clock frequency I2C t Bus idle time between stop and start conditions IDLE t Hold time for repeated start condition HLD; STR t Setup time for repeated start condition SET; STR t Setup time for stop condition SET; STP t Hold time for data HLD; DAT t Setup time for data SET; DAT t Duration of SCL clock low LOW t Duration of SCL clock high HIGH t SCL/SDA rise time RISE t SCL/SDA fall time FALL t Voltage spike pulse width that must be suppressed by the input filter SPIKE Rev. C | Page 32 of 63

Data Sheet AD9523-1 SPI SERIAL PORT OPERATION than eight SCLK cycles). Raising the CS pin on a nonbyte Pin Descriptions boundary terminates the serial transfer and flushes the buffer. SCLK (serial clock) is the serial shift clock. This pin is an input. In streaming mode (see Table 24), any number of data bytes can SCLK is used to synchronize serial control port reads and writes. be transferred in a continuous stream. The register address is Write data bits are registered on the rising edge of this clock, automatically incremented or decremented (see the SPI MSB/LSB and read data bits are registered on the falling edge. This pin is First Transfers section). CS must be raised at the end of the last internally pulled down by a 40 kΩ resistor to ground. byte to be transferred, thereby ending streaming mode. SDIO (serial data input/output) is a dual-purpose pin and acts Communication Cycle—Instruction Plus Data either as an input only (unidirectional mode) or as an input/ There are two parts to a communication cycle with the output (bidirectional mode). The AD9523-1 defaults to the AD9523-1. The first part writes a 16-bit instruction word into bidirectional I/O mode. the AD9523-1, coincident with the first 16 SCLK rising edges. SDO (serial data out) is used only in the unidirectional I/O mode The instruction word provides the AD9523-1 serial control port as a separate output pin for reading back data. SDO is always with information regarding the data transfer, which is the active; therefore, the unidirectional I/O mode should not be second part of the communication cycle. The instruction word used in a multislave environment. defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting CS (chip select bar) is an active low control that gates the read register address for the first byte of the data transfer. and write cycles. When CS is high, SDIO is in a high impedance Write state. This pin is internally pulled up by a 40 kΩ resistor to VDD3_REF. If the instruction word is for a write operation, the second part is the transfer of data into the serial control port buffer of the AD9523-1. Data bits are registered on the rising edge of SCLK. CS AD9523-1 The length of the transfer (one, two, or three bytes or streaming SCLK/SCL SERIAL mode) is indicated by two bits (W1, W0) in the instruction byte. CONTROL SDIO/SDA PORT When the transfer is one, two, or three bytes but not streaming, CS SDO 09278-034 c(eaxnc beep tr aaifsteedr athftee rla esat cbhy tsee,q wuehnercee iot fe enidghs tt hbeit sc ytcol es)ta. Wll thheen b tuhse bus Figure 38. Serial Control Port is stalled, the serial transfer resumes when CS is lowered. Raising SPI Mode Operation the CS pin on a nonbyte boundary resets the serial control port. During a write, streaming mode does not skip over reserved or In SPI mode, single or multiple byte transfers are supported, blank registers, and the user can write 0x00 to the reserved as well as MSB first or LSB first transfer formats. The AD9523-1 register addresses. serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/ Because data is written into a serial control port buffer area, and SDO). By default, the AD9523-1 is in bidirectional mode. Short not directly into the actual control registers of the AD9523-1, an instruction mode (8-bit instructions) is not supported. Only additional operation is needed to transfer the serial control port long (16-bit) instruction mode is supported. buffer contents to the actual control registers of the AD9523-1, thereby causing them to become active. The update registers A write or a read operation to the AD9523-1 is initiated by operation consists of setting the self clearing IO_Update bit, pulling CS low. Bit 0 of Register 0x234 (see Table 57). Any number of data bytes The CS stalled high mode is supported in data transfers where can be changed before executing an update registers operation. three or fewer bytes of data (plus instruction data) are transferred The update registers simultaneously actuates all register changes (see Table 24). In this mode, the CS pin can temporarily return that have been written to the buffer since any previous update. high on any byte boundary, allowing time for the system controller Read to process the next byte. CS can go high only on byte boundaries; The AD9523-1 supports only the long instruction mode. If the however, it can go high during either phase (instruction or data) instruction word is for a read operation, the next N × 8 SCLK of the transfer. cycles clock out the data from the address specified in the During this period, the serial control port state machine enters instruction word, where N is 1 to 3 as determined by Bits[W1:W0]. a wait state until all data is sent. If the system controller decides If N = 4, the read operation is in streaming mode, continuing to abort the transfer before all of the data is sent, the state machine until CS is raised. During an SPI read, serial data on SDIO (or must be reset either by completing the remaining transfers or by SDO, in 4-wire mode) transitions on the SCLK falling edge, and returning CS low for at least one complete SCLK cycle (but fewer is normally sampled on the SCLK rising edge. To read the last bit correctly, the SPI host must be able to tolerate a zero hold Rev. C | Page 33 of 63

AD9523-1 Data Sheet time. In cases where zero hold time is not possible, the user can SPI MSB/LSB FIRST TRANSFERS either use streaming mode and delay the rising edge of CS, or The AD9523-1 instruction word and byte data can be MSB first sample the serial data on the SCLK falling edge. However, to or LSB first. Any data written to Register 0x000 must be mirrored: sample the data correctly on the SCLK falling edge, the user must Bit 7 is mirrored to Bit 0, Bit 6 to Bit 1, Bit 5 to Bit 2, and Bit 4 to ensure that the setup time is greater than t (time data valid). DV Bit 3. This makes it irrelevant whether LSB first or MSB first is Streaming mode does not skip over reserved or blank registers. in effect. The default for the AD9523-1 is MSB first. The default mode of the AD9523-1 serial control port is the When LSB first is set by Register 0x000, Bit 1, and Register 0x000, bidirectional mode. In bidirectional mode, both the sent data Bit 6, it takes effect immediately because it affects only the and the readback data appear on the SDIO pin. It is also possible operation of the serial control port and does not require that to set the AD9523-1 to unidirectional mode. In unidirectional an update be executed. mode, the readback data appears on the SDO pin. When MSB first mode is active, the instruction and data bytes A readback request reads the data that is in the serial control port must be written from MSB to LSB. Multibyte data transfers in buffer area or the data that is in the active registers (see Figure 39). MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow in order from the high address to the CS low address. In MSB first mode, the serial control port internal SCLK/SCL SERIAL address generator decrements for each data byte of the CONTROL SDIO/SDA PORT multibyte transfer cycle. SDO UPDATE REGISTERS When LSB first mode is active, the instruction and data bytes REBGUIFSFTEERRS REAGCISTITVEERS 09278-035 mLSuBs tf ibrest w forritmteant fsrtoamrt wLSitBh taon M inSsBtr.u Mctuioltnib byytete d tahtaat tirnacnlsufderess itnh e Figure 39. Relationship Between Serial Control Port Buffer Registers and register address of the least significant data byte, followed by Active Registers multiple data bytes. In a multibyte transfer cycle, the internal SPI INSTRUCTION WORD (16 BITS) byte address generator of the serial port increments for each byte. The AD9523-1 serial control port register address decrements The MSB of the instruction word is R/W, which indicates from the register address just written toward 0x000 for whether the instruction is a read or a write. The next two bits multibyte I/O operations if the MSB first mode is active ([W1:W0]) indicate the length of the transfer in bytes. The final (default). If the LSB first mode is active, the register address of 13 bits are the address ([A12:A0]) at which to begin the read or the serial control port increments from the address just written write operation. toward 0x234 for multibyte I/O operations. Unused addresses For a write, the instruction word is followed by the number of are not skipped for these operations. bytes of data indicated by Bits[W1:W0] (see Table 24). For multibyte accesses that cross Address 0x234 or Address 0x000 Table 24. Byte Transfer Count in MSB first mode, the SPI internally disables writes to subsequent W1 W0 Bytes to Transfer registers and returns zeros for reads to subsequent registers. 0 0 1 Streaming mode always terminates when crossing address 0 1 2 boundaries (as shown in Table 25). 1 0 3 1 1 Streaming mode Table 25. Streaming Mode (No Addresses Are Skipped) Write Mode Address Direction Stop Sequence Bits[A12:A0] select the address within the register map that is MSB First Decrement …, 0x001, 0x000, stop written to or read from during the data transfer portion of the communications cycle. Only Bits[A11:A0] are needed to cover the range of the 0x234 registers used by the AD9523-1. Bit A12 must always be 0. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes decrement the address. Rev. C | Page 34 of 63

Data Sheet AD9523-1 Table 26. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R/W W1 W0 A12 = 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLKDON'T CARE DON'T CARE SDIODON'T CARE R/W W1 W0 A12A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA 09278-038 Figure 40. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data CS SCLK DON'T CARE DON'T CARE SDIO R/WW1W0A12A11A10A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDO DON'T CARE D7 D6 D5D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5D4 D3 D2 D1 D0 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA DCOANR'ET 09278-039 Figure 41. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data tDS tHIGH tS tDH tCLK tC CS tLOW SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 09278-040 Figure 42. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements CS SCLK t DV SSDDIOO DATABITN DATABITN–1 09278-041 Figure 43. Timing Diagram for Serial Control Port Register Read CS SCLKDON'T CARE DON'T CARE SDIODON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10A11A12 W0 W1R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA 09278-042 Figure 44. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data Rev. C | Page 35 of 63

AD9523-1 Data Sheet tS tC CS tCLK tHIGH tLOW SCLK tDS tDH SDIO BIT N BIT N + 1 09278-043 Figure 45. Serial Control Port Timing—Write Table 27. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK tS Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) tC Setup time between the SCLK rising edge and CS rising edge (end of communication cycle) t Minimum period that SCLK should be in a logic high state HIGH t Minimum period that SCLK should be in a logic low state LOW t SCLK to valid SDIO and SDO (see Figure 43) DV Rev. C | Page 36 of 63

Data Sheet AD9523-1 EEPROM OPERATIONS The AD9523-1 contains an internal EEPROM (nonvolatile 3. Set the enable EEPROM write bit (Bit 0, Register 0xB02) memory). The EEPROM can be programmed by the user to to 1 to enable the EEPROM. create and store a user-defined register setting file when the 4. Set the REG2EEPROM bit (Bit 0, Register 0xB03) to 1. power is off. This setting file can be used for power-up and chip This starts the process of writing data into the EEPROM to reset as a default setting. The EEPROM size is 512 bytes. See create the EEPROM setting file. This enables the EEPROM Table 58 and Table 59 for descriptions of the EEPROM registers controller to transfer the current register values, as well as that control EEPROM operation. the memory address and instruction bytes from the EEPROM buffer segment, into the EEPROM. After the write process During the data transfer process, the write and read registers is completed, the internal controller sets bit REG2EEPROM are generally not available via the serial port, except for one back to 0. readback bit: Status_EEPROM (Register 0xB00, Bit 0). Bit 0 of the Status_EEPROM register (Register 0xB00) To determine the data transfer state through the serial port in is used to indicate the data transfer status between the SPI mode, users can read the value of the Status_EEPROM bit EEPROM and the control registers (1 = data transfer in (1 = data transfer in process and 0 = data transfer complete). process, and 0 = data transfer complete). At the beginning In I²C mode, the user can address the AD9523-1 slave port with the of the data transfer, the Status_EEPROM bit is set to 1 by external I²C master (send an address byte to the AD9523-1). If the the EEPROM controller and cleared to 0 at the end of the AD9523-1 responds with a no acknowledge bit, the data transfer data transfer. The user can access Status_EEPROM via the was not received. If the AD9523-1 responds with an acknowledge STATUS0 pin when the STATUS0 pin is programmed to bit, the data transfer process is complete. The user can monitor the monitor the Status_EEPROM bit. Alternatively, the user Status_EEPROM bit or use Register 0x232, Bit 4, to program the can monitor the Status_EEPROM bit directly. STATUS0 pin to monitor the status of the data transfer (see Table 55). 5. When the data transfer is complete (Status_EEPROM = 0), set the enable EEPROM write bit (Register 0xB02, Bit 0) to 1. To transfer all 512 bytes to the EEPROM, it takes approximately Clearing the enable EEPROM write bit to 0 disables 46 ms. To transfer the contents of the EEPROM to the active writing to the EEPROM. register, it takes approximately 40 ms. RESET, a hard reset (an asynchronous hard reset is executed by To ensure that the data transfer has completed correctly, verify that the EEPROM data error bit (Register 0xB01, Bit 0) = 0. briefly pulling RESET low), restores the chip either to the setting A value of 1 in this bit indicates a data transfer error. When an stored in EEPROM (the EEPROM pin = 1) or to the on-chip EEPROM save/load transfer is complete, wait a minimum of setting (the EEPROM pin = 0). A hard reset also executes a 10 µs before starting the next EEPROM save/load transfer. SYNC operation that brings the outputs into phase alignment according to the default settings. When EEPROM is inactive READING FROM THE EEPROM (the EEPROM pin = 0), it takes ~2 µs for the outputs to begin The following reset-related events can start the process of toggling after RESET is issued. When EEPROM is active (the restoring the settings stored in the EEPROM to the control EEPROM pin = 1), it takes ~40 ms for the outputs to toggle after registers. When the EEPROM_SEL pin is set high, do any of RESET is brought high. the following to initiate an EEPROM read: WRITING TO THE EEPROM • Power up the AD9523-1. The EEPROM cannot be programmed directly through the serial • Perform a hardware chip reset by pulling the RESET pin port interface. To program the EEPROM and store a register low and then releasing RESET. setting file, follow these steps: • Set the self clearing soft reset bit (Bit 5, Register 0x000) to 1. 1. Program the AD9523-1 registers to the desired circuit state. When the EEPROM_SEL pin is set low, set the self clearing If the user wants PLL2 to lock automatically after power-up, Soft_EEPROM bit (Bit 1, Register 0xB02) to 1. The AD9523-1 the calibrate VCO bit (Register 0x0F3, Bit 1) must be set to 1. then starts to read the EEPROM and loads the values into the This allows VCO calibration to start automatically after AD9523-1 registers. If the EEPROM_SEL pin is low during reset register loading. Note that a valid input reference signal or power-up, the EEPROM is not active, and the AD9523-1 must be present during VCO calibration. default values are loaded instead. 2. Program the EEPROM buffer registers, if necessary (see When using the EEPROM to automatically load the AD9523-1 the Programming the EEPROM Buffer Segment section). register values and lock the PLL, the calibrate VCO bit (Bit 1, This step is necessary only if users want to use the EEPROM Register 0x0F3) must be set to 1 when the register values are to control the default settings of some (but not all) of the written to the EEPROM. This allows VCO calibration to start AD9523-1 registers, or if they want to control the register automatically after register loading. A valid input reference setting update sequence during power-up or chip reset. signal must be present during VCO calibration. Rev. C | Page 37 of 63

AD9523-1 Data Sheet To ensure that the data transfer has completed correctly, verify IO_Update (Operational Code 0x80) that the EEPROM data error bit (Register 0xB01, Bit 0) is set to 0. The EEPROM controller uses this operational code to generate A value of 1 in this bit indicates a data transfer error. When an an IO_Update signal to update the active control register bank EEPROM save/load transfer is complete, wait a minimum of from the buffer register bank during the download process. 10 µs before starting the next EEPROM save/load transfer. At a minimum, there should be at least one IO_Update PROGRAMMING THE EEPROM BUFFER SEGMENT operational code after the end of the final register section The EEPROM buffer segment is a register space that allows the definition group. This is needed so that at least one IO_Update user to specify which groups of registers are stored to the EEPROM occurs after all of the AD9523-1 registers are loaded when the during EEPROM programming. Normally, this segment does EEPROM is read. If this operational code is absent during a not need to be programmed by the user. Instead, the default write to the EEPROM, the register values loaded from the power-up values for the EEPROM buffer segment allow the EEPROM are not transferred to the active register space, and user to store all of the register values from Register 0x000 to these values do not take effect after they are loaded from the Register 0x234 to the EEPROM. EEPROM to the AD9523-1. For example, if the user wants to load only the output driver End-of-Data (Operational Code 0xFF) settings from the EEPROM without disturbing the PLL register The EEPROM controller uses the end of data operational code settings currently stored in the EEPROM, the EEPROM buffer to terminate the data transfer process between EEPROM and segment can be modified to include only the registers that apply the control register during the upload and download process. The to the output drivers and exclude the registers that apply to the last item appearing in the EEPROM buffer segment should be PLL configuration. either this operational code or the pseudo-end-of-data There are two parts to the EEPROM buffer segment: register operational code. section definition groups and operational codes. Each register Pseudo-End-of-Data (Operational Code 0xFE) section definition group contains the starting address and The AD9523-1 EEPROM buffer segment has 23 bytes that can number of bytes to be written to the EEPROM. Note that any contain up to seven register section definition groups. If the register within the EEPROM buffer segment can be defined as a user wants to define more than seven register section definition part of a definition group or an operational code. groups, the pseudo-end-of-data operational code can be used. If the AD9523-1 register map were continuous from Address 0x000 During the upload process, when the EEPROM controller to Address 0x234, only one register section definition group receives the pseudo-end-of-data operational code, it halts would consist of a starting address of 0x000 and a length of the data transfer process, clears the REG2EEPROM bit (Bit 0, 563 bytes. However, this is not the case. The AD9523-1 register Register 0xB03), and enables the AD9523-1 serial port. The map is noncontiguous, and the EEPROM is only 512 bytes long. user can then program the EEPROM buffer segment again and Therefore, the register section definition group tells the EEPROM reinitiate the data transfer process by setting the REG2EEPROM controller how the AD9523-1 register map is segmented. bit to 1 and the IO_Update bit (Register 0x234, Bit 0) to 1. The There are three operational codes: IO_Update, end-of-data, and internal I²C master then begins writing to the EEPROM, starting pseudo-end-of-data. It is important that the EEPROM buffer from the EEPROM address held from the last writing. segment always have either an end-of-data or a pseudo-end-of- This sequence enables more discrete instructions to be written data operational code and that an IO_Update operation code to the EEPROM than would otherwise be possible due to the appear at least once before the end-of-data operational code. limited size of the EEPROM buffer segment. It also permits the Register Section Definition Group user to write to the same register multiple times with a different value each time. The register section definition group is used to define a continuous register section for the EEPROM profile. It consists of three bytes. The first byte defines how many continuous register bytes are in this group. If the user inputs 0x000 in the first byte, it means there is only one byte in this group. If the user inputs 0x001, it means there are two bytes in this group. The maximum number of registers in one group is 128. The next two bytes are the low byte and high byte of the memory address (16 bits) of the first register in this group. Rev. C | Page 38 of 63

Data Sheet AD9523-1 Table 28. Example of an EEPROM Buffer Segment Register Address (Hex) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Start EEPROM Buffer Segment 0xA00 0 Number of bytes of the first group of registers (Bits[6:0]) 0xA01 Address of the first group of registers (Bits[15:8]) 0xA02 Address of the first group of registers (Bits[7:0]) 0xA03 0 Number of bytes of the second group of registers (Bits[6:0]) 0xA04 Address of the second group of registers (Bits[15:8]) 0xA05 Address of the second group of registers (Bits[7:0]) 0xA06 0 Number of bytes of the third group of registers (Bits[6:0]) 0xA07 Address of the third group of registers (Bits[15:8]) 0xA08 Address of the third group of registers (Bits[7:0]) 0xA09 IO_Update operational code (0x80) 0xA0A End-of-data operational code (0xFF) Rev. C | Page 39 of 63

AD9523-1 Data Sheet DEVICE INITIALIZATION FLOWCHARTS The flowcharts in this section show a typical AD9523-1 The count variables (RST_COUNT and CAL_COUNT) in the initialization routine using an evaluation software generated AD9523-1 device initialization flow chart act as system level setup file (.stp) and calibration routines designed for robust count limits for the loop to prevent an infinite loop. These system startup. Other valid start up sequences exist and, as count variables are not AD9523-1 device settings or status such, these flow charts are provided as recommendations. readbacks. Rev. C | Page 40 of 63

Data Sheet AD9523-1 START USERPOWER APPLYVDD SUPPLIES (ALLDOMAINS) INITIALIZATIONAND POWER-ONRESET WAIT NO VDDSETTLED? YES POR:WAIT60ms APPLYREFERENCE CHIPLEVELRESET LOOP INPUT(S) RST_COUNT= ISSUEAPIN LEVEL RST_COUNT=0 RST_COUNT+1 RESET ORSOFTRESET SUBPROCESS: WRITEREGISTERS FROM SETUPFILE PLL2RECALIBRATIONLOOP CAL_COUNT=0 ISSUEVCO WRITE: CALIBRATION R0x0F3[1]=0 COMMAND WRITE: R0x234=0x01 WRITE: R0x0F3[1]=1 WRITE: R0x234=0x01 NO NO CCAALL_C_COOUUNNTT+=1 CAL_COUNT>1YES RST_COUNT>0YES RADIESBERUFEGLAGADGI:NGFO.R R0x22C TOR0x22D PLL2LOCK STARTTIMEOUTCLOCK: DETECTPOLLING TIME=0 LOOP NO NO YES R0x22C[1]=1 TIMEOUTCLOCK: TIME>100ns YES PLL1LOCK STARTTIMEOUTCLOCK: DETECTPOLLING TIME=0 LOOP NO R0x22C[0]=1 NO TTIIMMEEO>UPTLCL2L_OTCOK1: YES YES END 1PLL2_TO IS A CALCULATED TIMEOUT VALUE. SEE THE THEORY OF OPERATION, COMPONENT BLOCKS—INPUT PLL (PLL1) FOR ITS FORMULA. 09278-145 Figure 46. AD9523-1 Device Initialization Rev. C | Page 41 of 63

AD9523-1 Data Sheet SOFTWARE START GENERATED AD9523-1SETUP FILE WRITE: R0x000TOR0x006 WRITE: R0x010TOR0x01D WRITE: R0x0F0TOR0x0F9 WRITE: R0x190TOR0x1BB WRITE: R0x230TOR0x233 WRITE: R0xA00TOR0xA16 WRITE: R0x234=0x01 END 09278-146 Figure 47. Subprocess: Write Registers from Setup File Rev. C | Page 42 of 63

Data Sheet AD9523-1 POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9523-1 is a multifunctional, high speed device that Values of Ψ are provided for package comparison and PCB JB targets a wide variety of clock applications. The numerous design considerations. innovative features contained in the device each consume CLOCK SPEED AND DRIVER MODE incremental power. If all outputs are enabled in the maximum Clock speed directly and linearly influences the total power frequency and mode that have the highest power, the safe dissipation of the device and, therefore, the junction temperature. thermal operating conditions of the device may be exceeded. Two operating frequencies are listed under the incremental power Careful analysis and consideration of power dissipation and dissipation parameter in Table 3. Using linear interpretation is thermal management are critical elements in the successful a sufficient approximation for frequency not listed in the table. application of the AD9523-1 device. When calculating power dissipation for thermal consideration, The AD9523-1 device is specified to operate within the the amount of power dissipated in the 100 Ω resistor should be industrial temperature range of –40°C to +85°C. This removed. If using the data in Table 2, this power is already specification is conditional, however, such that the absolute removed. If using the current vs. frequency graphs provided in maximum junction temperature is not exceeded (as specified the Typical Performance Characteristics section, the power into in Table 16). At high operating temperatures, extreme care must the load must be subtracted, using the following equation: be taken when operating the device to avoid exceeding the junction temperature and potentially damaging the device. DifferentialOutput Voltage Swing2 100 Ω A maximum junction temperature is listed in Table 1 with the ambient operating range. The ambient range and maximum EVALUATION OF OPERATING CONDITIONS junction temperature specifications ensure the performance of The first step in evaluating the operating conditions is to the device, as guaranteed in the Specifications section. determine the maximum power consumption (PD) internal to Many variables contribute to the operating junction temperature the AD9523-1. The maximum PD excludes power dissipated in within the device, including the load resistors of the drivers because such power is external • Selected driver mode of operation to the device. Use the power dissipation specifications listed in • Output clock speed Table 3 to calculate the total power dissipated for the desired • Supply voltage configuration. The base typical configuration parameter in • Ambient temperature Table 3 lists a power of 434.7 mW, which includes one LVPECL output at 122.88 MHz. If the frequency of operation is not listed The combination of these variables determines the junction in Table 3, see the Typical Performance Characteristics section, temperature within the AD9523-1 device for a given set of current vs. frequency and driver mode to calculate the power operating conditions. dissipation; then add 20% for maximum current draw. Remove The AD9523-1 is specified for an ambient temperature (T ). To the power dissipated in the load resistor to achieve the most A ensure that T is not exceeded, an airflow source can be used. accurate power dissipation internal to the AD9523-1. See Table 29 A for a summary of the incremental power dissipation from the Use the following equation to determine the junction base power configuration for two different examples. temperature on the application PCB: T = T + (Ψ × PD) Table 29. Temperature Gradient Examples J CASE JT Frequency Maximum where: Description Mode (MHz) Power (mW) T is the junction temperature (°C). J Example 1 T is the case temperature (°C) measured by the user at the CASE Base Typical 434.7 top center of the package. Configuration Ψ is the value from Table 17. JT Output Driver 6 × LVPECL 122.88 306 PD is the power dissipation of the AD9523-1. Output Driver 3 × LVDS 61.44 89 Values of θJA are provided for package comparison and PCB Output Driver 3 × LVDS 245.76 135 design considerations. θJA can be used for a first-order Total Power 966 approximation of TJ by the equation Example 2 T = T + (θ × PD) Base Typical 434.7 J A JA Configuration where T is the ambient temperature (°C). A Output Driver 13 × LVPECL 983.04 2066 Values of θJC are provided for package comparison and PCB Total Power 2500 design considerations when an external heat sink is required. Rev. C | Page 43 of 63

AD9523-1 Data Sheet The second step is to multiply the power dissipated by the thermal THERMALLY ENHANCED PACKAGE MOUNTING impedance to determine the maximum power gradient. For GUIDELINES this example, a thermal impedance of θJA = 20.1°C/W was used. See the AN-772 Application Note, A Design and Manufacturing Example 1 Guide for the Lead Frame Chip Scale Package (LFCSP), for more information about mounting devices with an exposed paddle. (966 mW × 20.1°C/W) = 19.4°C With an ambient temperature of 85°C, the junction temperature is T = 85°C + 19.4°C = 104°C J This junction temperature is below the maximum allowable. Example 2 (2500 mW × 20.1°C/W) = 50.2°C With an ambient temperature of 85°C, the junction temperature is T = 85°C + 50°C = 135°C J This junction temperature exceeds the maximum allowable range. To operate in the condition of Example 2, the ambient temperature must be lowered to 65°C. Rev. C | Page 44 of 63

Data Sheet AD9523-1 CONTROL REGISTERS CONTROL REGISTER MAP Register addresses that are not listed in Table 30 are not used, and writing to those registers has no effect. Registers that are marked as reserved should never have their values changed. When writing to registers with bits that are marked reserved, the user should take care to always write the default value for the reserved bits. Table 30. Control Register Map Default Addr Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Serial Port Configuration 0x000 SPI mode SDO LSB first/ Soft reset Reserved Reserved Soft reset LSB first/ SDO active 0x00 serial port active address address configuration increment increment I2C mode Reserved Reserved Soft reset Reserved Reserved Soft reset Reserved Reserved 0x00 serial port configuration 0x004 Readback Reserved Reserved Reserved Reserved Reserved Reserved Reserved Read back 0x00 control active registers 0x005 EEPROM EEPROM customer version ID[7:0] (LSB) 0x00 0x006 customer EEPROM customer version ID[15:8] (MSB) 0x00 version ID Input PLL (PLL1) 0x010 PLL1 REFA 10-bit REFA R divider[7:0] (LSB) 0x00 0x011 R divider Reserved 10-bit REFA R divider[9:8] 0x00 control (MSB) 0x012 PLL1 REFB 10-bit REFB R divider[7:0] (LSB) 0x00 0x013 R divider Reserved 10-bit REFB R divider[9:8] 0x00 control (MSB) 0x014 PLL1 reference Reserved Reserved REF_TEST divider 0x00 test divider 0x015 PLL1 reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x00 0x016 PLL1 feedback 10-bit PLL1 feedback divider[7:0] (LSB) 0x00 0x017 N divider Reserved 10-bit PLL1 feedback divider[9:8] 0x00 control (MSB) 0x018 PLL1 charge PLL1 PLL1 charge pump control 0x0C pump control charge pump tristate 0x019 Reserved Reserved Reserved Enable SPI Antibacklash PLL1 charge pump mode 0x00 control of pulse width control antibacklash pulse width 0x01A PLL1 REF_TEST REFB REFA REFB receiver REFA Input OSC_IN OSC_IN 0x00 input receiver input differential differential enable receiver REFA, REFB single-ended differential control receiver receiver receiver enable receiver receiver receiver enable enable enable power- mode enable mode enable down (CMOS mode) control enable 0x01B REF_TEST, Bypass Bypass Zero delay OSC_IN signal ZD_IN ZD_IN REFB REFA 0x00 REFA, REFB, REF_TEST feedback mode feedback single- differ- single-ended single-ended and ZD_IN divider divider for PLL1 ended ential receiver receiver control receiver receiver mode enable mode enable mode mode (CMOS mode) (CMOS mode) enable enable (CMOS mode) 0x01C PLL1 Enable OSC_CTRL Reserved Reference selection mode Bypass REFB Bypass REFA 0x00 miscellaneous REFB control R divider R divider control R divider voltage to indepen- VCC/2 dent when ref division clock fails control Rev. C | Page 45 of 63

AD9523-1 Data Sheet Default Addr Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) 0x01D PLL1 loop Reserved Reserved Reserved Reserved PLL1 loop filter, RZERO 0x00 filter zero resistor control Output PLL (PLL2) 0x0F0 PLL2 charge PLL2 charge pump control 0x00 pump control 0x0F1 PLL2 A counter B counter 0x04 feedback N divider control 0x0F2 PLL2 control PLL2 lock Reserved Enable Enable SPI Antibacklash PLL2 charge pump mode 0x03 detector frequency control of pulse width control power- doubler antibacklash down pulse width 0x0F3 VCO control Reserved Reserved Reserved Force release Treat Force Calibrate VCO Reserved 0x00 of distribution reference VCO to (not auto- sync when as valid midpoint clearing) PLL2 is frequency unlocked 0x0F4 VCO dividers Reserved VCO VCO Divider M2 Reserved VCO VCO Divider M1 0x00 Divider M2 Divider power- M1 down power- down 0x0F5 PLL2 loop Pole 2 resistor (RPOLE2) Zero resistor (RZERO) Pole 1 capacitor (CPOLE1) 0x00 filter control 0x0F6 (9 bits) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bypass internal 0x00 RZERO resistor 0x0F7 PLL2 R2 Reserved Reserved Reserved PLL R2 divider 0x00 divider Clock Distribution 0x190 Channel 0 Invert Ignore Power Lower power Driver mode 0x00 control divider sync down mode output channel 0x191 10-bit channel divider[7:0] (LSB) 0x1F 0x192 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x193 Channel 1 Invert Ignore Power Lower power Driver mode 0x20 control divider sync down mode output channel 0x194 10-bit channel divider[7:0] (LSB) 0x1F 0x195 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x196 Channel 2 Invert Ignore Power Lower power Driver mode 0x00 control divider sync down mode output channel 0x197 10-bit channel divider[7:0] (LSB) 0x1F 0x198 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x199 Channel 3 Invert Ignore Power Lower power Driver mode 0x20 control divider sync down mode output channel 0x19A 10-bit channel divider[7:0] (LSB) 0x1F 0x19B Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x19C Channel 4 Invert Ignore Power Lower power Driver mode 0x00 control divider sync down mode output channel 0x19D 10-bit channel divider[7:0] (LSB) 0x1F 0x19E Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x19F Channel 5 Invert Ignore Power Lower power Driver mode 0x20 control divider sync down mode output channel 0x1A0 10-bit channel divider[7:0] (LSB) 0x1F 0x1A1 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 Rev. C | Page 46 of 63

Data Sheet AD9523-1 Default Addr Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) 0x1A2 Channel 6 Invert Ignore Power Lower power Driver mode 0x00 control divider sync down mode output channel 0x1A3 10-bit channel divider[7:0] (LSB) 0x1F 0x1A4 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1A5 Channel 7 Invert Ignore Power Lower power Driver mode 0x20 control divider sync down mode output channel 0x1A6 10-bit channel divider[7:0] (LSB) 0x1F 0x1A7 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1A8 Channel 8 Invert Ignore Power Lower power Driver mode 0x00 control divider sync down mode output channel 0x1A9 10-bit channel divider[7:0] (LSB) 0x1F 0x1AA Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1AB Channel 9 Invert Ignore Power Lower power Driver mode 0x20 control divider sync down mode output channel 0x1AC 10-bit channel divider[7:0] (LSB) 0x1F 0x1AD Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1AE Channel 10 Invert Ignore Power Lower power Driver mode 0x00 control divider sync down mode output channel 0x1AF 10-bit channel divider[7:0] (LSB) 0x1F 0x1B0 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1B1 Channel 11 Invert Ignore Power Lower power Driver mode 0x20 control divider sync down mode output channel 0x1B2 10-bit channel divider[7:0] (LSB) 0x1F 0x1B3 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1B4 Channel 12 Invert Ignore Power Lower power Driver mode 0x00 control divider sync down mode output channel 0x1B5 10-bit channel divider[7:0] (LSB) 0x1F 0x1B6 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1B7 Channel 13 Invert Ignore Power Lower power Driver mode 0x20 control divider sync down mode output channel 0x1B8 10-bit channel divider[7:0] (LSB) 0x1F 0x1B9 Divider phase[5:0] 10-bit channel divider[9:8] (MSB) 0x04 0x1BA PLL1 output CLK2 select[2:0] PLL1 output Out PLL1 output 0x00 control CMOS driver strength 0x1BB PLL1 output PLL1 CLK2 select[5:3] Reserved Route Route Route VCXO Route VCXO 0x80 channel output VCXO VCXO clock to Ch 1 clock to Ch 0 control driver clock to clock to divider input divider input power- Ch 3 Ch 2 down divider divider input input Readback 0x22C Readback 0 Status Status Status Status Status Status Lock detect Lock detect PLL2 PLL2 VCXO REF_TEST REFB REFA PLL2 PLL1 reference feedback clock clock 0x22D Readback 1 Reserved Reserved Reserved Reserved Holdover Selected Reserved VCO active reference calibration (in auto in progress mode) 0x22E Readback 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x22F Readback 3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Rev. C | Page 47 of 63

AD9523-1 Data Sheet Default Addr Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Other 0x230 Status signals Reserved Reserved Status Monitor 0 control 0x00 0x231 Reserved Reserved Status Monitor 1 control 0x00 0x232 Reserved Reserved Reserved Enable Status_ STATUS1 STATUS0 Reserved Sync dividers 0x00 EEPROM on pin pin (manual STATUS0 pin divider divider control) enable enable 0: sync signal inactive 1: dividers held in sync (same as SYNC pin low) 0x233 Power-down Reserved Reserved Reserved Reserved Reserved PLL1 PLL2 Distribution 0x07 control power- power-down power-down down 0x234 Update all Reserved IO_Update 0x00 registers EEPROM Buffer 0xA00 EEPROM Instruction (data)[7:0] (serial port configuration register) 0x00 Buffer Segment 0xA01 Register 1 to High byte of register address (serial port configuration register) 0x00 EEPROM 0xA02 Buffer Segment Low byte of register address (serial port configuration register) 0x00 Register 3 0xA03 EEPROM Instruction (data)[7:0] (reaback control register) 0x02 Buffer Segment 0xA04 Register 4 to High byte of register address (reaback control register) 0x00 EEPROM 0xA05 Buffer Segment Low byte of register address (reaback control register) 0x04 Register 6 0xA06 EEPROM Instruction (data)[7:0] (PLL segment) 0x0E Buffer Segment 0xA07 Register 7 to High byte of register address (PLL segment) 0x00 EEPROM 0xA08 Buffer Segment Low byte of register address (PLL segment) 0x10 Register 9 0xA09 EEPROM Instruction (data)[7:0] (PECL/CMOS output segment) 0x0E Buffer Segment 0xA0A Register 10 to High byte of register address (PECL/CMOS output segment) 0x00 EEPROM 0xA0B Buffer Segment Low byte of register address (PECL/CMOS output segment) 0xF0 Register 12 0xA0C EEPROM Instruction (data)[7:0] (divider segment) 0x2B Buffer Segment 0xA0D Register 13 to High byte of register address (divider segment) 0x01 EEPROM 0xA0E Buffer Segment Low byte of register address (divider segment) 0x90 Register 15 0xA0F EEPROM Instruction (data)[7:0] (clock input and REF segment) 0x01 Buffer Segment 0xA10 Register 16 to High byte of register address (clock input and REF segment) 0x01 EEPROM 0xA11 Buffer Segment Low byte of register address (clock input and REF segment) 0xE0 Register 18 0xA12 EEPROM Instruction (data)[7:0] (other segment) 0x03 Buffer Segment 0xA13 Register 19 to High byte of register address (other segment) 0x02 EEPROM 0xA14 Buffer Segment Low byte of register address (other segment) 0x30 Register 21 0xA15 EEPROM I/O update 0x80 Buffer Segment Register 22 Rev. C | Page 48 of 63

Data Sheet AD9523-1 Default Addr Register (MSB) (LSB) Value (Hex) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) 0xA16 EEPROM End of data 0xFF Buffer Segment Register 23 EEPROM Control 0xB00 Status_ Reserved Reserved Reserved Reserved Reserved Reserved Reserved Status_ 0x00 EEPROM EEPROM (read only) (read only) 0xB01 EEPROM error Reserved Reserved Reserved Reserved Reserved Reserved Reserved EEPROM 0x00 checking data error readback (read only) (read only) 0xB02 EEPROM Reserved Reserved Reserved Reserved Reserved Reserved Soft_EEPROM Enable 0x00 Control 1 EEPROM write 0xB03 EEPROM Reserved Reserved Reserved Reserved Reserved Reserved Reserved REG2EEPROM 0x00 Control 2 Rev. C | Page 49 of 63

AD9523-1 Data Sheet CONTROL REGISTER MAP BIT DESCRIPTIONS Serial Port Configuration (Address 0x000 to Address 0x006) Table 31. SPI Mode Serial Port Configuration Address Bits Bit Name Description 0x000 7 SDO active Selects unidirectional or bidirectional data transfer mode. This bit is ignored in I2C mode. 0: SDIO pin used for write and read; SDO is high impedance (default). 1: SDO used for read; SDIO used for write; unidirectional mode. 6 LSB first/ SPI MSB or LSB data orientation. This bit is ignored in I2C mode. address 0: data-oriented MSB first; addressing decrements (default). increment 1: data-oriented LSB first; addressing increments. 5 Soft reset Soft reset. 1 (self clearing): soft reset; restores default values to internal registers. 4 Reserved Reserved. [3:0] Mirror[7:4] Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB first or LSB first mode (see Register 0x000, Bit 6). Set bits as follows: Bit 0 = Bit 7. Bit 1 = Bit 6. Bit 2 = Bit 5. Bit 3 = Bit 4. 0x004 0 Read back For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer. active registers 0 (default): reads values currently applied to the internal logic of the device. 1: reads buffered values that take effect on the next assertion of the I/O update. Table 32. I2C Mode Serial Port Configuration Address Bits Bit Name Description 0x000 [7:6] Reserved Reserved. 5 Soft reset Soft reset. 1 (self clearing): soft reset; restores default values to internal registers. 4 Reserved Reserved. [3:0] Mirror[7:4] Bits[3:0] should always mirror Bits[7:4]. Set bits as follows: Bit 0 = Bit 7. Bit 1 = Bit 6. Bit 2 = Bit 5. Bit 3 = Bit 4. 0x004 0 Read back For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer. active registers 0 (default): reads values currently applied to the internal logic of the device. 1: reads buffered values that take effect on the next assertion of the I/O update. Table 33. EEPROM Customer Version ID Address Bits Bit Name Description 0x005 [7:0] EEPROM 16-bit EEPROM ID, Bits[7:0]. This register, along with Register 0x006, allows the user to store a unique customer ID to identify which version of the AD9523-1 register settings is stored in the EEPROM. It does not version ID (LSB) affect AD9523-1 operation in any way (default: 0x00). 0x006 [7:0] EEPROM 16-bit EEPROM ID, Bits[15:8]. This register, along with Register 0x005, allows the user to store a unique customer ID to identify which version of the AD9523-1 register settings is stored in the EEPROM. It does not version ID (MSB) affect AD9523-1 operation in any way (default: 0x00). Rev. C | Page 50 of 63

Data Sheet AD9523-1 Input PLL (PLL1) (Address 0x010 to Address 0x01D) Table 34. PLL1 REFA R Divider Control Address Bits Bit Name Description 0x010 [7:0] REFA R divider 10-bit REFA R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023. 00000000, 00000001: divide-by-1. 0x011 [1:0] 10-bit REFA R divider, Bits[9:8] (MSB). Table 35. PLL1 REFB R Divider Control1 Address Bits Bit Name Description 0x012 [7:0] REFB R divider 10-bit REFB R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023. 00000000, 00000001: divide-by-1. 0x013 [1:0] 10-bit REFB R divider, Bits[9:8] (MSB). 1 Requires Register 0x01C, Bit 7 = 1 for division that is independent of REFA division. Table 36. PLL1 Reference Test Divider Address Bits Bit Name Description 0x014 [7:6] Reserved Reserved. [5:0] REF_TEST divider 6-bit reference test divider. Divide-by-1 to divide-by-63. 000000, 000001: divide-by-1. Table 37. PLL1 Reserved Address Bits Bit Name Description 0x015 [7:0] Reserved Reserved. Table 38. PLL1 Feedback N Divider Control Address Bits Bit Name Description 0x016 [7:0] PLL1 feedback N divider control 10-bit feedback divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023. (N_PLL1) 00000000, 00000001: divide-by-1. 0x017 [1:0] 10-bit feedback divider, Bits[1:0] (MSB). Table 39. PLL1 Charge Pump Control Address Bits Bit Name Description 0x018 7 PLL1 charge pump tristate Tristates the PLL1 charge pump. [6:0] PLL1 charge pump control These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 μA with a full-scale magnitude of ~63.5 μA. 0x019 [7:5] Reserved Reserved. 4 Enable SPI control of antibacklash Controls the functionality of Register 0x019, Bits[3:2]. pulse width 0 (default): the device automatically controls the antibacklash period. 1: antibacklash period defined by Register 0x019, Bits[3:2]. [3:2] Antibacklash pulse width control Controls the PFD antibacklash period. These bits default to the high setting unless reprogrammed using Register 0x019[4] = 1b. The high setting decreases the maximum allowable PLL1 PFD rate. See Table 7 for ranges. 00: minimum. 01: low. 10: high(initial state unless changed via Register 0x019[4] = 1b). 11: maximum. [1:0] PLL1 charge pump mode Controls the mode of the PLL1 charge pump. 00: tristate. 01: pump up. 10: pump down. 11 (default): normal. Rev. C | Page 51 of 63

AD9523-1 Data Sheet Table 40. PLL1 Input Receiver Control Address Bits Bit Name Description 0x01A 7 REF_TEST input receiver enable 1: enabled. 0: disabled (default). 6 REFB differential receiver enable 1: differential receiver mode. 0: single-ended receiver mode (also depends on Register 0x01B, Bit 1) (default). 5 REFA differential receiver enable 1: differential receiver mode. 0: single-ended receiver mode (also depends on Register 0x01B, Bit 0) (default). 4 REFB receiver enable REFB receiver power-down control mode only when Bit 2 = 1. 1: enable REFB receiver. 0: power-down (default). 3 REFA receiver enable REFA receiver power-down control mode only when Bit 2 = 1. 1: enable REFA receiver. 0: power-down (default). 2 Input REFA and REFB receiver Enables control over power-down of the input receivers, REFA and REFB. power-down control enable 1: power-down control enabled. 0: both receivers enabled (default). 1 OSC_IN single-ended receiver Selects which single-ended input pin is enabled when in the single-ended receiver mode enable (CMOS mode) mode (Register 0x01A, Bit 0 = 0). 1: negative receiver from oscillator input (OSC_IN pin) selected. 0: positive receiver from oscillator input (OSC_IN pin) selected (default). 0 OSC_IN differential receiver mode 1: differential receiver mode. enable 0: single-ended receiver mode (also depends on Bit 1) (default). Table 41. REF_TEST, REFA, REFB, and ZD_IN Control Address Bits Bit Name Description 0x01B 7 Bypass REF_TEST divider Puts the divider into bypass mode (same as programming the divider word to 0 or 1). 1: divider in bypass mode (divide = 1). 0: divider normal operation. 6 Bypass feedback divider Puts the divider into bypass mode (same as programming the divider word to 0 or 1). 1: divider in bypass mode (divide = 1). 0: divider normal operation. 5 Zero delay mode Selects the zero delay mode used (via the ZD_IN pin) when Register 0x01B, Bit 4 = 0. Otherwise, this bit is ignored. 1: internal zero delay mode. The zero delay receiver is powered down. The internal zero delay path from Distribution Divider Channel 0 is used. 0: external zero delay mode. The ZD_IN receiver is enabled. 4 OSC_IN signal feedback for PLL1 Controls the input PLL feedback path, local feedback from the OSC_IN receiver or zero delay mode. 1: OSC_IN receiver input used for the input PLL feedback (non-zero delay mode). 0: zero delay mode enabled (also depends on Register 0x01B, Bit 4 to select the zero delay path. 3 ZD_IN single-ended receiver Selects which single-ended input pin is enabled when in the single-ended receiver mode enable (CMOS mode) mode (Register 0x01B, Bit 2 = 0). 1: ZD_IN pin enabled. 0: ZD_IN pin enabled. 2 ZD_IN differential receiver mode 1: differential receiver mode. enable 0: single-ended receiver mode (also depends on Register 0x01B, Bit 3). 1 REFB single-ended receiver mode Selects which single-ended input pin is enabled when in single-ended receiver mode enable (CMOS mode) (Register 0x01A, Bit 6 = 0). 1: REFB pin enabled. 0: REFB pin enabled. 0 REFA single-ended receiver mode Selects which single-ended input pin is enabled when in single-ended receiver mode enable (CMOS mode) (Register 0x01A, Bit 5 = 0). 1: REFA pin enabled. 0: REFA pin enabled. Rev. C | Page 52 of 63

Data Sheet AD9523-1 Table 42. PLL1 Miscellaneous Control Address Bits Bit Name Description 0x01C 7 Enable REFB R divider 1: REFB R divider is controlled by Register 0x012 and Register 0x013. independent division control 0: REFB R divider is set to the same setting as the REFA R divider (Register 0x010 and Register 0x011). This requires that, for the loop to stay locked, the REFA and REFB input frequencies must be the same. 6 OSC_CTRL control voltage to High permits the OSC_CTRL control voltage to be forced to midsupply when the VCC/2 when reference clock fails feedback or input clocks fail. Low tristates the charge pump output. 1: OSC_CTRL control voltage goes to VCC/2. 0: OSC_CTRL control voltage tracks the tristated (high impedance) charge pump (through the buffer). 5 Reserved Reserved. [4:2] Reference selection mode Programs the REFA, REFB mode selection (default = 000). REF_SEL Pin Bit 4 Bit 3 Bit 2 Description X1 0 0 0 Nonrevertive: stay on REFB. X1 0 0 1 Revert to REFA. X1 0 1 0 Select REFA. X1 0 1 1 Select REFB. 0 1 X1 X1 REF_SEL pin = 0 (low): REFA. 1 1 X1 X1 REF_SEL pin = 1 (high): REFB. 1 Bypass REFB R divider Puts the divider into bypass mode (same as programming divider word to 0 or 1). 1: divider in bypass mode (divide = 1). 0: divider normal operation. 0 Bypass REFA R divider Puts the divider into bypass mode (same as programming divider word to 0 or 1). 1: divider in bypass mode (divide = 1). 0: divider normal operation. 1 X = don’t care. Table 43. PLL1 Loop Filter Zero Resistor Control Address Bits Bit Name Description 0x01D [7:4] Reserved Reserved. [3:0] PLL1 loop filter, R Programs the value of the zero resistor, R . ZERO ZERO Bit 3 Bit 2 Bit 1 Bit 0 R Value (kΩ) ZERO 0 0 0 0 883 0 0 0 1 677 0 0 1 0 341 0 0 1 1 135 0 1 0 0 10 0 1 0 1 10 0 1 1 0 10 0 1 1 1 10 1 0 0 0 Use external resistor Output PLL (PLL2) (Address 0x0F0 to Address 0x0F7) Table 44. PLL2 Charge Pump Control Address Bits Bit Name Description 0x0F0 [7:0] PLL2 charge pump control These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 μA with a full-scale magnitude of ~900 μA. Rev. C | Page 53 of 63

AD9523-1 Data Sheet Table 45. PLL2 Feedback N Divider Control Address Bits Bit Name Description 0x0F1 [7:6] A counter A counter word. [5:0] B counter B counter word. Feedback Divider Constraints A Counter (Bits[7:6]) B Counter (Bits[5:0]) Allowed N Division (4 × B + A) A = 0 B = 3 12 A = 0 or A = 1 B = 4 16, 17 A = 0 to A = 2 B = 5 20, 21, 22 A = 0 to A = 2 B = 6 24, 25, 26 A = 0 to A = 3 B ≥ 7 28, 29 … continuous to 255 Table 46. PLL2 Control Address Bits Bit Name Description 0x0F2 7 PLL2 lock detector power-down Controls power-down of the PLL2 lock detector. 1: lock detector powered down. 0: lock detector active. 6 Reserved Default = 0; value must remain 0. 5 Enable frequency doubler Enables doubling of the PLL2 reference input frequency. 1: enabled. 0: disabled. 4 Enable SPI control of antibacklash Controls the functionality of Register 0x0F2, Bits[2:1]. pulse width 0 (default): device automatically controls the antibacklash period. 1: antibacklash period defined by Register 0x0F2, Bits[2:1]. [3:2] Antibacklash pulse width control Controls the PFD antibacklash period. These bits default to the high setting unless reprogrammed using Register 0x0F2[4] = 1b. The high setting decreases the maximum allowable PLL2 PFD rate. See Table 11 for ranges. 00 minimum. 01: low. 10: high (initial state unless changed via Register 0x0F2[4] = 1b). 11: maximum. [1:0] PLL2 charge pump mode Controls the mode of the PLL2 charge pump. 00: tristate. 01: pump up. 10: pump down. 11 (default): normal. Table 47. VCO Control Address Bits Bit Name Description 0x0F3 [7:5] Reserved Reserved. 4 Force release of distribution sync 0 (default): distribution is held in sync (static) until the output PLL locks. Then it is when PLL2 is unlocked automatically released from sync with all dividers synchronized. 1: overrides the PLL2 lock detector state; forces release of the distribution from sync. 3 Treat reference as valid 0 (default): uses the PLL1 VCXO indicator to determine when the reference clock to the PLL2 is valid. 1: treats the reference clock as valid even if PLL1 does not consider it to be valid. 2 Force VCO to midpoint frequency Selects VCO control voltage functionality. 0 (default): normal VCO operation. 1: forces VCO control voltage to midscale. 1 Calibrate VCO (not autoclearing) 1: initiates VCO calibration (this is not an autoclearing bit). 0: resets the VCO calibration. 0 Reserved Reserved. Rev. C | Page 54 of 63

Data Sheet AD9523-1 Table 48. VCO Divider Control Address Bits Bit Name Description 0x0F4 7 Reserved Reserved. 6 VCO Divider M2 1: powers down the divider. power-down 0: normal operation. [5:4] VCO Divider M2 Note that VCO Divider M2 connects to Output Channel 4 through Output Channel 9. Bit 5 Bit 4 Divider Value 0 0 Divide-by-3 0 1 Divide-by-4 1 0 Divide-by-5 1 1 Divide-by-3 3 Reserved Reserved. 2 VCO Divider M1 1: powers down the divider. power-down 0: normal operation. [1:0] VCO Divider M1 Note that VCO Divider M1 connects to all output channels. Bit 1 Bit 0 Divider Value 0 0 Divide-by-3 0 1 Divide-by-4 1 0 Divide-by-5 1 1 Divide-by-3 Table 49. PLL2 Loop Filter Control Address Bits Bit Name Description 0x0F5 [7:6] Pole 2 resistor (RPOLE2) RPOLE2 Bit 7 Bit 6 (Ω) 0 0 900 0 1 450 1 0 300 1 1 225 [5:3] Zero resistor (RZERO) RZERO Bit 5 Bit 4 Bit 3 (Ω) 0 0 0 3250 0 0 1 2750 0 1 0 2250 0 1 1 2100 1 0 0 3000 1 0 1 2500 1 1 0 2000 1 1 1 1850 [2:0] Pole 1 capacitor (CPOLE1) CPOLE1 Bit 2 Bit 1 Bit 0 (pF) 0 0 0 0 0 0 1 8 0 1 0 16 0 1 1 24 1 0 0 24 1 0 1 32 1 1 0 40 1 1 1 48 0x0F6 [7:1] Reserved Reserved. 0 Bypass internal R Bypasses the internal R resistor (R = 0 Ω). Requires the use of a series external zero ZERO ZERO ZERO resistor resistor. This bit is the MSB of the loop filter control register (Address 0x0F5 and Address 0x0F6). Rev. C | Page 55 of 63

AD9523-1 Data Sheet Table 50. PLL2 R2 Divider Address Bits Bit Name Description 0x0F7 [7:5] Reserved Reserved. [4:0] PLL2 R2 divider Divide-by-1 to divide-by-31. 00000, 00001: divide-by-1. Clock Distribution (Register 0x190 to Register 0x1B9) Table 51. Channel 0 to Channel 13 Control (This Same Map Applies to All 14 Channels) Address Bits Bit Name Description 0x190 7 Invert divider output Inverts the polarity of the divider’s output clock. 6 Ignore sync 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 5 Power down channel 1: powers down the entire channel. 0: normal operation. 4 Lower power mode Reduces power used in the differential output modes (LVDS/LVPECL/HSTL). This (differential modes only) reduction may result in power savings but at the expense of performance. Note that this bit does not affect output swing and current, just the internal driver power. 1: low strength/lower power. 0: normal operation. [3:0] Driver mode Driver mode. Bit 3 Bit 2 Bit 1 Bit 0 Driver Mode 0 0 0 0 Tristate output 0 0 0 1 LVPECL (8 mA) 0 0 1 0 LVDS (3.5 mA) 0 0 1 1 LVDS (7 mA) 0 1 0 0 HSTL-0 (16 mA) 0 1 0 1 HSTL-1 (8 mA) 0 1 1 0 CMOS (both outputs in phase) + Pin: true phase relative to divider output − Pin: true phase relative to divider output 0 1 1 1 CMOS (opposite phases on outputs) + Pin: true phase relative to divider output − Pin: complement phase relative to divider output 1 0 0 0 CMOS + Pin: true phase relative to divider output − Pin: high-Z 1 0 0 1 CMOS + Pin: high-Z − Pin: true phase relative to divider output 1 0 1 0 CMOS + Pin: high-Z − Pin: high-Z 1 0 1 1 CMOS (both outputs in phase) + Pin: complement phase relative to divider output − Pin: complement phase relative to divider output 1 1 0 0 CMOS (both outputs out of phase) + Pin: complement phase relative to divider output − Pin: true phase relative to divider output 1 1 0 1 CMOS + Pin: complement phase relative to divider output − Pin: high-Z 1 1 1 0 CMOS + Pin: high-Z − Pin: complement phase relative to divider output 1 1 1 1 Tristate output Rev. C | Page 56 of 63

Data Sheet AD9523-1 Address Bits Bit Name Description 0x191 [7:0] Channel divider, Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1 Bits[7:0] (LSB) is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB). 0x192 [7:2] Divider phase Divider initial phase after a sync is asserted relative to the divider input clock (from the VCO divider output). LSB = ½ of a period of the divider input clock. Phase = 0: no phase offset. Phase = 1: ½ period offset, … Phase = 63: 31.5 period offset. [1:0] Channel divider, Bits[9:8] (MSB) 10-bit channel divider, Bits[9:8] (MSB). Table 52. PLL1 Output Control (PLL1_OUT, Pin 72) Address Bits Bit Name Description 0x1BA [7:5] CLK2 select[2:0] Bits[2:0] of the VCO divider channel select. Bit 7 selects Channel Output 6. Bit 6 selects Channel Output 5. Bit 5 selects Channel Output 4. 0: VCO Divider M1. 1: VCO Divider M2. 4 PLL1 output CMOS driver CMOS driver strength. strength 1: weak. 0: strong. [3:0] PLL1 output divider 0000: divide-by-1. 0001: divide-by-2 (default). 0010: divide-by-4. 0100: divide-by-8. 1000: divide-by-16. No other inputs permitted. Table 53. PLL1 Output Channel Control Address Bits Bit Name Description 0x1BB 7 PLL1 output driver power-down PLL1 output driver power-down. [6:4] CLK2 select[5:3] Bits[5:3] of the VCO divider channel select. Bit 6 selects Channel Output 9. Bit 5 selects Channel Output 8. Bit 4 selects Channel Output 7. 0: VCO Divider M1. 1: VCO Divider M2. 3 Route VCXO clock to 1: channel uses VCXO clock. Routes VCXO clock to divider input. Channel 3 divider input 0: channel uses VCO divider output clock. 2 Route VCXO clock to 1: channel uses VCXO clock. Routes VCXO clock to divider input. Channel 2 divider input 0: channel uses VCO divider output clock. 1 Route VCXO clock to 1: channel uses VCXO clock. Routes VCXO clock to divider input. Channel 1 divider input 0: channel uses VCO divider output clock. 0 Route VCXO clock to 1: channel uses VCXO clock. Routes VCXO clock to divider input. Channel 0 divider input 0: channel uses VCO divider output clock. Rev. C | Page 57 of 63

AD9523-1 Data Sheet Readback (Address 0x22C to Address 0x22D) Table 54. Readback Registers (Readback 0 and Readback 1) Address Bits Bit Name Description 0x22C 7 Status PLL2 reference clock 1: OK. 0: off/clocks are missing. 6 Status PLL2 feedback clock 1: OK. 0: off/clocks are missing. 5 Status VCXO 1: OK. 0: off/clocks are missing. 4 Status REF_TEST 1: OK. 0: off/clocks are missing. 3 Status REFB 1: OK. 0: off/clocks are missing. 2 Status REFA 1: OK. 0: off/clocks are missing. 1 Lock detect PLL2 1: locked. 0: unlocked. 0 Lock detect PLL1 1: locked. 0: unlocked. 0x22D [7:4] Reserved Reserved. 3 Holdover active 1: holdover is active (both references are missing). 0: normal operation. 2 Selected reference Selected reference (applies only when the device automatically selects the reference; (in auto mode) for example, not in manual control mode). 1: REFB. 0: REFA. 1 Reserved Reserved. 0 VCO calibration in progress 1: VCO calibration in progress. 0: VCO calibration not in progress. Rev. C | Page 58 of 63

Data Sheet AD9523-1 Other (Address 0x230 to Address 0x234) Table 55. Status Signals Address Bits Bit Name Description 0x230 [7:6] Reserved Reserved. [5:0] Status Monitor 0 control Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout 0 0 0 0 0 0 GND 0 0 0 0 0 1 PLL1 and PLL2 locked 0 0 0 0 1 0 PLL1 locked 0 0 0 0 1 1 PLL2 locked 0 0 0 1 0 0 Both references are missing (REFA and REFB) 0 0 0 1 0 1 Both references are missing and PLL2 is locked 0 0 0 1 1 0 REFB selected (applies only to auto select mode) 0 0 0 1 1 1 REFA is OK 0 0 1 0 0 0 REFB is OK 0 0 1 0 0 1 REF_TEST is OK 0 0 1 0 1 0 VCXO is OK 0 0 1 0 1 1 PLL1 feedback is OK 0 0 1 1 0 0 PLL2 reference clock is OK 0 0 1 1 0 1 Reserved 0 0 1 1 1 0 REFA and REFB are OK 0 0 1 1 1 1 All clocks are OK (except REF_TEST) 0 1 0 0 0 0 PLL1 feedback is divide-by-2 0 1 0 0 0 1 PLL1 PFD down divide-by-2 0 1 0 0 1 0 PLL1 REF divide-by-2 0 1 0 0 1 1 PLL1 PFD up divide-by-2 0 1 0 1 0 0 GND 0 1 0 1 0 1 GND 0 1 0 1 1 0 GND 0 1 0 1 1 1 GND Note that all bit combinations after 010111 are reserved. Rev. C | Page 59 of 63

AD9523-1 Data Sheet Address Bits Bit Name Description 0x231 [7:6] Reserved Reserved. [5:0] Status Monitor 1 control Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout 0 0 0 0 0 0 GND 0 0 0 0 0 1 PLL1 and PLL2 locked 0 0 0 0 1 0 PLL1 locked 0 0 0 0 1 1 PLL2 locked 0 0 0 1 0 0 Both references are missing (REFA and REFB) 0 0 0 1 0 1 Both references are missing and PLL2 is locked 0 0 0 1 1 0 REFB selected (applies only to auto select mode) 0 0 0 1 1 1 REFA is OK 0 0 1 0 0 0 REFB is OK 0 0 1 0 0 1 REF_TEST is OK 0 0 1 0 1 0 VCXO is OK 0 0 1 0 1 1 PLL1 feedback is OK 0 0 1 1 0 0 PLL2 reference clock is OK 0 0 1 1 0 1 Reserved 0 0 1 1 1 0 REFA and REFB are OK 0 0 1 1 1 1 All clocks are OK (except REF_TEST) 0 1 0 0 0 0 GND 0 1 0 0 0 1 GND 0 1 0 0 1 0 GND 0 1 0 0 1 1 GND 0 1 0 1 0 0 PLL2 feedback is divide-by-2 0 1 0 1 0 1 PLL2 PFD down divide-by-2 0 1 0 1 1 0 PLL2 REF divide-by-2 0 1 0 1 1 1 PLL2 PFD up divide-by-2 Note that all bit combinations after 010111 are reserved. 0x232 [7:5] Reserved Reserved. 4 Enable Status_EEPROM Enables the EEPROM status on the STATUS0 pin. on STATUS0 pin 1: enable status. 3 STATUS1 pin divider Enables a divide-by-4 on the STATUS1 pin, allowing dynamic signals to be viewed at a lower enable frequency (such as the PFD input clocks). Not to be used with dc states on the status pins, which occur when the settings of Register 0x231, Bits[5:0] are in the range of 000000 to 001111. 1: enabled. 0: disabled. 2 STATUS0 pin divider Enables a divide-by-4 on the STATUS0 pin, allowing dynamic signals to be viewed at a lower enable frequency (such as the PFD input clocks). Not to be used with dc states on the status pins, which occur when the settings of Register 0x230, Bits[5:0] are in the range of 000000 to 001111. 1: enable. 0: disable. 1 Reserved Reserved. 0 Sync dividers Set bit to put dividers in sync; clear bit to release. Functions like SYNC pin low. (manual control) 1: sync. 0: normal. Rev. C | Page 60 of 63

Data Sheet AD9523-1 Table 56. Power-Down Control Address Bits Bit Name Description 0x233 [7:3] Reserved Reserved. 2 PLL1 power-down 1: power-down (default). 0: normal operation. 1 PLL2 power-down 1: power-down (default). 0: normal operation. 0 Distribution Powers down the distribution. power-down 1: power-down (default). 0: normal operation. Table 57. Update All Registers Address Bits Bit Name Description 0x234 [7:1] Reserved Reserved. 0 IO_Update This bit must be set to 1 to transfer the contents of the buffer registers into the active registers, which happens on the next SCLK rising edge. This bit is self clearing; that is, it does not have to be set back to 0. 1 (self clearing): update all active registers to the contents of the buffer registers. EEPROM Buffer (Address 0xA00 to Address 0xA16) Table 58. EEPROM Buffer Segment Address Bits Bit Name Description 0xA00 [7:0] EEPROM Buffer The EEPROM buffer segment section stores the starting address and number of bytes that are to to Segment Register 1 be stored and read back to and from the EEPROM. Because the register space is noncontiguous, 0xA16 to EEPROM Buffer the EEPROM controller needs to know the starting address and number of bytes in the register Segment Register 23 space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM controller: operational codes (that is, IO_Update and end-of-data) that are also stored in the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment registers is designed such that all registers are transferred to/from the EEPROM, and an IO_Update is issued after the transfer (see the Programming the EEPROM Buffer Segment section). EEPROM Control (Address 0xB00 to Address 0xB03) Table 59. Status_EEPROM Address Bits Bit Name Description 0xB00 [7:1] Reserved Reserved. 0 Status_EEPROM This read-only bit indicates the status of the data transferred between the EEPROM and the buffer (read only) register bank during the writing and reading of the EEPROM. This signal is also available at the STATUS0 pin when Register 0x232, Bit 4, is set. 0: data transfer is complete. 1: data transfer is not complete. Table 60. EEPROM Error Checking Readback Address Bits Bit Name Description 0xB01 [7:1] Reserved Reserved. 0 EEPROM data error This read-only bit indicates an error during the data transfer between the EEPROM and the buffer. (read only) 0: no error; data is correct. 1: incorrect data detected. Rev. C | Page 61 of 63

AD9523-1 Data Sheet Table 61. EEPROM Control 1 Address Bits Bit Name Description 0xB02 [7:2] Reserved Reserved. 1 Soft_EEPROM When the EEPROM_SEL pin is tied low, setting the Soft_EEPROM bit resets the AD9523-1 using the settings saved in EEPROM. 1: soft reset with EEPROM settings (self clearing). 0 Enable EEPROM write Enables the user to write to the EEPROM. 0: EEPROM write protection is enabled. User cannot write to EEPROM (default). 1: EEPROM write protection is disabled. User can write to EEPROM. Table 62. EEPROM Control 2 Address Bits Bit Name Description 0xB03 [7:1] Reserved Reserved. 0 REG2EEPROM Transfers data from the buffer register to the EEPROM (self clearing). 1: setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process); it is reset by the I²C master after the data transfer is done. Rev. C | Page 62 of 63

Data Sheet AD9523-1 OUTLINE DIMENSIONS 10.10 0.60 0.30 10.00 SQ 0.60 0.42 0.23 9.90 0.42 0.24 0.18 PIN 1 0.24 5455 721 INDICATOR PIN 1 INDICATOR 9.85 0.50 9.75 SQ BSC 6.15 9.65 EXPOSED 6.00 SQ PAD 5.85 0.50 0.40 18 TOP VIEW 0.30 3367 BOTTOM VIEW 19 0.25 MIN 12° MAX 0.80 MAX 8.50 REF 1.00 0.65 TYP 0.85 0.80 0.05 MAX FOR PROPER CONNECTION OF 0.02 NOM THE EXPOSED PAD, REFER TO COPLANARITY THE PIN CONFIGURATION AND SEPALTAINNGE 0.20 REF 0.08 FSUENCCTITOIONN O DFE TSHCISR IDPATTIOAN SSHEET. A COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 06-25-2012- Figure 48. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-7) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9523-1BCPZ −40°C to +85°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-7 AD9523-1BCPZ-REEL7 −40°C to +85°C 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-72-7 AD9523-1/PCBZ Evaluation Board 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09278-0-9/15(C) Rev. C | Page 63 of 63

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