12 LVDS/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO Data Sheet AD9522-0 FEATURES FUNCTIONAL BLOCK DIAGRAM CP LF Low phase noise, phase-locked loop (PLL) On-chip voltage controlled oscillator (VCO) tunes from 2.53 GHz to 2.95 GHz OPTIONAL REF1 RR STATUS EO MONITOR 1Su dpifpfeorretsn teixatle orrn 2a ls 3in.3g lVe/-5e Vnd VeCdO r/eVfCeXreOn tcoe 2in.4p uGtHs z REFIN CHOVMONIT PLL VCO Accepts CMOS, LVPECL, or LVDS references to 250 MHz REFIN REF2 SWITAND Accepts 16.62 MHz to 33.3 MHz crystal for reference input ZERO DELAY Optional reference clock doubler DIVIDER CLK AND MUXES Reference monitoring capability LVDS/ Revertive automatic and manual reference switchover/ CMOS OUT0 holdover modes DIV/Φ OUT1 OUT2 Glitch-free switchover between references OUT3 Automatic recovery from holdover DIV/Φ OUT4 OUT5 Digital or analog lock detect, selectable OUT6 Optional zero delay operation DIV/Φ OUT7 OUT8 Twelve 800 MHz LVDS outputs divided into 4 groups OUT9 Each group of 3 has a 1-to-32 divider with phase delay DIV/Φ OUT10 OUT11 Additive output jitter as low as 242 fs rms Channel-to-channel skew grouped outputs < 60 ps SPI/I2C CONTROL Ea(cfho rL VfDS ≤ o 2u5tp0u Mt Hcazn) be configured as 2 CMOS outputs DIGPOITRATL ALNODGIC EEPROM AD9522 07219-001 OUT Figure 1. Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed The AD9522 serial interface supports both SPI and I²C® ports. SPI- and I²C-compatible serial control port An in-package EEPROM can be programmed through the 64-lead LFCSP serial interface and store user-defined register settings for Nonvolatile EEPROM stores configuration settings power-up and chip reset. APPLICATIONS The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two Low jitter, low phase noise clock distribution 250 MHz CMOS outputs. Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Each group of outputs has a divider that allows both the divide Forward error correction (G.710) ratio (from 1 to 32) and the phase (coarse delay) to be set. Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs The AD9522 is available in a 64-lead LFCSP and can be operated High performance wireless transceivers from a single 3.3 V supply. The external VCO can have an ATE and high performance instrumentation operating voltage up to 5.5 V. Broadband infrastructures The AD9522 is specified for operation over the standard industrial GENERAL DESCRIPTION range of −40°C to +85°C. The AD9522-01 provides a multioutput clock distribution The AD9520-0 is an equivalent part to the AD9522-0 featuring function with subpicosecond jitter performance, along with an LVPECL/CMOS drivers instead of LVDS/CMOS drivers. on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used. 1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-0 is used, it is referring to that specific member of the AD9522 family. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD9522-0 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Mode 1: Clock Distribution or External VCO < 1600 MHz Applications ....................................................................................... 1 .................................................................................................. 31 General Description ......................................................................... 1 Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz .................................................. 33 Functional Block Diagram .............................................................. 1 Phase-Locked Loop (PLL) .................................................... 35 Revision History ............................................................................... 4 Configuration of the PLL ...................................................... 35 Specifications ..................................................................................... 5 Phase Frequency Detector (PFD) ........................................ 35 Power Supply Requirements ....................................................... 5 Charge Pump (CP) ................................................................. 35 PLL Characteristics ...................................................................... 5 On-Chip VCO ........................................................................ 36 Clock Inputs .................................................................................. 8 PLL External Loop Filter ....................................................... 36 Clock Outputs ............................................................................... 8 PLL Reference Inputs ............................................................. 36 Timing Characteristics ................................................................ 9 Reference Switchover ............................................................. 37 Timing Diagrams ..................................................................... 9 Reference Divider R ............................................................... 37 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ...................................................................... 10 VCO/VCXO Feedback Divider N: P, A, B .......................... 37 Clock Output Absolute Phase Noise (Internal VCO Used) .. 11 Digital Lock Detect (DLD) ................................................... 39 Analog Lock Detect (ALD) ................................................... 39 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ............................................................................. 11 Current Source Digital Lock Detect (CSDLD) .................. 39 Clock Output Absolute Time Jitter (Clock Cleanup Using External VCXO/VCO Clock Input (CLK/CLK) ................ 40 Internal VCO) ............................................................................. 11 Holdover .................................................................................. 40 Clock Output Absolute Time Jitter (Clock Generation Using External/Manual Holdover Mode ........................................ 40 External VCXO) ......................................................................... 12 Automatic/Internal Holdover Mode .................................... 40 Clock Output Additive Time Jitter (VCO Divider Not Used) ....................................................................................................... 12 Frequency Status Monitors ................................................... 42 Clock Output Additive Time Jitter (VCO Divider Used) ..... 13 VCO Calibration .................................................................... 42 Serial Control Port—SPI Mode ................................................ 13 Zero Delay Operation ................................................................ 45 Serial Control Port—I²C Mode ................................................ 14 Internal Zero Delay Mode..................................................... 45 PD, SYNC, and RESET Pins ..................................................... 15 External Zero Delay Mode .................................................... 45 Serial Port Setup Pins: SP1, SP0 ............................................... 15 Clock Distribution ..................................................................... 46 LD, STATUS, and REFMON Pins ............................................ 15 Operation Modes ................................................................... 46 Power Dissipation ....................................................................... 16 Clock Frequency Division ..................................................... 47 Absolute Maximum Ratings .......................................................... 17 VCO Divider ........................................................................... 47 Thermal Resistance .................................................................... 17 Channel Dividers ................................................................... 47 ESD Caution ................................................................................ 17 Synchronizing the Outputs—SYNC Function ................... 49 Pin Configuration and Function Descriptions ........................... 18 LVDS Output Drivers ............................................................ 50 Typical Performance Characteristics ........................................... 21 CMOS Output Drivers .......................................................... 51 Test Circuits ..................................................................................... 26 Reset Modes ................................................................................ 51 Terminology .................................................................................... 27 Power-On Reset ...................................................................... 51 Detailed Block Diagram ................................................................ 28 Hardware Reset via the RESET Pin ..................................... 51 Theory of Operation ...................................................................... 29 Soft Reset via the Serial Port ................................................. 51 Operational Configurations ...................................................... 29 Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port ......................................................................... 51 Mode 0: Internal VCO and Clock Distribution ................. 29 Rev. A | Page 2 of 84

Data Sheet AD9522-0 Power-Down Modes ................................................................... 51 SPI MSB/LSB First Transfers ..................................................... 57 Chip Power-Down via PD ..................................................... 51 EEPROM Operations ..................................................................... 60 PLL Power-Down .................................................................... 52 Writing to the EEPROM ............................................................ 60 Distribution Power-Down ..................................................... 52 Reading from the EEPROM ...................................................... 60 Individual Clock Output Power-Down................................ 52 Programming the EEPROM Buffer Segment.......................... 61 Individual Clock Channel Power-Down ............................. 52 Register Section Definition Group ....................................... 61 Serial Control Port .......................................................................... 53 IO_UPDATE (Operational Code 0x80) .............................. 61 SPI/I²C Port Selection ................................................................ 53 End-of-Data (Operational Code 0xFF) ............................... 61 I²C Serial Port Operation ........................................................... 53 Pseudo-End-of-Data (Operational Code 0xFE) ................. 61 I2C Bus Characteristics ........................................................... 53 Thermal Performance ..................................................................... 63 Data Transfer Process ............................................................. 54 Register Map .................................................................................... 64 Data Transfer Format ............................................................. 55 Register Map Descriptions ............................................................. 68 I²C Serial Port Timing ............................................................ 55 Applications Information ............................................................... 82 SPI Serial Port Operation ........................................................... 56 Frequency Planning Using the AD9522 .................................. 82 Pin Descriptions ...................................................................... 56 Using the AD9522 Outputs for ADC Clock Applications..... 82 SPI Mode Operation ............................................................... 56 LVDS Clock Distribution ........................................................... 82 Communication Cycle—Instruction Plus Data .................. 56 CMOS Clock Distribution ......................................................... 83 Write .........................................................................................5 6 Outline Dimensions ........................................................................ 84 Read ..........................................................................................5 6 Ordering Guide ........................................................................... 84 SPI Instruction Word (16 Bits) .................................................. 57 Rev. A | Page 3 of 84

AD9522-0 Data Sheet REVISION HISTORY 3/15—Rev. 0 to Rev. A Changes to External VCXO/VCO Clock Input (CLK/CLK) and Changes to Features Section............................................................ 1 Holdover Section ............................................................................ 40 Changes to Table 1 and Table 2 ....................................................... 5 Changes to Frequency Status Monitors Section and VCO Change to Input Frequency Parameter, Table 3 ........................... 8 Calibration Section ......................................................................... 42 Changes to Table 4 ............................................................................ 8 Changes to Figure 49 Caption ...................................................... 43 Changes to SDIO, SDO (Outputs) Parameter, Test Added Table 31; Renumbered Sequentially ................................ 44 Conditions/Comments Column, Table 13 .................................. 13 Changes to Zero Delay Operation Section and Internal Zero Changes to Table 17 ........................................................................ 15 Delay Mode Section ....................................................................... 45 Change to VCP Supply Parameter, Table 18 ............................... 16 Changes to Clock Distribution Section ....................................... 46 Change to Junction Temperature Parameter, Table 19 .............. 17 Added Channel Divider Maximum Frequency Section ............ 47 Changes to Pin 4 Description Column, Table 21 and Pin 22 Changes to Duty Cycle and Duty-Cycle Correction Section and Description Column, Table 21 ...................................................... 18 Table 37 ............................................................................................ 48 Deleted Figure 13; Renumbered Sequentially............................. 21 Changes to Synchronizing the Outputs—SYNC Function Added Test Circuits Section .......................................................... 26 Section .............................................................................................. 49 Moved Figure 33 and Figure 34 .................................................... 26 Changes to CMOS Output Drivers Section, Power-On Reset Changes to Figure 33 and Figure 34 ............................................. 26 Section, Hardware Reset via the RESET Pin Section, and Soft Changes to Mode 0: Internal VCO and Clock Distribution Reset via the Serial Port Section ................................................... 51 Section .............................................................................................. 29 Changes to Pin Descriptions Section and SPI Mode Operation Deleted Configuration and Register Settings Section ............... 29 Section .............................................................................................. 56 Changes to Figure 36 ...................................................................... 30 Changes to SPI Instruction Word (16 Bits) Section .................. 57 Changes to Figure 37 ...................................................................... 32 Changes to Figure 66, Figure 67 Caption, and Figure 68 .......... 58 Changes to Figure 38 ...................................................................... 34 Changes to EEPROM Operation Section .................................... 60 Changes to Configuration of the PLL Section and Charge Pump Changes to Table 49 ....................................................................... 64 (CP) Section .................................................................................... 35 Changes to Table 50 and Table 51 ................................................ 68 Changes to On-Chip VCO Section, Figure 40, and PLL Changes to Table 53 ....................................................................... 69 Reference Inputs Section ............................................................... 36 Changes to Table 55 ....................................................................... 77 Added Figure 42 and Figure 43; Renumbered Sequentially ..... 36 Changes to Table 58 ....................................................................... 81 Changes to Reference Switchover Section ................................... 37 Change to Frequency Planning Using the AD9522 Section ..... 82 Changes to Prescaler Section, A and B Counters Section, R and Updated Outline Dimensions ....................................................... 84 N Divider Delays, and Table 29 .................................................... 38 Changes to Current Source Digital Lock Detect (CSDLD) 10/08—Revision 0: Initial Version Section .............................................................................................. 39 Rev. A | Page 4 of 84

Data Sheet AD9522-0 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; T = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum A (min) and maximum (max) values are given over full VS and T (−40°C to +85°C) variation. A POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments VS 3.135 3.3 3.465 V 3.3 V ± 5% VCP VS 5.25 V This supply is usually at the same voltage as VS; set VCP = 5.0 V ± 5% only if connecting a 5 V external VCO/VCXO RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 5.1 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground PLL CHARACTERISTICS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments VCO (ON-CHIP) Frequency Range 2530 2950 MHz VCO Gain (K ) 52 MHz/V See Figure 8 VCO Tuning Voltage (V) 0.5 VCP − V VCP ≤ VS when using internal VCO T 0.5 Frequency Pushing (Open-Loop) 1 MHz/V Phase Noise at 1 kHz Offset −60 dBc/Hz LVDS output; f = 2750 MHz; f = 685MHz VCO OUT Phase Noise at 100 kHz Offset −118 dBc/Hz LVDS output; f = 2750 MHz; f = 685MHz VCO OUT Phase Noise at 1 MHz Offset −135 dBc/Hz LVDS output; f = 2750 MHz; f = 685MHz VCO OUT REFERENCE INPUTS Differential Mode (REFIN, REFIN) Differential mode (can accommodate single-ended input by ac grounding the unused complementary input) Input Frequency 0 250 MHz Frequencies below about 1 MHz must be dc-coupled; be careful to match V (self-bias voltage) CM Input Sensitivity 280 mV p-p PLL figure of merit (FOM) increases with increasing slew rate (see Figure 12); the input sensitivity is sufficient for ac-coupled LVDS and LVPECL signals Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN 1.30 1.50 1.60 V Self-bias voltage of REFIN1 Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN 4.4 5.3 6.4 kΩ Self-biased1 Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs Input Frequency (AC-Coupled) 10 250 MHz Slew rate must be > 50 V/µs with DC Offset Off) Input Frequency (AC-Coupled 250 MHz Slew rate must be > 50 V/µs, and input amplitude with DC Offset On) sensitivity specification must be met; see input sensitivity Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/µs; CMOS levels Input Sensitivity (AC-Coupled 0.55 3.28 V p-p VIH must not exceed VS with DC Offset Off) Input Sensitivity (AC-Coupled 1.5 2.78 V p-p VIH must not exceed VS with DC Offset On) Input Logic High, DC Offset Off 2.0 V Input Logic Low, DC Offset Off 0.8 V Input Current −100 +100 µA Input Capacitance 2 pF Each pin, REFIN (REF1)/REFIN (REF2) Pulse Width High/Low 1.8 ns Amount of time a square wave is high/low determines the allowable input duty cycle Rev. A | Page 5 of 84

AD9522-0 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments Crystal Oscillator Crystal Resonator Frequency Range 16.62 33.33 MHz Maximum Crystal Motional Resistance 30 Ω PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Reference Input Clock Doubler Frequency 0.004 50 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b 2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b 6.0 ns Register 0x017[1:0] = 10b CHARGE PUMP (CP) I Sink/Source Programmable CP High Value 4.8 mA With CPRSET = 5.1 kΩ; higher I is possible by CP changing CPRSET Low Value 0.60 mA With CPRSET = 5.1 kΩ; lower I is possible by CP changing CPRSET Absolute Accuracy 2.5 % Charge pump voltage set to V /2 CP CPRSET Range 2.7 10 kΩ I High Impedance Mode Leakage 1 nA CP Sink-and-Source Current Matching 1 % 0.5 V < V < VCP − 0.5 V; V is the voltage on the CP (charge CP CP pump) pin; VCP is the voltage on the VCP power supply pin I vs. V 1.5 % 0.5 V < V < VCP − 0.5 V CP CP CP I vs. Temperature 2 % V = VCP/2 V CP CP PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 200 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input frequency divided by P) PLL N DIVIDER DELAY Register 0x019[2:0]; see Table 53 000 Off 001 385 ps 010 504 ps 011 623 ps 100 743 ps 101 866 ps 110 989 ps 111 1112 ps PLL R DIVIDER DELAY Register 0x019[5:3]; see Table 53 000 Off 001 365 ps 010 486 ps 011 608 ps 100 730 ps 101 852 ps 110 976 ps 111 1101 ps Rev. A | Page 6 of 84

Data Sheet AD9522-0 Parameter Min Typ Max Unit Test Conditions/Comments PHASE OFFSET IN ZERO DELAY REF refers to REFIN (REF1)/REFIN (REF2) Phase Offset (REF-to-LVDS Clock Output 1890 2348 3026 ps When N delay and R delay are bypassed Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVDS Clock Output 900 1217 1695 ps When N delay = Setting 111 and R delay is bypassed Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in 318 677 1085 ps When N delay and R delay are bypassed External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in −329 +33 +360 ps When N delay = Setting 011 and R delay is bypassed External Zero Delay Mode NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ The PLL in-band phase noise floor is estimated by Phase Frequency Detector (In-Band measuring the in-band phase noise at the output of Means Within the LBW of the PLL) the VCO and subtracting 20 log(N) (where N is the value of the N divider) At 500 kHz PFD Frequency −165 dBc/Hz At 1 MHz PFD Frequency −162 dBc/Hz At 10 MHz PFD Frequency −152 dBc/Hz At 50 MHz PFD Frequency −144 dBc/Hz PLL Figure of Merit (FOM) −222 dBc/Hz Reference slew rate > 0.5 V/ns; FOM + 10 log(f ) is an PFD approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed-loop, the phase noise, as observed at the VCO output, is increased by 20 log(N); PLL figure of merit decreases with decreasing slew rate; see Figure 12 PLL DIGITAL LOCK DETECT WINDOW2 Signal available at the LD, STATUS, and REFMON pins when selected by appropriate register settings; lock detect window settings can be varied by changing the CPRSET resistor Lock Threshold (Coincidence of Edges) Selected by Register 0x017[1:0] and Register 0x018[4] (this is the threshold to go from unlock to lock) Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b Unlock Threshold (Hysteresis)2 Selected by Register 0x017[1:0] and Register 0x018[4] (this is the threshold to go from lock to unlock) Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 11 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b 1 The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. 2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time. Rev. A | Page 7 of 84

AD9522-0 Data Sheet CLOCK INPUTS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK, CLK) Differential input Input Frequency 01 2.4 GHz High frequency distribution (VCO divider) 01 2 GHz Distribution only (VCO divider bypassed); this is the frequency range supported by the channel divider, see the Channel Divider Maximum Frequency section Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Input Level, Differential 2 V p-p Larger voltage swings can turn on the protection diodes and can degrade jitter performance Input Common-Mode Voltage, V 1.3 1.57 1.8 V Self-biased; enables ac coupling CM Input Common-Mode Range, V 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled CMR Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF 1 Below about 1 MHz, the input must be dc-coupled. Take care to match VCM. CLOCK OUTPUTS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LVDS CLOCK OUTPUTS Termination = 100 Ω across differential pair OUT0, OUT1, OUT2, OUT3, OUT4, OUT5, Differential (OUT, OUT) OUT6, OUT7, OUT8, OUT9, OUT10, OUT11 Output Frequency 800 MHz The AD9522 outputs toggle at higher frequencies, but the output amplitude may not meet the V OD specification Output Differential Voltage, V 247 360 454 mV V − V for each leg of a differential pair for default OD OH OL amplitude setting with the driver not toggling; the peak-to-peak amplitude measured using a differential probe across the differential pair with the driver toggling is roughly 2× these values (see Figure 20) Delta V 25 mV Absolute difference between voltage swing of OD normal pin and inverted pin, output driver static Output Offset Voltage, V 1.125 1.25 1.375 V (V + V )/2 across a differential pair OS OH OL Delta V 25 mV This is the absolute value of the difference between OS V when the normal output is high vs. when the OS complementary output is high Short-Circuit Current, I , I 14 24 mA Output shorted to GND SA SB Tristate Leakage Current per Output <1 nA Output in tristate with 100 Ω across differential pair CMOS CLOCK OUTPUTS OUT0A, OUT0B, OUT1A, OUT1B, OUT2A, Single-ended; termination = 10 pF OUT2B, OUT3A, OUT3B, OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B, OUT7A, OUT7B, OUT8A, OUT8B, OUT9A, OUT9B, OUT10A, OUT10B, OUT11A, OUT11B Output Frequency 250 MHz See Figure 21 Output Voltage High, V VS − 0.1 V At 1 mA load OH Output Voltage Low, V 0.1 V At 1 mA load OL Output Voltage High, V 2.7 V At 10 mA load OH Output Voltage Low, V 0.5 V At 10 mA load OL Rev. A | Page 8 of 84

Data Sheet AD9522-0 TIMING CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT RISE/FALL TIMES Termination = 100 Ω across differential pair Output Rise Time, t 150 350 ps 20% to 80%, measured differentially RP Output Fall Time, t 150 350 ps 80% to 20%, measured differentially FP PROPAGATION DELAY, t , CLK-TO-LVDS OUTPUT LVDS For All Divide Values 1866 2313 2812 ps High frequency clock distribution configuration 1808 2245 2740 ps Clock distribution configuration Variation with Temperature 1 ps/°C OUTPUT SKEW, LVDS OUTPUTS1 Termination = 100 Ω across differential pair LVDS Outputs That Share the Same Divider 7 60 ps LVDS Outputs on Different Dividers 19 162 ps All LVDS Outputs Across Multiple Parts 432 ps CMOS OUTPUT RISE/FALL TIMES Termination = open Output Rise Time, t 625 835 ps 20% to 80%; C = 10 pF RC LOAD Output Fall Time, t 625 800 ps 80% to 20%; C = 10 pF FC LOAD PROPAGATION DELAY, t , CLK-TO-CMOS OUTPUT Clock distribution configuration CMOS For All Divide Values 1913 2400 2950 ps Variation with Temperature 2 ps/°C OUTPUT SKEW, CMOS OUTPUTS1 CMOS Outputs That Share the Same Divider 10 55 ps All CMOS Outputs on Different Dividers 27 230 ps All CMOS Outputs Across Multiple Parts 500 ps OUTPUT SKEW, LVDS-TO-CMOS OUTPUT1 All settings identical; different logic type Outputs That Share the Same Divider −31 +152 +495 ps LVDS to CMOS on the same part Outputs That Are on Different Dividers −193 +160 +495 ps LVDS to CMOS on the same part 1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. Timing Diagrams tCLK CLK SINGLE-ENDED tLVDS 80% CMOS 10pF LOAD 20% tCMOS 07219-060 tRC tFC 07219-063 Figure 2. CLK/CLK to Clock Output Timing, DIV = 1 Figure 4. CMOS Timing, Single-Ended, 10 pF Load DIFFERENTIAL 80% LVDS 20% tRP tFP 07219-061 Figure 3. LVDS Timing, Differential Rev. A | Page 9 of 84

AD9522-0 Data Sheet CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVDS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1.6 GHz, Output = 800 MHz Input slew rate > 1 V/ns Divider = 2 At 10 Hz Offset −100 dBc/Hz At 100 Hz Offset −110 dBc/Hz At 1 kHz Offset −117 dBc/Hz At 10 kHz Offset −126 dBc/Hz At 100 kHz Offset −134 dBc/Hz At 1 MHz Offset −137 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −148 dBc/Hz CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns Divider = 5 At 10 Hz Offset −111 dBc/Hz At 100 Hz Offset −123 dBc/Hz At 1 kHz Offset −132 dBc/Hz At 10 kHz Offset −141 dBc/Hz At 100 kHz Offset −146 dBc/Hz At 1 MHz Offset −150 dBc/Hz >10 MHz Offset −156 dBc/Hz CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 500 MHz Input slew rate > 1 V/ns Divider = 2 At 10 Hz Offset −102 dBc/Hz At 100 Hz Offset −114 dBc/Hz At 1 kHz Offset −122 dBc/Hz At 10 kHz Offset −129 dBc/Hz At 100 kHz Offset −135 dBc/Hz At 1 MHz Offset −140 dBc/Hz >10 MHz Offset −150 dBc/Hz CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns Divider = 20 At 10 Hz Offset −125 dBc/Hz At 100 Hz Offset −136 dBc/Hz At 1 kHz Offset −144 dBc/Hz At 10 kHz Offset −152 dBc/Hz At 100 kHz Offset −157 dBc/Hz At 1 MHz Offset −160 dBc/Hz >10 MHz Offset −164 dBc/Hz Rev. A | Page 10 of 84

Data Sheet AD9522-0 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter Min Typ Max Unit Test Conditions/Comments LVDS ABSOLUTE PHASE NOISE Internal VCO; VCO divider = 4; LVDS output and for loop bandwidths < 1 kHz VCO = 2950 MHz; Output = 737.5 MHz At 1 kHz Offset −59 dBc/Hz At 10 kHz Offset −90 dBc/Hz At 100 kHz Offset −115 dBc/Hz At 1 MHz Offset −133 dBc/Hz At 10 MHz Offset −146 dBc/Hz At 40 MHz Offset −149 dBc/Hz VCO = 2750 MHz; Output = 685 MHz At 1 kHz Offset −60 dBc/Hz At 10 kHz Offset −92 dBc/Hz At 100 kHz Offset −118 dBc/Hz At 1 MHz Offset −135 dBc/Hz At 10 MHz Offset −148 dBc/Hz At 40 MHz Offset −151 dBc/Hz VCO = 2550 MHz; Output = 632.5 MHz At 1 kHz Offset −64 dBc/Hz At 10 kHz Offset −95 dBc/Hz At 100 kHz Offset −120 dBc/Hz At 1 MHz Offset −137 dBc/Hz At 10 MHz Offset −148 dBc/Hz At 40 MHz Offset −151 dBc/Hz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R DIV = 1 VCO = 2949 MHz; LVDS = 245.76 MHz; PLL LBW = 55 kHz 187 fs rms Integration bandwidth = 200 kHz to 10 MHz 352 fs rms Integration bandwidth = 12 kHz to 20 MHz VCO = 2580 MHz; LVDS = 122.88 MHz; PLL LBW = 55 kHz 166 fs rms Integration bandwidth = 200 kHz to 10 MHz 321 fs rms Integration bandwidth = 12 kHz to 20 MHz VCO = 2580 MHz; LVDS = 61.44 MHz; PLL LBW = 55 kHz 218 fs rms Integration bandwidth = 200 kHz to 10 MHz 378 fs rms Integration bandwidth = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 19.44 MHz; R DIV = 162 VCO = 2799 MHz; LVDS = 155.52 MHz; PLL LBW = 1.8 kHz 617 fs rms Integration bandwidth = 12 kHz to 20 MHz VCO = 2580 MHz; LVDS = 122.88 MHz; PLL LBW = 1.8 kHz 514 fs rms Integration bandwidth = 12 kHz to 20 MHz Rev. A | Page 11 of 84

AD9522-0 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R DIV = 1 LVDS = 245.76 MHz; PLL LBW = 125 Hz 87 fs rms Integration bandwidth = 200 kHz to 5 MHz 108 fs rms Integration bandwidth = 200 kHz to 10 MHz 146 fs rms Integration bandwidth = 12 kHz to 20 MHz LVDS = 122.88 MHz; PLL LBW = 125 Hz 120 fs rms Integration bandwidth = 200 kHz to 5 MHz 151 fs rms Integration bandwidth = 200 kHz to 10 MHz 207 fs rms Integration bandwidth = 12 kHz to 20 MHz LVDS = 61.44 MHz; PLL LBW = 125 Hz 157 fs rms Integration bandwidth = 200 kHz to 5 MHz 210 fs rms Integration bandwidth = 200 kHz to 10 MHz 295 fs rms Integration bandwidth = 12 kHz to 20 MHz CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; measured at rising edge of clock signal CLK = 622.08 MHz 69 fs rms Integration bandwidth = 12 kHz to 20 MHz Any LVDS Output = 622.08 MHz Divide Ratio = 1 CLK = 622.08 MHz 116 fs rms Integration bandwidth = 12 kHz to 20 MHz Any LVDS Output = 155.52 MHz Divide Ratio = 4 CLK = 100 MHz 263 fs rms Calculated from SNR of ADC method Any LVDS Output = 100 MHz Broadband jitter Divide Ratio = 1 CLK = 500 MHz 242 fs rms Calculated from SNR of ADC method Any LVDS Output = 100 MHz Broadband jitter Divide Ratio = 5 CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO CLK = 200 MHz 289 fs rms Calculated from SNR of ADC method Any CMOS Output Pair = 100 MHz Broadband jitter Divide Ratio = 2 Rev. A | Page 12 of 84

Data Sheet AD9522-0 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter Min Typ Max Unit Test Conditions/Comments LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 500 MHz; VCO DIV = 5; LVDS = 100 MHz; 248 fs rms Calculated from SNR of ADC method Bypass Channel Divider; Duty-Cycle Correction = On (broadband jitter) CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz; 290 fs rms Calculated from SNR of ADC method Bypass Channel Divider; Duty-Cycle Correction = Off (broadband jitter) CLK = 200 MHz; VCO DIV = 1; CMOS = 100 MHz; 288 fs rms Calculated from SNR of ADC method Bypass Channel Divider; Duty-Cycle Correction = Off (broadband jitter) SERIAL CONTROL PORT—SPI MODE Table 13. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 µA Input Logic 0 Current −110 µA The minus sign indicates that current is flowing out of the AD9522, which is due to the internal pull-up resistor Input Capacitance 2 pF SCLK (INPUT) IN SPI MODE SCLK has an internal 30 kΩ pull-down resistor in SPI mode, but not in I2C mode Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 1 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V At 1 mA current; maximum recommended current: 5 mA Output Logic 0 Voltage 0.4 V At 1 mA current TIMING Clock Rate (SCLK, 1/t ) 25 MHz SCLK Pulse Width High, t 16 ns HIGH Pulse Width Low, t 16 ns LOW SDIO to SCLK Setup, t 4 ns DS SCLK to SDIO Hold, t 0 ns DH SCLK to Valid SDIO and SDO, t 11 ns DV CS to SCLK Setup and Hold, tS, tC 2 ns CS Minimum Pulse Width High, tPWH 3 ns Rev. A | Page 13 of 84

AD9522-0 Data Sheet SERIAL CONTROL PORT—I²C MODE Table 14. Parameter Min Typ Max Unit Test Conditions/Comments SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage 0.7 × VS V Input Logic 0 Voltage 0.3 × VS V Input Current with an Input Voltage Between −10 +10 µA 0.1 × VS and 0.9 × VS Hysteresis of Schmitt Trigger Inputs 0.015 × VS V Pulse Width of Spikes That Must Be Suppressed by 50 ns the Input Filter, t SPIKE SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current 0.4 V Output Fall Time from VIH to VIL with a Bus 20 + 0.1 C 250 ns C = capacitance of one bus line in pF MIN MAX b b Capacitance from 10 pF to 400 pF TIMING Note that all I2C timing values refer to VIH (0.3 × VS) and MIN VIL levels (0.7 × VS) MAX Clock Rate (SCL, f ) 400 kHz I2C Bus Free Time Between a Stop and Start Condition, t 1.3 µs IDLE Setup Time for a Repeated Start Condition, t 0.6 µs SET; STR Hold Time (Repeated) Start Condition (After This Period, 0.6 µs the First Clock Pulse Is Generated), t HLD; STR Setup Time for Stop Condition, t 0.6 µs SET; STP Low Period of the SCL Clock, t 1.3 µs LOW High Period of the SCL Clock, t 0.6 µs HIGH SCL, SDA Rise Time, t 20 + 0.1 C 300 ns C = capacitance of one bus line in pF RISE b b SCL, SDA Fall Time, t 20 + 0.1 C 300 ns C = capacitance of one bus line in pF FALL b b Data Setup Time, t 120 ns This is a minor deviation from the SET; DAT original I²C specification of 100 ns minimum Data Hold Time, t 140 880 ns This is a minor deviation from the HLD; DAT original I²C specification of 0 ns minimum1 Capacitive Load for Each Bus Line, C 400 pF b 1 According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL falling edge. Rev. A | Page 14 of 84

Data Sheet AD9522-0 PD, SYNC, AND RESET PINS Table 15. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS Each of these pins has an 30 kΩ internal pull-up resistor Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 1 µA Logic 0 Current −110 µA The minus sign indicates that current is flowing out of the AD9522, which is due to the internal pull-up resistor Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns RESET Inactive to Start of Register Programming 100 ns SYNC TIMING Pulse Width Low 1.3 ns High speed clock is CLK input signal SERIAL PORT SETUP PINS: SP1, SP0 Table 16. Parameter Min Typ Max Unit Test Conditions/Comments SP1, SP0 These pins do not have internal pull-up/pull-down resistors Logic Level 0 0.25 × VS V VS is the voltage on the VS pin Logic Level ½ 0.4 × VS 0.65 × VS V User can float these pins to obtain Logic Level ½; if floating this pin, connect a capacitor to ground Logic Level 1 0.8 × VS V LD, STATUS, AND REFMON PINS Table 17. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 53, Register 0x017, Register 0x01A, and Register 0x01B Output Voltage High, V 2.7 V At 1 mA current; maximum recommended current: 5 mA OH Output Voltage Low, V 0.4 V At 1 mA current OL MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter output, or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; note that spurs can couple to output when any of these pins are toggling ANALOG LOCK DETECT Capacitance 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect read back; use a pull-up resistor REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range 1.02 MHz Frequency above which the monitor indicates the presence of the reference Extended Range 8 kHz Frequency above which the monitor indicates the presence of the reference LD PIN COMPARATOR Trip Point 1.6 V Hysteresis 260 mV Rev. A | Page 15 of 84

AD9522-0 Data Sheet POWER DISSIPATION Table 18. Parameter Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION, CHIP Does not include power dissipated in external resistors; all LVDS outputs terminated with 100 Ω across differential pair; all CMOS outputs have 10 pF capacitive loading Power-On Default 0.88 1.0 W No clock; no programming; default register values PLL Locked; One LVDS Output Enabled 0.54 0.63 W f = 25 MHz; f = 250 MHz; VCO = 2750 MHz; VCO divider = 2; REF OUT one LVDS output and output divider enabled; zero delay off; I = 4.8 mA CP PLL Locked; One CMOS Output Enabled 0.55 0.66 W f = 25 MHz; f = 62.5 MHz; VCO = 2750 MHz; VCO divider = 2; REF OUT one CMOS output and output divider enabled; zero delay off; I = 4.8 mA CP Distribution Only Mode; VCO Divider On; 0.36 0.43 W f = 2.4 GHz; f = 200 MHz; VCO divider = 2; one LVDS output CLK OUT One LVDS Output Enabled and output divider enabled; zero delay off Distribution Only Mode; VCO Divider Off; 0.33 0.4 W f = 2.4 GHz; f = 200 MHz; VCO divider bypassed; one LVDS CLK OUT One LVDS Output Enabled output and output divider enabled; zero delay off Maximum Power, Full Operation 1.1 1.3 W PLL on; internal VCO = 2750 MHz; VCO divider = 2; all channel dividers on; 12 LVDS outputs at 125 MHz; zero delay on PD Power-Down 35 50 mW PD pin pulled low; does not include power dissipated in termination resistors PD Power-Down, Maximum Sleep 27 43 mW PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b; power-down SYNC, Register 0x230[2] = 1b; power-down distribution reference, Register 0x230[1] = 1b VCP Supply 2.3 8 mW PLL operating; typical closed-loop configuration POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled VCO Divider On/Off 33 43 mW VCO divider not used REFIN (Differential) Off 25 31 mW Delta between reference input off and differential reference input mode REF1, REF2 (Single-Ended) On/Off 16 22 mW Delta between reference inputs off and one single-ended reference enabled; double this number if both REF1 and REF2 are powered up VCO On/Off 60 95 mW Internal VCO disabled; CLK input selected PLL Dividers and Phase Detector On/Off 54 67 mW PLL off to PLL on, normal operation; no reference enabled LVDS Channel 118 146 mW No LVDS output on to one LVDS output on; channel divider set to 1 LVDS Driver 11 15 mW Second LVDS output turned on, same channel CMOS Channel 120 154 mW No CMOS output on to one CMOS output on; channel divider set to 1; f = 62.5 MHz and 10 pF of capacitive loading OUT CMOS Driver On/Off 16 30 mW Additional CMOS outputs within the same channel turned on Channel Divider Enabled 33 40 mW Delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by-32 Zero Delay Block On/Off 30 35 mW Rev. A | Page 16 of 84

Data Sheet AD9522-0 ABSOLUTE MAXIMUM RATINGS Table 19. Stresses at or above those listed under Absolute Maximum With Ratings may cause permanent damage to the product. This is a Parameter or Pin Respect to Rating stress rating only; functional operation of the product at these VS GND −0.3 V to +3.6 V or any other conditions above those indicated in the operational VCP, CP GND −0.3 V to +5.8 V section of this specification is not implied. Operation beyond REFIN, REFIN GND −0.3 V to VS + 0.3 V the maximum operating conditions for extended periods may RSET, LF, BYPASS GND −0.3 V to VS + 0.3 V affect product reliability. CPRSET GND −0.3 V to VS + 0.3 V THERMAL RESISTANCE CLK, CLK GND −0.3 V to VS + 0.3 V Thermal impedance measurements were taken on a JEDEC CLK CLK −1.2 V to +1.2 V JESD51-5 2S2P test board in still air in accordance with JEDEC SCLK/SCL, SDIO/SDA, SDO, CS GND −0.3 V to VS + 0.3 V JESD51-2. See the Thermal Performance section for more details. OUT0, OUT0, OUT1, OUT1, GND −0.3 V to VS + 0.3 V OUT2, OUT2, OUT3, OUT3, Table 20. OUT4, OUT4, OUT5, OUT5, Package Type θ Unit JA OUT6, OUT6, OUT7, OUT7, 64-Lead LFCSP (CP-64-4) 22 °C/W OUT8, OUT8, OUT9, OUT9, OUT10, OUT10, OUT11, OUT11 SYNC, RESET, PD GND −0.3 V to VS + 0.3 V ESD CAUTION REFMON, STATUS, LD GND −0.3 V to VS + 0.3 V SP0, SP1, EEPROM GND −0.3 V to VS + 0.3 V Junction Temperature1 125°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C 1 See the Specifications section for operating temperature range (TA). Rev. A | Page 17 of 84

AD9522-0 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EFIN (REF1)EFIN (REF2)PRSETSSNDSETSUT0 (OUT0A)UT0 (OUT0B)SUT1 (OUT1A)UT1 (OUT1B)UT2 (OUT2A)UT2 (OUT2B)S RRCVVGRVOOVOOOOV 4321098765432109 6666655555555554 VS 1 PIN 1 48OUT3 (OUT3A) REFMON 2 INDICATOR 47OUT3 (OUT3B) LD 3 46VS VCP 4 45OUT4 (OUT4A) CP 5 44OUT4 (OUT4B) STATUS 6 43OUT5 (OUT5A) REF_SEL 7 AD9522 42OUT5 (OUT5B) SYNC 8 41VS TOP VIEW LF 9 (Not to Scale) 40VS BYPASS10 39OUT8 (OUT8B) VS11 38OUT8 (OUT8A) VS12 37OUT7 (OUT7B) CLK13 36OUT7 (OUT7A) CLK14 35VS CS15 34OUT6 (OUT6B) SCLK/SCL16 33OUT6 (OUT6A) 7890123456789012 1112222222222333 SDIO/SDASDOGNDSP1SP0EEPROMRESETPDT9 (OUT9A)T9 (OUT9B)VS0 (OUT10A)0 (OUT10B)1 (OUT11A)1 (OUT11B)VS UU 1111 OO UTUTUTUT N1.O ETXEPSOSED DIE PAD MUST BE CONNECTED TO OGNOD.OO 07219-003 Figure 5. Pin Configuration Table 21. Pin Function Descriptions Input/ Pin Pin No. Output Type Mnemonic Description 1, 11, 12, 27, I Power VS 3.3 V Power Pins. 32, 35, 40, 41, 46, 49, 54, 57, 60, 61 2 O 3.3 V CMOS REFMON Reference Monitor (Output). This pin has multiple selectable outputs. 3 O 3.3 V CMOS LD Lock Detect (Output). This pin has multiple selectable outputs. 4 I Power VCP Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V. VCP must still be connected to 3.3 V if the PLL is not used. 5 O Loop filter CP Charge Pump (Output). This pin connects to an external loop filter. This pin can be left unconnected if the PLL is not used. 6 O 3.3 V CMOS STATUS Programmable Status Output. 7 I 3.3 V CMOS REF_SEL Reference Select. It selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. 8 I 3.3 V CMOS SYNC Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. 9 I Loop filter LF Loop Filter (Input). It connects internally to the VCO control voltage node. 10 O Loop filter BYPASS This pin is for bypassing the LDO to ground with a 220 nF capacitor. This pin can be left unconnected if the PLL is not used. 13 I Differential CLK Along with CLK, this pin is the differential input for the clock distribution section. clock input 14 I Differential CLK Along with CLK, this pin is the differential input for the clock distribution section. If a clock input single-ended input is connected to the CLK pin, connect a 0.1 µF bypass capacitor from this pin to ground. Rev. A | Page 18 of 84

Data Sheet AD9522-0 Input/ Pin Pin No. Output Type Mnemonic Description 15 I 3.3 V CMOS CS Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor. 16 I 3.3 V CMOS SCLK/SCL Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode. 17 I/O 3.3 V CMOS SDIO/SDA Serial Control Port Bidirectional Serial Data In/Out. 18 O 3.3 V CMOS SDO Serial Control Port Unidirectional Serial Data Out. 19, 59 I GND GND Ground Pins. 20 I Three-level SP1 Select SPI or I²C as the serial interface port and select the I²C slave address in I²C logic mode. Three-level logic. This pin is internally biased for the open logic level. 21 I Three-level SP0 Select SPI or I²C as the serial interface port and select the I²C slave address in I²C logic mode. Three-level logic. This pin is internally biased for the open logic level. 22 I 3.3 V CMOS EEPROM Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9522 to load the hard-coded default register values at power-up/reset. This pin has an internal 30 kΩ pull-down resistor. Note that to guarantee the proper loading of EEPROM during startup, a high-low-high pulse on the RESET pin occurs after the power supply stabilizes. 23 I 3.3 V CMOS RESET Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. 24 I 3.3 V CMOS PD Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor. 25 O LVDS or OUT9 (OUT9A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 26 O LVDS or OUT9 (OUT9B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 28 O LVDS or OUT10 (OUT10A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 29 O LVDS or OUT10 (OUT10B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 30 O LVDS or OUT11 (OUT11A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 31 O LVDS or OUT11 (OUT11B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 33 O LVDS or OUT6 (OUT6A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 34 O LVDS or OUT6 (OUT6B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 36 O LVDS or OUT7 (OUT7A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 37 O LVDS or OUT7 (OUT7B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 38 O LVDS or OUT8 (OUT8A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 39 O LVDS or OUT8 (OUT8B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 42 O LVDS or OUT5 (OUT5B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 43 O LVDS or OUT5 (OUT5A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 44 O LVDS or OUT4 (OUT4B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 45 O LVDS or OUT4 (OUT4A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. Rev. A | Page 19 of 84

AD9522-0 Data Sheet Input/ Pin Pin No. Output Type Mnemonic Description 47 O LVDS or OUT3 (OUT3B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 48 O LVDS or OUT3 (OUT3A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 50 O LVDS or OUT2 (OUT2B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 51 O LVDS or OUT2 (OUT2A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 52 O LVDS or OUT1 (OUT1B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 53 O LVDS or OUT1 (OUT1A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 55 O LVDS or OUT0 (OUT0B) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 56 O LVDS or OUT0 (OUT0A) Clock Output. This pin can be configured as one side of a differential LVDS output CMOS or as a single-ended CMOS output. 58 O Current set RSET Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin resistor to GND. 62 O Current set CPRSET Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND. resistor This resistor can be omitted if the PLL is not used. 63 I Reference REFIN (REF2) Along with REFIN, this is the differential input for the PLL reference. Alternatively, input this pin is a single-ended input for REF2. 64 I Reference REFIN (REF1) Along with REFIN, this is the differential input for the PLL reference. Alternatively, input this pin is a single-ended input for REF1. EPAD GND GND The exposed die pad must be connected to GND. Rev. A | Page 20 of 84

Data Sheet AD9522-0 TYPICAL PERFORMANCE CHARACTERISTICS 275 5 3 CHANNELS—6 LVDS 250 225 mA) 4 3 CHANNELS—3 LVDS N ( PUMP DOWN PUMP UP mA) 200 P PI 3 RENT ( 175 ROM C CUR 150 2 CHANNELS—2 LVDS NT F 2 E R R 125 U C 1 100 1 CHANNEL—1 LVDS 75 0 0 200 FR4E00QUENCY (6M0H0z) 800 1000 07219-108 0 0.5 1.0VOLTA1G.5E ON C2P.0 PIN (V)2.5 3.0 3.5 07219-111 Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), Channel and Figure 9. Charge Pump Characteristics at VCP = 3.3 V VCO Divider Bypassed, LVDS Outputs Terminated 100 Ω Across Differential Pair 240 5 2 CHANNELS—8 CMOS 220 200 mA) 4 N ( PUMP DOWN PUMP UP mA) 180 P PI 3 RENT ( 160 2 CHANNELS—2 CMOS ROM C CUR 140 NT F 2 E R 120 1 CHANNEL—2 CMOS UR C 1 100 1 CHANNEL—1 CMOS 80 0 0 50 FR1E00QUENCY (1M5H0z) 200 250 07219-109 0 0.5 1.0 1.V5OLT2A.0GE O2.N5 CP3 P.0IN (V3).5 4.0 4.5 5.0 07219-112 Figure 7. Total Current vs. Frequency, CLK-to-Output (PLL Off), Channel and Figure 10. Charge Pump Characteristics at VCP = 5.0 V VCO Divider Bypassed, CMOS Outputs with 10 pF Load 65 –140 T U P N 60 FD I –145 P O D T –150 K (MHz/V)VCO 5505 SE REFERRE(dBc/Hz)–155 OI –160 N E S 45 PHA –165 D F P 402.55 2.65 VCO FREQ2U.7E5NCY (GHz) 2.85 2.95 07219-010 –1700.1 P1FD FREQUENCY (MH10z) 100 07219-013 Figure 8. KVCO vs. VCO Frequency Figure 11. PFD Phase Noise Referred to PFD Input vs. PFD Frequency Rev. A | Page 21 of 84

AD9522-0 Data Sheet –208 3.5 VS_DRV = 3.3V –210 3.0 Hz) VS_DRV = 3.135V c/ –212 B 2.5 VS_DRV = 2.5V d RIT ( –214 VS_DRV = 2.35V ME V) 2.0 F –216 (H O O E V 1.5 UR –218 G DIFFERENTIAL INPUT L FI –220 1.0 L P –222 0.5 SINGLE-ENDED INPUT –2240 0.2 0.4INPUT 0S.L6EW RA0T.8E (V/ns1).0 1.2 1.4 07219-114 010k RESISTIV1Ek LOAD (Ω) 100 07219-118 Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN Figure 15. CMOS Output VOH (Static) vs. RLOAD (to Ground) 0 0.4 –10 0.3 –20 V) 0.2 –30 T ( U m) –40 TP 0.1 B U WER (d ––5600 TIAL O 0 PO –70 REN –0.1 E F –80 F DI –0.2 –90 –0.3 –100 –110 –0.4 100 105 110 115FREQ12U0ENC1Y2 5(MHz1)30 135 140 145 07219-116 0 1 2 3 4 5 6TIM7E (8ns)9 10 11 12 13 14 15 07219-014 Figure 13. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz; Figure 16. LVDS Output (Differential) at 100 MHz LBW = 127 kHz; ICP = 3.0 mA; fVCO = 2580 MHz Output Terminated 100 Ω Across Differential Pair 0 0.4 –10 0.3 –20 p) p- 0.2 –30 V dBm) –40 WING ( 0.1 POWER ( ––5600 ENTIAL S –0.10 R –70 E F F –0.2 –80 DI –0.3 –90 –100 –0.4 122.38 122.58 F12R2E.7Q8UENCY1 (2M2.H9z8) 123.18 123.38 07219-117 0 0.5 1.0 TIM1E.5 (ns) 2.0 2.5 3.0 07219-015 Figure 14. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz; Figure 17. LVDS Differential Voltage Swing at 800 MHz LBW = 127 kHz; ICP = 3.0 mA; fVCO = 2580 MHz Output Terminated 100 Ω Across Differential Pair Rev. A | Page 22 of 84

Data Sheet AD9522-0 4.0 3.2 3.5 2.8 2.4 3.0 DE (V) 2.0 E (V) 2.5 2pF U D PLIT 1.6 LITU 2.0 M P 10pF A 1.2 M 1.5 A 0.8 1.0 20pF 0.4 0.5 0 0 10 20 30 40TIM5E0 (ns)60 70 80 90 100 07219-018 00 100 200 FRE3Q00UENCY4 0(M0Hz) 500 600 700 07219-124 Figure 18. CMOS Output with 10 pF Load at 25 MHz Figure 21. CMOS Output Swing vs. Frequency and Capacitive Load –50 3.2 2pF LOAD –60 2.8 –70 2.4 L1O0pAFD Hz) –80 PLITUDE (V) 21..06 NOISE (dBc/ ––11–109000 M E A 1.2 S –120 A H P –130 0.8 –140 0.4 –150 0 –160 0 1 2 3 4 TIME5 (ns)6 7 8 9 10 07219-019 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 07219-023 Figure 19. CMOS Output with 2 pF and 10 pF Load at 250 MHz Figure 22. Internal VCO Phase Noise (Absolute), LVDS Output at 633 MHz 1600 –50 –60 1400 p) 7mA SETTING –70 mV p- 1200 Hz) –80 G ( 1000 Bc/ –90 N d WI E ( –100 S 800 S AL DEFAULT 3.5mA SETTING NOI –110 NTI 600 SE –120 E A R H E P –130 F 400 F DI –140 200 –150 0 –160 0 200 FR40E0QUENCY (6G0H0z) 800 1000 07219-123 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 07219-024 Figure 20. LVDS Differential Voltage Swing vs. Frequency Figure 23. Internal VCO Phase Noise (Absolute), LVDS Output at 685 MHz Output Terminated 100 Ω Across Differential Pair Rev. A | Page 23 of 84

AD9522-0 Data Sheet –50 –100 –60 –70 –110 Hz) –80 Hz) dBc/ –90 dBc/ –120 E ( –100 E ( S S NOI –110 NOI E E –130 S –120 S A A H H P –130 P –140 –140 –150 –160 –150 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 07219-025 10 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 07219-130 Figure 24. Internal VCO Phase Noise (Absolute), LVDS Output at 737 MHz Figure 27. Additive (Residual) Phase Noise, CLK-to-LVDS at 800 MHz, Divide-by-1 –100 –110 –110 –120 c/Hz) –120 c/Hz) –130 B B d d E ( E ( OIS –130 OIS –140 N N E E S S A –140 A –150 H H P P –150 –160 –160 –170 10 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 07219-128 10 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 07219-131 Figure 25. Additive (Residual) Phase Noise, Figure 28. Additive (Residual) Phase Noise, CLK-to-LVDS at 245.76 MHz, Divide-by-1 CLK-to-CMOS at 50 MHz, Divide-by-20 –100 –100 –110 –110 Bc/Hz) –120 Bc/Hz) –120 d d E ( E ( OIS –130 OIS –130 N N E E S S A –140 A –140 H H P P –150 –150 –16010 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 07219-129 –16010 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 07219-132 Figure 26. Additive (Residual) Phase Noise, Figure 29. Additive (Residual) Phase Noise, CLK-to-LVDS at 200 MHz, Divide-by-5 CLK-to-CMOS at 250 MHz, Divide-by-4 Rev. A | Page 24 of 84

Data Sheet AD9522-0 –100 –80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs –90 –110 –100 Bc/Hz) –120 Bc/Hz) –110 d d E ( E ( OIS –130 OIS –120 N N SE SE –130 A –140 A H H P P –140 –150 –150 –160 –160 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 07219-033 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 07219-135 Figure 30. Phase Noise (Absolute) Clock Generation; Internal VCO at Figure 32. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) 2580 MHz; PFD = 15.36 MHz; LBW = 40 kHz; LVDS Output = 122.88 MHz at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVDS Output = 245.76 MHz –80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 617fs INTEGRATED RMS JITTER (20kHz TO 80MHz): 450fs (EXTRAPOLATED) –90 –100 Hz) Bc/ –110 d E ( OIS –120 N SE –130 A H P –140 –150 –160 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 07219-034 Figure 31. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 2799 MHz; PFD = 120 kHz; LBW = 1.92 kHz; LVDS Output = 155.52 MHz Rev. A | Page 25 of 84

AD9522-0 Data Sheet TEST CIRCUITS R2 R2 390Ω 3kΩ CP LF CP LF C2 C2 C1 240nF C3 C1 4.7µF C3 62pF R1 33pF 1.5nF R1 2.2nF 820Ω 2.1kΩ BYPASS BYPASS CAPFBOAYCRPI TLAODSORS C22102nF 07219-234 CAPFBOAYCRPI TLAODSORS C22102nF 07219-235 Figure 33. PLL Loop Filter Used for Clock Generation Plot (See Figure 30) Figure 34. PLL Loop Filter Used for Clock Cleanup Plot (See Figure 31) Rev. A | Page 26 of 84

Data Sheet AD9522-0 TERMINOLOGY Time Jitter Phase Jitter and Phase Noise Phase noise is a frequency domain phenomenon. In the time An ideal sine wave can be thought of as having a continuous domain, the same effect is exhibited as time jitter. When observing and even progression of phase with time from 0° to 360° for a sine wave, the time of successive zero crossings varies. In a square each cycle. Actual signals, however, display a certain amount wave, the time jitter is a displacement of the edges from their of variation from ideal phase progression over time. This ideal (regular) times of occurrence. In both cases, the variations in phenomenon is called phase jitter. Although many causes can timing from the ideal are the time jitter. Because these variations contribute to phase jitter, one major cause is random noise, are random in nature, the time jitter is specified in seconds root which is characterized statistically as Gaussian (normal) in mean square (rms) or 1 sigma of the Gaussian distribution. distribution. Time jitter that occurs on a sampling clock for a DAC or an This phase jitter leads to a spreading out of the energy of the ADC decreases the signal-to-noise ratio (SNR) and dynamic sine wave in the frequency domain, producing a continuous range of the converter. A sampling clock with the lowest possible power spectrum. This power spectrum is usually reported as a jitter provides the highest performance from a given converter. series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio Additive Phase Noise (expressed in decibels) of the power contained within a 1 Hz Additive phase noise is the amount of phase noise that is bandwidth with respect to the power at the carrier frequency. attributable to the device or subsystem being measured. For each measurement, the offset from the carrier frequency is The phase noise of any external oscillators or clock sources is also given. subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in It is meaningful to integrate the total power contained within conjunction with the various oscillators and clock sources, each some interval of offset frequencies (for example, 10 kHz to of which contributes its own phase noise to the total. In many 10 MHz). This is called the integrated phase noise over that cases, the phase noise of one element dominates the system frequency offset interval and can be readily related to the time phase noise. When there are multiple contributors to phase jitter due to the phase noise within that offset frequency interval. noise, the total is the square root of the sum of squares of the Phase noise has a detrimental effect on the performance of ADCs, individual contributors. DACs, and RF mixers. It lowers the achievable dynamic range of Additive Time Jitter the converters and mixers, although they are affected in somewhat Additive time jitter is the amount of time jitter that is attributable to different ways. the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. A | Page 27 of 84

AD9522-0 Data Sheet DETAILED BLOCK DIAGRAM REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 E LOCK BL DETECT OPTIONALREFIN REF2 BUFSTATUSSTATUS CLOCKDOUBLER RDIVIDER PROGRAMMA R DELAY PLLREFERENCE HOLD REFIN AMP STATUS BYPASS LOW DROPOUT REGULATOR (LDO) PHASE PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK OUT0 OUT0 1 0 DIVIDE BY OUT1 PD 1 TO 32 OUT1 DIGITAL EEPROM SYNC LOGIC RESET OUT2 OUT2 EEPROM OUT3 SP1 SERIAL OUT3 PORT SP0 DECODE DIVIDE BY OUT4 1 TO 32 OUT4 SPI I2C UT INTERFACE INTERFACE P OUT5 T U SCLK/SCL OUT5 O S SDIO/SDA O M SDO C CS OUT6 LV OUT6 S/ D V L DIVIDE BY OUT7 1 TO 32 OUT7 OUT8 OUT8 OUT9 OUT9 DIVIDE BY OUT10 1 TO 32 OUT10 AD9522 OUT11 OUT11 07219-028 Figure 35. Rev. A | Page 28 of 84

Data Sheet AD9522-0 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS Table 22. Settings When Using Internal VCO The AD9522 can be configured in several ways. These Register Description configurations must be set up by loading the control registers 0x010[1:0] = 00b PLL normal operation (PLL on) (see Table 49 to Table 60). Each section or function must be 0x010 to 0x01E PLL settings; select and enable a reference individually programmed by setting the appropriate bits in the input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration corresponding control register or registers. After the desired 0x1E1[1] = 1b VCO selected as the source configuration is programmed, the user can store these values in 0x01C[2:0] Enable reference inputs the on-board EEPROM to allow the part to power up in the 0x1E0[2:0] Set VCO divider desired configuration without user intervention. 0x1E1[0] = 0b Use the VCO divider as the source for Mode 0: Internal VCO and Clock Distribution the distribution section When using the internal VCO and PLL, the VCO divider must 0x018[0] = 0b Reset VCO calibration and issue IO_UPDATE be employed to ensure in most cases that the input frequency to the 0x232[0] = 1b (not necessary for the first time after power-up, but must be done subsequently) channel dividers does not exceed its specified maximum frequency 0x018[0] = 1b Initiate VCO calibration, issue IO_UPDATE (see Table 3). The exceptions to this are VCO direct mode and 0x232[0] = 1b cases where the VCO frequency is ≤2000 MHz. The channel divider maximum input frequency is 2000 MHz provided that the user does not choose a divide-by-17 or a divide-by-3. If divide-by-3 or divide-by-17 is desired, the maximum channel divider input frequency is 1600 MHz. The internal PLL uses an external loop filter to set the loop bandwidth. The external loop filter is also crucial to the loop stability. The internal PLL uses an external loop filter to set the loop bandwidth. The external loop filter is also crucial to the loop stability. When using the internal VCO, it is necessary to calibrate the VCO (Register 0x018[0] = 1b) to ensure optimal performance. For internal VCO and clock distribution applications, use the register settings shown in Table 22. Rev. A | Page 29 of 84

AD9522-0 Data Sheet REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 E LOCK BL DETECT OPTIONALREFIN REF2 BUFSTATUSSTATUS CLOCKDOUBLER RDIVIDER PROGRAMMA R DELAY PLLREFERENCE HOLD REFIN AMP STATUS BYPASS LOW DROPOUT REGULATOR (LDO) PHASE PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK OUT0 OUT0 1 0 DIVIDE BY OUT1 PD 1 TO 32 OUT1 DIGITAL EEPROM SYNC LOGIC RESET OUT2 OUT2 EEPROM OUT3 SP1 SERIAL OUT3 PORT SP0 DECODE DIVIDE BY OUT4 1 TO 32 OUT4 SPI I2C T INTERFACE INTERFACE U OUT5 P T SCLK/SCL OUT5 OU SDIO/SDA S O SDO M CS OUT6 S/C OUT6 D V L DIVIDE BY OUT7 1 TO 32 OUT7 OUT8 OUT8 OUT9 OUT9 DIVIDE BY OUT10 1 TO 32 OUT10 AD9522 OUT11 OUT11 07219-030 Figure 36. Internal VCO and Clock Distribution (Mode 0) Rev. A | Page 30 of 84

Data Sheet AD9522-0 Mode 1: Clock Distribution or External VCO < 1600 MHz Table 24. Settings for Using Internal PLL with External VCO < 1600 MHz When the external clock source to be distributed or the external Register Description VCO/VCXO is <1600 MHz, a configuration that bypasses the VCO divider can be used. This is the only difference from Mode 2. 0x1E1[0] = 1b Bypass the VCO divider as the source for the distribution section Bypassing the VCO divider limits the frequency of the clock 0x010[1:0] = 00b PLL normal operation (PLL on) along source to <1600 MHz (due to the maximum input frequency with other appropriate PLL settings in allowed at the channel dividers). Register 0x010 to Register 0x01E For clock distribution applications where the external clock is <1600 MHz, use the register settings shown in Table 23. An external VCO/VCXO requires an external loop filter that must be connected between CP and the tuning pin of the VCO/ Table 23. Settings for Clock Distribution < 1600 MHz VCXO. This loop filter determines the loop bandwidth and stability Register Description of the PLL. Make sure to select the proper PFD polarity for the 0x010[1:0] = 01b PLL asynchronous power-down (PLL off) VCO/VCXO being used. 0x1E1[0] = 1b Bypass the VCO divider as the source for the distribution section Table 25. Setting the PFD Polarity 0x1E1[1] = 0b CLK selected as the source Register Description 0x010[7] = 0b PFD polarity positive (higher control voltage When using the internal PLL with an external VCO < 1600 MHz, produces higher frequency) the PLL must be turned on. 0x010[7] = 1b PFD polarity negative (higher control voltage produces lower frequency) Rev. A | Page 31 of 84

AD9522-0 Data Sheet REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 E LOCK BL DETECT OPTIONALREFIN REF2 BUFSTATUSSTATUS CLOCKDOUBLER RDIVIDER PROGRAMMA R DELAY PLLREFERENCE HOLD REFIN AMP STATUS BYPASS LOW DROPOUT REGULATOR (LDO) PHASE PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK OUT0 OUT0 1 0 DIVIDE BY OUT1 PD 1 TO 32 OUT1 DIGITAL EEPROM SYNC LOGIC RESET OUT2 OUT2 EEPROM OUT3 SP1 SERIAL OUT3 PORT SP0 DECODE DIVIDE BY OUT4 1 TO 32 OUT4 SPI I2C S INTERFACE INTERFACE OUT5 PUT SCLK/SCL OUT5 UT O SDIO/SDA S SDO MO CS OUT6 C OUT6 DS/ V L DIVIDE BY OUT7 1 TO 32 OUT7 OUT8 OUT8 OUT9 OUT9 DIVIDE BY OUT10 1 TO 32 OUT10 AD9522 OUT11 OUT11 07219-031 Figure 37. Clock Distribution or External VCO < 1600 MHz (Mode 1) Rev. A | Page 32 of 84

Data Sheet AD9522-0 Mode 2: High Frequency Clock Distribution—CLK or Table 26. Default Register Settings for Clock Distribution Mode External VCO > 1600 MHz Register Description The AD9522 power-up default configuration has the PLL 0x010[1:0] = 01b PLL asynchronous power-down (PLL off) powered off and the routing of the input set so that the CLK/ 0x1E0[2:0] = 000b Set VCO divider = 2 CLK input is connected to the distribution section through the 0x1E1[0] = 0b Use the VCO divider VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ 0x1E1[1] = 0b CLK selected as the source divide-by-5/divide-by-6). This is a distribution-only mode that allows for an external input up to 2400 MHz (see Table 3). The When using the internal PLL with an external VCO, the PLL maximum frequency that can be applied to the channel dividers must be turned on. is 1600 MHz; therefore, higher input frequencies must be divided down before reaching the channel dividers. Table 27. Settings When Using an External VCO Register Description When the PLL is enabled, this routing also allows the use of the 0x010[1:0] = 00b PLL normal operation (PLL on) PLL with an external VCO or VCXO with a frequency <2400 MHz. 0x010 to 0x01E PLL settings; select and enable a In this configuration, the internal VCO is not used and is powered reference input; set R, N (P, A, B), PFD off. The external VCO/VCXO feeds directly into the prescaler. polarity, and I according to the intended CP The register settings shown in Table 26 are the default values of loop configuration these registers at power-up or after a reset operation. 0x1E1[1] = 0b CLK selected as the source An external VCO requires an external loop filter that must be connected between CP and the tuning pin of the VCO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO being used. Table 28. Setting the PFD Polarity Register Description 0x010[7] = 0b PFD polarity positive (higher control voltage produces higher frequency) 0x010[7] = 1b PFD polarity negative (higher control voltage produces lower frequency) Rev. A | Page 33 of 84

AD9522-0 Data Sheet REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 E LOCK BL DETECT OPTIONALREFIN REF2 BUFSTATUSSTATUS CLOCKDOUBLER RDIVIDER PROGRAMMA R DELAY PLLREFERENCE HOLD REFIN AMP STATUS BYPASS LOW DROPOUT REGULATOR (LDO) PHASE PRPE,SPC +A L1ER COUAN/TBERS PRO GNR DAEMLMAYABLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK OUT0 OUT0 1 0 DIVIDE BY OUT1 PD 1TO 32 OUT1 DIGITAL EEPROM SYNC LOGIC RESET OUT2 OUT2 EEPROM OUT3 SP1 SERIAL OUT3 PORT SP0 DECODE DIVIDE BY OUT4 1TO 32 OUT4 SPI I2C S INTERFACE INTERFACE OUT5 PUT SCLK/SCL OUT5 UT O SDIO/SDA S SDO O M CS OUT6 C OUT6 DS/ V L DIVIDE BY OUT7 1TO 32 OUT7 OUT8 OUT8 OUT9 OUT9 DIVIDE BY OUT10 1TO 32 OUT10 AD9522 OUT11 OUT11 07219-029 Figure 38. High Frequency Clock Distribution or External VCO > 1600 MHz (Mode 2) Rev. A | Page 34 of 84

Data Sheet AD9522-0 Phase-Locked Loop (PLL) REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 E LOCK BL DETECT OPTIONALREFIN REF2 BUFSTATUSSTATUS CLOCKDOUBLER RDIVIDER PROGRAMMA R DELAY PLLREFERENCE HOLD REFIN STATUS BYPASS LOW DROPOUT REGULATOR (LDO) PHASE PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK FROM CHANNEL CLK DIVIDER 0 1 0 07219-064 Figure 39. PLL Functional Block Diagram The AD9522 includes an on-chip PLL with an on-chip VCO. including the design of the PLL loop filter. The UG-077 is the The PLL blocks can be used either with the on-chip VCO to AD9522 evaluation software user guide that allows users to easily create a complete phase-locked loop or with an external VCO set the correct register values when the desired configuration is or VCXO. The PLL requires an external loop filter, which determined. Both are available at www.analog.com/clocks. usually consists of a small number of capacitors and resistors. Phase Frequency Detector (PFD) The configuration and components of the loop filter help to The PFD takes inputs from the R divider and the N divider and establish the loop bandwidth and stability of the operating PLL. produces an output proportional to the phase and frequency The AD9522 PLL is useful for generating clock frequencies difference between them. The PFD includes a programmable from a supplied reference frequency. This includes conversion delay element that controls the width of the antibacklash pulse. of reference frequencies to much higher frequencies for subsequent This pulse ensures that there is no dead zone in the PFD transfer division and distribution. In addition, the PLL can be used to clean function and minimizes phase noise and reference spurs. The up jitter and phase noise on a noisy reference. The exact choice of antibacklash pulse width is set by Register 0x017[1:0]. PLL parameters and loop dynamics is application specific. The An important limit to keep in mind is the maximum frequency flexibility and depth of the AD9522 PLL allow the part to be tailored allowed into the PFD. The maximum input frequency into the to function in many different applications and signal environments. PFD is a function of the antibacklash pulse setting, as specified Configuration of the PLL in the phase/frequency detector (PFD) parameter in Table 2. Charge Pump (CP) The AD9522 allows flexible configuration of the PLL, accommodating various reference frequencies, PFD comparison The charge pump is controlled by the PFD. The PFD monitors frequencies, VCO frequencies, internal or external VCO/VCXO, the phase and frequency relationship between its two inputs and and loop dynamics. This is accomplished by the various settings tells the CP to pump up or pump down to charge or discharge the for the R divider, the N divider, the PFD polarity (only applicable to integrating node (part of the loop filter). The integrated and external VCO/VCXO), the antibacklash pulse width, the charge filtered CP current is transformed into a voltage that drives the pump current, the selection of internal VCO or external VCO/ tuning node of the internal VCO through the LF pin (or the tuning VCXO, and the loop bandwidth. These are managed through pin of an external VCO) to move the VCO frequency up or down. programmable register settings (see Table 49 and Table 53) and The CP can be set (Register 0x010[3:2]) for high impedance by the design of the external loop filter. (allows holdover operation), for normal operation (attempts to lock the PLL loop), for pump-up, or for pump-down (test modes). Successful PLL operation and satisfactory PLL loop performance The CP current is programmable in eight steps from (nominally) are highly dependent upon proper configuration of the PLL 0.6 mA to 4.8 mA. The exact value of the CP current LSB is set by settings, and the design of the external loop filter is crucial to the CPRSET resistor and is calculated using the following equation: the proper operation of the PLL. 3.06 I = ADIsimCLK™ is a free program that can help with the design CP CPRSET and exploration of the capabilities and features of the AD9522, Rev. A | Page 35 of 84

AD9522-0 Data Sheet On-Chip VCO AD9522 EXTERNAL The AD9522 includes an on-chip VCO covering the frequency VCO/VCXO CLK/CLK range shown in Table 2. The calibration procedure ensures that the VCO operating voltage is centered for the desired VCO CP R2 frequency. The VCO must be calibrated when the VCO loop CHARGE R1 is first set up, as well as any time the nominal VCO frequency PUMP C1 C2 C3 scuhfafnicgieesn.t H oopwereavteinr,g o rnacneg teh teo V sCtaOy lios cckaelidb roavteedr ,t tehme pVeCraOtu hraes a nd 07219-265 voltage extremes without needing additional calibration. See Figure 41. Example of External Loop Filter for a PLL Using an External VCO the VCO Calibration section for additional information. Figure 42 and Figure 43 show the typical PLL loop filters used to To tune over the wide range of frequencies covered by this generate the plots in Figure 30 and Figure 31, respectively. VCO, tuning ranges are used. The calibration procedure selects R2 390Ω the correct range for the desired VCO frequency. See the VCO CP LF C2 Calibration section for additional information. C1 240nF C3 62pF R1 33pF The on-chip VCO is powered by an on-chip, low dropout (LDO), 820Ω BYPASS linear voltage regulator. The LDO provides some isolation of tBhYeP VACSOS p firno mm uvsatr ibaeti coonns ninec ttheed ptoo wgreor usnudp pblyy av o2l2ta0g neF le cvaepl.a Tcihtoer CAPFBAOYCRPI TALODSRSO C22102nF 07219-334 to ensure stability. This LDO employs the same technology used Figure 42. Typical PLL Loop Filter Used for Clock Generation in the anyCAP® line of regulators from Analog Devices, Inc., R2 making it insensitive to the type of capacitor used. Driving an 3kΩ CP LF external load from the BYPASS pin is not supported. C2 C1 4.7µF C3 When using an external VCO/VCXO, leave the BYPASS and LF 1.5nF R1 2.2nF 2.1kΩ pins floating. This configuration is shown in Figure 41. BYPASS PWLhLe Enx utseirnnga tlh Leo inotpe rFnialtl eVrC O, the external loop filter must be CAPFBAOYCRPI TALODSRSO C22102nF 07219-335 referenced to the BYPASS pin for optimal noise and spurious Figure 43. Typical PLL Loop Filter Used for Clock Cleanup performance. An example of an external loop filter for a PLL PLL Reference Inputs that uses the internal VCO is shown in Figure 40. A loop filter The AD9522 features a flexible PLL reference input circuit that must be calculated for each desired PLL configuration. The values allows a fully differential input, two separate single-ended inputs, of the components depend upon the VCO frequency, the K , VCO or a 16.62 MHz to 33.33 MHz crystal oscillator with an on-chip the PFD frequency, the CP current, the desired loop bandwidth, maintaining amplifier. An optional reference clock doubler and the desired phase margin. The loop filter affects the phase can be used to double the PLL reference frequency. The input noise, the loop settling time, and the loop stability. A basic frequency range for the reference inputs is specified in Table 2. knowledge of PLL theory is helpful for understanding loop filter Both the differential and the single-ended inputs are self-biased, design. The ADIsimCLK can help with the calculation of a loop allowing for easy ac coupling of input signals. filter according to the application requirements. Either a differential or a single-ended reference must be specifically When using an external VCO, the external loop filter must be enabled. All PLL reference inputs are off by default. referenced to ground. An example of an external loop filter for a PLL using an external VCO is shown in Figure 41. The differential input and the single-ended inputs share two pins, REFIN (REF1) and REFIN (REF2). The desired reference input AD9522 type is selected and controlled by Register 0x01C (see Table 49 and VCO LF Table 53). 31pF When the differential reference input is selected, the self-bias CP R2 level of the two sides is offset slightly (~100 mV, see Table 2) to CHARGE R1 prevent chattering of the input buffer when the reference is slow PUMP C1 C2 C3 BYPASS or missing. This increases the voltage swing that is required of CBP = 220nF 07219-065 tinhpe udtr icvaenr bane dd roivveenrc boym eeitsh tehre a ocf-fcsoeut.p Tlehde L dVifDfeSr eonrt aiacl- croefueprleendc e Figure 40. Example of External Loop Filter for a PLL Using the Internal VCO LVPECL signals. Rev. A | Page 36 of 84

Data Sheet AD9522-0 The single-ended inputs can be driven by either a dc-coupled references. When used in conjunction with the automatic holdover CMOS level signal or an ac-coupled sine wave or square wave. function, the AD9522 can achieve a worst-case reference input To avoid input buffer chatter when a single-ended, ac-coupled switchover with an output frequency disturbance as low as 10 ppm. input signal stops toggling, the user can set Register 0x018[7] to The AD9522 features a dc offset option in single-ended mode. 1b. This setting shifts the dc offset bias point down 140 mV. To This option is designed to eliminate the risk of the reference increase isolation and reduce power, each single-ended input can inputs chattering when they are ac-coupled and the reference be independently powered down. clock disappears. When using the reference switchover, the single- The differential reference input receiver is powered down when ended reference inputs must be dc-coupled CMOS levels (with it is not selected or when the PLL is powered down. The single- the AD9522 dc offset feature disabled). Alternatively, the inputs ended buffers power down when the PLL is powered down or can be ac-coupled and dc offset feature enabled. Keep in mind, when their respective individual power-down registers are set. however, that the minimum input amplitude for the reference When the differential mode is selected, the single-ended inputs inputs is greater when the dc offset is turned on. are powered down. Reference switchover can be performed manually or automatically. VS Manual switchover is performed either through Register 0x01C or by using the REF_SEL pin. Manual switchover requires the presence of a clock on the reference input that is being switched 85kΩ to; otherwise, the deglitching feature must be disabled in Bit 7 of Register 0x01C. The reference switching logic fails if this REF1 condition is not met, and the PLL does not reacquire. Automatic revertive switchover relies on the REFMON pin to VS indicate when REF1 disappears. By programming Register 0x01B = 10kΩ 12kΩ 0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed REFIN 150Ω high when REF1 is invalid, which commands the switch to REFIN REF2. When REF1 is valid again, the REFMON pin goes low, and 150Ω the device again locks to REF1. The STATUS pin can also be used 10kΩ 10kΩ for this function, and REF2 can be used as the preferred reference. A switchover deglitch feature ensures that the PLL does not receive VS REF2 rising edges that are far out of alignment with the newly selected reference. For the switchover deglitch feature to work correctly, the presence of a clock is required on the reference input that is 85kΩ being switched to. The deglitching feature can also be disabled (Register 0x01C[7]). 07219-066 Automatic nonrevertive switching is not supported. Figure 44. REFIN Equivalent Circuit for Non-XTAL Mode Reference Divider R In differential mode, the reference input pins are internally self- The reference inputs are routed to the reference divider, R. R (a biased so that they can be ac-coupled via capacitors. It is possible to 14-bit counter) can be set to any value from 0 to 16,383 by writing dc couple to these inputs. If the differential REFIN is driven by to Register 0x011 and Register 0x012. (Both R = 0 and R = 1 give a single-ended signal, decouple the unused side (REFIN) via a divide-by-1.) The output of the R divider goes to one of the PFD suitable capacitor to a quiet ground. Figure 44 shows the inputs to be compared with the VCO frequency divided by the equivalent circuit of REFIN. N divider. The frequency applied to the PFD must not exceed the Crystal mode is nearly identical to differential mode. The user maximum allowable frequency, which depends on the enables a maintaining amplifier by setting the enable XTAL antibacklash pulse setting (see Table 2). OSC bit, and putting a series resonant, AT fundamental cut The R divider has its own reset. The R divider can be reset using crystal across the REFIN/REFIN pins. the shared reset bit of the R, A, and B counters. It can also be Reference Switchover reset by a SYNC operation. The AD9522 supports dual single-ended CMOS inputs, as well VCO/VCXO Feedback Divider N: P, A, B as a single differential reference input. In the dual single-ended The N divider is a combination of a prescaler (P) and two counters, reference mode, the AD9522 supports automatic revertive and A and B. The total divider value is manual PLL reference clock switching between REF1 (on N = (P × B) + A Pin REFIN) and REF2 (on Pin REFIN). This feature supports networking and other applications that require redundant where P can be 2, 4, 8, 16, or 32. Rev. A | Page 37 of 84

AD9522-0 Data Sheet Prescaler The maximum input frequency to the A/B counter is reflected in the maximum prescaler output frequency (~300 MHz) specified The prescaler of the AD9522 allows for two modes of operation: in Table 2. This is the prescaler input frequency (VCO or CLK) a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM) divided by P. For example, dual modulus P = 8/9 mode is not mode where the prescaler divides by P and (P + 1) {2 and 3, 4 allowed if the VCO frequency is greater than 2400 MHz and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of because the frequency going to the A/B counter is too high. operation are given in Table 53, Register 0x016[2:0]. Not all modes are available at all frequencies (see Table 2). It is common to use When the AD9522 B counter is bypassed (B = 1), the A counter a prescaler of 8 for VC frequencies <2400 MHz, and P = 32 is must be set to zero, and the overall resulting divide is equal to usually used for very large feedback divider values only. the prescaler setting, P. The possible divide ratios in this mode are 1, 2, 3, 4, 8, 16, and 32. When operating the AD9522 in dual modulus mode, P/(P + 1), the equation used to relate the input reference frequency to the Although manual reset is not normally required, the A/B counters VCO output frequency is have their own reset bit. Alternatively, the A and B counters can be reset using the shared reset bit of the R, A, and B counters. Note f = (f /R) × (P × B + A) = f × N/R VCO REF REF that these reset bits are not self-clearing. However, when operating the prescaler in FD Mode 1, FD Mode 2, R, A, and B Counters: SYNC Pin Reset or FD Mode 3, the A counter is not used (A = 0; the divide is a fixed divide of P = 2, 4, 8, 16, or 32) and the equation simplifies to The R, A, and B counters can be reset simultaneously through the f = (f /R) × (P × B) = f × N/R SYNC pin. This function is controlled by Register 0x019[7:6] (see VCO REF REF Table 53). The SYNC pin reset is disabled by default. By using combinations of DM and FD modes, the AD9522 can achieve values of N from 1 to 262,175. R and N Divider Delays Table 29 shows how a 10 MHz reference input can be locked to Both the R and N dividers feature a programmable delay cell. any integer multiple of N. Note that the same value of N can be These delays can be enabled to allow adjustment of the phase derived in different ways, as illustrated by the case of N = 12. The relationship between the PLL reference clock and the VCO or CLK, user can choose a fixed divide mode of P = 2 with B = 6, use the and are useful for controlling the input/output phase relationship in dual modulus mode of 2/3 with A = 0, B = 6, or use the dual zero delay mode. Each delay is controlled by three bits. The total modulus mode of 4/5 with A = 0, B = 3. delay range is about 1 ns. See Register 0x019 in Table 2 and Table 53. A and B Counters The B counter must be ≥3 or bypassed, and unlike the R counter, A = 0 is actually zero. The B counter must always be greater than or equal to the A counter. Table 29. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N (X= Don’t Care) f (MHz) R P A B N f (MHz) Mode Notes REF VCO 10 1 1 X 1 1 10 FD P = 1, B = 1 (A and B counters are bypassed). 10 1 2 X 1 2 20 FD P = 2, B = 1 (A and B counters are bypassed). 10 1 1 X 3 3 30 FD A counter is bypassed. 10 1 1 X 4 4 40 FD A counter is bypassed. 10 1 1 X 5 5 50 FD A counter is bypassed. 10 1 2 X 3 6 60 FD A counter is bypassed. 10 1 2 0 3 6 60 DM 10 1 2 1 3 7 70 DM Maximum frequency into prescaler in P 2/3 mode is 200 MHz. If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz to 300 MHz, use P = 1 and N = 7, or 11, respectively. 10 1 2 2 3 8 80 DM 10 1 2 1 4 9 90 DM 10 1 8 6 18 150 1500 DM 10 1 8 7 18 151 1510 DM 10 1 16 7 9 151 1510 DM 10 10 32 6 47 151 1510 DM 10 1 8 0 25 200 2000 DM 10 1 16 0 15 240 2400 DM 10 10 32 0 75 2400 2400 DM Rev. A | Page 38 of 84

Data Sheet AD9522-0 Digital Lock Detect (DLD) VS = 3.3V AD9522 By selecting the proper output through the mux on each pin, the R2 LD R1 VOUT DLD function is available at the LD, STATUS, and REFMON pins. The digital lock detect circuit indicates a lock when the time ALD C dspifefceirfeiendc ev aoluf eth (eth rei sloincgk ethdrgeessh aotl dt)h. eT PhFe Dlo sisn pofu ats l oisc kle isss itnhdainca ate d 07219-067 when the time difference exceeds a specified value (the unlock Figure 45. Example of Analog Lock Detect Filter Using N-Channel Open-Drain Driver threshold). Note that the unlock threshold is wider than the lock threshold, which allows some phase error in excess of the Current Source Digital Lock Detect (CSDLD) lock window to occur without chattering on the lock indicator. During the PLL locking sequence, it is normal for the DLD The lock detect window timing depends on the value of the signal to toggle a number of times before remaining steady. CPRSET resistor, as well as three settings: the digital lock detect There may be applications where it is necessary to have DLD window bit (Register 0x018[4]), the antibacklash pulse width bit asserted without chattering and only after the PLL is solidly (Register 0x017[1:0], see Table 2), and the lock detect counter locked. This is possible by using the current source digital lock (Register 0x018[6:5]). The lock and unlock detection values in detect function. Table 2 are for the nominal value of CPRSET = 5.11 kΩ. The current source lock detect provides a current of 110 μA when Doubling the CPRSET value to 10 kΩ doubles the values in DLD is true and shorts to ground when DLD is false. If a capacitor Table 2. is connected to the LD pin, it charges at a rate determined by the A lock is not indicated until there is a programmable number of current source during the DLD true time but is discharged nearly consecutive PFD cycles with a time difference less than the lock instantly when DLD is false. By monitoring the voltage at the detect threshold. The lock detect circuit continues to indicate a LD pin (top of the capacitor), LD = high happens only after the lock until a time difference greater than the unlock threshold DLD is true for a sufficiently long time. Any momentary DLD occurs on a single subsequent cycle. For the lock detect to work false resets the charging. By selecting a properly sized capacitor, properly, the period of the PFD frequency must be greater than it is possible to delay a lock detect indication until the PLL is the unlock threshold. The number of consecutive PFD cycles stably locked and the lock detect does not chatter. required for lock is programmable (Register 0x018[6:5]). To use current source digital lock detect, do the following: Note that it is possible in certain low (<500 Hz) loop bandwidth,  Place a capacitor to ground on the LD pin high phase margin cases that the DLD can chatter during  Set Register 0x01A[5:0] = 0x04 acquisition, which can cause the AD9522 to automatically enter  Enable the LD pin comparator (Register 0x01D[3] = 1) and exit holdover. To avoid this problem, it is recommended that the user make provisions for a capacitor to ground on the The LD pin comparator senses the voltage on the LD pin, and the LD pin so that current source digital lock detect (CSDLD) mode comparator output can be made available at the REFMON pin can be used. control (Register 0x01B[4:0]) or the STATUS pin control (Register 0x017[7:2]). The internal LD pin comparator trip point and Analog Lock Detect (ALD) hysteresis are given in Table 17. The voltage on the capacitor can The AD9522 provides an ALD function that can be selected for also be sensed by an external comparator connected to the LD use at the LD pin. There are two operating modes for ALD. pin. In this case, enabling the on-board LD pin comparator is  N-channel open-drain lock detect. This signal requires a not necessary. pull-up resistor to the positive supply, VS. The output is The user can asynchronously enable individual clock outputs only normally high with short, low going pulses. Lock is when CSDLD is high. To enable this feature, set the appropriate bits indicated by the minimum duty cycle of the low going pulses. in the enable output on the CSDLD registers (Register 0x0FC and  P-channel open-drain lock detect. This signal requires a Register 0x0FD). pull-down resistor to GND. The output is normally low with AD9522 short, high going pulses. Lock is indicated by the minimum duty cycle of the high going pulses. 110µA The analog lock detect function requires an RC filter to provide a DLD LD VOUT logic level indicating lock/unlock. The ADIsimCLK tool can be C used to help the user select the right passive component values for ALD to ensure its correct operation. LD PIN COMPARATOR REFMON OR STATUS 07219-068 Figure 46. Current Source Digital Lock Detect Rev. A | Page 39 of 84

AD9522-0 Data Sheet External VCXO/VCO Clock Input (CLK/CLK) External/Manual Holdover Mode This differential input is used to drive the AD9522 clock A manual holdover mode can be enabled that allows the user to distribution section. This input can receive up to 2.4 GHz. place the charge pump into a high impedance state when the The pins are internally self-biased, and the input signal must be SYNC pin is asserted low. This operation is edge sensitive, not ac-coupled via capacitors. level sensitive. The charge pump enters a high impedance state CLOCK INPUT immediately. To take the charge pump out of a high impedance STAGE state, take the SYNC pin high. The charge pump then leaves the VS high impedance state synchronously with the next PFD rising CLK edge from the reference clock. This prevents extraneous charge pump events from occurring during the time between SYNC CLK going high and the next PFD event. This also means that the 2.5kΩ 2.5kΩ charge pump stays in a high impedance state if there is no 5kΩ reference clock present. 5kΩ 07219-032 The B counter (in the N divider) is reset synchronously with the Figure 47. CLK Equivalent Input Circuit charge pump leaving the high impedance state on the reference path PFD event. This helps align the edges out of the R and N The self-biased CLK/CLK input can be used either as a dividers for faster settling of the PLL. Because the prescaler is distribution only input (with the PLL off) or as a feedback input not reset, this feature works best when the B and R numbers are for an external VCO/VCXO using the internal PLL when the close because this results in a smaller phase difference for the internal VCO is not used. These inputs are also used as a loop to settle out. feedback path for the external zero delay mode. When using this mode, set the channel dividers to ignore the Holdover SYNC pin (at least after an initial SYNC event). If the dividers are The AD9522 PLL has a holdover function. Holdover mode not set to ignore the SYNC pin, any time SYNC is taken low to allows the VCO to maintain a relatively constant frequency even put the part into holdover, the distribution outputs turn off. The though there is no reference clock. This function is useful when channel divider ignore SYNC function is found in the PLL reference clock is lost. Holdover is implemented by placing Register 0x191[6], Register 0x194[6], Register 0x197[6], and the charge pump in a high impedance state. Without this function, Register 0x19A[6] for Channel Divider 0, Channel Divider 1, the charge pump is placed into a constant pump-up or pump-down Channel Divider 2, and Channel Divider 3, respectively. state, resulting in a significant VCO frequency shift. Because the Automatic/Internal Holdover Mode charge pump is placed in a high impedance state, any leakage that occurs at the charge pump output or the VCO tuning node When enabled, this function automatically puts the charge causes a drift of the VCO frequency. This drift can be mitigated pump into a high impedance state when the loop loses lock. by using a loop filter that contains a large capacitive component The assumption is that the only reason the loop loses lock is due because this drift is limited by the current leakage induced to the PLL losing the reference clock; therefore, the holdover slew rate (ILEAK/C) of the VCO control voltage. function puts the charge pump into a high impedance state to maintain the VCO frequency as close as possible to the original Both a manual holdover mode, using the SYNC pin, and an frequency before the reference clock disappeared. automatic holdover mode are provided. To use either function, the holdover function must be enabled (Register 0x01D[0]). A flowchart of the automatic/internal holdover function operation is shown in Figure 48. Rev. A | Page 40 of 84

Data Sheet AD9522-0 PLL ENABLED LOOP OUT OF LOCK. DIGITAL LOCK NO DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED DLD == LOW BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD. YES NO ANALOG LOCK DETECT PIN INDICATES WAS LOCK WAS PREVIOUSLY ACHIEVED. LD PIN == HIGH (0x01D[3] = 1; USE LD PIN VOLTAGE WHEN DLD WENT WITH HOLDOVER. LOW? 0x01D[3] = 0; IGNORE LD PIN VOLTAGE, TREAT LD PIN AS ALWAYS HIGH.) YES HIGH IMPEDANCE CHARGE PUMP IS MADE CHARGE PUMP HIGH IMPEDANCE. PLL COUNTERS CONTINUE OPERATING NORMALLY. NO CHARGE PUMP REMAINS HIGH REFERENCE IMPEDANCE UNTIL THE REFERENCE EDGE AT PFD? RETURNS. YES YES RELEASE TAKE CHARGE PUMP OUT OF CHARGE PUMP HIGH IMPEDANCE. PLL CAN HIGH IMPEDANCE NOW RESETTLE. NO WAIT FOR DLD TO GO HIGH. THIS TAKES 5 TO 255 CYCLES (PROGRAMMING OF THE DLD DELAY COUNTER) WITH THE REFERENCE AND DLD == HIGH FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT THE PFD. THIS ENSURES THAT THE HOLDOVER FBRUEENFTORCITRGIEOG NTEH RWEEA DHI.TOSL DFOOVRE TRH FEU PNLCLT TIOON S CEATNTL BEE AND LOCK 07219-069 Figure 48. Flowchart of Automatic/Internal Holdover Mode The holdover function senses the logic level of the LD pin as a As in the external holdover mode, the B counter (in the N divider) condition to enter holdover. The signal at LD can be from the is reset synchronously with the charge pump leaving the high DLD, ALD, or current source LD (CSDLD) mode. It is possible impedance state on the reference path PFD event. This helps to disable the LD comparator (Register 0x01D[3]), which causes align the edges out of the R and N dividers for faster settling of the holdover function to always sense LD as high. If DLD is the PLL and reduces frequency errors during settling. Because used, it is possible for the DLD signal to chatter while the PLL is the prescaler is not reset, this feature works best when the B and reacquiring lock. The holdover function may retrigger, thereby R numbers are close because this results in a smaller phase preventing the holdover mode from terminating. Use of the difference for the loop to settle out. current source lock detect mode is recommended to avoid this After leaving holdover, the loop then reacquires lock and the situation (see the Current Source Digital Lock Detect (CSDLD) LD pin must go high (if Register 0x01D[3] = 1) before it can section). reenter holdover. When in holdover mode, the charge pump stays in a high impedance state as long as there is no reference clock present. Rev. A | Page 41 of 84

AD9522-0 Data Sheet The holdover function always responds to the state of the • Register 0x01A[5:0] = 000100b; program LD pin control to currently selected reference (Register 0x01C). If the loop loses current source lock detect mode. lock during a reference switchover (see the Reference Switchover • Register 0x01C[4] = 1b; enable automatic switchover. section), holdover is triggered briefly until the next reference • Register 0x01C[3] = 0b; prefer REF1. clock edge at the PFD. • Register 0x01C[2:1] = 11b; enable REF1 and REF2 input The following registers affect the automatic/internal holdover buffers. function: • Register 0x01D[3] = 1b; enable LD pin comparator. • Register 0x018[6:5]—lock detect counter. This changes • Register 0x01D[1] = 0b; disable external holdover mode and use automatic/internal holdover mode. how many consecutive PFD cycles with edges inside the lock detect window are required for the DLD indicator to • Register 0x01D[0] = 1b; enable holdover. indicate lock. This impacts the time required before the LD Frequency Status Monitors pin can begin to charge as well as the delay from the end of The AD9522 contains three frequency status monitors that are a holdover event until the holdover function can be used to indicate if the PLL reference (or references in the case of reengaged. single-ended mode) and the external VCO/CLK input fall below • Register 0x018[3]—disable digital lock detect. This bit a threshold frequency. Note that the VCO frequency monitor must be set to 0 to enable the DLD circuit. becomes a CLK input frequency monitor if the CLK input is Internal/automatic holdover does not operate correctly selected instead of the internal VCO. A diagram showing their without the DLD function enabled. location in the PLL is shown in Figure 49. • Register 0x01A[5:0]—lock detect pin control. Set this to The PLL reference monitors have two threshold frequencies: 000100b to put it in the current source lock detect mode if normal and extended (see Table 17). The reference frequency using the LD pin comparator. Load the LD pin with a monitor thresholds are selected in Register 0x01A[6]. capacitor of an appropriate value. • Register 0x01D[3]—LD pin comparator enable. 1 = enable; VCO Calibration 0 = disable. When disabled, the holdover function always The AD9522 on-chip VCO must be calibrated to ensure proper senses the LD pin as high. operation over process and temperature. The VCO calibration • Register 0x01D[1]—external holdover control. is controlled by a calibration controller running off a divided • Register 0x01D[0]—holdover enable. If holdover is REFIN clock. The calibration requires that the PLL be set up disabled, both external and automatic/internal holdover properly to lock the PLL loop and that the REFIN clock be are disabled. present. The REFIN clock must come from a stable source external to the AD9522. In the following example, automatic holdover is configured with VCO calibration can be performed two ways: automatically at • Automatic reference switchover, prefer REF1. power-up and manually. Automatic VCO calibration occurs when • Digital lock detect: five PFD cycles, high range window. the EEPROM is set to automatically load the preprogrammed • Automatic holdover using the LD pin comparator. values in the EEPROM and then automatically calibrate the The following registers are set (in addition to the normal PLL VCO. A valid reference must be provided at power-up in order registers): for the automatic calibration to complete. If this is not the case, the user must calibrate the VCO manually. • Register 0x018[6:5] = 00b; lock detect counter = five cycles. • Register 0x018[4] = 0b; digital lock detect window = high range. • Register 0x018[3] = 1b; disable DLD normal operation. Rev. A | Page 42 of 84

Data Sheet AD9522-0 REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 E LOCK BL DETECT OPTIONALREFIN REF2 BUFSTATUSSTATUS CLOCKDOUBLER RDIVIDER PROGRAMMA R DELAY PLLREFERENCE HOLD REFIN VCO STATUS BYPASS LOW DROPOUT REGULATOR (LDO) PHASE PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF ZERO DELAY BLOCK STATUS DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK FROM CHANNEL CLK DIVIDER 0 1 0 07219-070 Figure 49. Reference and VCO/CLK Frequency Status Monitors The VCO calibration clock divider is set as shown in Table 53 During the first initialization after a power-up or a reset of the (Register 0x018[2:1]). AD9522, a manual VCO calibration sequence is initiated by setting Register 0x018[0] = 1b. This can be done as part of the The calibration divider divides the PFD frequency (reference initial setup before executing update registers (Register 0x232[0] = frequency divided by R) down to the calibration clock. The 1b). Subsequent to the initial setup, a VCO calibration sequence calibration occurs at the PFD frequency divided by the calibration is initiated by resetting Register 0x018[0] = 0b, executing an update divider setting. Lower VCO calibration clock frequencies result in registers operation, setting Register 0x018[0] = 1b, and longer times for a calibration to be completed. executing another update registers operation. A readback bit The VCO calibration clock frequency is given by (Register 0x01F[6]) indicates when a VCO calibration is finished f = f /(R × CAL_DIV) by returning a logic true (that is, 1b). CAL_CLOCK REFIN where: The sequence of operations for the VCO calibration follows: f is the frequency of the REFIN signal. REFIN 1. Program the PLL registers to the proper values for the PLL R is the value of the R counter. loop. Note that the VCO divider (Register 0x1E0[2:0]) CAL_DIV is the division set for the VCO calibration divider must not be set to static during VCO calibration. (Register 0x018[2:1]). 2. For the initial setting of the registers after a power-up or Choose a calibration divider such that the calibration frequency reset, initiate a VCO calibration by setting Register is less than 6.25 MHz. Table 30 shows the appropriate value for 0x018[0] = 1b. Subsequently, whenever a calibration is the calibration divider. desired, set Register 0x018[0] = 0b, update registers and set Register 0x018[0] = 1b, update registers. Table 30. VCO Calibration Divider Values for Different 3. A SYNC operation is initiated internally, causing the Phase Detector Frequencies outputs to go to a static state determined by normal SYNC PFD Rate (MHz) Recommended VCO Calibration Divider function operation. <12 Any 4. VCO is calibrated to the desired setting for the requested 12 to 25 4, 8, 16 VCO frequency. 25 to 50 8, 16 5. Internally, the SYNC signal is released, allowing outputs to 50 to 100 16 continue clocking. 6. The PLL loop is closed. The VCO calibration takes 4400 calibration clock cycles. Therefore, 7. PLL locks. the VCO calibration time in PLL reference clock cycles is given by A SYNC is executed during the VCO calibration; therefore, Time to Calibrate VCO = the outputs of the AD9522 are held static during the calibration, 4400 × R × CAL_DIV PLL Reference Clock Cycles which prevents unwanted frequencies from being produced. However, at the end of a VCO calibration, the outputs may resume clocking before the PLL loop is completely settled. Rev. A | Page 43 of 84

AD9522-0 Data Sheet Table 31. Example Time to Complete a VCO Calibration In addition, because the calibration procedure results in rapid with Different f Frequencies changes in the VCO frequency, the distribution section is REFIN f (MHz) R Divider PFD Time to Calibrate VCO automatically placed in SYNC until the calibration is finished. REFIN 100 1 100 MHz 88 µs Therefore, expect this temporary loss of outputs. 10 10 1 MHz 8.8 ms Initiate a VCO calibration in the following conditions: 10 100 100 kHz 88 ms • After changing any of the PLL R, P, B, and A divider settings The AD9522 does not automatically recalibrate its VCO when or after a change in the PLL reference clock frequency. This, the PLL settings change. This feature allows for flexibility in in effect, means any time a PLL register or reference clock is deciding what order to program the registers and when to initiate a changed such that a different VCO frequency results. calibration, instead of having it happen every time certain PLL • When system calibration is desired. The VCO is designed to registers have their values change. For example, this feature operate properly over extremes of temperature even when it allows for the VCO frequency to be changed by small amounts is first calibrated at the opposite extreme. However, a VCO without having an automatic calibration occur each time; calibration can be initiated at any time, if desired. however, do this with caution and only when the VCO control voltage does not exceed the nominal best performance limits. For example, a few 100 kHz steps are fine, but a few MHz may not be. Rev. A | Page 44 of 84

Data Sheet AD9522-0 REFIN/ R R AD9522 REFIN DIVIDER DELAY PFD CP LOOP FILTER N N DIVIDER DELAY REG 0x01E[1] = 1 MUX1 INTERNAL FEEDBACK PATH LF ZERO DELAY FEEDBACK CLOCK X3 U M EXTERNAL FEEDBACK PATH DIVIDE BY 1, REG 0x01E[0] 2, 3, 4, 5, OR 6 ZERO DELAY CLK/CLK CHANNEL DIVIDER 0 OUT0 TO OUT2 1 0 CHANNEL DIVIDER 1 OUT3 TO OUT5 CHANNEL DIVIDER 2 OUT6 TO OUT8 CHANNEL DIVIDER 3 OUT9 TO OUT11 07219-053 Figure 50. Zero Delay Function ZERO DELAY OPERATION PLL can be programmed to compensate for the propagation delay from the output drivers and PLL components to minimize Zero delay operation aligns the phase of the output clocks with the phase offset between the clock output and the reference the phase of the external PLL reference input. There are two input to achieve zero delay. zero delay modes on the AD9522: internal and external. External Zero Delay Mode Note that when the AD9522 is configured in zero delay mode with output frequencies that are integer multiples of each other The external zero delay function of the AD9522 is achieved by (for example, 50 MHz, 100 MHz, 200 MHz), it is critical to use feeding one clock output back to the CLK input and ultimately the lowest output frequency in the feedback path of the PLL. back to the PLL N divider. In Figure 50, the change in signal Otherwise, the input/output phase relationship of the lowest routing for external zero delay mode is shown in red. frequency is not guaranteed. Set Register 0x01E[2:1] = 11b to select the external zero delay Internal Zero Delay Mode mode. In external zero delay mode, one of the twelve output clocks (OUT0 to OUT11) can be routed back to the PLL (N The internal zero delay function of the AD9522 is achieved by divider) through the CLK/CLK pins and through MUX3 and feeding the output of Channel Divider 0 back to the PLL N MUX1. This feedback path is shown in red in Figure 50. divider. In Figure 50, the change in signal routing for internal zero delay mode is shown in blue. The user must specify which channel divider is used for external zero delay mode in order for VCO calibration to work correctly. Set Register 0x01E[2:1] = 01b to select internal zero delay mode. Channel Divider 0 is the default. Channel Divider 1, Channel Divider In the default internal zero delay mode, the output of Channel 2, or Channel Divider 3 can be selected for zero delay feedback by Divider 0 is routed back to the PLL (N divider) through MUX3 changing the value in Register 0x01E[4:3]. and MUX1 (feedback path shown in blue in Figure 50). The PLL synchronizes the phase/edge of the output of Channel Divider 0 The PLL synchronizes the phase/edge of the feedback output clock with the phase/edge of the reference input. External zero delay with the phase/edge of the reference input. Because the channel mode must be used if Channel Divider 1, Channel Divider 2, or dividers are synchronized to each other, the clock outputs are Channel Divider 3 is used for zero delay feedback. This is synchronous with the reference input. Both the R delay and the accomplished by changing the value in Register 0x01E[4:3]. N delay inside the PLL can be programmed to compensate for the propagation delay from the PLL components to minimize the Because the channel dividers are synchronized to each other, phase offset between the feedback clock and the reference input. the outputs of the channel divider are synchronous with the reference input. Both the R delay and the N delay inside the Rev. A | Page 45 of 84

AD9522-0 Data Sheet PLL PLL PLL LF LF LF DIVIDE BY 1, DIVIDE BY 1, DIVIDE BY 1, 2, 3, 4, 5, OR 6 2, 3, 4, 5, OR 6 2, 3, 4, 5, OR 6 CLK CLK CLK CLK CLK CLK 1 0 1 0 1 0 CLOCK CLOCK CLOCK DISTRI- DISTRI- DISTRI- DISTRIBUTION BUTION DISTRIBUTION BUTION DISTRIBUTION BUTION CLOCK CLOCK CLOCK MODE 0 (INTERNAL VCO MODE) MODE 1 (CLOCK DISTRIBUTION MODE) MODE 2 (HF CLOCK DISTRIBUTION MODE) 07219-054 Figure 51. Simplified Diagram of the Three Clock Distribution Operation Modes CLOCK DISTRIBUTION In addition, the channel dividers allow a coarse phase offset or delay to be set. Depending on the division selected, the output A clock channel consists of three LVDS clock outputs or six can be delayed by up to 15 input clock cycles. For example, if CMOS clock outputs that share a common divider. A clock the frequency at the input of the channel divider is 1 GHz, the output consists of the drivers that connect to the output pins. channel divider output can be delayed by up to 15 ns. The The clock outputs have either LVDS or CMOS at the pins. divider outputs can also be set to start high or to start low. The AD9522 has four clock channels. Each channel has its own Operation Modes programmable divider that divides the clock frequency applied to its input. The channel dividers can divide by any integer from There are three clock distribution operating modes, and these 1 to 32. Divide by 1 is achieved by setting the Divider n bypass are shown in Figure 51. One of these modes uses the internal bit (where n = 0 through 3) in the appropriate channel divider VCO, whereas the other two modes bypass the internal VCO register. and use the signal provided on the CLK/CLK pins. The AD9522 features a VCO divider that divides the VCO output In Mode 0 (internal VCO mode), there are two signal paths by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers. available. In the first path, the VCO signal is sent to the VCO The VCO divider has two purposes. The first is to limit the max- divider and then to the individual channel dividers. In the imum input frequency of the channel dividers to 1.6 GHz. See the second path, the user bypasses the VCO and channel dividers VCO Divider section for discussion of special cases where the and sends the VCO signal directly to the drivers. channel divider maximum input frequency is >1.6 GHz. The When CLK is selected as the source, it is not necessary to use the other is to allow the AD9522 to generate lower output VCO divider if the CLK frequency is less than the maximum frequencies than is normally possible with only a simple post channel divider input frequency (1600 MHz); otherwise, the divider. External clock signals connected to the CLK input can VCO divider must be used to reduce the frequency going to also use the VCO divider. the channel dividers. The channel dividers allow for a selection of various duty cycles, Table 32 shows how the VCO, CLK, and VCO divider are selected. depending on the currently set division. That is, for any specific Register 0x1E1[1:0] selects the channel divider source and division, D, the output of the divider can be set to high for N + 1 determines whether the VCO divider is used. It is not possible input clock cycles and low for M + 1 input clock cycles (where to select the VCO without using the VCO divider. D = N + M + 2). For example, a divide-by-5 can be high for one divider input cycle and low for four cycles, or a divide-by-5 can Table 32. Operation Modes be high for three divider input cycles and low for two cycles. 0x1E1 Other combinations are also possible. Mode [1] [0] Channel Divider Source VCO Divider The channel dividers include a duty-cycle correction function 2 0 0 CLK Used that can be disabled. In contrast to the selectable duty cycle 1 0 1 CLK Not used just described, this function can correct a non-50% duty cycle 0 1 0 VCO Used caused by an odd division. However, this requires that the 1 1 Not allowed Not allowed division be set by M = N + 1. Note that the duty cycle correction feature is not available when the VCO divider is set to 1. Rev. A | Page 46 of 84

Data Sheet AD9522-0 Clock Frequency Division Channel Dividers The total frequency division is a combination of the VCO A channel divider drives each group of three LVDS outputs. divider (when used) and the channel divider. When the VCO There are four channel dividers (0, 1, 2, and 3) driving 12 LVDS divider is used, the total division from the VCO or CLK to the outputs (OUT0 to OUT11). Table 34 gives the register locations output is the product of the VCO divider (1, 2, 3, 4, 5, and 6) used for setting the division and other functions of these dividers. and the division of the channel divider. Table 33 indicates how the The division is set by the values of M and N. The divider can be frequency division for a channel is set. bypassed (equivalent to divide-by-1, divider circuit is powered down) by setting the bypass bit. The duty-cycle correction can Table 33. Frequency Division be enabled or disabled according to the setting of the disable Channel Resulting divider DCC bits. CLK or VCO VCO Divider Divider Frequency Selected Setting1 Setting Division Table 34. Setting D for the Output Dividers X CLK or VCO input 1 to 6 2 to 32 (1 to 6) × (2 to 32) Disable CLK or VCO input 2 to 6 Bypass (2 to 6) × (1) Divider Low Cycles M High Cycles N Bypass Div DCC CLK or VCO input 1 Bypass Output static 0 0x190[7:4] 0x190[3:0] 0x191[7] 0x192[0] (illegal state) 1 0x193[7:4] 0x193[3:0] 0x194[7] 0x195[0] CLK(internal VCO divider Bypass 1 2 0x196[7:4] 0x196[3:0] 0x197[7] 0x198[0] VCO off) bypassed 3 0x199[7:4] 0x199[3:0] 0x19A[7] 0x19B[0] CLK (internal VCO divider 2 to 32 2 to 32 VCO off) bypassed Channel Divider Maximum Frequency 1 The bypass VCO divider (Register 0x1E1[0] = 1) is not the same as VCO divider = 1. The maximum frequency at which all features of the channel The channel dividers feeding the output drivers contain one divider are guaranteed to work is 1.6 GHz; this is the number that 2-to-32 frequency divider. This divider provides for division-by-1 appears elsewhere in the data sheet. However, if the divide-by-3 to division-by-32. Division-by-1 is accomplished by bypassing and divide-by-17 settings are avoided, the maximum channel the divider. The dividers also provide for a programmable duty divider input frequency is 2 GHz. cycle, with optional duty-cycle correction when the divide ratio Channel Frequency Division (0, 1, 2, and 3) is odd. A phase offset or delay in increments of the input clock For each channel (where the channel number x is 0, 1, 2, or 3), cycle is selectable. The channel dividers operate with a signal at the frequency division, D , is set by the values of M and N X their inputs up to 1600 MHz. The features and settings of the (four bits each, representing Decimal 0 to Decimal 15), where dividers are selected by programming the appropriate setup and control registers (see Table 49 through Table 60). Number of Low Cycles = M + 1 Number of High Cycles = N + 1 VCO Divider The high and low cycles are cycles of the clock signal currently routed The VCO divider provides frequency division between the to the input of the channel dividers (VCO divider out or CLK). internal VCO or the external CLK input and the clock distribution channel dividers. The VCO divider can be set When a divider is bypassed, DX = 1. to divide by 1, 2, 3, 4, 5, or 6 (see Table 56, Register 0x1E0[2:0]). Otherwise, D = (N + 1) + (M + 1) = N + M + 2. This allows X However, when the VCO divider is set to 1, none of the channel each channel divider to divide by any integer from 2 to 32. output dividers can be bypassed. Duty Cycle and Duty-Cycle Correction The VCO divider can also be set to static, which is useful for The duty cycle of the clock signal at the output of a channel is a applications where the only desired output frequency is the result of some or all of the following conditions: VCO frequency. Making the VCO divider static increases the wide band spurious-free dynamic range (SFDR). If the VCO • The M and N values for the channel divider is static during VCO calibration, there is no output • DCC enabled/disabled signal. Therefore, it is important to calibrate the VCO with the • VCO divider enabled/bypassed VCO divider set to a nonstatic value during VCO calibration, • The CLK input duty cycle (note that the internal VCO has and then set the VCO divider to static when VCO calibration is a 50% duty cycle) complete. The DCC function is enabled by default for each channel divider. The recommended alternative to achieving the same SFDR However, the DCC function can be disabled individually for performance is to set the VCO divider to 1. This allows the user each channel divider by setting the disable divider DCC bit for to program the EEPROM with the desired values and does not that channel. require further action after the VCO calibration is complete. Rev. A | Page 47 of 84

AD9522-0 Data Sheet Certain M and N values for a channel divider result in a non- D Output Duty Cycle X 50% duty cycle. A non-50% duty cycle can also result with an VCO Disable Div even division, if M ≠ N. The duty-cycle correction function Divider N + M + 2 DCC = 1 Disable Div DCC = 0 automatically corrects non-50% duty cycles at the channel divider Odd = 5 Even (N + 1)/ 50%, requires M = N output to 50% duty cycle. Note that the duty-cycle correction (N + M + 2) feature is not available when the VCO divider is set to 1. Odd = 5 Odd (N + 1)/ (5N + 7 + X%)/(10N + 15), (N + M + 2) requires M = N + 1 Duty-cycle correction requires the following channel divider conditions: Table 37. Channel Divider Output Duty Cycle When the • An even division must be set as M = N. VCO Divider Is Enabled and Set to 1 • An odd division must be set as M = N + 1. Input DX Output Duty Cycle • The VCO divider is not set to 1. Clock Disable Div Duty Cycle N + M + 2 DCC = 1 Disable Div DCC = 0 When not bypassed or corrected by the DCC function, the duty Any Even (N + 1)/ 50%, requires M = N cycle of each channel divider output is the numerical value of (M + N + 2) (N + 1)/(N + M + 2) expressed as a percent. 50% Odd (N + 1)/ (N + 1)/(M + N + 2) The duty cycle at the output of the channel divider for various (M + N + 2) configurations is shown in Table 35 to Table 38. X% Odd (N + 1)/ (N + 1 + X%)/(2 × N + 3), (M + N + 2) requires M = N + 1 Table 35. Channel Divider Output Duty Cycle with VCO Divider ≠ 1, Input Duty Cycle Is 50% Note that the channel divider must be enabled when the VCO D Output Duty Cycle divider = 1. X Disable Div Disable Div Table 38. Channel Divider Output Duty Cycle When the VCO Divider N + M + 2 DCC = 1 DCC = 0 VCO Divider Is Bypassed Even Channel divider 50% 50% bypassed Input DX Output Duty Cycle Clock Disable Div Odd = 3 Channel divider 33.3% 50% Duty Cycle N + M + 2 DCC = 1 Disable Div DCC = 0 bypassed Any Channel Same as input Same as input duty Odd = 5 Channel divider 40% 50% divider duty cycle cycle bypassed bypassed Even, odd Even (N + 1)/ 50%, requires Any Even (N + 1)/ 50%, requires M = N (N + M + 2) M = N (M + N + 2) Even, odd Odd (N + 1)/ 50%, requires 50% Odd (N + 1)/ 50%, requires M = N + 1 (N + M + 2) M = N + 1 (M + N + 2) X% Odd (N + 1)/ (N + 1 + X%)/(2 × N + 3), Table 36. Channel Divider Output Duty Cycle with VCO (M + N + 2) requires M = N + 1 Divider ≠ 1, Input Duty Cycle Is X% D Output Duty Cycle X The internal VCO has a duty cycle of 50%. Therefore, when the VCO Disable Div VCO divider equals 1, the duty cycle is 50%. If the CLK input is Divider N + M + 2 DCC = 1 Disable Div DCC = 0 routed directly to the output, the duty cycle of the output is the Even Channel 50% 50% same as the CLK input. divider bypassed Phase Offset or Coarse Time Delay Odd = 3 Channel 33.3% (1 + X%)/3 Each channel divider allows for a phase offset, or a coarse time divider delay, to be programmed by setting register bits (see Table 39). bypassed These settings determine the number of cycles (successive rising Odd = 5 Channel 40% (2 + X%)/5 edges) of the channel divider input frequency by which to offset, or divider delay, the rising edge of the output of the divider. This delay is with bypassed respect to a nondelayed output (that is, with a phase offset of zero). Even Even (N + 1)/ 50%, requires M = N (N + M + 2) The amount of the delay is set by five bits loaded into the phase Even Odd (N + 1)/ 50%, requires M = N + 1 offset (PO) register plus the start high (SH) bit for each channel (N + M + 2) divider. When the start high bit is set, the delay is also affected Odd = 3 Even (N + 1)/ 50%, requires M = N by the number of low cycles (M) programmed for the divider. (N + M + 2) It is necessary to use the SYNC function to make phase offsets Odd = 3 Odd (N + 1)/ (3N + 4 + X%)/(6N + 9), effective (see the Synchronizing the Outputs— Function section). (N + M + 2) requires M = N + 1 Rev. A | Page 48 of 84

Data Sheet AD9522-0 Table 39. Setting Phase Offset and Division  Synchronization of the outputs can be executed as part of Start Phase Low Cycles High Cycles the chip power-up sequence. Divider High (SH) Offset (PO) M N  The RESET pin is forced low and then released (chip reset). 0 0x191[4] 0x191[3:0] 0x190[7:4] 0x190[3:0]  The PD pin is forced low and then released (chip power-down). 1 0x194[4] 0x194[3:0] 0x193[7:4] 0x193[3:0]  Whenever a VCO calibration is completed, an internal 2 0x197[4] 0x197[3:0] 0x196[7:4] 0x196[3:0] SYNC signal is automatically asserted at the beginning and 3 0x19A[4] 0x19A[3:0] 0x199[7:4] 0x199[3:0] released upon the completion of a VCO calibration. Let Δ = delay (in seconds). The most common way to execute the SYNC function is to use t Δ = delay (in cycles of clock signal at input to D ). the SYNC pin to perform a manual synchronization of the outputs. c X T = period of the clock signal at the input of the divider, D (in This requires a low going signal on the SYNC pin, which is held X X seconds). low and then released when synchronization is desired. The Φ = timing of the SYNC operation is shown in Figure 53 (using the 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0] VCO divider) and in Figure 54 (the VCO divider is not used). There is an uncertainty of up to one cycle of the clock at the The channel divide by is set as N = high cycles and M = low cycles. input to the channel divider due to the asynchronous nature of Case 1 the SYNC signal with respect to the clock edges inside the For Φ ≤ 15, AD9522. Δ = Φ × T t X The pipeline delay from the SYNC rising edge to the beginning Δ = Δ/T = Φ c t X of the synchronized output clocking is between 14 cycles and Case 2 15 cycles of clock at the channel divider input, plus one cycle of For Φ ≥ 16, the VCO divider input (see Figure 53) or one cycle of the channel Δ = (Φ − 16 + M + 1) × T t X divider input (see Figure 54), depending on whether the VCO Δ = Δ/T c t X divider is used. Cycles are counted from the rising edge of the By giving each divider a different phase offset, output-to-output signal. In addition, there is an additional 1.2 ns (typical) delay from delays can be set in increments of the channel divider input the SYNC signal to the internal synchronization logic, as well as clock cycle. Figure 52 shows the results of setting such a coarse the propagation delay of the output driver. The driver propagation offset between outputs. delay is approximately 100 ps for the LVDS driver and 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 approximately 1.5 ns for the CMOS driver. CHANNEL DIVIDER INPUT Tx Another common way to execute the SYNC function is by CHANNEL DIVIDER OUTPUTS DIV = 4, DUTY = 50% setting and resetting the soft SYNC bit at Register 0x230[0]. Both DIVIDER 0 PSOH == 00 setting and resetting of the soft SYNC bit require an update all registers (Register 0x232[0] = 1b) operation to take effect. SH = 0 DIVIDER 1 PO = 1 A SYNC operation brings all outputs that are not excluded (by the SH = 0 ignore SYNC bit) to a preset condition before allowing the DIVIDER 2 PO = 2 Figure 52. Effect of12 C ××o TTaxxrse Phase Offset (or Delay) 07219-071 otbaiutkt aepnsu dtins i tttoos pbahceacgsoineu ocnlftof stcehkte.i n Tsgeh tietnsi nes ygsnse tcithninr eogasnc ighcoi tvoyef. r Ttnhh ebe o cpthhrae tnshenet e cslot’san tsditcai tsrittoa nhte i g h Synchronizing the Outputs—SYNC Function of each output when the SYNC operation is happening and the The AD9522 clock outputs can be synchronized to each other. state and relative phase of the outputs when they begin clocking Outputs can be individually excluded from synchronization. again upon completion of the SYNC operation. A SYNC operation Synchronization consists of setting the nonexcluded outputs to a must take place for the phase offsets setting to take effect. preset set of static conditions. These conditions include the divider The AD9522 differential LVDS outputs are four groups of three, ratio and phase offsets for a given channel divider. This allows sharing a channel divider per triplet. In the case of CMOS, each the user to specify different divide ratios and phase offsets for each LVDS differential pair can be configured as two single-ended of the four channel dividers. Releasing the SYNC pin allows the CMOS outputs. The synchronization conditions apply to all of outputs to continue clocking with the preset conditions applied. the drivers that belong to that channel divider. Synchronization of the outputs is executed in the following ways: Each channel (a divider and its outputs) can be excluded from  The SYNC pin is forced low and then released (manual sync). any SYNC operation by setting the ignore SYNC bit of the channel.  By setting and then resetting any one of the following three Channels that are set to ignore SYNC (excluded channels) do bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit not set their outputs static during a SYNC operation, and their (Register 0x000[5] [mirrored]), and the power-down outputs are not synchronized with those of the included channels. distribution reference bit (Register 0x230[1]). Rev. A | Page 49 of 84

AD9522-0 Data Sheet CHANNEL DIVIDER CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC OUTPUT CLOCKING INPUT TO VCO DIVIDER 1 INPUT TO CHANNEL DIVIDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT 07219-073 Figure 53. SYNC Timing Pipeline Delay When the VCO Divider Is Used—CLK or VCO Is Input CHANNEL DIVIDER CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC OUTPUT CLOCKING INPUT TO CLK 1 INPUT TO CHANNEL DIVIDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT 07219-074 Figure 54. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used—CLK Input Only LVDS Output Drivers 3.5mA The AD9522 output drivers can be configured as either an LVDS differential output or as a pair of CMOS single-ended outputs. The LVDS outputs allow for selectable output current OUT from ~1.75 mA to ~7 mA. OUT The LVDS output polarity can be set as noninverting or inverting, which allows for the adjustment of the relative pbooalarrdi tlya yoof uotu cthpuantsg we. iEthaicnh a LnV aDppS loicuattpiount cwainth boeu itn rdeiqvuidiruianlgly a 3.5mA 07219-134 powered down to save power. Figure 55. LVDS Output Simplified Equivalent Circuit with 3.5 mA Typical Current Source Rev. A | Page 50 of 84

Data Sheet AD9522-0 CMOS Output Drivers When Bit 2 and Bit 5 are set and the EEPROM pin is high, the chip is restored to the settings saved in the EEPROM. When Bit 2 The user can also individually configure each LVDS output as a and Bit 5 are set and the EEPROM pin is low, the chip is restored to pair of CMOS outputs, which provides up to 24 CMOS outputs. the on-chip defaults. When an output is configured as CMOS, CMOS Output A and CMOS Output B are automatically turned on. For a given Except for the self-clearing bits, Bit 2 and Bit 5, Register 0x000 differential pair, either CMOS Output A or Output B can be retains its previous value prior to reset. During the internal reset, turned on or off independently. The user can also select the the outputs hold static. However, the self-clearing operation relative polarity of the CMOS outputs for any combination of does not complete until an additional serial port SCLK cycle inverting and noninverting (see Register 0x0F0 to Register 0x0FB). occurs, and the AD9520 is held in reset until that happens. The user can power down each CMOS output as needed to save Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via power. The CMOS output power-down is individually controlled the Serial Port by the enable CMOS output register (Register 0x0F0[6:5] to The serial port control register allows the chip to be reset to settings Register 0x0FB[6:5]). The CMOS driver is in tristate when it is in EEPROM when the EEPROM pin = 1 via Register 0xB02[1]. powered down. This bit is self-clearing. This bit does not have any effect when VS_DRV the EEPROM pin = 0. It takes ~20 ms for the outputs to begin toggling after the SOFT_EEPROM register is cleared. POWER-DOWN MODES OUT1/ OUT1 Chip Power-Down via PD 07219-035 Tthhee P ADD p9i5n2 l2o cwa.n P boew peur-t dinotwon a tpuorwnes ro-dffo mwno scto onfd tihtieo nfu bnyc ptiuolnlisn gan d Figure 56. CMOS Equivalent Output Circuit currents inside the AD9522. The chip remains in this power-down RESET MODES state until PD is brought back to logic high. When taken out of power-down mode, the AD9522 returns to the settings programmed The AD9522 has a power-on reset (POR) and several other into its registers prior to the power-down, unless the registers ways to apply a reset condition to the chip. are changed by new programming while the PD pin is held low. Power-On Reset Powering down the chip shuts down the currents on the chip. During chip power-up, a power-on reset pulse is issued when Because this is not a complete power-down, it can be called VS reaches ~2.6 V (<2.8 V) and restores the chip either to the sleep mode. The AD9522 contains special circuitry to prevent setting stored in EEPROM (with the EEPROM pin = 1) or to runt pulses on the outputs when the chip is entering or exiting the on-chip setting (with the EEPROM pin = 0). At power-on, sleep mode. the AD9522 also executes a SYNC operation, ~50 ms after the supply reaches ~2.4 V, which brings the outputs into phase When the AD9522 is in a PD power-down, the chip is in the alignment according to the default settings. It takes ~70 ms for following state: the outputs to begin toggling after the power-on reset pulse • The PLL is off (asynchronous power-down). signal is internally generated. • The VCO is off. Hardware Reset via the RESET Pin • The CLK input buffer is off, but the CLK input dc bias circuit is on. RESET, a hard reset (an asynchronous hard reset is executed by • In differential mode, the reference input buffer is off, but briefly pulling RESET low), restores the chip either to the setting the dc bias circuit is still on. stored in EEPROM (the EEPROM pin = 1b) or to the on-chip • In singled-ended mode, the reference input buffer is off, setting (the EEPROM pin = 0b). A hard reset also executes a and the dc bias circuit is off. SYNC operation, bringing the outputs into phase alignment • All dividers are off. according to the default settings. When EEPROM is inactive (the EEPROM pin = 0b), it takes ~2 µs for the outputs to begin • All CMOS outputs are tristated. toggling after RESET is issued. When EEPROM is active (the • All LVDS outputs are in power-down (high impedance) EEPROM pin = 1b), it takes ~20 ms for the outputs to toggle after mode. RESET is brought high. • The serial control port is active, and the chip responds to commands. Soft Reset via the Serial Port The serial port control register allows for a soft reset by setting Bit 2 and Bit 5 in Register 0x000. The function of this register is determined by the state of the EEPROM pin. Rev. A | Page 51 of 84

AD9522-0 Data Sheet PLL Power-Down Individual Clock Output Power-Down The PLL section of the AD9522 can be selectively powered Any of the clock distribution outputs can be put into power- down. There are two PLL power-down modes set by down mode by individually writing to the appropriate registers. Register 0x010[1:0]: asynchronous and synchronous. The register map details the individual power-down settings for each output. These settings are found in Register 0x0F0[0] to In asynchronous power-down mode, the device powers down as Register 0x0FB[0]. soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to Individual Clock Channel Power-Down prevent unwanted frequency jumps. The device goes into power- Any of the clock distribution channels can be powered down down on the occurrence of the next charge pump event after the individually by writing to the appropriate registers. Powering registers are updated. down a clock channel is similar to powering down an individual Distribution Power-Down driver, but it saves more power because the dividers are also powered down. Powering down a clock channel also automatically The distribution section can be powered down by writing powers down the drivers connected to it. The register map Register 0x230[1] = 1b, which turns off the bias to the details the individual power-down settings for each output distribution section. If the LVDS power-down mode is normal channel. These settings are found in Register 0x192[2], operation (0b), it is possible for a low impedance load on that Register 0x195[2], Register 0x198[2], and Register 0x19B[2]. LVDS output to draw significant current during this power- down. If the LVDS power-down mode is set to 1b, the LVDS output is not protected from reverse bias and can be damaged under certain termination conditions. Rev. A | Page 52 of 84

Data Sheet AD9522-0 SERIAL CONTROL PORT The AD9522 serial control port is a flexible, synchronous serial I2C Bus Characteristics communications port that allows an easy interface with many Table 41. I2C Bus Definitions industry-standard microcontrollers and microprocessors. The Abbreviation Definition AD9522 serial control port is compatible with most synchronous S Start transfer formats, including Philips I2C, Motorola® SPI®, and Sr Repeated start Intel® SSR protocols. The AD9522 I2C implementation deviates P Stop from the classic I2C specification on two specifications, and A Acknowledge these deviations are documented in Table 14 of this data sheet. The serial control port allows read/write access to all registers A No acknowledge that configure the AD9522. W Write R Read SPI/I²C PORT SELECTION The AD9522 has two serial interfaces, SPI and I2C. Users can One pulse on the SCL clock line is generated for each data bit select either SPI or I2C depending on the states of the three transferred. logic level (high, open, low) input pins, SP1 and SP0. When The data on the SDA line must not change during the high both SP1 and SP0 are high, the SPI interface is active. Otherwise, period of the clock. The state of the data line can change only when I2C is active with eight different I2C slave address (seven bits the clock on the SCL line is low. wide) settings, see Table 40. The four MSBs of the slave address are hardware coded as 1011, and the three LSBs are programmed DATA LINE CHANGE STABLE; OF DATA by SP1 and SP0. DATA VALID ALLOWED SDA Table 40. Serial Port Mode Selection SLoPw1 SLoPw0 AI²Cd,d 1r0e1s1s 000 SCL 07219-160 Low Open I²C, 1011001 Figure 57. Valid Bit Transfer Low High I²C, 1011010 A start condition is a transition from high to low on the SDA Open Low I²C, 1011011 line while SCL is high. The start condition is always generated Open Open I²C, 1011100 by the master to initialize the data transfer. Open High I²C, 1011101 A stop condition is a transition from low to high on the SDA High Low I²C, 1011110 line while SCL is high. The stop condition is always generated High Open I²C, 1011111 by the master to end the data transfer. High High SPI SDA I²C SERIAL PORT OPERATION The AD9522 I2C port is based on the I2C fast mode standard. SCL S P T(1h0e0 A kDH9z5) 2a2n dsu fpapsto rmtso bdoet h(4 I02C0 kpHrozt)o.c ols: standard mode COSNTDAIRTITON COSNTDOITPION 07219-161 Figure 58. Start and Stop Conditions The AD9522 I2C port has a 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). In an I2C bus system, A byte on the SDA line is always eight bits long. An acknowledge the AD9522 is connected to the serial bus (data bus SDA and bit must follow every byte. Bytes are sent MSB first. clock bus SCL) as a slave device, meaning that no clock is generated The acknowledge bit is the ninth bit attached to any 8-bit data by the AD9522. The AD9522 uses direct 16-bit (two bytes) byte. An acknowledge bit is always generated by the receiving memory addressing instead of traditional 8-bit (one byte) memory device (receiver) to inform the transmitter that the byte has addressing. been received. It is accomplished by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte. Rev. A | Page 53 of 84

AD9522-0 Data Sheet SDA MSB ACKNOWLEDGE FROM ACKNOWLEDGE FROM SLAVE-RECEIVER SLAVE-RECEIVER SCL S 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 1P0 07219-162 Figure 59. Acknowledge Bit SDA MSB = 0 ACKNOWLEDGE FROM ACKNOWLEDGE FROM SLAVE-RECEIVER SLAVE-RECEIVER SCL S 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 1P0 07219-163 Figure 60. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration) SDA MSB = 1 ACKNOWLEDGE FROM NO ACKNOWLEDGE MASTER-RECEIVER FROM SLAVE-RECEIVER SCL S 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 1P0 07219-164 Figure 61. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration) Data is then sent over the serial bus in the format of nine clock The no acknowledge bit is the ninth bit attached to any 8-bit pulses, one data byte (8-bit) from either master (write mode) or data byte. A no acknowledge bit is always generated by the slave (read mode) followed by an acknowledge bit from the receiving device (receiver) to inform the transmitter that the receiving device. The number of bytes that can be transmitted per byte has not been received. It is done by leaving the SDA line transfer is unrestricted. In write mode, the first two data bytes high during the ninth clock pulse after each 8-bit data byte. immediately after the slave address byte are the internal memory Data Transfer Process (control registers) address bytes with the high address byte first. The master initiates data transfer by asserting a start condition. This addressing scheme gives a memory address up to 216 − 1 = This indicates that a data stream follows. All I2C slave devices 65,535. The data bytes after these two memory address bytes are connected to the serial bus respond to the start condition. register data written into the control registers. In read mode, the data bytes after the slave address byte are register data read from The master then sends an 8-bit address byte over the SDA line, the control registers. consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, When all data bytes are read or written, stop conditions are whether data is written to or read from the slave device established. In write mode, the master (transmitter) asserts a (0 = write, 1 = read). stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the The peripheral whose address corresponds to the transmitted slave device (receiver). In read mode, the master device (receiver) address responds by sending an acknowledge bit. All other receives the last data byte from the slave device (transmitter) devices on the bus remain idle while the selected device waits but does not pull it low during the ninth clock pulse. This is for data to be read from or written to it. If the R/W bit is 0, the known as a no acknowledge bit. By receiving the no acknowledge master (transmitter) writes to the slave device (receiver). If the bit, the slave device knows that the data transfer is finished and R/W bit is 1, the master (receiver) reads from the slave device releases the SDA line. The master then takes the data line low (transmitter). during the low period before the 10th clock pulse and high The format for these commands is described in the Data during the 10th clock pulse to assert a stop condition. Transfer Format section. A repeated start (Sr) condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. Rev. A | Page 54 of 84

Data Sheet AD9522-0 Data Transfer Format Send byte format—the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A RAM Address High Byte A RAM Address Low Byte A P Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. RAM Address RAM Address S Slave Address W A High Byte A Low Byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address. S Slave Address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A P Read byte format—the combined format of the send byte and the receive byte. Slave RAM Address RAM Address Slave RAM RAM RAM S Address W A High Byte A Low Byte A Sr Address R A Data 0 A Data 1 A Data 2 A P I²C Serial Port Timing SDA tFALL tSET; DAT tFALL tHLD; STR tSPIKE tRISE tIDLE t t LOW RISE SCL S tHLD; STR tHLD; DAT tHIGH tSET; STR Sr tSET; STP P S 07219-165 Figure 62. I²C Serial Port Timing Table 42. I2C Timing Definitions Parameter Description f I²C clock frequency I2C t Bus idle time between stop and start conditions IDLE t Hold time for repeated start condition HLD; STR t Setup time for repeated start condition SET; STR t Setup time for stop condition SET; STP t Hold time for data HLD; DAT t Setup time for data SET; DAT t Duration of SCL clock low LOW t Duration of SCL clock high HIGH t SCL/SDA rise time RISE t SCL/SDA fall time FALL t Voltage spike pulse width that must be suppressed by the input filter SPIKE Rev. A | Page 55 of 84

AD9522-0 Data Sheet SPI SERIAL PORT OPERATION In the streaming mode (see Table 43), any number of data bytes Pin Descriptions can be transferred in a continuous stream. The register address is automatically incremented or decremented (see the SPI SCLK (serial clock) is the serial shift clock. This pin is an input. MSB/LSB First Transfers section). CS must be raised at the end SCLK is used to synchronize serial control port reads and writes. of the last byte to be transferred, thereby ending streaming mode. Write data bits are registered on the rising edge of this clock. Communication Cycle—Instruction Plus Data The read data bits transition on the falling edge of SCLK. This pin is internally pulled down by a 30 kΩ resistor to ground. There are two parts to a communication cycle with the AD9522. SDIO (serial data input/output) is a dual-purpose pin and acts The first part writes a 16-bit instruction word into the AD9522, either as an input only (unidirectional mode) or as an input/ coincident with the first 16 SCLK rising edges. The instruction output (bidirectional mode). The AD9522 defaults to the word provides the AD9522 serial control port with information bidirectional I/O mode (Register 0x000[7] = 0b). regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether SDO (serial data out) is used only in the unidirectional I/O mode the upcoming data transfer is a read or a write, the number of (Register 0x000[7] = 1b) as a separate output pin for reading back bytes in the data transfer, and the starting register address for data. the first byte of the data transfer. CS (chip select bar) is an active low control that gates the read Write and write cycles. When CS is high, SDO and SDIO are in a high If the instruction word is for a write operation, the second part impedance state. This pin is internally pulled up by a 30 kΩ is the transfer of data into the serial control port buffer of the resistor to VS. AD9522. Data bits are registered on the rising edge of SCLK. CS 15 The length of the transfer (one, two, or three bytes, or streaming AD9522 SCLK/SCL 16 mode) is indicated by two bits (W1:W0) in the instruction byte. SERIAL SDIO/SSDDOA 1187 COPNOTRRTOL 07219-036 CWSh ceann tbhee rtaraisnesdf earf tise ro enaec, htw soeq, oure nthcree oef b eyitgehst, bbuitts n toot ssttarella tmhein bgu, s Figure 63. Serial Control Port (except after the last byte, where it ends the cycle). When the bus SPI Mode Operation is stalled, the serial transfer resumes when CS is lowered. Raising the CS pin on a nonbyte boundary resets the serial control port. In SPI mode, single or multiple byte transfers are supported, as During a write, streaming mode does not skip over reserved or well as MSB first or LSB first transfer formats. The AD9522 blank registers, and the user can write 0x00 to the reserved serial control port can be configured for a single bidirectional register addresses. I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/ SDO). By default, the AD9522 is in bidirectional mode. Short Because data is written into a serial control port buffer area, not instruction mode (8-bit instructions) is not supported. Only directly into the actual control registers of the AD9522, an long (16-bit) instruction mode is supported. It is possible that additional operation is needed to transfer the serial control port serial activity on the SDIO/SDO pins may induce jitter on the buffer contents to the actual control registers of the AD9522, PLL while data is transmitted. thereby causing them to become active. The update registers operation consists of setting Register 0x232[0] = 1b (this bit is A write or a read operation to the AD9522 is initiated by pulling self-clearing). Any number of bytes of data can be changed CS low. before executing an update registers operation. The update The CS stalled high mode is supported in data transfers where registers operation simultaneously actuates all register changes three or fewer bytes of data (plus instruction data) are transferred that have been written to the buffer since any previous update. (see Table 43). In this mode, the CS pin can temporarily return Read high on any byte boundary, allowing time for the system controller The AD9522 supports only the long instruction mode. If the to process the next byte. CS can go high on byte boundaries only instruction word is for a read operation, the next N × 8 SCLK and can go high during either part (instruction or data) of the cycles clock out the data from the address specified in the transfer. instruction word, where N is 1 to 3 as determined by W1:W0. During this period, the serial control port state machine enters If N = 4, the read operation is in streaming mode, continuing a wait state until all data is sent. If the system controller decides until CS is raised. Streaming mode does not skip over reserved to abort the transfer before all of the data is sent, the state machine or blank registers. The readback data is valid on the falling must be reset by either completing the remaining transfers or by edge of SCLK. returning CS low for at least one complete SCLK cycle (but fewer than eight SCLK cycles). Raising the CS pin on a nonbyte boundary terminates the serial transfer and flushes the buffer. Rev. A | Page 56 of 84

Data Sheet AD9522-0 The default mode of the AD9522 serial control port is the SPI MSB/LSB FIRST TRANSFERS bidirectional mode. In bidirectional mode, both the sent data The AD9522 instruction word and byte data can be MSB first and the readback data appear on the SDIO pin. It is also possible to or LSB first. Any data written to Register 0x000 must be set the AD9522 to unidirectional mode (Register 0x000[7] = 1 mirrored; the upper four bits ([7:4]) must mirror the lower four and Register 0x000[0] = 1). In unidirectional mode, the bits ([3:0]). This makes it irrelevant whether LSB first or MSB readback data appears on the SDO pin. first is in effect. As an example of this mirroring, see the default A readback request reads the data that is in the serial control setting for Register 0x000, which mirrors Bit 4 and Bit 3. This port buffer area or the data that is in the active registers (see sets the long instruction mode, which is the default and the only Figure 64). Readback of the buffer or active registers is controlled mode supported. by Register 0x004[0]. The default for the AD9522 is MSB first. The AD9522 uses Register Address 0x000 to Register When LSB first is set by Register 0x000[1] and Register 0x000[6], it Address 0xB03. takes effect immediately because it only affects the operation of the serial control port and does not require that an update be SCLK/SCCSL REGISTERS REGISTERS eWxehceunt eMd.S B first mode is active, the instruction and data bytes SDIO/SDA ER UPDATE VE must be written from MSB to LSB. Multibyte data transfers in SDO SCPEOORRNITTARLOL BUFF REGISTERS ACTI MregSiBst feirr satd fdorremssa to fs ttahret mwiothst asnig innisftircuanctti odnat ab ybtyet eth. aStu ibnscelquudeens tt he WTOR IUTPED RAETGEI SRTEEGRIS 0TxE2R32S = 0x001 07219-037 dloawta a bdydtreess ms. uInst MfoSllBo wfi risnt omrdodere ,f rtohme s tehriea hl icgohn tardodl rpeossr tt oin ttheren al Figure 64. Relationship Between Serial Control Port Buffer Registers and address generator decrements for each data byte of the multibyte Active Registers of the AD9522 transfer cycle. SPI INSTRUCTION WORD (16 BITS) When LSB first is active, the instruction and data bytes must be The MSB of the instruction word is R/W, which indicates written from LSB to MSB. Multibyte data transfers in LSB first whether the instruction is a read or a write. The next two bits format start with an instruction byte that includes the register (W1:W0) indicate the length of the transfer in bytes. The final address of the least significant data byte followed by multiple 13 bits are the address (A12:A0) at which to begin the read or data bytes. In a multibyte transfer cycle, the internal byte write operation. address generator of the serial port increments for each byte. For a write, the instruction word is followed by the number of The AD9522 serial control port register address decrements bytes of data indicated by Bits[W1:W0], see Table 43. from the register address just written toward Register 0x000 for multibyte I/O operations if the MSB first mode is active Table 43. Byte Transfer Count (default). If the LSB first mode is active, the register address of W1 W0 Bytes to Transfer the serial control port increments from the address just written 0 0 1 toward Register 0x232 for multibyte I/O operations. 0 1 2 1 0 3 Streaming mode always terminates when it reaches Register 0x232. 1 1 Streaming mode Note that unused addresses are not skipped during multibyte I/O operations. Bits[A12:A0] select the address within the register map that is Table 44. Streaming Mode (No Addresses Are Skipped) written to or read from during the data transfer portion of the Write Mode Address Direction Stop Sequence communications cycle. For multibyte transfers, this address is LSB first Increment 0x230, 0x231, 0x232, stop the starting byte address. In MSB first mode, subsequent bytes MSB first Decrement 0x001, 0x000, 0x232, stop decrement the address. Rev. A | Page 57 of 84

AD9522-0 Data Sheet Table 45. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLKDON'T CARE DON'T CARE SDIODON'T CARE R/W W1 W0 A12A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA 07219-038 Figure 65. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data t DS t tS tDH HIGH tCLK tC CS tLOW SCLK DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A0 DON’T CARE SDO HIGH IMPEDANCE D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA 07219-039 Figure 66. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data tDS tHIGH tS t tCLK tC CS DH tLOW SCLK DON'TCARE DON'TCARE SDIO DON'TCARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'TCARE 07219-040 Figure 67. Serial Control Port Read—MSB First, 16-Bit Instruction, Timing Measurements CS SCLK t DV SSDDIOO ((43--WWIIRREE MMOODDEE)) DATABITN DATABITN–1 DATABIT1 DBAITTA0 HIGH IMPEDANCE 07219-041 Figure 68. Timing Diagram for Serial Control Port Register Read CS SCLKDON'T CARE DON'T CARE SDIODON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10A11A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA 07219-042 Figure 69. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data Rev. A | Page 58 of 84

Data Sheet AD9522-0 t t S C CS t CLK t t HIGH LOW t SCLK DS t DH SDIO BIT N BIT N + 1 07219-043 Figure 70. Serial Control Port Timing—Write Table 46. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) S t Setup time between SCLK rising edge and the CS rising edge (end of communication cycle) C t Minimum period that SCLK must be in a logic high state HIGH t Minimum period that SCLK must be in a logic low state LOW t SCLK to valid SDIO and SDO (see Figure 68) DV Rev. A | Page 59 of 84

AD9522-0 Data Sheet EEPROM OPERATIONS The AD9522 contains an internal EEPROM (nonvolatile memory). 2. The readback register, STATUS_EEPROM (Register 0xB00[0]), The EEPROM can be programmed by users to create and store is used to indicate the data transfer status between the a user-defined register setting file when the power is off. This EEPROM and the control registers (0 = done/inactive; 1 = setting file can be used for power-up and chip reset as a default in process/active). At the beginning of the data transfer, setting. The EEPROM size is 512 bytes. STATUS_EEPROM is set to 1 by the EEPROM controller and cleared to 0 at the end of the data transfer. The user To guarantee proper loading of the EEPROM during startup, a can access STATUS_EEPROM through the STATUS pin high-low-high pulse on the RESET pin must occur after the when the STATUS pin is programmed to monitor power supply stabilizes. STATUS_EEPROM. Alternatively, the user can monitor During the data transfer process, the write and read registers via the STATUS_EEPROM bit. the serial port are generally not available except for one readback 6. After the data transfer process is done (Register 0xB00[0] = 0), register, STATUS_EEPROM. set the enable EEPROM write register (Register 0xB02[0]) to 0 To determine the data transfer state through the serial port to disable writing to the EEPROM. in SPI mode, users can read the value of STATUS_EEPROM To verify that the data transfer has completed correctly, the user (1 = in process and 0 = completed). can verify that Register 0xB01[0] = 0. A value of 1 in this register In I²C mode, the user can address the AD9522 slave port with indicates a data transfer error. the external I²C master (send an address byte to the AD9522). If READING FROM THE EEPROM the AD9522 responds with a no acknowledge bit, the data transfer process is not done. If the AD9522 responds with an acknowledge The following reset-related events can start the process of bit, the data transfer process is completed. The user can monitor restoring the settings stored in EEPROM to control registers. the STATUS_EEPROM register or program the STATUS pin to When the EEPROM pin is set high, do any of the following: monitor the status of the data transfer. 1. Power up the AD9522. WRITING TO THE EEPROM 2. Perform a hardware chip reset by pulling the RESET pin The EEPROM cannot be programmed directly through the serial low, and then releasing RESET. port interface. To program the EEPROM and store a register 3. Set the self-clearing soft reset bit (Register 0x000[5]) to 1. setting file, do the following: When the EEPROM pin is set low, set the self-clearing 1. Program the AD9522 registers to the desired circuit state. If SOFT_EEPROM bit (Register 0xB02[1]) to 1. The AD9522 then the user wants the PLL to lock automatically after power-up, starts to read the EEPROM and loads the values into the the VCO calibration now bit (Register 0x018[0]) must be AD9522. set to 1. This allows VCO calibration to start automatically If the EEPROM pin is low during reset or power-up, the after register loading. Note that a valid input reference EEPROM is not active, and the AD9522 default values are signal must be present during VCO calibration. loaded instead. 2. Program the EEPROM buffer registers, if necessary (see When using the EEPROM to automatically load the AD9522 the Programming the EEPROM Buffer Segment section). register values and lock the PLL, the VCO calibration now bit 1. This is only necessary if users want to use the EEPROM to (Register 0x018[0]) must be set to 1 when the register values are control the default setting of some (but not all) of the written to the EEPROM. This allows VCO calibration to start AD9522 registers, or if they want to control the register automatically after register loading. A valid input reference setting update sequence during power-up or chip reset. signal must be present during VCO calibration. 3. Set the enable EEPROM write bit (Register 0xB02[0]) to 1 to enable the EEPROM. To verify that the data transfer has completed correctly, the user 4. Set the REG2EEPROM bit (Register 0xB03[0]) to 1. can verify that Register 0xB01[0] = 0. A value of 1 in this register 5. Set the IO_UPDATE bit (Register 0x232[0]) to 1, which indicates a data transfer error. starts the process of writing data into the EEPROM to create the EEPROM setting file. This enables the AD9522 EEPROM controller to transfer the current register values, as well as the memory address and instruction bytes from the EEPROM buffer segment, into the EEPROM. After the write process is completed, the internal controller sets Register 0xB03[0] (REG2EEPROM) back to 0. Rev. A | Page 60 of 84

Data Sheet AD9522-0 PROGRAMMING THE EEPROM BUFFER SEGMENT IO_UPDATE (Operational Code 0x80) The EEPROM buffer segment is a register space on the AD9522 The EEPROM controller uses Operational Code 0x80 to generate that allows the user to specify which groups of registers are an IO_UPDATE signal to update the active control register stored to the EEPROM during EEPROM programming. Normally, bank from the buffer register bank during the download process. this segment does not need to be programmed by the user. Instead, At a minimum, there must be at least one IO_UPDATE the default power-up values for the EEPROM buffer segment operational code after the end of the final register section definition allow the user to store all of the AD9522 register values from group. This is needed so that at least one IO_UPDATE occurs after Register 0x000 to Register 0x231 to the EEPROM. all of the AD9522 registers are loaded when the EEPROM is For example, if users want to load only the output driver settings read. If this operational code is absent during a write to the from the EEPROM without disturbing the PLL register settings EEPROM, the register values loaded from the EEPROM are not currently stored in the AD9522, they can alter the EEPROM buffer transferred to the active register space, and these values do not segment to include only the registers that apply to the output take effect after they are loaded from the EEPROM to the AD9522. drivers and exclude the registers that apply to the PLL configuration. End-of-Data (Operational Code 0xFF) There are two parts to the EEPROM buffer segment: register The EEPROM controller uses Operational Code 0xFF to section definition groups and operational codes. Each register terminate the data transfer process between EEPROM and the section definition group contains the starting address and control register during the upload and download process. The number of bytes to be written to the EEPROM. last item appearing in the EEPROM buffer segment must be If the AD9522 register map were continuous from Address 0x000 either this operational code or the pseudo-end-of-data to Address 0x232, only one register section definition group operational code. would consist of a starting address of 0x000 and a length of Pseudo-End-of-Data (Operational Code 0xFE) 563 bytes. However, this is not the case. The AD9522 register The AD9522 EEPROM buffer segment has 23 bytes that can map is noncontiguous, and the EEPROM is only 512 bytes long. contain up to seven register section definition groups. If users Therefore, the register section definition group tells the EEPROM want to define more than seven register section definition groups, controller how the AD9522 register map is segmented. the pseudo-end-of-data operational code (0xFE) can be used. There are three operational codes: IO_UPDATE, end-of-data, During the upload process, when the EEPROM controller and pseudo-end-of-data. It is important that the EEPROM buffer receives the pseudo-end-of-data operational code, it halts the segment always have either an end-of-data or a pseudo-end-of-data data transfer process, clears the REG2EEPROM bit, and enables operational code and that an IO_UPDATE operation code appear the AD9522 serial port. Users can then program the EEPROM at least once before the end-of-data op code. buffer segment again and reinitiate the data transfer process by Register Section Definition Group setting the REG2EEPROM bit (Register 0xB03) to 1 and the IO_UPDATE bit (Register 0x232) to 1. The internal I²C master The register section definition group is used to define a continuous then begins writing to the EEPROM starting from the EEPROM register section for the EEPROM profile. It consists of three bytes. address held from the last writing. The first byte defines how many continuous register bytes are in this group. If the user puts 0x000 in the first byte, it means there This sequence enables more discrete instructions to be written is only one byte in this group. If the user puts 0x001, it means to the EEPROM than would otherwise be possible due to the there are two bytes in this group. The maximum number of limited size of the EEPROM buffer segment. It also permits the registers in one group is 128. user to write to the same register multiple times with a different value each time. The next two bytes are the low byte and high byte of the memory address (16-bit) of the first register in this group. Rev. A | Page 61 of 84

AD9522-0 Data Sheet Table 47. Example of EEPROM Buffer Segment Reg Addr (Hex) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Start EEPROM Buffer Segment 0xA00 0 Number of bytes [6:0] of the first group of registers 0xA01 Address [15:8] of the first group of registers 0xA02 Address [7:0] of the first group of registers 0xA03 0 Number of bytes [6:0] of the second group of registers 0xA04 Address [15:8] of the second group of registers 0xA05 Address [7:0] of the second group of registers 0xA06 0 Number of bytes [6:0] of the third group of registers 0xA07 Address [15:8] of the third group of registers 0xA08 Address [7:0] of the third group of registers 0xA09 IO_UPDATE operational code (0x80) 0xA0A End-of-data operational code (0xFF) Rev. A | Page 62 of 84

Data Sheet AD9522-0 THERMAL PERFORMANCE Table 48. Thermal Parameters for the 64-Lead LFCSP Symbol Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Value (°C/W) θ Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) 22.0 JA θ Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) 19.2 JMA θ Junction-to-ambient thermal resistance, 2.0 m/sec airflow per JEDEC JESD51-6 (moving air) 17.2 JMA Ψ Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) 11.6 JB and JEDEC JESD51-8 θ Junction-to-case thermal resistance (die-to-heat sink) per MIL-STD 883, Method 1012.1 1.3 JC Ψ Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) 0.1 JT The AD9522 is specified for a case temperature (T ). To ensure Values of θ are provided for package comparison and PCB CASE JA that T is not exceeded, an airflow source can be used. design considerations. θ can be used for a first-order CASE JA approximation of T by the equation Use the following equation to determine the junction J temperature on the application PCB: T = T + (θ × PD) J A JA TJ = TCASE + (ΨJT × PD) where TA is the ambient temperature (°C). where: Values of θ are provided for package comparison and PCB JC T is the junction temperature (°C). design considerations when an external heat sink is required. J T is the case temperature (°C) measured by the user at the CASE Values of Ψ are provided for package comparison and PCB JB top center of the package. design considerations. Ψ is the value from Table 48. JT PD is the power dissipation (see the total power dissipation in Table 18.) Rev. A | Page 63 of 84

AD9522-0 Data Sheet REGISTER MAP Register addresses that are not listed in Table 49 are not used, and writing to those registers has no effect. Writing to register addresses marked unused must have 00h written to them, unless otherwise noted. N/A is not applicable. Table 49. Register Map Overview Default Addr Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) Serial Port Configuration 000 Serial port config SDO active LSB first/ Soft reset Unused Unused Soft reset LSB first/ SDO active 00 (SPI mode) addr incr (self- (self- addr incr clearing) clearing) Serial port config Unused Soft reset Unused Unused Soft reset Unused 00 (I²C mode) (self- (self- clearing) clearing) 001 Unused N/A 002 Silicon revision Silicon revision (read only) 11 003 Part ID Part ID (read only) 20 004 Readback Unused Readback 00 control active regs EEPROM ID 005 EEPROM EEPROM customer version ID (LSB) 00 customer 006 EEPROM customer version ID (MSB) 00 version ID 007 Unused 00 to 00F PLL 010 PFD charge PFD polarity Charge pump current Charge pump mode PLL power-down 7D pump 011 14-bit R counter, Bits[7:0] (LSB) 01 R counter 012 Unused 14-bit R counter, Bits[13:8] (MSB) 00 013 A counter Unused 6-bit A counter 00 014 13-bit B counter, Bits[7:0] (LSB) 03 B counter 015 Unused 13-bit B counter, Bits[12:8] (MSB) 00 016 PLL_CTRL_1 Set CP pin Reset Reset Reset all B counter Prescaler P 06 to VCP/2 R counter A and B counters bypass counters 017 PLL_CTRL_2 STATUS pin control Antibacklash pulse width 00 018 PLL_CTRL_3 Enable CMOS Lock detect counter Digital Disable VCO calibration divider VCO 06 reference input lock digital calibration dc offset detect lock detect now window 019 PLL_CTRL_4 R, A, B counters R path delay N path delay 00 SYNC pin reset 01A PLL_CTRL_5 Enable STATUS Ref freq LD pin control 00 pin divider monitor threshold 01B PLL_CTRL_6 Enable VCO Enable Enable REFMON pin control 00 frequency REF2 REF1 monitor frequency (REFIN) monitor frequency monitor 01C PLL_CTRL_7 Disable Select Use Reserved Enable Enable Enable 00 switchover REF2 REF_SEL REF2 REF1 differential deglitch pin reference 01D PLL_CTRL_8 Enable Enable Enable Disable Enable LD Unused Enable Enable 80 STATUS_EEPROM XTAL clock PLL status pin external holdover at STATUS pin OSC doubler register comparator holdover Rev. A | Page 64 of 84

Data Sheet AD9522-0 Default Addr Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) 01E PLL_CTRL_9 Unused External zero delay Enable Enable Unused 00 feedback external zero delay channel divider select zero delay 01F PLL_READBACK Unused VCO cal Holdover REF2 VCO freq > REF2 REF1 freq > Digital lock N/A (read only) finished active selected threshold freq > threshold detect threshold Output Driver Control 0F0 OUT0 control OUT0 format OUT0 CMOS OUT0 polarity OUT0 LVDS OUT0 62 configuration differential voltage LVDS power-down 0F1 OUT1 control OUT1 format OUT1 CMOS OUT1 polarity OUT1 LVDS OUT1 62 configuration differential voltage LVDS power-down 0F2 OUT2 control OUT2 format OUT2 CMOS OUT2 polarity OUT2 LVDS OUT2 62 configuration differential voltage LVDS power-down 0F3 OUT3 control OUT3 format OUT3 CMOS OUT3 polarity OUT3 LVDS OUT3 62 configuration differential voltage LVDS power-down 0F4 OUT4 control OUT4 format OUT4 CMOS OUT4 polarity OUT4 LVDS OUT4 62 configuration differential voltage LVDS power-down 0F5 OUT5 control OUT5 format OUT5 CMOS OUT5 polarity OUT5 LVDS OUT5 62 configuration differential voltage LVDS power-down 0F6 OUT6 control OUT6 format OUT6 CMOS OUT6 polarity OUT6 LVDS OUT6 62 configuration differential voltage LVDS power-down 0F7 OUT7 control OUT7 format OUT7 CMOS OUT7 polarity OUT7 LVDS OUT7 62 configuration differential voltage LVDS power-down 0F8 OUT8 control OUT8 format OUT8 CMOS OUT8 polarity OUT8 LVDS OUT8 62 configuration differential voltage LVDS power-down 0F9 OUT9 control OUT9 format OUT9 CMOS OUT9 polarity OUT9 LVDS OUT9 62 configuration differential voltage LVDS power-down 0FA OUT10 control OUT10 format OUT10 CMOS OUT10 polarity OUT10 LVDS OUT10 62 configuration differential voltage LVDS power-down 0FB OUT11 control OUT11 format OUT11 CMOS OUT11 polarity OUT11 LVDS OUT11 62 configuration differential voltage LVDS power-down 0FC Enable output CSDLD En CSDLD En CSDLD En CSDLD En CSDLD En CSDLD En CSDLD En CSDLD En 00 on CSDLD OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 0FD Enable output Unused Unused Unused Unused CSDLD En CSDLD En CSDLD En CSDLD En 00 on CSDLD OUT11 OUT10 OUT9 OUT8 0FE Unused 00 to 18F LVDS Channel Dividers 190 Divider 0 Divider 0 low cycles Divider 0 high cycles 77 191 Divider 0 Divider 0 Divider 0 Divider 0 Divider 0 00 bypass ignore force start high phase offset SYNC high 192 Unused Unused Channel 0 Reserved Disable 00 power- Divider 0 down DCC Rev. A | Page 65 of 84

AD9522-0 Data Sheet Default Addr Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) 193 Divider 1 Divider 1 low cycles Divider 1 high cycles 33 194 Divider 1 Divider 1 Divider 1 Divider 1 Divider 1 00 bypass ignore force start high phase offset SYNC high 195 Unused Unused Channel 1 Reserved Disable 00 power- Divider 1 down DCC 196 Divider 2 Divider 2 low cycles Divider 2 high cycles 11 197 Divider 2 Divider 2 Divider 2 Divider 2 Divider 2 00 bypass ignore force start high phase offset SYNC high 198 Unused Unused Channel 2 Reserved Disable 00 power- Divider 2 down DCC 199 Divider 3 Divider 3 low cycles Divider 3 high cycles 00 19A Divider 3 Divider 3 Divider 3 Divider 3 Divider 3 00 bypass ignore force start high phase offset SYNC high 19B Unused Unused Channel 3 Reserved Disable 00 power- Divider 3 down DCC 19C Unused 00 to 1DF VCO Divider and CLK Input 1E0 VCO divider Unused VCO divider 00 1E1 Input CLKs Unused Power - Power- Power- Select Bypass VCO 00 down down VCO down VCO or CLK divider clock clock VCO input interface and CLK section 1E2 Unused 00 to 22A System 230 Power-down Unused Disable Power- Power- Soft 00 and SYNC power-on down down SYNC SYNC SYNC distribution reference 231 Unused Unused 00 Update All Registers 232 IO_UPDATE Unused IO_UPDATE 00 (self-clearing) 233 Unused 00 to 9FF EEPROM Buffer Segment A00 Serial port Data transfer: one byte 00 A01 configuration Starting address: Address 0x000 00 A02 00 A03 EEPROM Data transfer: three bytes 02 A04 Customer Starting address: Address 0x004 00 Version ID A05 04 A06 PLL settings Data transfer: 16 bytes 0E A07 Starting address: Address 0x010 00 A08 10 A09 Output driver Data transfer: 16 bytes 0E A0A control Starting address: Address 0x0F0 00 A0B F0 Rev. A | Page 66 of 84

Data Sheet AD9522-0 Default Addr Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) A0C LVDS channel Data transfer: 12 bytes 0B A0D dividers Starting address: Address 0x190 01 A0E 90 A0F VDO divider Data transfer: two bytes 01 A10 and CLK input Starting address: Address 0x1E0 01 A11 E0 A12 Power-down Data transfer: two bytes 01 A13 and SYNC Starting address: Address 0x230 02 A14 30 A15 I/O update Action: IO_UPDATE 80 A16 End of data Action: end of data FF A17 Unused Unused (available for additional EEPROM instructions) 00 to AFF EEPROM Control B00 EEPROM status Unused Unused STATUS_ 00 (read only) EEPROM B01 EEPROM error Unused Unused EEPROM 00 checking data error (read only) B02 EEPROM Unused SOFT_ Enable 00 Control 1 EEPROM EEPROM (self- write clearing) B03 EEPROM Unused Unused REG2EEPROM 00 Control 2 (self-clearing) Rev. A | Page 67 of 84

AD9522-0 Data Sheet REGISTER MAP DESCRIPTIONS Table 50 through Table 60 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by squared brackets. For example, [3] refers to Bit 3 and [5:2] refers to the range of bits from Bit 5 through Bit 2. Table 50. SPI Mode Serial Port Configuration Reg Addr (Hex) Bit(s) Name Description 000 [7] SDO active Selects unidirectional or bidirectional data transfer mode. [7] = 0; SDIO pin used for write and read; SDO is high impedance (default). [7] = 1; SDO used for read; SDIO used for write; unidirectional mode. 000 [6] LSB first/addr incr SPI MSB or LSB data orientation. (This register is ignored in I2C mode.) [6] = 0; data-oriented MSB first; addressing decrements (default). [6] = 1; data-oriented LSB first; addressing increments. 000 [5] Soft reset Soft reset. [5] = 1 (self-clearing). Soft reset; restores default values to internal registers. This bit self-clears on the next SCLK cycle after the completion of writing to this register and does not reset the value of Register 0x000. 000 [4] Unused 000 [3:0] Mirror[7:4] Bits[3:0] must always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows: [0] = [7] [1] = [6] [2] = [5] [3] = [4] 002 [7:0] Silicon revision This read only register identifies the revision level of the AD9522. 003 [7:0] Part ID (read only) Uniquely identifies the dash version (AD9522-0 through AD9522-5) of the AD9522. AD9522-0: 0x20 AD9522-1: 0x60 AD9522-2: 0xA0 AD9522-3: 0x61 AD9522-4: 0xE1 AD9522-5: 0xE0 004 [0] Readback active registers Select register bank used for a readback. [0] = 0; read back buffer registers (default). [0] = 1; read back active registers. Table 51. I2C Mode Serial Port Configuration Reg Addr (Hex) Bit(s) Name Description 000 [7:6] Unused 000 [5] Soft reset Soft reset. [5] = 1 (self-clearing). Soft reset; restores default values to internal registers. This bit self clears on the next SCL cycle after the completion of writing to this register. 000 [4] Unused 000 [3:0] Mirror[7:4] Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows: [0] = [7] [1] = [6] [2] = [5] [3] = [4] 002 [7:0] Silicon revision This read only register identifies the revision level of the AD9522. Rev. A | Page 68 of 84

Data Sheet AD9522-0 Reg Addr (Hex) Bit(s) Name Description 003 [7:0] Part ID (read only) Uniquely identifies the dash version (AD9522-0 through AD9522-5) of the AD9522. AD9522-0: 0x20 AD9522-1: 0x60 AD9522-2: 0xA0 AD9522-3: 0x61 AD9522-4: 0xE1 AD9522-5: 0xE0 004 [0] Readback active registers Select register bank used for a readback. [0] = 0; read back buffer registers (default). [0] = 1; read back active registers. Table 52. EEPROM ID Reg Addr (Hex) Bit(s) Name Description 005 [7:0] EEPROM customer 16-bit EEPROM ID[7:0]. This register, along with Register 0x006, allows the user to version ID (LSB) store a unique ID to identify which version of the AD9522 register settings is stored in the EEPROM. It does not affect AD9522 operation in any way (default: 0x00). 006 [7:0] EEPROM customer 16-bit EEPROM ID[15:8]. This register, along with Register 0x005, allows the user to version ID (MSB) store a unique ID to identify which version of the AD9522 register settings is stored in the EEPROM. It does not affect AD9522 operation in any way (default: 0x00). Table 53. PLL Reg. Addr (Hex) Bit(s) Name Description 010 [7] PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity, [7] = 0. [7] = 0; positive (higher control voltage produces higher frequency) (default). [7] = 1; negative (higher control voltage produces lower frequency). 010 [6:4] CP current Charge pump current (with CPRSET = 5.1 kΩ). [6] [5] [4] I (mA) CP 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) 010 [3:2] CP mode Charge pump operating mode. [3] [2] Charge Pump Mode 0 0 High impedance state. 0 1 Force source current (pump up). 1 0 Force sink current (pump down). 1 1 Normal operation (default). 010 [1:0] PLL power- PLL operating mode. down [1] [0] Mode 0 0 Normal operation; this mode must be selected to use the PLL. 0 1 Asynchronous power-down (default). 1 0 Unused. 1 1 Synchronous power-down. 011 [7:0] 14-bit R counter, Reference divider LSBs—lower eight bits. The reference divider (also called the R divider or R counter) is Bits[7:0] (LSB) 14 bits long. The lower eight bits are in this register (default: 0x01). 012 [5:0] 14-bit R counter, Reference divider MSBs—upper six bits. The reference divider (also called the R divider or R counter) is Bits[13:8] (MSB) 14 bits long. The upper six bits are in this register (default: 0x00). Rev. A | Page 69 of 84

AD9522-0 Data Sheet Reg. Addr (Hex) Bit(s) Name Description 013 [5:0] 6-bit A counter A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00). 014 [7:0] 13-bit B counter, B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03). Bits[7:0] (LSB) 015 [4:0] 13-bit B counter, B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00). Bits[12:8] (MSB) 016 [7] Set CP pin Sets the CP pin to one-half of the VCP supply voltage. to VCP/2 [7] = 0; CP normal operation (default). [7] = 1; CP pin set to VCP/2. 016 [6] Reset R counter Reset R counter (R divider). [6] = 0; normal (default). [6] = 1; hold R counter in reset. 016 [5] Reset A and B Reset A and B counters (part of N divider). counters [5] = 0; normal (default). [5] = 1; hold A and B counters in reset. 016 [4] Reset all Reset R, A, and B counters. counters [4] = 0; normal (default). [4] = 1; hold R, A, and B counters in reset. 016 [3] B counter B counter bypass. When this bit is 1, set the A counter in Register 0x013 to 0. bypass [3] = 0; normal (default). [3] = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. 016 [2:0] Prescaler P Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider. [2] [1] [0] Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0. 0 1 1 DM Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0. 1 0 0 DM Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0. 1 0 1 DM Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0. 1 1 0 DM Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0 (default). 1 1 1 FD Divide-by-3. 017 [7:2] STATUS Selects the signal that appears at the STATUS pin. Register 0x01D[7] must be 0 to reprogram the STATUS pin. pin control Level or Dynamic [7] [6] [5] [4] [3] [2] Signal Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 0 1 DYN N divider output (after the delay). 0 0 0 0 1 0 DYN R divider output (after the delay). 0 0 0 0 1 1 DYN A divider output. 0 0 0 1 0 0 DYN Prescaler output. 0 0 0 1 0 1 DYN PFD up pulse. 0 0 0 1 1 0 DYN PFD down pulse. 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified. The selections that follow are the same as for REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). Rev. A | Page 70 of 84

Data Sheet AD9522-0 Reg. Addr (Hex) Bit(s) Name Description Level or Dynamic [7] [6] [5] [4] [3] [2] Signal Signal at STATUS Pin 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status of REF1 frequency (active high). 1 0 1 0 0 0 LVL Status of REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL DLD; active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL LD pin comparator output (active high). 1 1 0 0 0 0 LVL VS (PLL power supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL DLD (active low). 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL LD pin comparator output (active low). 017 [1:0] Antibacklash [1] [0] Antibacklash Pulse Width (ns) pulse width 0 0 2.9 (default) 0 1 1.3 1 0 6.0 1 1 2.9 018 [7] Enable CMOS Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost. reference input [7] = 0; disable dc offset (default). dc offset [7] = 1; enable dc offset. 018 [6:5] Lock detect Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates counter a locked condition. [6] [5] PFD Cycles to Determine Lock 0 0 5 (default) 0 1 16 1 0 64 1 1 255 Rev. A | Page 71 of 84

AD9522-0 Data Sheet Reg. Addr (Hex) Bit(s) Name Description 018 [4] Digital lock If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the detect window digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. [4] = 0; high range. The default setting is 3.5 ns. [4] = 1; low range. 018 [3] Disable digital Digital lock detect operation. lock detect [3] = 0; normal lock detect operation (default). [3] = 1; disable lock detect. 018 [2:1] VCO calibration Divider used to generate the VCO calibration clock from the PLL reference clock (see the VCO Calibration section for divider the recommended setting of the VCO calibration divider based on the PFD rate). [2] [1] VCO Calibration Clock Divider 0 0 2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is f /R. REF 0 1 4. This setting is fine for PFD frequencies < 25 MHz. The PFD frequency is f /R. REF 1 0 8. This setting is fine for PFD frequencies < 50 MHz. 1 1 16 (default). This setting is fine for any PFD frequency, but results in the longest VCO calibration time. 018 [0] VCO calibration Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The now sequence to initiate a calibration follows: program to 0, followed by an IO_UPDATE bit (Register 0x232[0]); then program to 1, followed by another IO_UPDATE bit (Register 0x232[0]). This sequence gives complete control over when the VCO calibration occurs relative to the programming of other registers that can impact the calibration (default = 0). Note that the VCO divider (Register 0x1E0[2:0]) must not be static during VCO calibration. 019 [7:6] R, A, B counters [7] [6] Action SYNC pin reset 0 0 Do nothing on SYNC (default). 0 1 Asynchronous reset. 1 0 Synchronous reset. 1 1 Do nothing on SYNC. 019 [5:3] R path delay R path delay, see Table 2 (default: 0x0). 019 [2:0] N path delay N path delay, see Table 2 (default: 0x0). 01A [7] Enable STATUS Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the pin divider R and N dividers. [7] = 0; divide-by-4 disabled on STATUS pin (default). [7] = 1; divide-by-4 enabled on STATUS pin. 01A [6] Ref freq monitor Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO threshold frequency monitor’s detection threshold (see Table 17, REF1, REF2, and VCO frequency status monitor parameter). [6] = 0; frequency valid if frequency is above 1.02 MHz (default). [6] = 1; frequency valid if frequency is above 8 kHz. 01A [5:0] LD pin Selects the signal that is connected to the LD pin. control Level or Dynamic [5] [4] [3] [2] [1] [0] Signal Signal at LD Pin 0 0 0 0 0 0 LVL Digital lock detect (high = lock; low = unlock, default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ Tristate (high-Z) LD pin. 0 0 0 1 0 0 CUR Current source lock detect (110 µA when DLD is true). 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified. The selections that follow are the same as for REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). Rev. A | Page 72 of 84

Data Sheet AD9522-0 Reg. Addr (Hex) Bit(s) Name Description Level or Dynamic [5] [4] [3] [2] [1] [0] Signal Signal at LD Pin 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status of REF1 frequency (active high). 1 0 1 0 0 0 LVL Status of REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL DLD; active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL Nor available, do not use. 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL DLD; active low. 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL N/A, do not use. 01B [7] Enable VCO Enables or disables the VCO frequency monitor. frequency [7] = 0; disable the VCO frequency monitor (default). monitor [7] = 1; enable the VCO frequency monitor. 01B [6] Enable REF2 Enables or disables the REF2 frequency monitor. frequency [6] = 0; disable the REF2 frequency monitor (default). monitor [6] = 1; enable the REF2 frequency monitor. 01B [5] Enable REF1 REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs (REFIN) (as selected by differential reference mode). frequency [5] = 0; disable the REF1 (REFIN) frequency monitor (default). monitor [5] = 1; enable the REF1 (REFIN) frequency monitor. Rev. A | Page 73 of 84

AD9522-0 Data Sheet Reg. Addr (Hex) Bit(s) Name Description 01B [4:0] REFMON pin Selects the signal that is connected to the REFMON pin. control Level or Dynamic [4] [3] [2] [1] [0] Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground, dc (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (N/A in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 LVL Status REF1 frequency (active high). 0 1 0 0 0 LVL Status REF2 frequency (active high). 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 0 1 0 1 1 LVL Status of VCO frequency (active high). 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 0 1 1 0 1 LVL DLD; active low. 0 1 1 1 0 LVL Holdover active (active high). 0 1 1 1 1 LVL LD pin comparator output (active high). 1 0 0 0 0 LVL VS (PLL supply). 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 0 1 LVL DLD; active low. 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 LVL LD pin comparator output (active low). 01C [7] Disable Disables or enables the switchover deglitch circuit. switchover [7] = 0; enable the switchover deglitch circuit (default). deglitch [7] = 1; disable the switchover deglitch circuit. 01C [6] Select REF2 If Register 0x01C[5] = 0, selects the reference for PLL when in manual; register selected reference control. [6] = 0; select REF1 (default). [6] = 1; select REF2. 01C [5] Use REF_SEL If Register 0x01C[4] = 0 (manual), sets the method of PLL reference selection. pin [5] = 0; use Register 0x01C[6] (default). [5] = 1; use REF_SEL pin. Rev. A | Page 74 of 84

Data Sheet AD9522-0 Reg. Addr (Hex) Bit(s) Name Description 01C [4:3] Reserved Default: 00b. 01C [2] Enable REF2 This bit turns the REF2 power on. [2] = 0; REF2 power off (default). [2] = 1; REF2 power on. 01C [1] Enable REF1 This bit turns the REF1 power on. [1] = 0; REF1 power off (default). [1] = 1; REF1 power on. 01C [0] Enable Selects the PLL reference mode, differential or single-ended. Register 0x01C[2:1] must be cleared when this differential bit is set. reference [0] = 0; single-ended reference mode (default). [0] = 1; differential reference mode. 01D [7] Enable Enables the STATUS_EEPROM signal at the STATUS pin. STATUS_EEPROM [7] = 0; the STATUS pin is controlled by the Register 0x017[7:2] selection. at STATUS pin [7] = 1; select the STATUS_EEPROM signal at STATUS pin. This bit overrides Register 0x017[7:2] (default). 01D [6] Enable Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input. XTAL OSC [6] = 0; crystal oscillator maintaining amplifier disabled (default). [6] = 1; crystal oscillator maintaining amplifier enabled. 01D [5] Enable clock Enable PLL reference input clock doubler. doubler [5] = 0; doubler disabled (default). [5] = 1; doubler enabled. 01D [4] Disable PLL Disables the PLL status register readback. status register [4] = 0; PLL status register enabled (default). [4] = 1; PLL status register disabled. If this bit is set, Register 0x01F is not automatically updated. 01D [3] Enable LD pin Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode. When comparator the AD9522 is in internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 48). Otherwise, this can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin. [3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover controller treats this pin as true (high, default). [3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked). 01D [1] Enable external Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.) holdover [1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default). [1] = 1; external holdover mode, holdover controlled by SYNC pin. 01D [0] Enable Enables the internally controlled holdover function. holdover [0] = 0; holdover disabled (default). [0] = 1; holdover enabled. 01E [4:3] External zero [4] [3] Selects Which Channel Divider to Use in the External Zero Delay Path delay 0 0 Select Channel Divider 0 (default). feedback 0 1 Select Channel Divider 1. channel divider select 1 0 Select Channel Divider 2. 1 1 Select Channel Divider 3 01E [2] Enable external Selects which zero delay mode to use. zero delay [2] = 0; enables internal zero delay mode if Register 0x01E[1] = 1 (default). [2] = 1; enables external zero delay mode if Register 0x01E[1] = 1. 01E [1] Enable zero Enables zero delay function. delay [1] = 0; disables zero delay function (default). [1] = 1; enables zero delay function. 01F [6] VCO calibration Readback register. Indicates the status of the VCO calibration. finished [6] = 0; VCO calibration not finished. (read only) [6] = 1; VCO calibration finished. Rev. A | Page 75 of 84

AD9522-0 Data Sheet Reg. Addr (Hex) Bit(s) Name Description 01F [5] Holdover active Readback register. Indicates if the part is in the holdover state (see Figure 48). This is not the same as (read only) holdover enabled. [5] = 0; not in holdover. [5] = 1; holdover state active. 01F [4] REF2 selected Readback register. Indicates which PLL reference is selected as the input to the PLL. (read only) [4] = 0; REF1 selected (or differential reference if in differential mode). [4] = 1; REF2 selected. 01F [3] VCO frequency Readback register. Indicates if the VCO frequency is greater than the threshold (see Table 17, REF1, REF2, and > threshold VCO frequency status monitor parameter). (read only) [3] = 0; VCO frequency is less than the threshold. [3] = 1; VCO frequency is greater than the threshold. 01F [2] REF2 frequency Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency > threshold set by Register 0x01A[6]. (read only) [2] = 0; REF2 frequency is less than the threshold frequency. [2] = 1; REF2 frequency is greater than the threshold frequency. 01F [1] REF1 frequency Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency > threshold set by Register 0x01A[6]. (read only) [1] = 0; REF1 frequency is less than the threshold frequency. [1] = 1; REF1 frequency is greater than the threshold frequency. 01F [0] Digital lock Readback register. Digital lock detect. detect [0] = 0; PLL is not locked. (read only) [0] = 1; PLL is locked. Table 54. Output Driver Control Reg. Addr (Hex) Bit(s) Name Description 0F0 [7] OUT0 format Selects the output type for OUT0. [7] = 0; LVDS (default). [7] = 1; CMOS. 0F0 [6:5] OUT0 CMOS Sets the CMOS output configuration for OUT0 when Register 0x0F0[7] = 1. configuration [6:5] OUT0A OUT0B 00 Tristate Tristate 01 On Tristate 10 Tristate On 11 (default) On On 0F0 [4:3] OUT0 polarity Sets the output polarity for OUT0. [7] [4] [3] Output Type OUT0A OUT0B 0 (default) X 0 LVDS Noninverting Inverting 0 X 1 LVDS Inverting Noninverting 1 0 (default) 0 (default) CMOS Noninverting Noninverting 1 0 1 CMOS Inverting Inverting 1 1 0 CMOS Noninverting Inverting 1 1 1 CMOS Inverting Noninverting 0F0 [2:1] OUT0 LVDS Sets the LVDS output differential voltage (V ). OD differential [2] [1] I (mA) OD voltage 0 0 1.75 (V = 175 mV for 100 Ω termination across differential pair) OD 0 (default) 1 (default) 3.5 (V = 350 mV for 100 Ω termination across differential pair) OD 1 0 5.25 (V = 525 mV for 100 Ω termination across differential pair) OD 1 1 7.0 (V = 700 mV for 100 Ω termination across differential pair) OD Rev. A | Page 76 of 84

Data Sheet AD9522-0 Reg. Addr (Hex) Bit(s) Name Description 0F0 [0] OUT0 LVDS LVDS power-down. power-down [0] = 0; normal operation (default). [0] = 1; power-down. Output driver is in a high impedance state. 0F1 [7:0] OUT1 control This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0. 0F2 [7:0] OUT2 control This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0. 0F3 [7:0] OUT3 control This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0. 0F4 [7:0] OUT4 control This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0. 0F5 [7:0] OUT5 control This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0. 0F6 [7:0] OUT6 control This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0. 0F7 [7:0] OUT7 control This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0. 0F8 [7:0] OUT8 control This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0. 0F9 [7:0] OUT9 control This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0. 0FA [7:0] OUT10 control This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0. 0FB [7:0] OUT11 control This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0. 0FC [7] CSDLD En OUT7 OUT7 is enabled only if CSDLD is high. [7] CSDLD Signal OUT7 Enable Status 0 0 Not affected by CSDLD signal (default). 1 0 Asynchronous power-down. 1 1 Asynchronously enable OUT7 if not powered down by other settings. To use this feature, the user must use current source digital lock detect, and set the enable LD pin comparator bit (Register 0x01D[3]). 0FC [6] CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [5] CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [4] CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [3] CSDLD En OUT3 OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [2] CSDLD En OUT2 OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [1] CSDLD En OUT1 OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FC [0] CSDLD En OUT0 OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FD [3] CSDLD En OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT11 0FD [2] CSDLD En OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT10 0FD [1] CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. 0FD [0] CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. Table 55. LVDS Channel Dividers Reg. Addr (Hex) Bit(s) Name Description 190 [7:4] Divider 0 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7). 190 [3:0] Divider 0 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7). 191 [7] Divider 0 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use the divider (default). [7] = 1; bypass the divider. 191 [6] Divider 0 ignore SYNC Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Rev. A | Page 77 of 84

AD9522-0 Data Sheet Reg. Addr (Hex) Bit(s) Name Description 191 [5] Divider 0 force high Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 191 [4] Divider 0 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 191 [3:0] Divider 0 phase offset Phase offset (default: 0x0). 192 [2] Channel 0 power-down Channel 0 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into the high impedance power-down mode by setting this bit.) 192 [0] Disable Divider 0 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 193 [7:4] Divider 1 low cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x3 means the divider is low for four input clock cycles (default: 0x3). 193 [3:0] Divider 1 high cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x3 means the divider is high for four input clock cycles (default: 0x3). 194 [7] Divider 1 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 194 [6] Divider 1 ignore SYNC Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. 194 [5] Divider 1 force high Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 194 [4] Divider 1 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 194 [3:0] Divider 1 phase offset Phase offset (default: 0x0). 195 [2] Channel 1 power-down Channel 1 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into the high impedance power-down mode by setting this bit.) 195 [0] Disable Divider 1 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 196 [7:4] Divider 2 low cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x1 means the divider is low for two input clock cycles (default: 0x1). 196 [3:0] Divider 2 high cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1). 197 [7] Divider 2 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 197 [6] Divider 2 ignore SYNC Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Rev. A | Page 78 of 84

Data Sheet AD9522-0 Reg. Addr (Hex) Bit(s) Name Description 197 [5] Divider 2 force high Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 197 [4] Divider 2 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 197 [3:0] Divider 2 phase offset Phase offset(default: 0x0). 198 [2] Channel 2 power-down Channel 2 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into the high impedance power-down mode by setting this bit.) 198 [0] Disable Divider 2 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. 199 [7:4] Divider 3 low cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x0 means the divider is low for one input clock cycle (default: 0x0). 199 [3:0] Divider 3 high cycles Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x0 means the divider is high for one input clock cycle (default: 0x0). 19A [7] Divider 3 bypass Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. 19A [6] Divider 3 ignore SYNC Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. 19A [5] Divider 3 force high Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that this bit has no effect if the channel divider is bypassed. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. 19A [4] Divider 3 start high Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. 19A [3:0] Divider 3 phase offset Phase offset (default: 0x0). 19B [2] Channel 3 power-down Channel 3 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are put into the high impedance power-down mode by setting this bit.) 19B [0] Disable Divider 3 DCC Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Rev. A | Page 79 of 84

AD9522-0 Data Sheet Table 56. VCO Divider and CLK Input Reg. Addr (Hex) Bit(s) Name Description 1E0 [2:0] VCO divider [2] [1] [0] Divide 0 0 0 2 (default) 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 1 (bypass) 1 1 1 Output static 1E1 [4] Power-down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). [4] = 0; normal operation (default). [4] = 1; power down. 1E1 [3] Power-down VCO clock interface Powers down the interface block between VCO and clock distribution. [3] = 0; normal operation (default). [3] = 1; power down. 1E1 [2] Power-down VCO and CLK Powers down both the CLK input and VCO. [2] = 0; normal operation (default). [2] = 1; power down. 1E1 [1] Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider. [1] = 0; select external CLK as input to VCO divider (default). [1] = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is selected. This bit must be set to use the PLL with the internal VCO. 1E1 [0] Bypass VCO divider Bypasses or uses the VCO divider. [0] = 0; use VCO divider (default). [0] = 1; bypass VCO divider; cannot select VCO as input when this is selected. Table 57. System Reg. Addr (Hex) Bit(s) Name Description 230 [3] Disable power-on SYNC Power-on SYNC mode. Used to disable the antiruntpulse circuitry. [3] = 0; enable the antiruntpulse circuitry (default). [3] = 1; disable the antiruntpulse circuitry. 230 [2] Power-down SYNC Powers down the SYNC function. [2] = 0; normal operation of the SYNC function (default). [2] = 1; power-down SYNC circuitry. 230 [1] Power-down distribution reference Powers down the reference for the distribution section. [1] = 0; normal operation of the reference for the distribution section (default). [1] = 1; powers down the reference for the distribution section. 230 [0] Soft SYNC The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed; that is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. [0] = 0; same as SYNC high. [0] = 1; same as SYNC low. Rev. A | Page 80 of 84

Data Sheet AD9522-0 Table 58. Update All Registers Reg. Addr (Hex) Bit(s) Name Description 232 [0] IO_UPDATE This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This bit is self- clearing; that is, it does not have to be set back to 0. [0] = 1 (self-clearing); update all active registers to the contents of the buffer registers. Table 59. EEPROM Buffer Segment Reg. Addr (Hex) Bit(s) Name Description A00 to [7:0] EEPROM Buffer The EEPROM buffer segment section stores the starting address and number of bytes that are to be A16 Segment Register 1 stored and read back to and from the EEPROM. Because the AD9522 register space is noncontiguous, to EEPROM Buffer the EEPROM controller needs to know the starting address and number of bytes in the AD9522 register Segment Register 23 space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment registers is designed such that all registers are transferred to/from the EEPROM, and an IO_UPDATE is issued after transfer. See the Programming the EEPROM Buffer Segment section for more information. Table 60. EEPROM Control Reg. Addr (Hex) Bit(s) Name Description B00 [0] STATUS_EEPROM This read only register indicates the status of the data transferred between the EEPROM and the buffer (read only) register bank during the writing and reading of the EEPROM. This signal is also available at the STATUS pin when Register 0x01D[7] is set. [0] = 0; data transfer is done. [0] = 1; data transfer is not done. B01 [0] EEPROM This read only register indicates an error during the data transferred between the EEPROM and the buffer. data error [0] = 0; no error. Data is correct. (read only) [0] = 1; incorrect data detected. B02 [1] SOFT_EEPROM When the EEPROM pin is tied low, setting SOFT_EEPROM resets the AD9522 using the settings saved in EEPROM. [1] = 1; soft reset with EEPROM settings (self-clearing). This bit self clears on the next serial port clock cycle after the completion of writing to this register. B02 [0] Enable EEPROM Enables the user to write to the EEPROM. write [0] = 0; EEPROM write protection is enabled. User cannot write to EEPROM (default). [0] = 1; EEPROM write protection is disabled. User can write to EEPROM. B03 [0] REG2EEPROM Transfers data from the buffer register to the EEPROM (self-clearing). [0] = 1; setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process); it is reset by the I²C master after the data transfer is done. Rev. A | Page 81 of 84

AD9522-0 Data Sheet APPLICATIONS INFORMATION FREQUENCY PLANNING USING THE AD9522 Figure 71 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). The AD9522 is a highly flexible PLL. When choosing the PLL 110 settings and version of the AD9522, keep the following 18 1 guidelines in mind. 100 SNR = 20log 2πfAtJ 16 The AD9522 has four frequency dividers: the reference (or R) 90 dcfdtrhhiievveaqii nVdsuineeoCernn,Ol c ,td yh sdi oevdi mvifidveiedeeid rdeo.er bfW oartahcrht ketie oh (fn eror e trecqr qhNyuuaie)nin nrdgnic nietvyogl i d d daaiei cvvlrhai,is rditieghoeverene , a V tcamha CpunoOas ub ra ntedlit lci dovouowifld naifernrerle gy,bq aaydun iehedfnifit gicthchhyueee rl rt SNR (dB) 678000 tttttJJJJJ ===== 12124pp000ss000fffsss 111024 ENOB phase detector frequency and more flexibility in choosing the 50 loop bandwidth. 40 tJ = 10ps 8 Within the AD9522 family, lower VCO frequencies generally 6 30 r(fersoumlt 1in2 sklHigzh ttoly 2 b0e MtteHr zji ottfefrs.e Tt)h feo rd tihffee rseanmcee ionu itnptuetg frraetqeude jnitcteyr i s 10 fA 1(M00Hz) 1k 07219-044 usually less than 150 fs over the entire VCO frequency range Figure 71. SNR and ENOB vs. Analog Input Frequency (1.4 GHz to 2.95 GHz) of the AD9522 family. If the desired See the AN-756 Application Note, Sampled Systems and the Effects frequency plan can be achieved with a version of the AD9522 of Clock Phase Noise and Jitter, and the AN-501 Application Note, that has a lower VCO frequency, choosing the lower frequency Aperture Uncertainty and ADC System Performance. part results in the lowest phase noise and the lowest jitter. Many high performance ADCs feature differential clock inputs However, choosing a higher VCO frequency can result in more to simplify the task of providing the required low jitter clock on flexibility in frequency planning. a noisy PCB. Distributing a single-ended clock on a noisy PCB Choosing a nominal charge pump current in the middle of the can result in coupled noise on the sampling clock. Differential allowable range as a starting point allows the designer to increase or distribution has inherent common-mode rejection that can decrease the charge pump current, and thus allows the designer provide superior clock performance in a noisy environment. to fine-tune the PLL loop bandwidth in either direction. The differential LVDS outputs of the AD9522 enable clock solutions that maximize converter SNR performance. ADIsimCLK is a powerful PLL modeling tool that is a very accurate tool for determining the optimal loop filter for a given Consider the input requirements of the ADC (differential or application. single-ended, logic level termination) when selecting the best USING THE AD9522 OUTPUTS FOR ADC CLOCK clocking/converter solution. In some cases, the LVPECL outputs of the AD9520 may be desirable for clocking a APPLICATIONS converter instead of the LVDS outputs of the AD9522. Any high speed ADC is extremely sensitive to the quality of the LVDS CLOCK DISTRIBUTION sampling clock of the AD9522. An ADC can be thought of as a sampling mixer, and any noise, distortion, or time jitter on the The AD9522 provides clock outputs that are selectable as either clock is combined with the desired signal at the analog-to- CMOS or LVDS level outputs. LVDS is a differential output digital output. Clock integrity requirements scale with the analog option that uses a current mode output stage. The nominal input frequency and resolution, with higher analog input current is 3.5 mA, which yields 350 mV output swing across a frequency applications at ≥14-bit resolution being the most 100 Ω resistor. An output current of 7 mA is also available in stringent. The theoretical SNR of an ADC is limited by the ADC cases where a larger output swing is required. The LVDS output resolution and the jitter on the sampling clock. Considering an meets or exceeds all ANSI/TIA/EIA-644 specifications. ideal ADC of infinite resolution where the step size and A recommended termination circuit for the LVDS outputs is quantization error can be ignored, the available SNR can be shown in Figure 72. If ac coupling is necessary, place decoupling expressed approximately by capacitors either before or after the 100 Ω termination resistor. VS VS   SNR(dB)=20log 1  2πfAtJ  100Ω LVDS DIFFERENTIAL (COUPLES)100Ω LVDS wfA hise rteh:e highest analog frequency being digitized. 07219-047 tJ is the rms jitter on the sampling clock. Figure 72. LVDS Output Termination See the AN-586 Application Note for more information on LVDS. Rev. A | Page 82 of 84

Data Sheet AD9522-0 CMOS CLOCK DISTRIBUTION Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9522 do not supply enough current The output drivers of the AD9522 can be configured as CMOS to provide a full voltage swing with a low impedance resistive, far- drivers. When selected as a CMOS driver, each output becomes end termination, as shown in Figure 74. The far-end termination a pair of CMOS outputs, each of which can be individually network must match the PCB trace impedance and provide the turned on or off and set as inverting or noninverting. These desired switching point. The reduced signal swing may still meet outputs are 3.3 V CMOS compatible. receiver input requirements in some applications. This can be When single-ended CMOS clocking is used, some of the useful when driving long trace lengths on less critical nets. following guidelines apply. VS Point-to-point connections must be designed such that each driver has only one receiver, if possible. Connecting outputs in 10Ω 50Ω 100Ω CMOS CMOS trhinisg minagn dnueer atoll opwoss sfoibrl esi mmpislem taetrcmhienda tiimonp esdchaenmceess oann dt hme ionuimtpiuzet s 100Ω 07219-077 trace. Series termination at the source is generally required to Figure 74. CMOS Output with Far-End Termination provide transmission line matching and/or to reduce current Because of the limitations of single-ended CMOS clocking, transients at the driver. consider using differential outputs when driving high speed The value of the resistor is dependent on the board design and signals over long traces. The AD9522 offers LVDS outputs that timing requirements (typically 10 Ω to 100 Ω is used). CMOS are better suited for driving long traces where the inherent noise outputs are also limited in terms of the capacitive load or trace immunity of differential signaling provides superior length that they can drive. Typically, trace lengths less than performance for clocking converters. 3 inches are recommended to preserve signal rise/fall times and signal integrity. 60.4Ω 10Ω (1.0 INCH) CMOS MICROSTRIP CMOS 07219-076 Figure 73. Series Termination of CMOS Output Rev. A | Page 83 of 84

AD9522-0 Data Sheet OUTLINE DIMENSIONS 9.10 0.60 0.30 9.00 SQ 0.42 0.23 0.60 8.90 0.24 0.18 0.42 PIN 1 0.24 INDICATOR 49 64 1 48 PIN 1 INDICATOR 8.85 0.50 EXPOSED 6.35 8.75 SQ BSC PAD 6.20 SQ 8.65 6.05 0.50 0.40 33 16 32 17 0.30 0.25 MIN TOP VIEW BOTTOM VIEW 7.50 REF 1.00 12° MAX 0.80 MAX 0.65 NOM 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND SEATING FUNCTION DESCRIPTIONS PLANE 0.20 REF SECTION OF THIS DATA SHEET. PKG-1184 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 01-22-2015-D Figure 75. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9522-0BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9522-0BCPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-4 AD9522-0/PCBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07219-0-3/15(A) Rev. A | Page 84 of 84

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9522-0BCPZ-REEL7 AD9522-0/PCBZ AD9522-0BCPZ