14-Output Clock Generator with Integrated 2.0 GHz VCO Data Sheet AD9516-3 FEATURES FUNCTIONAL BLOCK DIAGRAM Low phase noise, phase-locked loop (PLL) CP LF On-chip VCO tunes from 1.75 GHz to 2.25 GHz External VCO/VCXO to 2.4 GHz optional REF1 RR STATUS 1 differential or 2 single-ended reference inputs VETO MONITOR Reference monitoring capability REFIN CHOMONI PLL VCO Automatic revertive and manual reference REF2 WITND SA switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz DIVIDER Programmable delays in path to PFD CLK AND MUXs Digital or analog lock detect, selectable 6 pairs of 1.6 GHz LVPECL outputs DIV/Φ LVPECL OUT0 OUT1 Each output pair shares a 1-to-32 divider with coarse OUT2 DIV/Φ LVPECL OUT3 phase delay OUT4 DIV/Φ LVPECL Additive output jitter: 225 fs rms OUT5 Δt OUT6 Channel-to-channel skew paired outputs of <10 ps DIV/Φ DIV/Φ LVDS/CMOS Δt OUT7 4 pairs of 800 MHz LVDS clock outputs Δt OUT8 DIV/Φ DIV/Φ LVDS/CMOS Δt OUT9 Each output pair shares two cascaded 1-to-32 dividers SERIAL CONTROL PORT with coarse phase delay AND AD9516-3 AFidndei dtievlea oy uatdpjuuts tj i(tΔtet)r :o 2n7 e5a fcsh r mLVsD S output DIGITAL LOGIC 06422-001 Each LVDS output can be reconfigured as two 250 MHz Figure 1. CMOS outputs Automatic synchronization of all outputs on power-up Manual output synchronization available 64-lead LFCSP The AD9516-3 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can APPLICATIONS be reconfigured as two CMOS outputs. The LVPECL outputs Low jitter, low phase noise clock distribution operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and 10/40/100 Gb/sec networking line cards, including SONET, the CMOS outputs operate to 250 MHz. Synchronous Ethernet, OTU2/3/4 Each pair of outputs has dividers that allow both the divide Forward error correction (G.710) ratio and coarse delay (or phase) to be set. The range of division Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs High performance wireless transceivers allow a range of divisions up to a maximum of 1024. ATE and high performance instrumentation The AD9516-3 is available in a 64-lead LFCSP and can be GENERAL DESCRIPTION operated from a single 3.3 V supply. An external VCO, which The AD9516-31 provides a multi-output clock distribution requires an extended voltage range, can be accommodated function with subpicosecond jitter performance, along with an on- by connecting the charge pump supply (VCP) to 5 V. A separate chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to LVPECL power supply can be from 2.5 V to 3.3 V (nominal). 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz The AD9516-3 is specified for operation over the standard can be used. industrial range of −40°C to +85°C. The AD9516-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other 1 AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-3 is used, it refers to that specific member of the applications with demanding phase noise and jitter requirements. AD9516 family. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD9516-3 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 16 Applications ....................................................................................... 1 ESD Caution................................................................................ 16 General Description ......................................................................... 1 Pin Configuration and Function Descriptions ........................... 17 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 19 Revision History ............................................................................... 3 Terminology .................................................................................... 25 Specifications ..................................................................................... 4 Detailed Block Diagram ................................................................ 26 Power Supply Requirements ....................................................... 4 Theory of Operation ...................................................................... 27 PLL Characteristics ...................................................................... 4 Operational Configurations ...................................................... 27 Clock Inputs .................................................................................. 6 Digital Lock Detect (DLD) ....................................................... 36 Clock Outputs ............................................................................... 6 Clock Distribution ..................................................................... 40 Timing Characteristics ................................................................ 7 Reset Modes ................................................................................ 48 Clock Output Additive Phase Noise (Distribution Only; VCO Power-Down Modes .................................................................. 49 Divider Not Used) ........................................................................ 8 Serial Control Port ......................................................................... 50 Clock Output Absolute Phase Noise (Internal VCO Used) .... 9 Serial Control Port Pin Descriptions ....................................... 50 Clock Output Absolute Time Jitter (Clock Generation Using General Operation of Serial Control Port ............................... 50 Internal VCO) ............................................................................. 10 The Instruction Word (16 Bits) ................................................ 51 Clock Output Absolute Time Jitter (Clock Cleanup Using MSB/LSB First Transfers ........................................................... 51 Internal VCO) ............................................................................. 10 Thermal Performance .................................................................... 54 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ......................................................................... 10 Register Map Overview ................................................................. 55 Clock Output Additive Time Jitter (VCO Divider Not Used) Register Map Descriptions ............................................................ 59 ....................................................................................................... 11 Applications Information .............................................................. 77 Clock Output Additive Time Jitter (VCO Divider Used) ..... 11 Frequency Planning Using the AD9516 .................................. 77 Delay Block Additive Time Jitter .............................................. 12 Using the AD9516 Outputs for ADC Clock Applications .... 77 Serial Control Port ..................................................................... 12 LVPECL Clock Distribution ..................................................... 78 PD, RESET, and SYNC Pins ..................................................... 13 LVDS Clock Distribution .......................................................... 78 LD, STATUS, and REFMON Pins ............................................ 13 CMOS Clock Distribution ........................................................ 79 Power Dissipation ....................................................................... 14 Outline Dimensions ....................................................................... 80 Timing Diagrams ............................................................................ 15 Ordering Guide .......................................................................... 80 Absolute Maximum Ratings .......................................................... 16 Rev. C | Page 2 of 80

Data Sheet AD9516-3 REVISION HISTORY 2/13—Rev. B to Rev. C Changes to Reference Switchover and VCXO/VCO Changes to Register 0x140 to Register 0x143 Default Values; Feedback Divider N—P, A, B, R Sections .................................... 34 Table 52 ............................................................................................. 56 Changes to Table 28 ........................................................................ 35 Changes to Register 0x140 to Register 0x143 Default Values; Change to Holdover Section .......................................................... 37 Table 57 ............................................................................................. 71 Changes to VCO Calibration Section ........................................... 39 Updated Outline Dimensions ........................................................ 80 Changes to Clock Distribution Section ........................................ 40 Added Endnote to Table 34 ........................................................... 41 1/12—Rev. A to Rev. B Changes to Channel Dividers—LVDS/CMOS Outputs Changes to 0x232 Description Column, Table 62 ...................... 76 Section; Added Endnote to Table 39 ............................................ 43 Changes to Write Section ............................................................... 50 12/10—Rev. 0 to Rev. A Change to the Instruction Word (16 Bits) Section ..................... 51 Changes to Features, Applications, and General Description ..... 1 Change to Figure 65 ........................................................................ 52 Change to CPRSET Pin Resistor Parameter in Table 1 ................ 4 Added Thermal Performance Section .......................................... 54 Change to P = 2 DM (2/3) Parameter in Table 2 .......................... 5 Changes to Register Address 0x003 in Table 52 .......................... 55 Changes to Table 4 ............................................................................ 6 Changes to Table 53 ........................................................................ 59 Changes to V Supply Parameter in Table 17............................. 14 Changes to Table 54 ........................................................................ 60 CP Change to θ Value and Endnote in Table 19 ............................. 16 Changes to Table 55 ........................................................................ 66 JA Added Exposed Paddle Notation to Figure 6; Changes to Changes to Table 56 ........................................................................ 68 Table 20 ............................................................................................. 17 Changes to Table 57 ........................................................................ 71 Added Figure 41; Renumbered Sequentially ............................... 24 Changes to Table 58 ........................................................................ 73 Change to High Frequency Clock Distribution—CLK or Changes to Table 59 ........................................................................ 74 External VCO > 1600 MHz Section; Change to Table 22 .......... 27 Changes to Table 60 and Table 61 ................................................. 76 Changes to Table 24 ........................................................................ 29 Added Frequency Planning Using the AD9516 Section ............ 77 Change to Configuration and Register Settings Section ............ 31 Changes to Figure 71 and Figure 73; Added Figure 72 .............. 78 Change to Phase Frequency Detector (PFD) Section ................ 32 Changes to LVPECL Clock Distribution and LVDS Clock Changes to Charge Pump (CP), On-Chip VCO, PLL Distribution Sections ...................................................................... 78 External Loop Filter, and PLL Reference Inputs Sections ......... 33 Updated Outline Dimensions........................................................ 80 Change to Figure 47; Added Figure 48 ......................................... 33 6/07—Revision 0: Initial Version Rev. C | Page 3 of 80

AD9516-3 Data Sheet SPECIFICATIONS Typical is given for V = V = 3.3 V ± 5%; V ≤ V ≤ 5.25 V; T = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. S S_LVPECL S CP A Minimum and maximum values are given over full V and T (−40°C to +85°C) variation. S A POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments V 3.135 3.3 3.465 V 3.3 V ± 5% S V 2.375 V V Nominally 2.5 V to 3.3 V ± 5% S_LVPECL S V V 5.25 V Nominally 3.3 V to 5.0 V ± 5% CP S RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA); actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground PLL CHARACTERISTICS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments VCO (ON-CHIP) Frequency Range 1750 2250 MHz See Figure 15 VCO Gain (K ) 50 MHz/V See Figure 10 VCO Tuning Voltage (V) 0.5 V − V V ≤ V when using internal VCO; outside of this range, the CP T CP CP S 0.5 spurs may increase due to CP up/down mismatch Frequency Pushing (Open-Loop) 1 MHz/V Phase Noise at 100 kHz Offset −108 dBc/Hz f = 2000 MHz Phase Noise at 1 MHz Offset −126 dBc/Hz f = 2000 MHz REFERENCE INPUTS Differential Mode (REFIN, REFIN) Differential mode (can accommodate single-ended input by ac grounding undriven input) Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc-coupled; be careful to match V (self-bias voltage) CM Input Sensitivity 250 mV p-p PLL figure of merit (FOM) increases with increasing slew rate; see Figure 14 Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN 1.30 1.50 1.60 V Self-bias voltage of REFIN1 Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN 4.4 5.3 6.4 kΩ Self-biased1 Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/µs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/µs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed V p-p S Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 µA Input Capacitance 2 pF Each pin, REFIN/REFIN (REF1/REF2) PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b 2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b 6.0 ns Register 0x017[1:0] = 10b Rev. C | Page 4 of 80

Data Sheet AD9516-3 Parameter Min Typ Max Unit Test Conditions/Comments CHARGE PUMP (CP) I Sink/Source Programmable CP High Value 4.8 mA With CP = 5.1 kΩ RSET Low Value 0.60 mA Absolute Accuracy 2.5 % CP = V /2 V CP CP Range 2.7/10 kΩ RSET I High Impedance Mode Leakage 1 nA CP Sink-and-Source Current Matching 2 % 0.5 < CP < V − 0.5 V V CP I vs. CP 1.5 % 0.5 < CP < V − 0.5 V CP V V CP I vs. Temperature 2 % CP = V /2 CP V CP PRESCALER (PART OF N DIVIDER) See the VCXO/VCO Feedback Divider N—P, A, B, R section Prescaler Input Frequency P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 200 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input frequency divided by P) PLL DIVIDER DELAYS Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 54 000 Off ps 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps NOISE CHARACTERISTICS In-Band Phase Noise of the Charge The PLL in-band phase noise floor is estimated by measuring the Pump/Phase Frequency Detector in-band phase noise at the output of the VCO and subtracting (In-Band Is Within the LBW of the PLL) 20log(N) (where N is the value of the N divider) At 500 kHz PFD Frequency −165 dBc/Hz At 1 MHz PFD Frequency −162 dBc/Hz At 10 MHz PFD Frequency −151 dBc/Hz At 50 MHz PFD Frequency −143 dBc/Hz PLL Figure of Merit (FOM) −220 dBc/Hz Reference slew rate > 0.25 V/ns; FOM + 10log (f ) is an approxi- PFD mation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed loop, the phase noise, as observed at the VCO output, is increased by 20log(N) PLL DIGITAL LOCK DETECT WINDOW2 Signal available at LD, STATUS, and REFMON pins when selected by appropriate register settings Required to Lock (Coincidence of Edges) Selected by Register 0x017[1:0] and Register 0x018[4] Low Range (ABP 1.3 ns, 2.9 ns) 3.5 ns Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b To Unlock After Lock (Hysteresis)2 Low Range (ABP 1.3 ns, 2.9 ns) 7 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b High Range (ABP 1.3 ns, 2.9 ns) 15 ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b High Range (ABP 6.0 ns) 11 ns Register 0x017[1:0] = 10b; Register 0x018[4] = 0b 1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. 2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time. Rev. C | Page 5 of 80

AD9516-3 Data Sheet CLOCK INPUTS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK, CLK) Differential input Input Frequency 01 2.4 GHz High frequency distribution (VCO divider) 01 1.6 GHz Distribution only (VCO divider bypassed) Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Input Level, Differential 2 V p-p Larger voltage swings may turn on the protection diodes and may degrade jitter performance Input Common-Mode Voltage, V 1.3 1.57 1.8 V Self-biased; enables ac coupling CM Input Common-Mode Range, V 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled CMR Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM. CLOCK OUTPUTS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to V − 2 V S OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 Differential (OUT, OUT) Output Frequency, Maximum 2950 MHz Using direct to output; see Figure 25 for peak-to- peak differential amplitude Output High Voltage (V ) V − 1.12 V − 0.98 V − 0.84 V OH S S S Output Low Voltage (V ) V − 2.03 V − 1.77 V − 1.49 V OL S S S Output Differential Voltage (V ) 550 790 980 mV V − V for each leg of a differential pair for OD OH OL default amplitude setting with driver not toggling; see Figure 25 for variation over frequency LVDS CLOCK OUTPUTS Differential termination 100 Ω at 3.5 mA OUT6, OUT7, OUT8, OUT9 Differential (OUT, OUT) Output Frequency 800 MHz The AD9516 outputs toggle at higher frequencies, but the output amplitude may not meet the V OD specification; see Figure 26 Differential Output Voltage (V ) 247 360 454 mV V − V measurement across a differential pair at OD OH OL the default amplitude setting with output driver not toggling; see Figure 26 for variation over frequency Delta V 25 mV This is the absolute value of the difference OD between V when the normal output is high vs. OD when the complementary output is high Output Offset Voltage (V ) 1.125 1.24 1.375 V (V + V )/2 across a differential pair OS OH OL Delta V 25 mV This is the absolute value of the difference OS between V when the normal output is high vs. OS when the complementary output is high Short-Circuit Current (I , I ) 14 24 mA Output shorted to GND SA SB CMOS CLOCK OUTPUTS OUT6A, OUT6B, OUT7A, OUT7B, Single-ended; termination = 10 pF OUT8A, OUT8B, OUT9A, OUT9B Output Frequency 250 MHz See Figure 27 Output Voltage High (V ) V − 0.1 V At 1 mA load OH S Output Voltage Low (V ) 0.1 V At 1 mA load OL Rev. C | Page 6 of 80

Data Sheet AD9516-3 TIMING CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 50 Ω to V − 2 V; level = 810 mV S Output Rise Time, t 70 180 ps 20% to 80%, measured differentially RP Output Fall Time, t 70 180 ps 80% to 20%, measured differentially FP PROPAGATION DELAY, t , CLK-TO-LVPECL OUTPUT PECL High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 43 Clock Distribution Configuration 773 933 1090 ps See Figure 45 Variation with Temperature 0.8 ps/°C OUTPUT SKEW, LVPECL OUTPUTS1 LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps LVDS Termination = 100 Ω differential; 3.5 mA Output Rise Time, t 170 350 ps 20% to 80%, measured differentially2 RL Output Fall Time, t 160 350 ps 20% to 80%, measured differentially2 FL PROPAGATION DELAY, t , CLK-TO-LVDS OUTPUT Delay off on all outputs LVDS OUT6, OUT7, OUT8, OUT9 For All Divide Values 1.4 1.8 2.1 ns Variation with Temperature 1.25 ps/°C OUTPUT SKEW, LVDS OUTPUTS1 Delay off on all outputs LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps CMOS Termination = open Output Rise Time, t 495 1000 ps 20% to 80%; C = 10 pF RC LOAD Output Fall Time, t 475 985 ps 80% to 20%; C = 10 pF FC LOAD PROPAGATION DELAY, t , CLK-TO-CMOS OUTPUT Fine delay off CMOS For All Divide Values 1.6 2.1 2.6 ns Variation with Temperature 2.6 ps/°C OUTPUT SKEW, CMOS OUTPUTS1 Fine delay off CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps DELAY ADJUST3 LVDS and CMOS Shortest Delay Range4 Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 101111b Zero Scale 50 315 680 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b Full Scale 540 880 1180 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b Longest Delay Range4 Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 000000b Zero Scale 200 570 950 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b Quarter Scale 1.72 2.31 2.89 ns Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 001100b Full Scale 5.7 8.0 10.1 ns Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b Delay Variation with Temperature Short Delay Range5 Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C Long Delay Range5 Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Corresponding CMOS drivers set to A for noninverting and B for inverting. 3 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output. 4 Incremental delay; does not include propagation delay. 5 All delays between zero scale and full scale can be estimated by linear interpolation. Rev. C | Page 7 of 80

AD9516-3 Data Sheet CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter Min Typ Max Unit Test Conditions/Comments CLK-TO-LVPECL ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 1 GHz Input slew rate > 1 V/ns Divider = 1 At 10 Hz Offset −109 dBc/Hz At 100 Hz Offset −118 dBc/Hz At 1 kHz Offset −130 dBc/Hz At 10 kHz Offset −139 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −146 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz CLK = 1 GHz, Output = 200 MHz Input slew rate > 1 V/ns Divider = 5 At 10 Hz Offset −120 dBc/Hz At 100 Hz Offset −126 dBc/Hz At 1 kHz Offset −139 dBc/Hz At 10 kHz Offset −150 dBc/Hz At 100 kHz Offset −155 dBc/Hz At 1 MHz Offset −157 dBc/Hz >10 MHz Offset −157 dBc/Hz CLK-TO-LVDS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1.6 GHz, Output = 800 MHz Input slew rate > 1 V/ns Divider = 2 At 10 Hz Offset −103 dBc/Hz At 100 Hz Offset −110 dBc/Hz At 1 kHz Offset −120 dBc/Hz At 10 kHz Offset −127 dBc/Hz At 100 kHz Offset −133 dBc/Hz At 1 MHz Offset −138 dBc/Hz At 10 MHz Offset −147 dBc/Hz At 100 MHz Offset −149 dBc/Hz CLK = 1.6 GHz, Output = 400 MHz Input slew rate > 1 V/ns Divider = 4 At 10 Hz Offset −114 dBc/Hz At 100 Hz Offset −122 dBc/Hz At 1 kHz Offset −132 dBc/Hz At 10 kHz Offset −140 dBc/Hz At 100 kHz Offset −146 dBc/Hz At 1 MHz Offset −150 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK-TO-CMOS ADDITIVE PHASE NOISE Distribution section only; does not include PLL and VCO CLK = 1 GHz, Output = 250 MHz Input slew rate > 1 V/ns Divider = 4 At 10 Hz Offset −110 dBc/Hz At 100 Hz Offset −120 dBc/Hz At 1 kHz Offset −127 dBc/Hz At 10 kHz Offset −136 dBc/Hz At 100 kHz Offset −144 dBc/Hz At 1 MHz Offset −147 dBc/Hz >10 MHz Offset −154 dBc/Hz Rev. C | Page 8 of 80

Data Sheet AD9516-3 Parameter Min Typ Max Unit Test Conditions/Comments CLK = 1 GHz, Output = 50 MHz Input slew rate > 1 V/ns Divider = 20 At 10 Hz Offset −124 dBc/Hz At 100 Hz Offset −134 dBc/Hz At 1 kHz Offset −142 dBc/Hz At 10 kHz Offset −151 dBc/Hz At 100 kHz Offset −157 dBc/Hz At 1 MHz Offset −160 dBc/Hz >10 MHz Offset −163 dBc/Hz CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL ABSOLUTE PHASE NOISE Internal VCO; direct to LVPECL output VCO = 2.25 GHz; Output = 2.25 GHz At 1 kHz Offset −49 dBc/Hz At 10 kHz Offset −79 dBc/Hz At 100 kHz Offset −104 dBc/Hz At 1 MHz Offset −123 dBc/Hz At 10 MHz Offset −143 dBc/Hz At 40 MHz Offset −147 dBc/Hz VCO = 2.00 GHz; Output = 2.00 GHz At 1 kHz Offset −53 dBc/Hz At 10 kHz Offset −83 dBc/Hz At 100 kHz Offset −108 dBc/Hz At 1 MHz Offset −126 dBc/Hz At 10 MHz Offset −142 dBc/Hz At 40 MHz Offset −147 dBc/Hz VCO = 1.75 GHz; Output = 1.75 GHz At 1 kHz Offset −54 dBc/Hz At 10 kHz Offset −88 dBc/Hz At 100 kHz Offset −112 dBc/Hz At 1 MHz Offset −130 dBc/Hz At 10 MHz Offset −143 dBc/Hz At 40 MHz Offset −147 dBc/Hz Rev. C | Page 9 of 80

AD9516-3 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R = 1 VCO = 1.97 GHz; LVPECL = 245.76 MHz; PLL LBW = 143 kHz 129 fs rms Integration BW = 200 kHz to 10 MHz 303 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 143 kHz 135 fs rms Integration BW = 200 kHz to 10 MHz 302 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1.97 GHz; LVPECL = 61.44 MHz; PLL LBW = 143 kHz 179 fs rms Integration BW = 200 kHz to 10 MHz 343 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 10.0 MHz; R = 20 VCO = 1.87 GHz; LVPECL = 622.08 MHz; PLL LBW = 125 Hz 400 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1.87 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz 390 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz 485 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R = 1 LVPECL = 245.76 MHz; PLL LBW = 125 Hz 54 fs rms Integration BW = 200 kHz to 5 MHz 77 fs rms Integration BW = 200 kHz to 10 MHz 109 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 122.88 MHz; PLL LBW = 125 Hz 79 fs rms Integration BW = 200 kHz to 5 MHz 114 fs rms Integration BW = 200 kHz to 10 MHz 163 fs rms Integration BW = 12 kHz to 20 MHz LVPECL = 61.44 MHz; PLL LBW = 125 Hz 124 fs rms Integration BW = 200 kHz to 5 MHz 176 fs rms Integration BW = 200 kHz to 10 MHz 259 fs rms Integration BW = 12 kHz to 20 MHz Rev. C | Page 10 of 80

Data Sheet AD9516-3 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 40 fs rms BW = 12 kHz to 20 MHz CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 80 fs rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 215 fs rms Calculated from SNR of ADC method; DCC not used for even divides CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 245 fs rms Calculated from SNR of ADC method; DCC on LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2; 85 fs rms BW = 12 kHz to 20 MHz VCO Divider Not Used CLK = 1 GHz; LVDS = 200 MHz; Divider = 5 113 fs rms BW = 12 kHz to 20 MHz CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16 280 fs rms Calculated from SNR of ADC method; DCC not used for even divides CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16 365 fs rms Calculated from SNR of ADC method; DCC not used for even divides CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz; 210 fs rms Calculated from SNR of ADC method Divider = 12; Duty-Cycle Correction = Off LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz; 285 fs rms Calculated from SNR of ADC method Divider = 12; Duty-Cycle Correction = Off CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only; does not include PLL and VCO; uses rising edge of clock signal CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz; 350 fs rms Calculated from SNR of ADC method Divider = 12; Duty-Cycle Correction = Off Rev. C | Page 11 of 80

AD9516-3 Data Sheet DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter Min Typ Max Unit Test Conditions/Comments DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter 100 MHz Output Delay (1600 µA, 0x1C) Fine Adj. 000000 0.54 ps rms Delay (1600 µA, 0x1C) Fine Adj. 101111 0.60 ps rms Delay (800 µA, 0x1C) Fine Adj. 000000 0.65 ps rms Delay (800 µA, 0x1C) Fine Adj. 101111 0.85 ps rms Delay (800 µA, 0x4C) Fine Adj. 000000 0.79 ps rms Delay (800 µA, 0x4C) Fine Adj. 101111 1.2 ps rms Delay (400 µA, 0x4C) Fine Adj. 000000 1.2 ps rms Delay (400 µA, 0x4C) Fine Adj. 101111 2.0 ps rms Delay (200 µA, 0x1C) Fine Adj. 000000 1.3 ps rms Delay (200 µA, 0x1C) Fine Adj. 101111 2.5 ps rms Delay (200 µA, 0x4C) Fine Adj. 000000 1.9 ps rms Delay (200 µA, 0x4C) Fine Adj. 101111 3.8 ps rms 1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method. SERIAL CONTROL PORT Table 14. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 µA Input Logic 0 Current 110 µA Input Capacitance 2 pF SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF SDIO (WHEN INPUT) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/t ) 25 MHz SCLK Pulse Width High, t 16 ns HIGH Pulse Width Low, t 16 ns LOW SDIO to SCLK Setup, t 2 ns DS SCLK to SDIO Hold, t 1.1 ns DH SCLK to Valid SDIO and SDO, t 8 ns DV CS to SCLK Setup and Hold, tS, tH 2 ns CS Minimum Pulse Width High, tPWH 3 ns Rev. C | Page 12 of 80

Data Sheet AD9516-3 PD, RESET, AND SYNC PINS Table 15. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS These pins each have a 30 kΩ internal pull-up resistor Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 µA Logic 0 Current 1 µA Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns SYNC TIMING Pulse Width Low 1.5 High speed High speed clock is CLK input signal clock cycles LD, STATUS, AND REFMON PINS Table 16. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 54, Register 0x017, Register 0x01A, and Register 0x01B Output Voltage High (V ) 2.7 V OH Output Voltage Low (V ) 0.4 V OL MAXIMUM TOGGLE RATE 100 MHz Applies when mux is set to any divider or counter output or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling ANALOG LOCK DETECT Capacitance 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range 1.02 MHz Frequency above which the monitor always indicates the presence of the reference Extended Range (REF1 and REF2 Only) 8 kHz Frequency above which the monitor always indicates the presence of the reference LD PIN COMPARATOR Trip Point 1.6 V Hysteresis 260 mV Rev. C | Page 13 of 80

AD9516-3 Data Sheet POWER DISSIPATION Table 17. Parameter Min Typ Max Unit Test Conditions/Comments POWER DISSIPATION, CHIP Power-On Default 1.0 1.2 W No clock; no programming; default register values; does not include power dissipated in external resistors Full Operation; CMOS Outputs at 225 MHz 1.6 2.2 W PLL on; internal VCO = 2250 MHz; VCO divider = 2; all channel dividers on; six LVPECL outputs at 562.5 MHz; eight CMOS outputs (10 pF load) at 225 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors Full Operation; LVDS Outputs at 225 MHz 1.6 2.3 W PLL on; internal VCO = 2250 MHz, VCO divider = 2; all channel dividers on; six LVPECL outputs at 562.5 MHz; four LVDS outputs at 225 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors PD Power-Down 75 185 mW PD pin pulled low; does not include power dissipated in terminations PD Power-Down, Maximum Sleep 31 mW PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b; SYNC power-down, Register 0x230[2] = 1b; REF for distribution power-down, Register 0x230[1] = 1b VCP Supply 4 4.8 mW PLL operating; typical closed loop configuration POWER DELTAS, INDIVIDUAL FUNCTIONS Power delta when a function is enabled/disabled VCO Divider 30 mW VCO divider bypassed REFIN (Differential) 20 mW All references off to differential reference enabled REF1, REF2 (Single-Ended) 4 mW All references off to REF1 or REF2 enabled; differential reference not enabled VCO 70 mW CLK input selected to VCO selected PLL 75 mW PLL off to PLL on, normal operation; no reference enabled Channel Divider 30 mW Divider bypassed to divide-by-2 to divide-by-32 LVPECL Channel (Divider Plus Output Driver) 160 mW No LVPECL output on to one LVPECL output on, independent of frequency LVPECL Driver 90 mW Second LVPECL output turned on, same channel LVDS Channel (Divider Plus Output Driver) 120 mW No LVDS output on to one LVDS output on; see Figure 8 for dependence on output frequency LVDS Driver 50 mW Second LVDS output turned on, same channel CMOS Channel (Divider Plus Output Driver) 100 mW Static; no CMOS output on to one CMOS output on; see Figure 9 for variation over output frequency CMOS Driver (Second in Pair) 0 mW Static; second CMOS output, same pair, turned on CMOS Driver (First in Second Pair) 30 mW Static; first output, second pair, turned on Fine Delay Block 50 mW Delay block off to delay block enabled; maximum current setting Rev. C | Page 14 of 80

Data Sheet AD9516-3 TIMING DIAGRAMS tCLK CLK DIFFERENTIAL tPECL 80% LVDS tLVDS 20% tCMOS 06422-060 tRL tFL 06422-062 Figure 2. CLK/CLK to Clock Output Timing, DIV = 1 Figure 4. LVDS Timing, Differential DIFFERENTIAL SINGLE-ENDED 80% 80% LVPECL CMOS 10pF LOAD 20% 20% tRP tFP 06422-061 tRC tFC 06422-063 Figure 3. LVPECL Timing, Differential Figure 5. CMOS Timing, Single-Ended, 10 pF Load Rev. C | Page 15 of 80

AD9516-3 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 18. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress VS, VS_LVPECL to GND −0.3 V to +3.6 V rating only; functional operation of the device at these or any VCP to GND −0.3 V to+5.8 V other conditions above those indicated in the operational REFIN, REFIN to GND −0.3 V to VS + 0.3 V section of this specification is not implied. Exposure to absolute REFIN to REFIN −3.3 V to +3.3 V maximum rating conditions for extended periods may affect RSET to GND −0.3 V to V + 0.3 V device reliability. S CPRSET to GND −0.3 V to V + 0.3 V THERMAL RESISTANCE S CLK, CLK to GND −0.3 V to VS + 0.3 V Table 19. CLK to CLK −1.2 V to +1.2 V Package Type1 θ Unit SCLK, SDIO, SDO, CS to GND −0.3 V to VS + 0.3 V JA 64-Lead LFCSP 22 °C/W OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, −0.3 V to VS + 0.3 V OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, 1 Thermal impedance measurements were taken on a 4-layer board in still air OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, in accordance with EIA/JESD51-2. OUT9, OUT9 to GND SYNC to GND −0.3 V to VS + 0.3 V ESD CAUTION REFMON, STATUS, LD to GND −0.3 V to V + 0.3 V S Junction Temperature1 150°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C 1 See Table 19 for θJA. Rev. C | Page 16 of 80

Data Sheet AD9516-3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EFIN (REF1)EFIN (REF2)PRSETSSNDSETSUT0UT0S_LVPECLUT1UT1SSS RRCVVGRVOOVOOVVV 4321098765432109 6666655555555554 LVPECLLVPECL UST VS 1 PIN 1 SDJ 48OUT6 (OUT6A) REFMON 2 INDICATOR MOY A 47OUT6 (OUT6B) RSETFA_VTSCCULEDPPSL 34567 AD9516-3 LVDS/Cw/FINE DELAVPECL 4444465432OOGOOUUNUUTTDTT7722 ((OOUUTT77AB)) SYNLCF 89 (NToOt Pto V SIEcaWle) ECLL 4410VOSU_TL3VPECL BYPASVSS1101 USTLVP 3398OVSUT3 VS12 SDJ 37GND OA CLK13 MY 36OUT9 (OUT9B) SCCNLLCKK111456 LVDS/CNE DELA 333543OOOUUUTTT988 (((OOOUUUTTT988ABA))) LVPECLLVPECL w/FI NC = NO CONNECT 7890123456789012 1112222222222333 SCCCOOTD44L55SSS CNNNSDSDIESEPOUTOUTPECOUTOUTVVV R V L _ S V N21O.. TNTCEHCOSE N= N ENEXOCT ETCREODNN ANTLOE CP GATR.D ODDOULN END OO FNTO CTRHO PENR NBOEOPCTETTR OT OOM P TOEHFRI SAT HTPIEION PN.A.CKAGE MUST BE 06422-003 Figure 6. Pin Configuration Table 20. Pin Function Descriptions Input/ Pin No. Output Pin Type Mnemonic Description 1, 11, 12, 30, I Power VS 3.3 V Power Pins. 31, 32, 38, 49, 50, 51, 57, 60, 61 2 I 3.3 V CMOS REFMON Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54, Register 0x01B. 3 O 3.3 V CMOS LD Lock Detect (Output). This pin has multiple selectable outputs; see Table 54, Register 0x1A. 4 I Power VCP Power Supply for Charge Pump (CP); V ≤ V ≤ 5.0 V. S CP 5 O 3.3 V CMOS CP Charge Pump (Output). Connects to external loop filter. 6 O 3.3 V CMOS STATUS Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017. 7 I 3.3 V CMOS REF_SEL Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. 8 I 3.3 V CMOS SYNC Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is also used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. 9 I Loop filter LF Loop Filter (Input). Connects to VCO control voltage node internally. This pin has 31 pF of internal capacitance to ground, which may influence the loop filter design for large (>500 kHz) loop bandwidths. 10 O Loop filter BYPASS This pin is for bypassing the LDO to ground with a capacitor. 13 I Differential CLK Along with CLK, this is the differential input for the clock distribution section. clock input 14 I Differential CLK Along with CLK, this is the differential input for the clock distribution section. clock input Rev. C | Page 17 of 80

AD9516-3 Data Sheet Input/ Pin No. Output Pin Type Mnemonic Description 15, 18, 19, 20 N/A NC NC No Connect. Do not connect to this pin. 16 I 3.3 V CMOS SCLK Serial Control Port Data Clock Signal. 17 I 3.3 V CMOS CS Serial Control Port Chip Select, Active Low. This pin has an internal 30 kΩ pull-up resistor. 21 O 3.3 V CMOS SDO Serial Control Port Unidirectional Serial Data Out. 22 I/O 3.3 V CMOS SDIO Serial Control Port Bidirectional Serial Data In/Out. 23 I 3.3 V CMOS RESET Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. 24 I 3.3 V CMOS PD Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor. 27, 41, 54 I Power VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. 37, 44, 59, N/A GND GND Ground Pins, Including External Paddle (EPAD). The external paddle on the bottom of EPAD the package must be connected to ground for proper operation. 56 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 55 O LVPECL OUT0 LVPECL Output; One Side of a Differential LVPECL Output. 53 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 52 O LVPECL OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 43 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 42 O LVPECL OUT2 LVPECL Output; One Side of a Differential LVPECL Output. 40 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 39 O LVPECL OUT3 LVPECL Output; One Side of a Differential LVPECL Output. 25 O LVPECL OUT4 LVPECL Output; One Side of a Differential LVPECL Output. 26 O LVPECL OUT4 LVPECL Output; One Side of a Differential LVPECL Output. 28 O LVPECL OUT5 LVPECL Output; One Side of a Differential LVPECL Output. 29 O LVPECL OUT5 LVPECL Output; One Side of a Differential LVPECL Output. 48 O LVDS or OUT6 LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS CMOS (OUT6A) Output. 47 O LVDS or OUT6 LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS CMOS (OUT6B) Output. 46 O LVDS or OUT7 LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS CMOS (OUT7A) Output. 45 O LVDS or OUT7 LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS CMOS (OUT7B) Output. 33 O LVDS or OUT8 LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS CMOS (OUT8A) Output. 34 O LVDS or OUT8 LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS CMOS (OUT8B) Output. 35 O LVDS or OUT9 LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS CMOS (OUT9A) Output. 36 O LVDS or OUT9 LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS CMOS (OUT9B) Output. 58 O Current set RSET A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ. resistor 62 O Current set CPRSET A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ. resistor 63 I Reference REFIN Along with REFIN, this pin is the differential input for the PLL reference. input (REF2) Alternatively, this pin is a single-ended input for REF2. 64 I Reference REFIN Along with REFIN, this pin is the differential input for the PLL reference. input (REF1) Alternatively, this pin is a single-ended input for REF1. Rev. C | Page 18 of 80

Data Sheet AD9516-3 TYPICAL PERFORMANCE CHARACTERISTICS 300 70 280 3 CHANNELS—6 LVPECL 65 260 60 240 55 CURRENT (mA) 122802000 3 CHANNELS—3 LVPECL K (MHz/V)VCO 5405 40 160 2 CHANNELS—2 LVPECL 35 140 120 30 1 CHANNEL—1 LVPECL 100 25 0 500 100F0REQUE15N0C0Y (MHz2)000 2500 3000 06422-007 1.7 1.8 V1C.9O FREQ2U.E0NCY (GH2.z1) 2.2 2.3 06422-010 Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs Figure 10. VCO KVCO vs. Frequency 180 5.0 2 CHANNELS—4 LVDS 4.5 160 A) 4.0 m N ( 3.5 mA) 140 P PI 3.0 PUMP DOWN PUMP UP T ( M C URREN 120 2 CHANNELS—2 LVDS T FRO 22..50 C N E R 1.5 R U 100 C 1.0 0.5 1 CHANNEL—1 LVDS 800 200 FREQUE4N0C0Y (MHz) 600 800 06422-008 00 0.5 1.V0OLTAG1E.5 ON CP2 P.0IN (V) 2.5 3.0 06422-011 Figure 8. Current vs. Frequency—LVDS Outputs Figure 11. Charge Pump Characteristics at VCP = 3.3 V (Includes Clock Distribution Current Draw) 240 5.0 4.5 220 200 mA) 4.0 2 CHANNELS—8 CMOS N ( 3.5 mA) 180 P PI 3.0 PUMP DOWN PUMP UP RENT ( 160 2 CHANNELS—2 CMOS ROM C 2.5 CUR 140 NT F 2.0 E R 1.5 R 120 U 1 CHANNEL—2 CMOS C 1.0 100 0.5 1 CHANNEL—1 CMOS 80 0 0 50 FR1E00QUENCY (1M5H0z) 200 250 06422-009 0 0.5 1.0 1.V5OLT2.A0GE 2O.N5 CP3 P.0IN (V3).5 4.0 4.5 5.0 06422-012 Figure 9. Current vs. Frequency—CMOS Outputs Figure 12. Charge Pump Characteristics at VCP = 5.0 V Rev. C | Page 19 of 80

AD9516-3 Data Sheet –140 10 T U 0 P N D I –145 –10 F P –20 O B) ERRED THz)–150 OWER (d ––4300 OISE REF(dBc/––115650 LATIVE P –––765000 SE N RE –80 A PH –165 –90 FD –100 P –1700.1 P1FD FREQUENCY (MH10z) 100 06422-013 –110 CENTER 122.88MHz 5MHz/DIV SPAN 50MHz 06422-137 Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz –210 10 0 –212 –10 Hz) Bc/ –214 B) –20 T (d R (d –30 ERI –216 WE –40 M O OF E P –50 FIGURE ––222108 RELATIV ––7600 L –80 L P –90 –222 –100 –2240 0.5 SL1.E0W RATE (V1/.n5s) 2.0 2.5 06422-136 –110 CENTER 122.88MHz 100kHz/DIV SPAN 1MHz 06422-135 Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz 1.9 10 0 1.7 V) –10 E ( AG B) –20 OLT 1.5 R (d –30 G V WE –40 N O UNI 1.3 E P –50 VCO T ELATIV ––7600 1.1 R –80 –90 0.9 –100 1.7 1.8 V1.C9O FREQ2U.0ENCY (G2H.z1) 2.2 2.3 06422-138 –110 CENTER 122.88MHz 100kHz/DIV SPAN 1MHz 06422-134 Figure 15. VCO Tuning Voltage vs. Frequency Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz; (Note that VCO calibration centers the dc tuning voltage LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz for the PLL setup that is active during calibration.) Rev. C | Page 20 of 80

Data Sheet AD9516-3 1.0 0.4 0.6 V) V) 0.2 T ( T ( U U P P UT 0.2 UT O O AL AL 0 TI TI EN –0.2 EN R R E E F F F F DI DI –0.2 –0.6 –1.0 –0.4 0 5 10TIME (ns)15 20 25 06422-014 0 1 TIME (ns) 2 06422-017 Figure 19. LVPECL Output (Differential) at 100 MHz Figure 22. LVDS Output (Differential) at 800 MHz 1.0 2.8 DIFFERENTIAL OUTPUT (V) –000...262 DIFFERENTIAL OUTPUT (V) 01..88 –0.6 –1.00 TIME1 (ns) 2 06422-015 –0.20 20 40TIME (ns)60 80 100 06422-018 Figure 20. LVPECL Output (Differential) at 1600 MHz Figure 23. CMOS Output at 25 MHz 0.4 2.8 V) 0.2 T ( U TP V) OU T ( 1.8 TIAL 0 UTPU N O E R E F 0.8 F DI –0.2 –0.40 5 10TIME (ns)15 20 25 06422-016 –0.20 2 4 TIME6 (ns) 8 10 12 06422-019 Figure 21. LVDS Output (Differential) at 100 MHz Figure 24. CMOS Output at 250 MHz Rev. C | Page 21 of 80

AD9516-3 Data Sheet 1600 –80 –90 p) mV p- 1400 Hz) –100 G ( Bc/ WIN E (d –110 FFERENTIAL S 11020000 PHASE NOIS ––112300 DI –140 8000 1FREQUENCY (GHz)2 3 06422-020 –15010k 100k FREQU1EMNCY (Hz) 10M 100M 06422-023 Figure 25. LVPECL Differential Swing vs. Frequency Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2250 MHz Using a Differential Probe Across the Output Pair –80 700 –90 p) p- V G (m c/Hz) –100 N B SWI E (d –110 AL 600 OIS TI N –120 N E RE AS E H FF P –130 DI –140 500 0 100 200 F30R0EQUE4N00CY (M5H0z0) 600 700 800 06422-021 –15010k 100k FREQU1EMNCY (Hz) 10M 100M 06422-024 Figure 26. LVDS Differential Swing vs. Frequency Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2000 MHz Using a Differential Probe Across the Output Pair –80 CL = 2pF 3 –90 UT SWING (V) 2 CL = 10pF OISE (dBc/Hz) ––110100 P N –120 UT CL = 20pF SE O A 1 H P –130 –140 0 0 100 OU2T00PUT FRE3Q00UENCY 4(M00Hz) 500 600 06422-133 –15010k 100k FREQU1EMNCY (Hz) 10M 100M 06422-025 Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 1750 MHz Rev. C | Page 22 of 80

Data Sheet AD9516-3 –120 –110 –125 –120 –130 Hz) Hz) dBc/ –135 dBc/ –130 E ( E ( OIS –140 OIS N N SE –145 SE –140 A A H H P P –150 –150 –155 –160 –160 10 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 06422-026 10 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 06422-142 Figure 31. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1 Figure 34. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1 –110 –100 –120 –110 Hz) Hz) dBc/ –130 dBc/ –120 E ( E ( S S OI OI N N E –140 E –130 S S A A H H P P –150 –140 –16010 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 06422-027 –15010 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 06422-130 Figure 32. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5 Figure 35. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2 –100 –120 –110 –130 Hz) Hz) dBc/ –120 dBc/ –140 E ( E ( S S OI OI N N E –130 E –150 S S A A H H P P –140 –160 –15010 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 06422-128 –17010 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 06422-131 Figure 33. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1 Figure 36. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20 Rev. C | Page 23 of 80

AD9516-3 Data Sheet –100 –120 –110 –130 c/Hz) –120 c/Hz) B B d d E ( E ( OIS –130 OIS –140 N N E E S S A –140 A H H P P –150 –150 –160 –160 10 100 1k FR1E0QkUENC1Y0 0(kHz) 1M 10M 100M 06422-132 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 06422-140 Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4 Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz –100 1000 OC-48 OBJECTIVE MASK AD9516 –110 )P P c/Hz) –120 DE (UI 100 E (dB LITU OIS –130 MP 10 FOBJ N A E R S E HA –140 TT P JI T U 1 –150 P IN NOTE: 375UI MAX AT 10Hz OFFSET IS THE MAXIMUM JITTER THAT CAN BE GENERATED BY THE TEST EQUIPMENT. –160 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 06422-141 0.10.01 FAI0L.1URE JPIOTTINETR1 I SF RGERQEUAETNEC1R0Y T (HkAHNz) 3751U0I.0 1000 06422-148 Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO at Figure 41. GR-253 Jitter Tolerance Plot 1.97 GHz; PFD = 15.36 MHz; LBW = 143 kHz; LVPECL Output = 122.88 MHz –90 –100 Hz) –110 c/ B E (d –120 S OI N –130 E S A H P –140 –150 –160 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 06422-139 Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 1.87 GHz; PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz Rev. C | Page 24 of 80

Data Sheet AD9516-3 TERMINOLOGY Time Jitter Phase Jitter and Phase Noise Phase noise is a frequency domain phenomenon. In the time An ideal sine wave can be thought of as having a continuous domain, the same effect is exhibited as time jitter. When and even progression of phase with time from 0° to 360° for observing a sine wave, the time of successive zero crossings each cycle. Actual signals, however, display a certain amount varies. In a square wave, the time jitter is a displacement of the of variation from ideal phase progression over time. This edges from their ideal (regular) times of occurrence. In both phenomenon is called phase jitter. Although many causes can cases, the variations in timing from the ideal are the time jitter. contribute to phase jitter, one major cause is random noise, Because these variations are random in nature, the time jitter is which is characterized statistically as being Gaussian (normal) specified in units of seconds root mean square (rms) or 1 sigma in distribution. of the Gaussian distribution. This phase jitter leads to a spreading out of the energy of the Time jitter that occurs on a sampling clock for a DAC or an sine wave in the frequency domain, producing a continuous ADC decreases the signal-to-noise ratio (SNR) and dynamic power spectrum. This power spectrum is usually reported as a range of the converter. A sampling clock with the lowest possible series of values whose units are dBc/Hz at a given offset in jitter provides the highest performance from a given converter. frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz Additive Phase Noise bandwidth with respect to the power at the carrier frequency. Additive phase noise is the amount of phase noise that can be For each measurement, the offset from the carrier frequency is attributed to the device or subsystem being measured. The phase also given. noise of any external oscillators or clock sources is subtracted. It is meaningful to integrate the total power contained within This makes it possible to predict the degree to which the device some interval of offset frequencies (for example, 10 kHz to impacts the total system phase noise when used in conjunction 10 MHz). This is called the integrated phase noise over that with the various oscillators and clock sources, each of which frequency offset interval and can be readily related to the time contributes its own phase noise to the total. In many cases, the jitter due to the phase noise within that offset frequency interval. phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total Phase noise has a detrimental effect on the performance of is the square root of the sum of squares of the individual ADCs, DACs, and RF mixers. It lowers the achievable dynamic contributors. range of the converters and mixers, although they are affected in somewhat different ways. Additive Time Jitter Additive time jitter is the amount of time jitter that can be attributed to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. C | Page 25 of 80

AD9516-3 Data Sheet DETAILED BLOCK DIAGRAM REF_ SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 LOCK DETECT REF2 STATUS CE R PROGRAMMABLE N DIVIDER R DELAY LE LR STATUS PE REFIN (REF1) VCO STATUS REF HOLD REFIN (REF2) PHASE BYPASS RELGOUWL ADTROORP O(LUDTO) PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF VCO DIVIDE BY STATUS 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY OUT0 1 TO 32 PD LVPECL DIGITAL OUT1 SYNC LOGIC OUT1 RESET OUT2 DIVIDE BY OUT2 1 TO 32 LVPECL SCLK OUT3 SDIO SERIAL OUT3 CONTROL SDO PORT CS OUT4 DIVIDE BY OUT4 1 TO 32 LVPECL OUT5 OUT5 OUT6 (OUT6A) ∆t OUT6 (OUT6B) DIVIDE BY DIVIDE BY LVDS/CMOS 1 TO 32 1 TO 32 OUT7 (OUT7A) ∆t OUT7 (OUT7B) OUT8 (OUT8A) ∆t OUT8 (OUT8B) DIVIDE BY DIVIDE BY LVDS/CMOS 1 TO 32 1 TO 32 AD9516-3 OUT9 (OUT9A) ∆t OUT9 (OUT9B) 06422-002 Figure 42. Detailed Block Diagram Rev. C | Page 26 of 80

Data Sheet AD9516-3 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS Table 21. Default Settings of Some PLL Registers Register Function The AD9516 can be configured in several ways. These configurations must be set up by loading the control registers 0x010[1:0] = 01b PLL asynchronous power-down (PLL off). (see Table 52 and Table 53 through Table 62). Each section 0x1E0[2:0] = 010b Set VCO divider = 4. or function must be individually programmed by setting the 0x1E1[0] = 0b Use the VCO divider. appropriate bits in the corresponding control register or registers. 0x1E1[1] = 0b CLK selected as the source. High Frequency Clock Distribution—CLK or External When using the internal PLL with an external VCO, the PLL VCO > 1600 MHz must be turned on. The AD9516 power-up default configuration has the PLL Table 22. Settings When Using an External VCO powered off and the routing of the input set so that the Register Function CLK/CLK input is connected to the distribution section 0x010[1:0] = 00b PLL normal operation (PLL on). through the VCO divider (divide-by-2/ divide-by-3/divide-by- 0x010 to 0x01D PLL settings. Select and enable a reference 4/divide-by-5/divide-by-6). This is a distribution only mode input; set R, N (P, A, B), PFD polarity, and I , CP that allows for an external input up to 2400 MHz (see Table 3). according to the intended loop configuration. The maximum frequency that can be applied to the channel 0x1E1[1] = 0b CLK selected as the source. dividers is 1600 MHz; therefore, higher input frequencies must An external VCO requires an external loop filter that must be be divided down before reaching the channel dividers. This connected between CP and the tuning pin of the VCO. This input routing can also be used for lower input frequencies, but loop filter determines the loop bandwidth and stability of the the minimum divide is 2 before the channel dividers. PLL. Make sure to select the proper PFD polarity for the VCO When the PLL is enabled, this routing also allows the use of the being used. PLL with an external VCO or VCXO with a frequency of less than 2400 MHz. In this configuration, the internal VCO is not Table 23. Setting the PFD Polarity used and is powered off. The external VCO/VCXO feeds Register Function directly into the prescaler. 0x010[7] = 0b PFD polarity positive (higher control voltage produces higher frequency). The register settings shown in Table 21 are the default values of 0x010[7] = 1b PFD polarity negative (higher control these registers at power-up or after a reset operation. If the voltage produces lower frequency). contents of the registers are altered by prior programming after power-up or reset, these registers can also be set intentionally to these values. After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect. Rev. C | Page 27 of 80

AD9516-3 Data Sheet REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 LOCK DETECT REF2 STATUS CE R PROGRAMMABLE N DIVIDER R DELAY LLRE STATUS PE REFIN (REF1) VCO STATUS REF HOLD REFIN (REF2) PHASE BYPASS RELGOUWL ADTROORP O(LUDTO) PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF VCO DIVIDE BY STATUS 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY OUT0 1 TO 32 PD LVPECL DIGITAL OUT1 SYNC LOGIC OUT1 RESET OUT2 DIVIDE BY OUT2 1 TO 32 LVPECL SCLK OUT3 SDIO SERIAL OUT3 CONTROL SDO PORT CS OUT4 DIVIDE BY OUT4 1 TO 32 LVPECL OUT5 OUT5 OUT6 (OUT6A) ∆t OUT6 (OUT6B) DIVIDE BY DIVIDE BY LVDS/CMOS 1 TO 32 1 TO 32 OUT7 (OUT7A) ∆t OUT7 (OUT7B) OUT8 (OUT8A) ∆t OUT8 (OUT8B) DIVIDE BY DIVIDE BY LVDS/CMOS 1 TO 32 1 TO 32 AD9516-3 OUT9 (OUT9A) ∆t OUT9 (OUT9B) 06422-029 Figure 43. High Frequency Clock Distribution or External VCO > 1600 MHz Rev. C | Page 28 of 80

Data Sheet AD9516-3 REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 LOCK DETECT REF2 STATUS CE R PROGRAMMABLE N DIVIDER R DELAY LLRE STATUS PE RREEFFIINN ((RREEFF12)) VCO STATUS REF HOLD PHASE BYPASS RELGOUWL ADTROORP O(LUDTO) PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF VCO DIVIDE BY STATUS 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY OUT0 1 TO 32 PD LVPECL SYNC DLIGOIGTIACL OOUUTT11 RESET OUT2 DIVIDE BY OUT2 1 TO 32 LVPECL SCLK OUT3 SDIO SERIAL OUT3 CONTROL SDO PORT CS OUT4 DIVIDE BY OUT4 1 TO 32 LVPECL OUT5 OUT5 OUT6 (OUT6A) ∆t OUT6 (OUT6B) DIVIDE BY DIVIDE BY LVDS/CMOS 1 TO 32 1 TO 32 OUT7 (OUT7A) ∆t OUT7 (OUT7B) OUT8 (OUT8A) ∆t OUT8 (OUT8B) DIVIDE BY DIVIDE BY LVDS/CMOS 1 TO 32 1 TO 32 AD9516-3 OUT9 (OUT9A) ∆t OUT9 (OUT9B) 06422-030 Figure 44. Internal VCO and Clock Distribution Internal VCO and Clock Distribution Table 24. Settings When Using Internal VCO Register Function When using the internal VCO and PLL, the VCO divider must 0x010[1:0] = 00b PLL normal operation (PLL on). be employed to ensure that the frequency presented to the 0x010 to 0x01E PLL settings. Select and enable a reference channel dividers does not exceed their specified maximum input; set R, N (P, A, B), PFD polarity, and I , CP frequency of 1600 MHz (see Table 3). The internal PLL uses an according to the intended loop configuration. external loop filter to set the loop bandwidth. The external loop 0x018[0] = 0b, Reset VCO calibration. This is not required filter is also crucial to the loop stability. 0x232[0] = 1b the first time after power-up, but it must be performed subsequently. When using the internal VCO, it is necessary to calibrate the 0x1E0[2:0] Set VCO divider to divide-by-2, divide-by-3, VCO (Register 0x018[0]) to ensure optimal performance. divide-by-4, divide-by-5, and divide-by-6. 0x1E1[0] = 0b Use the VCO divider as source for the For internal VCO and clock distribution applications, use the distribution section. register settings that are shown in Table 24. 0x1E1[1] = 1b Select VCO as the source. 0x018[0] = 1b, Initiate VCO calibration. 0x232[0] = 1b Rev. C | Page 29 of 80

AD9516-3 Data Sheet REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 LOCK DETECT REF2 STATUS CE R PROGRAMMABLE N DIVIDER R DELAY LLRE STATUS PE REFIN (REF1) VCO STATUS REF HOLD REFIN (REF2) PHASE BYPASS RELGOUWL ADTROORP O(LUDTO) PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP N DIVIDER LF VCO DIVIDE BY STATUS 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY OUT0 1 TO 32 PD LVPECL DIGITAL OUT1 SYNC LOGIC OUT1 RESET OUT2 DIVIDE BY OUT2 1 TO 32 LVPECL SCLK OUT3 SDIO SERIAL OUT3 CONTROL SDO PORT CS OUT4 DIVIDE BY OUT4 1 TO 32 LVPECL OUT5 OUT5 OUT6 (OUT6A) ∆t OUT6 (OUT6B) DIVIDE BY DIVIDE BY LVDS/CMOS 1 TO 32 1 TO 32 OUT7 (OUT7A) ∆t OUT7 (OUT7B) OUT8 (OUT8A) ∆t OUT8 (OUT8B) DIVIDE BY DIVIDE BY LVDS/CMOS 1 TO 32 1 TO 32 AD9516-3 OUT9 (OUT9A) ∆t OUT9 (OUT9B) 06422-028 Figure 45. Clock Distribution or External VCO < 1600 MHz Rev. C | Page 30 of 80

Data Sheet AD9516-3 Clock Distribution or External VCO < 1600 MHz When using the internal PLL with an external VCO of <1600 MHz, When the external clock source to be distributed or the external the PLL must be turned on. VCO/VCXO is less than 1600 MHz, a configuration that bypasses Table 26. Settings for Using Internal PLL with External VCO < the VCO divider can be used. This configuration differs from the 1600 MHz High Frequency Clock Distribution—CLK or External VCO > Register Function 1600 MHz section only in that the VCO divider (divide-by-2, divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed. 0x1E1[0] = 1b Bypass the VCO divider as source for distribution section This limits the frequency of the clock source to <1600 MHz (due 0x010[1:0] = 00b PLL normal operation (PLL on), along with to the maximum input frequency allowed at the channel dividers). other appropriate PLL settings in Register 0x010 Configuration and Register Settings to Register 0x01E For clock distribution applications where the external clock is An external VCO/VCXO requires an external loop filter that <1600 MHz, use the register settings that are shown in Table 25. must be connected between CP and the tuning pin of the VCO/VCXO. This loop filter determines the loop bandwidth Table 25. Settings for Clock Distribution < 1600 MHz and stability of the PLL. Make sure to select the proper PFD Register Function polarity for the VCO/VCXO being used. 0x010[1:0] = 01b PLL asynchronous power-down (PLL off) 0x1E1[0] = 1b Bypass the VCO divider as source for Table 27. Setting the PFD Polarity distribution section Register Function 0x1E1[1] = 0b CLK selected as the source 0x010[7] = 0b PFD polarity positive (higher control voltage produces higher frequency) 0x010[7] = 1b PFD polarity negative (higher control voltage produces lower frequency) After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect. Rev. C | Page 31 of 80

AD9516-3 Data Sheet Phase-Locked Loop (PLL) REF_SEL VS GND RSET REFMON CPRSET VCP DIST REFERENCE REF SWITCHOVER LD REF1 DLEOTECCKT STATUS REF2 R DIVIDER PROGRAMMABLE PLL HOLD R DELAY REF STATUS REFIN (REF1) REFIN (REF2) PHASE N DIVIDER FREQUENCY CHARGE PUMP CP BYPASS RELGOUWL ADTROORP O(LUDTO) P, P + 1 A/B PROGRAMMABLE DETECTOR PRESCALER COUNTERS N DELAY LF VCO STATUS STATUS VCO DIVIDE BY 0 2, 3, 4, 5, OR 6 CLK 1 CLK 1 0 06422-064 Figure 46. PLL Functional Blocks The AD9516 includes an on-chip PLL with an on-chip VCO. These are managed through programmable register settings (see The PLL blocks can be used either with the on-chip VCO to Table 52 and Table 54) and by the design of the external loop create a complete phase-locked loop, or with an external VCO filter. Successful PLL operation and satisfactory PLL loop or VCXO. The PLL requires an external loop filter, which performance are highly dependent upon proper configuration of usually consists of a small number of capacitors and resistors. the PLL settings. The design of the external loop filter is crucial The configuration and components of the loop filter help to to the proper operation of the PLL. A thorough knowledge of establish the loop bandwidth and stability of the operating PLL. PLL theory and design is helpful. The AD9516 PLL is useful for generating clock frequencies ADIsimCLK™ (V1.2 or later) is a free program that can help from a supplied reference frequency. This includes conversion with the design and exploration of the capabilities and features of reference frequencies to much higher frequencies for subsequent of the AD9516, including the design of the PLL loop filter. It is division and distribution. In addition, the PLL can be exploited to available at www.analog.com/clocks. clean up jitter and phase noise on a noisy reference. The exact Phase Frequency Detector (PFD) choices of PLL parameters and loop dynamics are very application The PFD takes inputs from the R counter and N counter and specific. The flexibility and depth of the AD9516 PLL allow the produces an output proportional to the phase and frequency part to be tailored to function in many different applications difference between them. The PFD includes a programmable and signal environments. delay element that controls the width of the antibacklash pulse. Configuration of the PLL This pulse ensures that there is no dead zone in the PFD The AD9516 allows flexible configuration of the PLL, transfer function and minimizes phase noise and reference accommodating various reference frequencies, PFD comparison spurs. The antibacklash pulse width is set by Register 0x017[1:0]. frequencies, VCO frequencies, internal or external VCO/VCXO, An important limit to keep in mind is the maximum frequency and loop dynamics. This is accomplished by the various settings allowed into the PFD, which in turn determines the correct that include the R divider, the N divider, the PFD polarity (only antibacklash pulse setting. The antibacklash pulse setting is applicable to external VCO/VCXO), the antibacklash pulse specified in the phase/frequency detector parameter of Table 2. width, the charge pump current, the selection of internal VCO or external VCO/VCXO, and the loop bandwidth. Rev. C | Page 32 of 80

Data Sheet AD9516-3 Charge Pump (CP) AD9516-3 The charge pump is controlled by the PFD. The PFD monitors VCO LF the phase and frequency relationship between its two inputs, and tells the CP to pump up or pump down to charge or discharge 31pF CP R2 the integrating node (part of the loop filter). The integrated and CHARGE R1 filtered CP current is transformed into a voltage that drives the PUMP C1 C2 C3 tuning node of the internal VCO through the LF pin (or the tuning BYPASS pTihne o Cf aPn c eaxnt ebren asle Vt (CROeg) itsot emr o0vxe0 1th0e[ 6V:4C]O) f forre qhuigehn ciym uppe dora ndcoew n. CBP = 220nF 06422-065 Figure 47. Example of External Loop Filter for a PLL Using the Internal VCO (allows holdover operation), for normal operation (attempts to lock the PLL loop), for pump up, or for pump down (test modes). When using an external VCO, the external loop filter should be The CP current is programmable in eight steps from (nominally) referenced to ground. See Figure 48 for an example of an 600 µA to 4.8 mA. The exact value of the CP current LSB is set external loop filter for a PLL using an external VCO. by the CPRSET resistor, which is nominally 5.1 kΩ. If the value of the resistor connected to the CP_RSET pin is doubled, the AD9516-3 EXTERNAL VCO/VCXO resulting charge pump current range becomes 300 µA to 2.4 mA. CLK/CLK On-Chip VCO CP R2 The AD9516 includes an on-chip VCO covering the frequency CHARGE R1 range shown in Table 2. The calibration procedure ensures that PUMP C1 C2 C3 tfrheeq VueCnOcy .o Tpherea VtinCgO v omltuasgte b ies cceanlitberraetded fo wr htheen dtheesi rVeCd OV CloOop is first 06422-265 set up, as well as any time the nominal VCO frequency changes. Figure 48. Example of External Loop Filter for a PLL Using an External VCO However, once the VCO is calibrated, the VCO has sufficient PLL Reference Inputs operating range to stay locked over temperature and voltage The AD9516 features a flexible PLL reference input circuit that extremes without needing additional calibration. See the VCO allows either a fully differential input or two separate single- Calibration section for more information. ended inputs. The input frequency range for the reference The on-chip VCO is powered by an on-chip, low dropout inputs is specified in Table 2. Both the differential and the (LDO), linear voltage regulator. The LDO provides some single-ended inputs are self-biased, allowing for easy ac isolation of the VCO from variations in the power supply coupling of input signals. voltage level. The BYPASS pin should be connected to ground The differential input and the single-ended inputs share the two by a 220 nF capacitor to ensure stability. This LDO employs the pins, REFIN/REFIN (REF1 and REF2, respectively). The desired same technology used in the anyCAP® line of regulators from reference input type is selected and controlled by Register 0x01C Analog Devices, Inc., making it insensitive to the type of (see Table 52 and Table 54). capacitor used. Driving an external load from the BYPASS pin is not supported. When the differential reference input is selected, the self-bias level of the two sides is offset slightly (~100 mV, see Table 2) to Note that the reference input signal must be present and the prevent chattering of the input buffer when the reference is slow VCO divider must not be static during VCO calibration. or missing. This increases the voltage swing that is required of the PLL External Loop Filter driver and overcomes the offset. The differential reference input When using the internal VCO, the external loop filter should can be driven by either ac-coupled LVDS or ac-coupled LVPECL be referenced to the BYPASS pin for optimal noise and spurious signals. performance. An example of an external loop filter for a PLL The single-ended inputs can be driven by either a dc-coupled that uses the internal VCO is shown in Figure 47. The third- CMOS level signal or an ac-coupled sine wave or square wave. order design shown in Figure 47 usually offers best performance. Each single-ended input can be independently powered down A loop filter must be calculated for each desired PLL configuration. when not needed to increase isolation and reduce power. Either The values of the components depend upon the VCO frequency, a differential or a single-ended reference must be specifically the K , the PFD frequency, the CP current, the desired loop VCO enabled. All PLL reference inputs are off by default. bandwidth, and the desired phase margin. The loop filter affects The differential reference input is powered down whenever the the phase noise, the loop settling time, and loop stability. A basic PLL is powered down, or when the differential reference input knowledge of PLL theory is helpful for understanding loop filter is not selected. The single-ended buffers power down when the design. ADIsimCLK can help with calculation of a loop filter PLL is powered down, and when their individual power down according to the application requirements. registers are set. When the differential mode is selected, the single-ended inputs are powered down. Rev. C | Page 33 of 80

AD9516-3 Data Sheet In differential mode, the reference input pins are internally self- Automatic revertive switchover relies on the REFMON pin to biased so that they can be ac-coupled via capacitors. It is possible to indicate when REF1 disappears. By programming Register 0x01B = dc couple to these inputs. If the differential REFIN is driven by 0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed a single-ended signal, the unused side (REFIN) should be to be high when REF1 is invalid, which commands the switch to decoupled via a suitable capacitor to a quiet ground. Figure 49 REF2. When REF1 is valid again, the REFMON pin goes low, and shows the equivalent circuit of REFIN. the part again locks to REF1. It is also possible to use the STATUS pin for this function, and REF2 can be used as the preferred VS reference. A switchover deglitch feature ensures that the PLL does not 85kΩ receive rising edges that are far out of alignment with the newly selected reference. REF1 Automatic nonrevertive switching is not supported. Reference Divider R VS 10kΩ 12kΩ The reference inputs are routed to the reference divider, R. REFIN R (a 14-bit counter) can be set to any value from 0 to 16383 by 150Ω writing to Register 0x011 and Register 0x012. (Both R = 0 and REFIN 150Ω R = 1 give divide-by-1.) The output of the R divider goes to one of the PFD inputs to be compared to the VCO frequency 10kΩ 10kΩ divided by the N divider. The frequency applied to the PFD must not exceed the maximum allowable frequency, which VS REF2 depends on the antibacklash pulse setting (see Table 2). The R counter has its own reset. R counter can be reset using 85kΩ the shared reset bit of the R, A, and B counters. It can also be reset by a SYNC operation. 06422-066 VCXO/VCO Feedback Divider N—P, A, B, R Figure 49. REFIN Equivalent Circuit The N divider is a combination of a prescaler (P) and two counters, A and B. The total divider value is Reference Switchover N = (P × B) + A The AD9516 supports dual single-ended CMOS inputs, as well as a single differential reference input. In the dual single-ended where the value of P can be 2, 4, 8, 16, or 32. reference mode, the AD9516 supports automatic and manual Prescaler PLL reference clock switching between REF1 (on Pin REFIN) The prescaler of the AD9516 allows for two modes of operation: and REF2 (on Pin REFIN). This feature supports networking a fixed divide (FD) mode of 1, 2, or 3, and dual modulus (DM) and other applications that require smooth switching of redundant mode where the prescaler divides by P and (P + 1) {2 and 3, 4 references. When used in conjunction with the automatic and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of holdover function, the AD9516 can achieve a worst-case operation are given in Table 54, Register 0x016[2:0]. Not all reference input switchover with an output frequency disturbance as modes are available at all frequencies (see Table 2). low as 10 ppm. When operating the AD9516 in dual modulus mode (P//P + 1), When using reference switchover, the single-ended reference the equation used to relate input reference frequency to VCO inputs should be dc-coupled CMOS levels and never be allowed output frequency is to go to high impedance. If these inputs are allowed to go to high impedance, noise may cause the buffer to chatter, causing a fVCO = (fREF/R) × (P × B + A) = fREF × N/R false detection of the presence of a reference. However, when operating the prescaler in FD mode, 1, 2, or 3, Reference switchover can be performed manually or auto- the A counter is not used (A = 0) and the equation simplifies to matically. Manual switchover is performed either through f = (f /R) × (P × B) = f × N/R VCO REF REF Register 0x01C or by using the REF_SEL pin. Manual switchover When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32, requires the presence of a clock on the reference input that is in which case the previous equation also applies. being switched to, or that the deglitching feature be disabled (Register 0x01C[7]). The reference switching logic fails if this condition isn’t met, and the PLL does not reacquire. Rev. C | Page 34 of 80

Data Sheet AD9516-3 By using combinations of DM and FD modes, the AD9516 can CLK) divided by P. For example, a dual modulus mode of P = 8/9 achieve values of N all the way down to N = 1 and up to N = is not allowed if the VCO frequency is greater than 2400 MHz 26,2175. Table 28 shows how a 10 MHz reference input can be because the frequency going to the A/B counter is too high. locked to any integer multiple of N. When the AD9516 B counter is bypassed (B = 1), the A counter Note that the same value of N can be derived in different ways, should be set to 0, and the overall resulting divide is equal to the as illustrated by the case of N = 12. The user can choose a fixed prescaler setting, P. The possible divide ratios in this mode are divide mode of P = 2 with B = 6; use the dual modulus mode of 1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an 2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with external VCO/VCXO is used because the frequency range of the A = 0, B = 3. internal VCO requires an overall feedback divider greater than 32. The maximum frequency into the prescaler in 2/3 dual-modulus Although manual reset is not normally required, the A/B counters mode is limited to 200 MHz. There are only two cases where have their own reset bit. Alternatively, the A and B counters can be this frequency limitation limits the flexibility of that N divider: reset using the shared reset bit of the R, A, and B counters. Note N = 7 and N = 11. In these two cases, the maximum frequency that these reset bits are not self-clearing. into the prescaler is 300 MHz and is achieved by using the P = 1 R, A, and B Counters—SYNC Pin Reset FD mode. In all other cases, the user can achieve the desired N divider value by using the other prescaler modes. The R, A, and B counters can also be reset simultaneously through the SYNC pin. This function is controlled by Register 0x019[7:6] A and B Counters (see Table 54). The SYNC pin reset is disabled by default. The B counter must be ≥3 or bypassed, and, unlike the R counter, R and N Divider Delays A = 0 is actually zero. Both the R and N dividers feature a programmable delay cell. When the prescaler is in dual modulus mode, the A counter These delays can be enabled to allow adjustment of the phase must be less than the B counter. relationship between the PLL reference clock and the VCO or The maximum input frequency to the A/B counter is reflected CLK. Each delay is controlled by three bits. The total delay in the maximum prescaler output frequency (~300 MHz) that is range is about 1 ns. See Register 0x019 in Table 54. specified in Table 2. This is the prescaler input frequency (VCO or Table 28. Using a 10 MHz Reference Input to Generate Different VCO Frequencies f f REF VCO (MHz) R P A B N (MHz) Mode Comments/Conditions 10 1 1 X 1 1 10 FD P = 1, B = 1 (A and B counters are bypassed). 10 1 2 X 1 2 20 FD P = 2, B = 1 (A and B counters are bypassed). 10 1 1 X 3 3 30 FD A counter is bypassed. 10 1 1 X 4 4 40 FD A counter is bypassed. 10 1 1 X 5 5 50 FD A counter is bypassed. 10 1 2 X 3 6 60 FD A counter is bypassed. 10 1 2 0 3 6 60 DM 10 1 2 1 3 7 70 DM Maximum frequency into prescaler in P = 2/3 mode is 200 MHz. If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz to 300 MHz, use P = 1, and N = 7 or 11, respectively. 10 1 2 2 3 8 80 DM 10 1 2 1 4 9 90 DM 10 1 2 X 5 10 100 FD 10 1 2 0 5 10 100 DM 10 1 2 1 5 11 110 DM 10 1 2 X 6 12 120 FD 10 1 2 0 6 12 120 DM 10 1 4 0 3 12 120 DM P = 8 is not allowed (2700 ÷ 8 > 300 MHz). P = 32 is not allowed (A > B not allowed). 10 1 4 1 3 13 130 DM P = 32, A = 22, B = 84. P = 16 is also permitted. Rev. C | Page 35 of 80

AD9516-3 Data Sheet DIGITAL LOCK DETECT (DLD) when it is selected as the output from the LD pin control (Register 0x01A[5:0]). By selecting the proper output through the mux on each pin, the DLD function can be made available at the LD, STATUS, The current source lock detect provides a current of 110 µA and REFMON pins. The DLD circuit indicates a lock when the when DLD is true, and it shorts to ground when DLD is false. time difference of the rising edges at the PFD inputs is less than If a capacitor is connected to the LD pin, it charges at a rate that a specified value (the lock threshold). The loss of a lock is is determined by the current source during the DLD true time indicated when the time difference exceeds a specified value but is discharged nearly instantly when DLD is false. By (the unlock threshold). Note that the unlock threshold is wider monitoring the voltage at the LD pin (top of the capacitor), it is than the lock threshold, which allows some phase error in possible to get a logic high level only after the DLD has been excess of the lock window to occur without chattering on the true for a sufficiently long time. Any momentary DLD false lock indicator. resets the charging. By selecting a properly sized capacitor, it is possible to delay a lock detect indication until the PLL is stably The lock detect window timing depends on three settings: the locked, and the lock detect does not chatter. digital lock detect window bit (Register 0x018[4]), the anti- backlash pulse width setting (Register 0x017[1:0], see Table 2), The voltage on the capacitor can be sensed by an external and the lock detect counter (Register 0x018[6:5]). A lock is not comparator connected to the LD pin. However, there is an indicated until there is a programmable number of consecutive internal LD pin comparator that can be read at the REFMON PFD cycles with a time difference that is less than the lock pin control (Register 0x01B[4:0]) or the STATUS pin control detect threshold. The lock detect circuit continues to indicate (Register 0x017[7:2]) as an active high signal. It is also available a lock until a time difference greater than the unlock threshold as an active low signal (REFMON, Register 0x01B[4:0] and occurs on a single subsequent cycle. For the lock detect to work STATUS, Register 0x017[7:2]). The internal LD pin comparator properly, the period of the PFD frequency must be greater than trip point and hysteresis are listed in Table 16. the unlock threshold. The number of consecutive PFD cycles AD9516-3 required for lock is programmable (Register 0x018[6:5]). 110µA Analog Lock Detect (ALD) The AD9516 provides an ALD function that can be selected for DLD LD VOUT use at the LD pin. There are two versions of ALD, as follows: C • N-channel open-drain lock detect. This signal requires LD PIN a pull-up resistor to positive supply, VS. The output is COMPARATOR REFMON OR nbyo rtmhea lmly ihniigmhu wmit hd ushtyo rcty, clolew o gfo tihneg lpouwls-egso. iLnogc pk uisls iensd. icated STATUS 06422-068 Figure 51. Current Source Lock Detect • P-channel open-drain lock detect. This signal requires a pull-down resistor to GND. The output is normally External VCXO/VCO Clock Input (CLK/CLK) low with short, high going pulses. Lock is indicated by CLK is a differential input that can be used as an input to drive the minimum duty cycle of the high-going pulses. the AD9516 clock distribution section. This input can receive The analog lock detect function requires an R-C filter to up to 2.4 GHz. The pins are internally self-biased and the input provide a logic level indicating lock/unlock. signal should be ac-coupled via capacitors. VS = 3.3V CLOSCTKA GINEPUT AD9516-3 R2 VS LD R1 VOUT CLK ALD C 06422-067 CLK 2.5kΩ 2.5kΩ Figure 50. Example of Analog Lock Detect Filter, Using 5kΩ Current Source DiNg-iCthaaln Lnoelc Okp Dene-Dteracint (DDrivLeDr ) 5kΩ 06422-032 Figure 52. CLK Equivalent Input Circuit During the PLL locking sequence, it is normal for the DLD signal to toggle a number of times before remaining steady The CLK/CLK input can be used either as a distribution only when the PLL is completely locked and stable. There may be input (with the PLL off), or as a feedback input for an external applications where it is desirable to have DLD asserted only VCO/VCXO using the internal PLL, when the internal VCO is after the PLL is solidly locked. This is made possible by using not used. The CLK/CLK input can be used for frequencies up the current source lock detect function. This function is set to 2.4 GHz. Rev. C | Page 36 of 80

Data Sheet AD9516-3 Holdover Automatic/Internal Holdover Mode The AD9516 PLL has a holdover function. Holdover is When enabled, this function automatically puts the charge implemented by putting the charge pump into a state of high pump into a high impedance state when the loop loses lock. impedance. This is useful when the PLL reference clock is lost. The assumption is that the only reason the loop loses lock is due Holdover mode allows the VCO to maintain a relatively constant to the PLL losing the reference clock; therefore, the holdover frequency even though there is no reference clock. Without this function puts the charge pump into a high impedance state to function, the charge pump is placed into a constant pump-up or maintain the VCO frequency as close as possible to the original pump-down state resulting in a massive VCO frequency shift. frequency before the reference clock disappears. Because the charge pump is placed in a high impedance state, See Figure 53 for a flowchart of the internal/automatic holdover any leakage that occurs at the charge pump output or the VCO function operation. tuning node causes a drift of the VCO frequency. This can be mitigated by using a loop filter that contains a large capacitive PLL ENABLED component because this drift is limited by the current leakage- induced slew rate (I /C) of the VCO control voltage. For most LEAK applications, the frequency accuracy is sufficient for 3 sec to 5 sec. LOOP OUT OF LOCK. DIGITAL LOCK Both a manual holdover, using the SYNC pin, and an automatic NO DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED holdover mode are provided. To use either function, the DLD == LOW BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD. holdover function must be enabled (Register 0x01D[0] and Register 0x01D[2]). Note that the VCO cannot be calibrated with the holdover enabled YES NO because the holdover resets the N divider during calibration, which prevents proper calibration. Disable holdover before ANALOG LOCK DETECT PIN INDICATES WAS LOCK WAS PREVIOUSLY ACHIEVED. issuing a VCO calibration. LD PIN == HIGH REGISTER 0x1D[3] = 1: USE LD PIN WHEN DLD WENT VOLTAGE WITH HOLDOVER. LOW? REGISTER 0x1D[3] = 0: IGNORE LD PIN Manual Holdover Mode VOLTAGE,TREAT LD PIN AS ALWAYS HIGH. A manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the YES SYNC pin is asserted low. This operation is edge sensitive, not level sensitive. The charge pump enters a high impedance state HCIGHHA RIMGPEE PDUAMNCPE CHHIGAHR IGMEP PEUDMANPC ISE .MADE PLL COUNTERS CONTINUE immediately. To take the charge pump out of a high impedance OPERATING NORMALLY. state take the SYNC pin high. The charge pump then leaves YES high impedance state synchronously with the next PFD rising NO edge from the reference clock. This prevents extraneous charge pump events from occurring during the time between SYNC CHARGE PUMP REMAINS HIGH REFERENCE IMPEDANCE UNTIL THE REFERENCE EDGE AT PFD? HAS RETURNED. going high and the next PFD event. This also means that the charge pump stays in a high impedance state as long as there is no reference clock present. YES YES The B counter (in the N divider) is reset synchronously with the TAKE CHARGE PUMP OUT OF charge pump leaving the high impedance state on the reference RELEASE HIGH IMPEDANCE. PLL CAN CHARGE PUMP NOW RESETTLE. path PFD event. This helps align the edges out of the R and N HIGH IMPEDANCE dividers for faster settling of the PLL. Because the prescaler is YES not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out. NO WAIT FOR DLD TO GO HIGH. THIS TAKES 5 TO 255 CYCLES (PROGRAMMING OF When using this mode, set the channel dividers to ignore the THE DLD DELAY COUNTER) WITH THE DLD == HIGH REFERENCE AND FEEDBACK CLOCKS SYNC pin (at least after an initial SYNC event). If the dividers are INSIDE THE LOCK WINDOW AT THE PFD. THIS ENSURES THAT THE HOLDOVER neaocth s etitm toe iSgYnoNrCe tihs et aSkYeNn Clo wpi nto, tphuet d tihsetr pibaurtt iionnto o huotplduotsv etur.r n off FAFUUNNNDCC LTTOIIOOCNNK WCBAEANFITO BSRE FE RO TERHT ETR HIHGEOG PLELDRLOE VTDOE.R SETTLE 06422-069 Figure 53. Flowchart of Automatic/Internal Holdover Mode Rev. C | Page 37 of 80

AD9516-3 Data Sheet The holdover function senses the logic level of the LD pin as a For example, to use automatic holdover with the following: condition to enter holdover. The signal at LD can be from the • Automatic reference switchover, prefer REF1 DLD, ALD, or current source LD mode. It is possible to disable • Digital lock detect: five PFD cycles, high range window the LD comparator (Register 0x01D[3]), which causes the holdover • Automatic holdover using the LD pin comparator function to always sense LD as high. If DLD is used, it is possible for the DLD signal to chatter some while the PLL is reacquiring Set the following registers (in addition to the normal PLL registers): lock. The holdover function may retrigger, thereby preventing • Register 0x018[6:5] = 00b; lock detect counter = five cycles. the holdover mode from ever terminating. Use of the current • Register 0x018[4] = 0b; lock detect window = high range. source lock detect mode is recommended to avoid this situation • Register 0x018[3] = 0b; DLD normal operation. (see the Current Source Digital Lock Detect section). • Register 0x01A[5:0] = 000100b; current source lock detect Once in holdover mode, the charge pump stays in a high mode. impedance state as long as there is no reference clock present. • Register 0x01B[7:0] = 0xF7; set REFMON pin to status of As in the external holdover mode, the B counter (in the N REF1 (active low). divider) is reset synchronously with the charge pump leaving the • Register 0x01C[2:1] = 11b; enable REF1 and REF2 input high impedance state on the reference path PFD event. This buffers. helps align the edges out of the R and N dividers for faster settling • Register 0x01D[3] = 1b; enable LD pin comparator. of the PLL and to reduce frequency errors during settling. Because • Register 0x01D[2]=1b; enable the holdover function. the prescaler is not reset, this feature works best when the B and • Register 0x01D[1] = 0b; use internal/automatic holdover R numbers are close because this results in a smaller phase mode. difference for the loop to settle out. • Register 0x01D[0] = 1b; enable the holdover function. After leaving holdover, the loop then reacquires lock and the (VCO calibration must be complete before this bit is LD pin must charge (if Register 0x01D[3] = 1) before it can enabled.) re-enter holdover (CP high impedance). • Connect REFMON pin to REFSEL pin. The holdover function always responds to the state of the Frequency Status Monitors currently selected reference (Register 0x01C). If the loop loses The AD9516 contains three frequency status monitors that are lock during a reference switchover (see the Reference Switchover used to indicate if the PLL reference (or references in the case of section), holdover is triggered briefly until the next reference single-ended mode) and the VCO have fallen below a threshold clock edge at the PFD. frequency. A diagram showing their location in the PLL is The following registers affect the internal/automatic holdover shown in Figure 54. function: The PLL reference frequency monitors have two threshold • Register 0x018[6:5], lock detect counter. These bits change frequencies: normal and extended (see Table 16). The reference the number of consecutive PFD cycles with edges inside the frequency monitor thresholds are selected in Register 0x01B[7:5]. lock detect window that are required for the DLD indicator Frequency monitor status can be found in Register 0x01F[3:1]. to indicate lock. This impacts the time required before the LD pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be reengaged. • Register 0x018[3], disable digital lock detect. This bit must be set to a 0 to enable the DLD circuit. Internal/automatic holdover does not operate correctly without the DLD function enabled. • Register 0x01A[5:0], lock detect pin output select. Set these bits to 000100b for the current source lock detect mode if using the LD pin comparator. Load the LD pin with a capacitor of an appropriate value. • Register 0x01D[3], enable LD pin comparator. 1 = enable, 0 = disable. When disabled, the holdover function always senses the LD pin as high. • Register 0x01D[1], enable external holdover control. • Register 0x01D[0] and Register 0x01D[2], holdover function enable. If holdover is disabled, both external and internal/automatic holdover are disabled. Rev. C | Page 38 of 80

Data Sheet AD9516-3 REF_SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 LOCK DETECT REF2 STATUS R PROGRAMMABLE NCE DIVIDER R DELAY LLRE STATUS PE REFIN (REF1) EF HOLD R REFIN (REF2) N DIVIDER PHASE BYPASS RELGOUWL ADTROORP O(LUDTO) PRPE,S PC A+ L1ER COUAN/TBERS PRO GNR DAEMLMAAYBLE FDREETQEUCETNOCRY CHPUAMRGPE CP LF VCO STATUS VCO DIVIDE BY 0 STATUS 2, 3, 4, 5, OR 6 CLK 1 CLK 1 0 06422-070 Figure 54. Reference and VCO Status Monitors VCO Calibration A sync is executed during the VCO calibration; therefore, the outputs of the AD9516 are held static during the calibration, The AD9516 on-chip VCO must be calibrated to ensure proper which prevents unwanted frequencies from being produced. operation over process and temperature. The VCO calibration However, at the end of a VCO calibration, the outputs may is controlled by a calibration controller running off of a divided resume clocking before the PLL loop is completely settled. REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present. The VCO calibration clock divider is set as shown in Table 54 During the first initialization after a power-up or a reset of the (Register 0x018[2:1]). AD9516, a VCO calibration sequence is initiated by setting The calibration divider divides the PFD frequency (reference Register 0x018[0] = 1b. This can be done as part of the initial frequency divided by R) down to the calibration clock. The setup, before executing update registers (Register 0x232[0] = 1b). calibration occurs at the PFD frequency divided by the Subsequent to the initial setup, a VCO calibration sequence is calibration divider setting. Lower VCO calibration clock initiated by resetting Register 0x018[0] = 0b, executing an update frequencies result in longer times for a calibration to be registers operation, setting Register 0x018[0] = 1b, and executing completed. another update registers operation. A readback bit, Bit 6 in The VCO calibration clock frequency is given by Register 0x01F, indicates when a VCO calibration is finished by returning a logic true (that is, 1b). f = f /(R × cal_div) CAL_CLOCK REFIN The sequence of operations for the VCO calibration is as follows: where: f is the frequency of the REFIN signal.  Program the PLL registers to the proper values for the REFIN R is the value of the R divider. PLL loop. Note that that automatic holdover mode cal_div is the division set for the VCO calibration divider must be disabled, and the VCO divider must not be (Register 0x018[2:1]). set to “Static.”  Ensure that the input reference signal is present. The VCO calibration takes 4400 calibration clock cycles.  For the initial setting of the registers after a power-up or Therefore, the VCO calibration time in PLL reference clock reset, initiate VCO calibration by setting Register cycles is given by 0x018[0] = 1b. Subsequently, whenever a calibration is Time to Calibrate VCO = desired, set Register 0x018[0] = 0b, update registers; 4400 × R × cal_div PLL Reference Clock Cycles and then set Register 0x018[0] = 1b, update registers.  A SYNC operation is initiated internally, causing the Table 29. Example Time to Complete a VCO Calibration outputs to go to a static state determined by normal with Different f Frequencies REFIN SYNC function operation. f (MHz) R Divider PFD Time to Calibrate VCO REFIN  VCO calibrates to the desired setting for the requested 100 1 100 MHz 88 μs VCO frequency. 10 10 1 MHz 8.8 ms  Internally, the SYNC signal is released, allowing 10 100 100 kHz 88 ms outputs to continue clocking.  PLL loop is closed.  PLL locks. Rev. C | Page 39 of 80

AD9516-3 Data Sheet VCO calibration must be manually initiated. This allows for The channel dividers allow for a selection of various duty cycles, flexibility in deciding what order to program registers and when depending on the currently set division. That is, for any specific to initiate a calibration, instead of having it happen every time division, D, the output of the divider can be set to high for N + 1 certain PLL registers have their values change. For example, this input clock cycles and low for M + 1 input clock cycles (where allows for the VCO frequency to be changed by small amounts D = N + M + 2). For example, a divide-by-5 can be high for one without having an automatic calibration occur each time; this divider input cycle and low for four cycles, or a divide-by-5 can should be done with caution and only when the user knows that be high for three divider input cycles and low for two cycles. the VCO control voltage is not going to exceed the nominal best Other combinations are also possible. performance limits. For example, a few 100 kHz steps are fine, The channel dividers include a duty-cycle correction function, but a few MHz might not be). In addition, because the calibration that can be disabled. In contrast to the selectable duty cycle procedure results in rapid changes in the VCO frequency, the just described, this function can correct a non-50% duty cycle distribution section is automatically placed in SYNC until the caused by an odd division. However, this requires that the calibration is finished. Therefore, this temporary loss of outputs division be set by M = N + 1. must be expected. In addition, the channel dividers allow a coarse phase offset or A VCO calibration should be initiated under the following delay to be set. Depending on the division selected, the output conditions: can be delayed by up to 31 input clock cycles. The divider • After changing any of the PLL R, P, B, and A divider outputs can also be set to start high or start low. settings, or after a change in the PLL reference clock Internal VCO or External CLK as Clock Source frequency. This, in effect, means any time a PLL register The clock distribution of the AD9516 has two clock input sources: or reference clock is changed such that a different VCO an internal VCO or an external clock connected to the CLK/ frequency results. CLK pins. Either the internal VCO or CLK must be chosen as • Whenever system calibration is desired. The VCO is designed the source of the clock signal to distribute. When the internal to operate properly over extremes of temperatures even when VCO is selected as the source, the VCO divider must be used. first calibrated at the opposite extreme. However, a VCO When CLK is selected as the source, it is not necessary to use calibration can be initiated at any time, if desired. the VCO divider if the CLK frequency is less than the CLOCK DISTRIBUTION maximum channel divider input frequency (1600 MHz); otherwise, the VCO divider must be used to reduce the A clock channel consists of a pair (or double pair, in the case of frequency to one acceptable by the channel dividers. Table 30 CMOS) of outputs that share a common divider. A clock output shows how the VCO, CLK, and VCO divider are selected. consists of the drivers that connect to the output pins. The clock Register 0x1E1[1:0] selects the channel divider source and outputs have either LVPECL or LVDS/CMOS signal levels at determines whether the VCO divider is used. It is not possible the pins. to select the VCO without using the VCO divider. The AD9516 has five clock channels: three channels are LVPECL (six outputs); two channels are LVDS/CMOS (up to four LVDS Table 30. Selecting VCO or CLK as Source for Channel outputs, or up to eight CMOS outputs). Divider, and Whether VCO Divider Is Used Register 0x1E1 Each channel has its own programmable divider that divides Bit 1 Bit 0 Channel Divider Source VCO Divider the clock frequency that is applied to its input. The LVPECL channel dividers can divide by any integer from 2 to 32, or 0 0 CLK Used the divider can be bypassed to achieve a divide by one. Each 0 1 CLK Not used LVDS/CMOS channel divider contains two of these divider 1 0 VCO Used blocks in a cascaded configuration. The total division of the 1 1 Not allowed Not allowed channel is the product of the divide value of the cascaded dividers. This allows divide values of (1 to 32) × (1 to 32), or up to 1024 CLK or VCO Direct to LVPECL Outputs (note that this is not all values from 1 to 1024 but only the set It is possible to connect either the internal VCO or the CLK of numbers that are the product of the two dividers). (whichever is selected as the input to the VCO divider) directly Because the internal VCO frequency is above the maximum to the LVPECL outputs, OUT0 to OUT5. This configuration channel divider input frequency (1600 MHz), the VCO divider can pass frequencies up to the maximum frequency of the VCO must be used after the on-chip VCO. The VCO divider can be directly to the LVPECL outputs. The LVPECL outputs may not set to divide by 2, 3, 4, 5, or 6. External clock signals connected be able to provide full voltage swing at the highest frequencies. to the CLK input also require the VCO divider if the frequency of the signal is greater than 1600 MHz. Rev. C | Page 40 of 80

Data Sheet AD9516-3 To connect the LVPECL outputs directly to the internal VCO or The channel dividers feeding the LVPECL output drivers CLK, the VCO divider must be selected as the source to the contain one 2-to-32 frequency divider. This divider provides for distribution section, even if no channel uses it. division by 2 to 32. Division by 1 is accomplished by bypassing the divider. The dividers also provide for a programmable duty Either the internal VCO or the CLK can be selected as the cycle, with optional duty-cycle correction when the divide ratio source for the direct to output routing. is odd. A phase offset or delay in increments of the input clock Table 31. Settings for Routing VCO Divider Input Directly cycle is selectable. The channel dividers operate with a signal at to LVPECL Outputs their inputs up to 1600 MHz. The features and settings of the Register Setting Selection dividers are selected by programming the appropriate setup 0x1E1[1:0] = 00b CLK is the source; VCO divider selected and control registers (see Table 52 through Table 62). 0x1E1[1:0] = 10b VCO is the source; VCO divider selected VCO Divider 0x192[1] = 1b Direct to output OUT0, OUT1 The VCO divider provides frequency division between 0x195[1] = 1b Direct to output OUT2, OUT3 the internal VCO or the external CLK input and the clock 0x198[1] = 1b Direct to output OUT4, OUT5 distribution channel dividers. The VCO divider can be set Clock Frequency Division to divide by 2, 3, 4, 5, or 6 (see Table 60, Register 0x1E0[2:0]). The total frequency division is a combination of the VCO Channel Dividers—LVPECL Outputs divider (when used) and the channel divider. When the VCO Each pair of LVPECL outputs is driven by a channel divider. divider is used, the total division from the VCO or CLK to the There are three channel dividers (0, 1, and 2) driving a total of output is the product of the VCO divider (2, 3, 4, 5, 6) and the six LVPECL outputs (OUT0 to OUT5). Table 34 lists the register division of the channel divider. Table 32 and Table 33 indicate locations used for setting the division and other functions of how the frequency division for a channel is set. For the LVPECL these dividers. The division is set by the values of M and N. The outputs, there is only one divider per channel. For the LVDS/ divider can be bypassed (equivalent to divide-by-1, divider circuit CMOS outputs, there are two dividers (X.1, X.2) cascaded is powered down) by setting the bypass bit. The duty-cycle per channel. correction can be enabled or disabled according to the setting of the DCCOFF bits. Table 32. Frequency Division for Divider 0 to Divider 2 CLK Table 34. Setting D for Divider 0, Divider 1, and Divider 21 X or VCO VCO Channel Direct to Frequency Low Cycles High Cycles Selected Divider Divider Output Division Divider M N Bypass DCCOFF CLK/VCO 2 to 6 1 (bypassed) Yes 1 0 0x190[7:4] 0x190[3:0] 0x191[7] 0x192[0] CLK/VCO 2 to 6 1 (bypassed) No (2 to 6) × (1) 1 0x193[7:4] 0x193[3:0] 0x194[7] 0x195[0] CLK/VCO 2 to 6 2 to 32 No (2 to 6) × 2 0x196[7:4] 0x196[3:0] 0x197[7] 0x198[0] (2 to 32) CLK Not used 1 (bypassed) No 1 1 Note that the value stored in the register = # of cycles minus 1. CLK Not used 2 to 32 No 2 to 32 Channel Frequency Division (0, 1, and 2) For each channel (where the channel number is x: 0, 1, or 2), Table 33. Frequency Division for Divider 3 and Divider 4 the frequency division, D , is set by the values of M and N X CLK (four bits each, representing Decimal 0 to Decimal 15), where or VCO VCO Channel Divider Frequency Selected Divider X.1 X.2 Division Number of Low Cycles = M + 1 CLK/VCO 2 to 6 1 1 (2 to 6) × Number of High Cycles = N + 1 (bypassed) (bypassed) (1) × (1) The cycles are cycles of the clock signal currently routed to the CLK/VCO 2 to 6 2 to 32 1 (2 to 6) × (bypassed) (2 to 32) × (1) input of the channel dividers (VCO divider out or CLK). CLK/VCO 2 to 6 2 to 32 2 to 32 (2 to 6) × When a divider is bypassed, D = 1. X (2 to 32) × (2 to 32) Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows CLK Not used 1 1 1 each channel divider to divide by any integer from 2 to 32. CLK Not used 2 to 32 1 (2 to 32) × (1) CLK Not used 2 to 32 2 to 32 2 to 32 × (2 to 32) Rev. C | Page 41 of 80

AD9516-3 Data Sheet Duty Cycle and Duty-Cycle Correction (0, 1, and 2) Table 36. Duty Cycle with VCO Divider, Input Duty Cycle Is X% The duty cycle of the clock signal at the output of a channel is VCO DX Output Duty Cycle a result of some or all of the following conditions: Divider N + M + 2 DCCOFF = 1 DCCOFF = 0 Even 1 (divider 50% 50% • What are the M and N values for the channel? bypassed) • Is the DCC enabled? Odd = 3 1 (divider 33.3% (1 + X%)/3 • Is the VCO divider used? bypassed) • What is the CLK input duty cycle? (The internal VCO has Odd = 5 1 (divider 40% (2 + X%)/5 a 50% duty cycle.) bypassed) Even Even (N + 1)/ 50%, The DCC function is enabled by default for each channel divider. (N + M + 2) requires M = N However, the DCC function can be disabled individually for Odd (N + 1)/ 50%, each channel divider by setting the DCCOFF bit for that channel. (N + M + 2) requires M = N + 1 Odd = 3 Even (N + 1)/ 50%, Certain M and N values for a channel divider result in a non-50% (N + M + 2) requires M = N duty cycle. A non-50% duty cycle can also result with an even Odd = 3 Odd (N + 1)/ (3N + 4 + X%)/(6N + 9), division, if M ≠ N. The duty-cycle correction function (N + M + 2) requires M = N + 1 automatically corrects non-50% duty cycles at the channel Odd = 5 Even (N + 1)/ 50%, divider output to 50% duty cycle. Duty-cycle correction (N + M + 2) requires M = N requires the following channel divider conditions: Odd = 5 Odd (N + 1)/ (5N + 7 + X%)/(10N + 15), • An even division must be set as M = N (N + M + 2) requires M = N + 1 • An odd division must be set as M = N + 1 Table 37. Channel Divider Output Duty Cycle When the When not bypassed or corrected by the DCC function, the duty VCO Divider Is Not Used cycle of each channel divider output is the numerical value of Input D Output Duty Cycle X (N + 1)/(N + M + 2), expressed as a percentage (%). Clock Duty The duty cycle at the output of the channel divider for various Cycle N + M + 2 DCCOFF = 1 DCCOFF = 0 configurations is shown in Table 35 to Table 37. Any 1 1 (divider Same as input bypassed) duty cycle Table 35. Duty Cycle with VCO Divider, Input Duty Cycle Is 50% Any Even (N + 1)/ 50%, requires M = N VCO D Output Duty Cycle X (M + N + 2) Divider N + M + 2 DCCOFF = 1 DCCOFF = 0 50% Odd (N + 1)/ 50%, requires Even 1 (divider 50% 50% (M + N + 2) M = N + 1 bypassed) X% Odd (N + 1)/ (N + 1 + X%)/(2 × N + 3), Odd = 3 1 (divider 33.3% 50% (M + N + 2) requires M = N + 1 bypassed) Odd = 5 1 (divider 40% 50% The internal VCO has a duty cycle of 50%. Therefore, when the bypassed) VCO is connected directly to the output, the duty cycle is 50%. Even, Odd Even (N + 1)/ 50%; requires M = N If the CLK input is routed directly to the output, the duty cycle of (N + M + 2) the output is the same as the CLK input. Even, Odd Odd (N + 1)/ 50%; requires M = N + 1 (N + M + 2) Rev. C | Page 42 of 80

Data Sheet AD9516-3 Phase Offset or Coarse Time Delay (0, 1, and 2) Channel Dividers—LVDS/CMOS Outputs Each channel divider allows for a phase offset, or a coarse time Channel Divider 3 and Channel Divider 4 each drive a pair of delay, to be programmed by setting register bits (see Table 38). LVDS outputs, giving a total of four LVDS outputs (OUT6 to These settings determine the number of cycles (successive OUT9). Alternatively, each of these LVDS differential outputs rising edges) of the channel divider input frequency by which to can be configured individually as a pair (A and B) of CMOS offset or delay the rising edge of the output of the divider. This single-ended outputs, providing for up to eight CMOS outputs. delay is with respect to a nondelayed output (that is, with a By default, the B output of each pair is off but can be turned on phase offset of zero). The amount of the delay is set by five bits as desired. loaded into the phase offset (PO) register, plus the start high Channel Divider 3 and Channel Divider 4 each consist of two (SH) bit for each channel divider. When the start high bit is set, cascaded, 2 to 32, frequency dividers. The channel frequency the delay is also affected by the number of low cycles (M) that division is D × D or up to 1024. Divide-by-1 is achieved by X.1 X.2 are programmed for the divider. bypassing one or both of these dividers. Both of the dividers The SYNC function must be used to make phase offsets effective also have DCC enabled by default, but this function can be (see the Synchronizing the Outputs—SYNC Function section). disabled, if desired, by setting the DCCOFF bit of the channel. A coarse phase offset or delay is also programmable (see the Table 38. Setting Phase Offset and Division for Divider 0, Phase Offset or Coarse Time Delay (Divider 3 and Divider 4) Divider 1, and Divider 2 section). The channel dividers operate up to 1600 MHz. The Start Phase Low High features and settings of the dividers are selected by programming Divider High (SH) Offset (PO) Cycles (M) Cycles (N) the appropriate setup and control registers (see Table 52 and 0 0x191[4] 0x191[3:0] 0x190[7:4] 0x190[3:0] Table 53 through Table 62). 1 0x194[4] 0x194[3:0] 0x193[7:4] 0x193[3:0] 2 0x197[4] 0x197[3:0] 0x196[7:4] 0x196[3:0] Table 39. Setting Division (DX) for Divider 3, Divider 41 Divider M N Bypass DCCOFF Let 3 3.1 0x199[7:4] 0x199[3:0] 0x19C[4] 0x19D[0] Δt = delay (in seconds). 3.2 0x19B[7:4] 0x19B[3:0] 0x19C[5] 0x19D[0] Δc = delay (in cycles of clock signal at input to D ). X 4 4.1 0x19E[7:4] 0x19E[3:0] 0x1A1[4] 0x1A2[0] T = period of the clock signal at the input of the divider, D X X 4.2 0x1A0[7:4] 0x1A0[3:0] 0x1A1[5] 0x1A2[0] (in seconds). Φ = 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0] 1 Note that the value stored in the register = # of cycles minus 1. The channel divide-by is set as N = high cycles, and M = low cycles. Channel Frequency Division (Divider 3 and Divider 4) Case 1 The division for each channel divider is set by the bits in the For Φ ≤ 15: registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2) Δt = Φ × TX Number of Low Cycles = MX.Y + 1 Δc = Δt/T = Φ X Number of High Cycles = N + 1 X.Y Case 2 When both X.1 and X.2 are bypassed, D = 1 × 1 = 1. X For Φ ≥ 16: When only X.2 is bypassed, D = (N + M + 2) × 1. Δt = (Φ − 16 + M + 1) × T X X.1 X.1 X Δc = Δt/TX When both X.1 and X.2 are not bypassed, DX = (NX.1 + MX.1 + 2) × (N + M + 2). X.2 X.2 By giving each divider a different phase offset, output-to-output By cascading the dividers, channel division up to 1024 can be delays can be set in increments of the channel divider input obtained. However, not all integer value divisions from 1 to clock cycle. Figure 55 shows the results of setting such a coarse 1024 are obtainable; only the values that are the product of the offset between outputs. separate divisions of the two dividers (D × D ) can be realized. X.1 X.2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CHANNEL If only one divider is needed when using Divider 3 and Divider 4, DIVIDER INPUT Tx use the first one (X.1) and bypass the second one (X.2). Do not CHANNEL DIVIDER OUTPUTS DIV = 4, DUTY = 50% bypass X.1 and use X.2. SH = 0 DIVIDER 0 PO = 0 SH = 0 DIVIDER 1 PO = 1 SH = 0 DIVIDER 2 PO = 2 12 ×× TTxx 06419-071 Figure 55. Effect of Coarse Phase Offset (or Delay) Rev. C | Page 43 of 80

AD9516-3 Data Sheet Duty Cycle and Duty-Cycle Correction (Divider 3 and Table 42. Divider 3, Divider 4 Duty Cycle; VCO Divider Divider 4) Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO Divider Input Duty Cycle = 50% The same duty cycle and DCC considerations apply to Divider 3 D D and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the VCO X.1 X.2 Output Divider N + M + 2 N + M + 2 Duty Cycle Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section); X.1 X.1 X.2 X.2 Even 1 1 50% however, with these channel dividers, the number of possible configurations is even more complex. Odd 1 1 50% Even Even (N = M ) 1 50% X.1 X.1 Duty-cycle correction on Divider 3 and Divider 4 requires the Odd Even (N = M ) 1 50% X.1 X.1 following channel divider conditions: Even Odd (M = N + 1) 1 50% X.1 X.1 • An even DX.Y must be set as MX.Y = NX.Y (low cycles = high Odd Odd (MX.1 = NX.1 + 1) 1 50% cycles). Even Even (N = M ) Even (N = M ) 50% X.1 X.1 X.2 X.2 • An odd DX.Y must be set as MX.Y = NX.Y + 1 (the number of Odd Even (NX.1 = MX.1) Even (NX.2 = MX.2) 50% low cycles must be one greater than the number of high Even Odd (MX.1 = NX.1 + 1) Even (NX.2 = MX.2) 50% cycles). Odd Odd (M = N + 1) Even (N = M ) 50% X.1 X.1 X.2 X.2 • If only one divider is bypassed, it must be the second Even Odd (MX.1 = NX.1 + 1) Odd (MX.2 = NX.2 + 1) 50% divider, X.2. Odd Odd (MX.1 = NX.1 + 1) Odd (MX.2 = NX.2 + 1) 50% • If only one divider has an even divide by, it must be the Table 43. Divider 3, Divider 4 Duty Cycle; VCO Divider second divider, X.2. Used; Duty Cycle Correction On (DCCOFF = 0); VCO The possibilities for the duty cycle of the output clock from Divider Input Duty Cycle = X% Divider 3 and Divider 4 are shown in Table 40 through Table 44. D D VCO X.1 X.2 Output Table 40. Divider 3, Divider 4 Duty Cycle; VCO Divider Divider NX.1 + MX.1 + 2 NX.2 + MX.2 + 2 Duty Cycle Used; Duty Cycle Correction Off (DCCOFF = 1) Even 1 1 50% VCO DX.1 DX.2 Output Duty Odd = 3 1 1 (1 + X%)/3 Divider N + M + 2 N + M + 2 Cycle Odd = 5 1 1 (2 + X%)/5 X.1 X.1 X.2 X.2 Even Even Even 1 1 50% 1 50% (N = M ) Odd = 3 1 1 33.3% X.1 X.1 Odd Even Odd = 5 1 1 40% 1 50% (N = M ) X.1 X.1 Even Even, odd 1 (N + 1)/ X.1 Even Odd (N + M + 2) 1 50% X.1 X.1 (M = N + 1) X.1 X.1 Odd Even, odd 1 (N + 1)/ X.1 Odd = 3 Odd (3N + 4 + X%)/ (N + M + 2) 1 X.1 X.1 X.1 (M = N + 1) (6N + 9) X.1 X.1 X.1 Even Even, odd Even, odd (N + 1)/ X.2 Odd = 5 Odd (5N + 7 + X%)/ (N + M + 2) 1 X.1 X.2 X.2 (M = N + 1) (10N + 15) X.1 X.1 X.1 Odd Even, odd Even, odd (N + 1)/ X.2 Even Even Even (N + M + 2) 50% X.2 X.2 (N = M ) (N = M ) X.1 X.1 X.2 X.2 Odd Even Even 50% Table 41. Divider 3, Divider 4 Duty Cycle; VCO Divider Not (N = M ) (N = M ) X.1 X.1 X.2 X.2 Used; Duty Cycle Correction Off (DCCOFF = 1) Even Odd Even 50% Input Clock DX.1 DX.2 Output (MX.1 = NX.1 + 1) (NX.2 = MX.2) Duty Cycle N + M + 2 N + M + 2 Duty Cycle Odd Odd Even X.1 X.1 X.2 X.2 50% (M = N + 1) (N = M ) 50% 1 1 50% X.1 X.1 X.2 X.2 Even Odd Odd X% 1 1 X% 50% (M = N + 1) (M = N + 1) 50% Even, odd 1 (N + 1)/ X.1 X.1 X.2 X.2 X.1 Odd = 3 (6N N + 9N + (N + M + 2) X.1 X.2 X.1 X.1 X.1 Odd Odd 9N + 13 + X%)/ X% Even, odd 1 (N + 1)/ X.2 (NX.1 + M + 2) (MX.1 = NX.1 + 1) (MX.2 = NX.2 + 1) (3(2NX.1 + 3) X.1 X.1 (2N + 3)) X.2 50% Even, odd Even, odd (N + 1)/ X.2 Odd = 5 (10N N + 15N + (N + M + 2) X.1 X.2 X.1 X.2 X.2 Odd Odd 15N + 22 + X%)/ X.2 X% Even, odd Even, odd (NX.2 + 1)/ (MX.1 = NX.1 + 1) (MX.2 = NX.2 + 1) (5(2 NX.1 + 3) (NX.2 + MX.2 + 2) (2 NX.2 + 3)) Rev. C | Page 44 of 80

Data Sheet AD9516-3 Table 44. Divider 3, Divider 4 Duty Cycle; VCO Divider Not Let Δt = delay (in seconds). Used; Duty Cycle Correction On (DCCOFF = 0) Φ = 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + x.y Input 1 × PO[0]. D D Clock X.1 X.2 T = period of the clock signal at the input to D (in seconds). Duty Output X.1 X.1 Cycle NX.1 + MX.1 + 2 NX.2 + MX.2 + 2 Duty Cycle TX.2 = period of the clock signal at the input to DX.2 (in seconds). 50% 1 1 50% Case 1 50% Even 1 50% When Φ ≤ 15 and Φ ≤ 15: (N = M ) x.1 x.2 X.1 X.1 X% 1 1 X% (High) Δt = Φx.1 × TX.1 + ΦX.2 × Tx.2 X% Even 1 50% Case 2 (N = M ) X.1 X.1 When Φ ≤ 15 and Φ ≥ 16: 50% Odd 1 50% x.1 x.2 (MX.1 = NX.1 + 1) Δt = ΦX.1 × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2 X% Odd 1 (N + 1 + X%)/ X.1 Case 3 (M = N + 1) (2N + 3) X.1 X.1 X.1 Odd 1 (NX.1 + 1 + X%)/ When ΦX.1 ≥ 16 and ΦX.2 ≤ 15: (M = N + 1) (2N + 3) X.1 X.1 X.1 Δt = (Φ − 16 + M + 1) × T + Φ × T X.1 X.1 X.1 X.2 X.2 50% Even Even 50% (N = M ) (N = M ) Case 4 X.1 X.1 X.2 X.2 X% Even Even 50% When Φ ≥ 16 and Φ ≥ 16: X.1 X.2 (N = M ) (N = M ) X.1 X.1 X.2 X.2 50% Odd Even 50% Δt = (M = N + 1) (N = M ) X.1 X.1 X.2 X.2 (Φ − 16 + M + 1) × T + (Φ − 16 + M + 1) × T X.1 X.1 X.1 X.2 X.2 X.2 X% Odd Even 50% (M = N + 1) (N = M ) Fine Delay Adjust (Divider 3 and Divider 4) X.1 X.1 X.2 X.2 50% Odd Odd 50% Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes (M = N + 1) (M = N + 1) X.1 X.1 X.2 X.2 an analog delay element that can be programmed to give X% Odd Odd (2N N + 3N + X.1 X.2 X.1 variable time delays (Δt) in the clock signal at that output. (MX.1 = NX.1 + 1) (MX.2 = NX.2 + 1) 3NX.2 + 4 + X%)/ ((2NX.1 + 3)(2NX.2 + 3)) VCO BYPASS CLK DIVIDER CMOS OUTM Δt LVDS Phase Offset or Coarse Time Delay (Divider 3 and Divider 4) OUTM FINE DELAY CMOS ADJUST Divider 3 and Divider 4 can be set to have a phase offset or DIVIDER DIVIDER OUTPUT delay. The phase offset is set by a combination of the bits in the X.1 X.2 DRIVERS BYPASS phase offset and start high registers (see Table 45). CMOS OUTN Δt LVDS OUTN TDaivbildee 4r5 4. Setting Phase Offset and Division for Divider 3 and FINAED JDUESLTAY CMOS 06422-072 Start Phase Low High Figure 56. Fine Delay (OUT6 to OUT9) Divider High (SH) Offset (PO) Cycles M Cycles N The amount of delay applied to the clock signal is determined 3 3.1 0x19C[0] 0x19A[3:0] 0x199[7:4] 0x199[3:0] by programming four registers per output (see Table 46). 3.2 0x19C[1] 0x19A[7:4] 0x19B[7:4] 0x19B[3:0] 4 4.1 0x1A1[0] 0x19F[3:0] 0x19E[7:4] 0x19E[3:0] Table 46. Setting Analog Fine Delays 4.2 0x1A1[1] 0x19F[7:4] 0x1A0[7:4] 0x1A0[3:0] OUTPUT Ramp Ramp Delay Delay (LVDS/CMOS) Capacitors Current Fraction Bypass OUT6 0x0A1[5:3] 0x0A1[2:0] 0x0A2[5:0] 0x0A0[0] OUT7 0x0A4[5:3] 0x0A4[2:0] 0x0A5[5:0] 0x0A3[0] OUT8 0x0A7[5:3] 0x0A7[2:0] 0x0A8[5:0] 0x0A6[0] OUT9 0x0AA[5:3] 0x0AA[2:0] 0x0AB[5:0] 0x0A9[0] Rev. C | Page 45 of 80

AD9516-3 Data Sheet Calculating the Fine Delay Synchronization of the outputs is executed in several ways, as follows: The following values and equations are used to calculate the delay of the delay block. • By forcing the SYNC pin low and then releasing it (manual sync). I (µA) = 200 × (Ramp Current + 1) RAMP • By setting and then resetting any one of the following three Number of Capacitors = Number of Bits = bits: the soft sync bit (Register 0x230[0]), the soft reset bit 0 in Ramp Capacitors + 1 (Register 0x000[2] [mirrored]), and the power-down Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3; distribution reference bit (Register 0x230[1]). 001 = 2 + 1 = 3; 111 = 0 + 1 = 1. • By executing synchronization of the outputs as part of the Delay Range (ns) = 200 × ((No. of Caps + 3)/(I )) × 1.3286 chip power-up sequence. RAMP • By forcing the RESET pin low and then releasing it (chip Offset(ns)=0.34+(1600−IRAMP)×10−4+No.oIfRCAMaPps−1×6 • rBeys efot)r.c ing the PD pin low and then releasing it (chip power- Delay Full Scale (ns) = Delay Range + Offset down). Fine Delay (ns) = • Following completion of a VCO calibration. An internal Delay Range × Delay Fraction × (1/63) + Offset SYNC signal is automatically asserted at the beginning and released upon the completion of a VCO calibration. Note that only delay fraction values up to 47 decimal (101111b; 0x2F) are supported. The most common way to execute the SYNC function is to use the SYNC pin to do a manual synchronization of the outputs. In no case can the fine delay exceed one-half of the output clock period. If a delay longer than half of the clock period is attempted, This requires a low-going signal on the SYNC pin, which is held the output stops clocking. low and then released when synchronization is desired. The timing of the SYNC operation is shown in Figure 57 (using The delay function adds some jitter that is greater than that VCO divider) and Figure 58 (VCO divider not used). There is specified for the nondelayed output. This means that the delay an uncertainty of up to one cycle of the clock at the input to the function should be used primarily for clocking digital chips, channel divider due to the asynchronous nature of the SYNC such as FPGA, ASIC, DUC, and DDC. An output with this signal with respect to the clock edges inside the AD9516. The delay enabled may not be suitable for clocking data converters. delay from the SYNC rising edge to the beginning of synchronized The jitter is higher for long full scales because the delay block output clocking is between 14 and 15 cycles of clock at the uses a ramp and trip points to create the variable delay. A slower channel divider input, plus either one cycle of the VCO divider ramp time produces more time jitter. input (see Figure 57) or one cycle of the channel divider input Synchronizing the Outputs—SYNC Function (see Figure 58), depending on whether the VCO divider is used. The AD9516 clock outputs can be synchronized to each other. Cycles are counted from the rising edge of the signal. Outputs can be individually excluded from synchronization. Another common way to execute the SYNC function is by Synchronization consists of setting the nonexcluded outputs to setting and resetting the soft sync bit at Register 0x230[0] (see a preset set of static conditions and, subsequently, releasing Table 53 through Table 62 for details). Both setting and these outputs to continue clocking at the same instant with the resetting of the soft sync bit require an update all registers preset conditions applied. This allows for the alignment of the operation (Register 0x232[0] = 1) to take effect. edges of two or more outputs or for the spacing of edges, according to the coarse phase offset settings for two or more outputs. Rev. C | Page 46 of 80

Data Sheet AD9516-3 CHANNEL DIVIDER CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC OUTPUT CLOCKING INPUT TO VCO DIVIDER 1 INPUT TO CHANNEL DIVIDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT 06422-073 Figure 57. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input CHANNEL DIVIDER CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC OUTPUT CLOCKING INPUT TO CLK 1 INPUT TO CHANNEL DIVIDER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYNC PIN OUTPUT OF CHANNEL DIVIDER 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT 06422-074 Figure 58. SYNC Timing When VCO Divider Is Not Used—CLK Input Only A sync operation brings all outputs that have not been excluded Each channel (a divider and its outputs) can be excluded from (by the nosync bit) to a preset condition before allowing the any sync operation by setting the nosync bit of the channel. outputs to begin clocking in synchronicity. The preset condition Channels that are set to ignore SYNC (excluded channels) do takes into account the settings in each of the channel’s start high not set their outputs static during a sync operation, and their bit and its phase offset. These settings govern both the static outputs are not synchronized with those of the nonexcluded state of each output when the SYNC operation is happening and channels. the state and relative phase of the outputs when they begin Clock Outputs clocking again upon completion of the SYNC operation. The AD9516 offers three different output level choices: Between outputs and after synchronization, this allows for the LVPECL, LVDS, and CMOS. OUT0 to OUT5 are LVPECL setting of phase offsets. differential outputs; and OUT6 to OUT9 are LVDS/CMOS The AD9516 outputs are in pairs, sharing a channel divider per outputs. These outputs can be configured as either LVDS pair (two pairs of pairs, four outputs, in the case of CMOS). The differential or as pairs of single-ended CMOS outputs. synchronization conditions apply to both outputs of a pair. Rev. C | Page 47 of 80

AD9516-3 Data Sheet LVPECL Outputs—OUT0 to OUT5 3.5mA The LVPECL differential voltage (V ) is selectable from ~400 mV OD to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]). The LVPECL outputs have dedicated pins for power supply OUT (VS_LVPECL), allowing a separate power supply to be used. OUT V can be from 2.5 V to 3.3 V. S_LVPECL The LVPECL output polarity can be set as noninverting or ipnovlearrtiitny go,f w ohuitcphu tasl lwowiths ifno ra tnh aep apdljiucasttimonen wt iothf othuet rreelqautiivrein g a 3.5mA 06422-034 board layout change. Each LVPECL output can be powered Figure 60. LVDS Output Simplified Equivalent Circuit with 3.5 mA Typical Current Source down or powered up, as needed. Because of the architecture of the LVPECL output stages, there is the possibility of electrical Each LVDS/CMOS output can be powered down as needed to overstress and breakdown under certain power-down conditions. save power. The CMOS output power-down is controlled by the For this reason, the LVPECL outputs have several power-down same bit that controls the LVDS power-down for that output. modes. This includes a safe power-down mode that continues This power-down control affects both CMOS Output A and to protect the output devices while powered down, although it CMOS Output B. However, when CMOS Output A is powered up, consumes somewhat more power than a total power-down. If CMOS Output B can be powered on or off separately. the LVPECL output pins are terminated, it is best to select the VS safe power-down mode. If the pins are not connected (unused), it is acceptable to use the total power-down mode. 3.3V OUT1/ OUT1 06422-035 OUT Figure 61. CMOS Equivalent Output Circuit OUT RESET MODES The AD9516 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active. GND 06422-033 APopwpleier-dO n Reset—Start-Up Conditions When VS Is Figure 59. LVPECL Output Simplified Equivalent Circuit A power-on reset (POR) is issued when the V power supply is S LVDS/CMOS Outputs—OUT6 to OUT9 turned on. This initializes the chip to the power-on conditions OUT6 to OUT9 can be configured as either an LVDS that are determined by the default register settings. These are differential output or as a pair of CMOS single-ended outputs. indicated in the Default Value (Hex) column of Table 52. At The LVDS outputs allow for selectable output current from power-on, the AD9516 also executes a SYNC operation, which ~1.75 mA to ~7 mA. brings the outputs into phase alignment according to the default settings. The LVDS output polarity can be set as noninverting or Asynchronous Reset via the RESET Pin inverting, which allows for the adjustment of the relative polarity of outputs within an application without requiring a An asynchronous hard reset is executed by momentarily pulling board layout change. Each LVDS output can be powered down RESET low. A reset restores the chip registers to the default settings. if not needed to save power. Soft Reset via Register 0x000[2] OUT6 to OUT9 can also be CMOS outputs. Each LVDS output A soft reset is executed by writing Register 0x000[2] and can be configured to be two CMOS outputs. This provides for Register 0x000[5] = 1b. This bit is not self-clearing; it must be up to eight CMOS outputs: OUT6A, OUT6B, OUT7A, OUT7B, cleared by writing Register 0x000[2] and Register 0x000[5] = 0b to OUT8A, OUT8B, OUT9A, and OUT9B. When an output is reset it and complete the soft reset operation. A soft reset restores configured as CMOS, CMOS Output A is automatically turned on. the default values to the internal registers. The soft reset bit does CMOS Output B can be turned on or off independently. The not require an update registers command (Register 0x232) to be relative polarity of the CMOS outputs can also be selected for any issued. combination of inverting and noninverting (see Table 57 for Register 0x140[7:5], Register 0x141[7:5], Register 0x142[7:5], and Register 0x143[7:5]). Rev. C | Page 48 of 80

Data Sheet AD9516-3 POWER-DOWN MODES In asynchronous power-down mode, the device powers down Chip Power-Down via PD as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is The AD9516 can be put into a power-down condition by gated by the charge pump to prevent unwanted frequency pulling the PD pin low. Power-down turns off most of the jumps. The device goes into power-down on the occurrence functions and currents inside the AD9516. The chip remains in of the next charge pump event after the registers are updated. this power-down state until PD is brought back to logic high. Distribution Power-Down When the AD9516 wakes up, it returns to the settings programmed into its registers prior to the power-down, unless the registers The distribution section can be powered down by writing are changed by new programming while the PD pin is held low. Register 0x230[1] = 1b. This turns off the bias to the distribution section. If the LVPECL power-down mode is normal operation The PD power-down shuts down the currents on the chip, except (00b), it is possible for a low impedance load on that LVPECL the bias current that is necessary to maintain the LVPECL output to draw significant current during this power-down. outputs in a safe shutdown mode. This is needed to protect the If the LVPECL power-down mode is set to 11b, the LVPECL LVPECL output circuitry from damage that could be caused by output is not protected from reverse bias and may be damaged certain termination and load configurations when tristated. under certain termination conditions. Because this is not a complete power-down, it can be called sleep mode. Individual Clock Output Power-Down When the AD9516 is in a PD power-down, the chip is in the Any of the clock distribution outputs can be powered down following state: individually by writing to the appropriate registers. The register map details the individual power-down settings for each output • The PLL is off (asynchronous power-down). (see Table 52). The LVDS/CMOS outputs can be powered • The VCO is off. down, regardless of their output load configuration. • The CLK input buffer is off. The LVPECL outputs have multiple power-down modes • All dividers are off. (see Table 56), which give some flexibility in dealing with the • All LVDS/CMOS outputs are off. various output termination conditions. When the mode is set to • All LVPECL outputs are in safe off mode. 10b, the LVPECL output is protected from reverse bias to • The serial control port is active, and the chip responds 2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is to commands. not protected from reverse bias and can be damaged under If the AD9516 clock outputs must be synchronized to each certain termination conditions. This setting also affects the other, a SYNC is required upon exiting power-down (see the operation when the distribution block is powered down with Synchronizing the Outputs—SYNC Function section). A VCO Register 0x230[1] = 1b (see the Distribution Power-Down section). calibration is not required when exiting power-down. Individual Circuit Block Power-Down PLL Power-Down Other AD9516 circuit blocks (such as CLK, REF1, and REF2) The PLL section of the AD9516 can be selectively powered can be powered down individually. This gives flexibility in down. There are three PLL operating modes that are set by configuring the part for power savings whenever certain chip Register 0x010[1:0], as shown in Table 54. functions are not needed. Rev. C | Page 49 of 80

AD9516-3 Data Sheet SERIAL CONTROL PORT The AD9516 serial control port is a flexible, synchronous, serial During this period, the serial control port state machine enters communications port that allows an easy interface with many a wait state until all data is sent. If the system controller decides industry-standard microcontrollers and microprocessors. The to abort the transfer before all of the data is sent, the state machine AD9516 serial control port is compatible with most synchronous must be reset, either by completing the remaining transfers or transfer formats, including both the Motorola SPI® and Intel® by returning the CS low for at least one complete SCLK cycle SSR® protocols. The serial control port allows read/write access (but less than eight SCLK cycles). Raising the CS on a nonbyte to all registers that configure the AD9516. Single or multiple boundary terminates the serial transfer and flushes the buffer. byte transfers are supported, as well as MSB first or LSB first In the streaming mode (see Table 47), any number of data bytes transfer formats. The AD9516 serial control port can be can be transferred in a continuous stream. The register address configured for a single bidirectional I/O pin (SDIO only) or is automatically incremented or decremented (see the MSB/LSB for two unidirectional I/O pins (SDIO/SDO). By default, the First Transfers section). CS must be raised at the end of the last AD9516 is in bidirectional mode, long instruction (long byte to be transferred, thereby ending the stream mode. instruction is only instruction mode supported). Communication Cycle—Instruction Plus Data SERIAL CONTROL PORT PIN DESCRIPTIONS There are two parts to a communication cycle with the AD9516. SCLK (serial clock) is the serial shift clock. This pin is an input. The first part writes a 16-bit instruction word into the AD9516, SCLK is used to synchronize serial control port reads and coincident with the first 16 SCLK rising edges. The instruction writes. Write data bits are registered on the rising edge of this word provides the AD9516 serial control port with information clock, and read data bits are registered on the falling edge. This regarding the data transfer, which is the second part of the pin is internally pulled down by a 30 kΩ resistor to ground. communication cycle. The instruction word defines whether SDIO (serial data input/output) is a dual-purpose pin that acts the upcoming data transfer is a read or a write, the number of as either an input only (unidirectional mode) or as both an bytes in the data transfer, and the starting register address for input/output (bidirectional mode). The AD9516 defaults to the the first byte of the data transfer. bidirectional I/O mode (Register 0x000[0] = 0b). Write SDO (serial data out) is used only in the unidirectional I/O If the instruction word is for a write operation, the second part mode (Register 0x000[0] = 1b) as a separate output pin for is the transfer of data into the serial control port buffer of the reading back data. AD9516. Data bits are registered on the rising edge of SCLK. CS (chip select bar) is an active low control that gates the read The length of the transfer (1, 2, 3 bytes or streaming mode) is and write cycles. When CS is high, SDO and SDIO are in a high indicated by two bits ([W1:W0]) in the instruction byte. When impedance state. This pin is internally pulled up by a 30 kΩ the transfer is 1, 2, or 3 bytes, but not streaming, CS can be resistor to VS. raised after each sequence of eight bits to stall the bus (except after the last byte, where it ends the cycle). When the bus is SCLK 16 AD9516-3 stalled, the serial transfer resumes when CS is lowered. Raising CS CS 17 SSDDIOO 2212 CSOPENORTRIRATOLL 06422-036 owrenrg iaitse nt,e osrtnsr;be tyahtmee ribenofgou rmned,o atdhryee rdueosseeersts mn tohutes stsk ekirpnia oolw vceo trnh trere obslei tpr vpoeradtt.t eoDrrnu b rtlioann gwk ar ite Figure 62. Serial Control Port to the reserved registers to preserve proper operation of the part. GENERAL OPERATION OF SERIAL CONTROL PORT Refer to the register map (see Table 52) to determine if the default A write or a read operation to the AD9516 is initiated by pulling value for reserved registers is nonzero. It does not matter what data CS low. is written to blank registers. Because data is written into a serial control port buffer area, and CS stall high is supported in modes where three or fewer bytes not directly into the actual control registers of the AD9516, an of data (plus instruction data) are transferred (see Table 47). additional operation is needed to transfer the serial control port In these modes, CS can temporarily return high on any byte buffer contents to the actual control registers of the AD9516, boundary, allowing time for the system controller to process the thereby causing them to become active. The update registers next byte. CS can go high on byte boundaries only and can go operation consists of setting Register 0x232[0] = 1b (this bit is high during either part (instruction or data) of the transfer. self-clearing). Any number of bytes of data can be changed before executing an update registers. The update registers operation simultaneously actuates all register changes that have been written to the buffer since any previous update. Rev. C | Page 50 of 80

Data Sheet AD9516-3 Read The 13 bits found in [A12:A0] select the address within the register map that is written to or read from during the data If the instruction word is for a read operation, the next N × 8 transfer portion of the communications cycle. Only Bits[A9:A0] SCLK cycles clock out the data from the address specified in the are needed to cover the range of the 0x232 registers used by the instruction word, where N is 1 to 3 as determined by [W1:W0]. AD9516. Bits[A12:A10] must always be 0b. For multibyte If N = 4, the read operation is in streaming mode, continuing transfers, this address is the starting byte address. In MSB first until CS is raised. Streaming mode does not skip over reserved mode, subsequent bytes decrement the address. or blank registers. The readback data is valid on the falling edge of SCLK. MSB/LSB FIRST TRANSFERS The default mode of the AD9516 serial control port is the The AD9516 instruction word and byte data can be MSB first bidirectional mode. In bidirectional mode, both the sent data or LSB first. Any data written to Register 0x000 must be mirrored; and the readback data appear on the SDIO pin. It is also possible the upper four bits (Bits[7:4]) with the lower four bits (Bits[3:0]). to set the AD9516 to unidirectional mode via the SDO active bit This makes it irrelevant whether LSB first or MSB first is in (Register 0x000[0] = 1b). In unidirectional mode, the readback effect. As an example of this mirroring, see the default setting data appears on the SDO pin. for this register: 0x18, which mirrors Bit 4 and Bit 3. This sets the long instruction mode (which is the default and the only A readback request reads the data that is in the serial control mode that is supported). port buffer area, or the data that is in the active registers (see Figure 63). Readback of the buffer or active registers is controlled The default for the AD9516 is MSB first. by Register 0x004[0]. When LSB first is set by Register 0x000[1] and Register 0x000[6], The AD9516 supports only the long instruction mode, therefore it takes effect immediately because it affects only the operation Register 0x000[4:3] must be set to 11b. (This register uses mirrored of the serial control port and does not require that an update bits). Long instruction mode is the default at power-up or reset. be executed. The AD9516 uses Register Address 0x000 to Register When MSB first mode is active, the instruction and data bytes Address 0x232. must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the RS RS register address of the most significant data byte. Subsequent SSCDLIOK GISTE GISTE data bytes must follow, in order, from the high address to the SDCOS SCEORNITARLOL BUFFER RE REUGPIDSATTEERS ACTIVE RE lamodwudl rtaeidbsdys trgeee stnsre.a rInanst foMerr S dcBey ccfrileres.m t menotsd efo, rt heea csher diaalt ac obnyttreo ol fp tohret internal PORT WTOR IUTDEA RTEEG RISETGEISRT 0ExR2S32 = 0x01 06422-037 Wwrhitetenn L fSrBom fir LstS Bis taoc tMivSe,B t.h Me uinltsitbryutcet idoant aa ntrda ndsaftear sb yinte Ls SmBu fsirt sbt e Figure 63. Relationship Between Serial Control Port Buffer Registers and format start with an instruction byte that includes the register Active Registers of the AD9516 address of the least significant data byte followed by multiple THE INSTRUCTION WORD (16 BITS) data bytes. The internal byte address generator of the serial control port increments for each byte of the multibyte The MSB of the instruction word is R/W, which indicates transfer cycle. whether the instruction is a read or a write. The next two bits, [W1:W0], indicate the length of the transfer in bytes. The final The AD9516 serial control port register address decrements from 13 bits are the address ([A12:A0]) at which to begin the read or the register address just written toward 0x000 for multibyte I/O write operation. operations if the MSB first mode is active (default). If the LSB first mode is active, the register address of the serial control port For a write, the instruction word is followed by the number of increments from the address just written toward Address 0x232 bytes of data indicated by Bits[W1:W0] (see Table 47). for multibyte I/O operations. Table 47. Byte Transfer Count Streaming mode always terminates when it hits Address 0x232. W1 W0 Bytes to Transfer Note that unused addresses are not skipped during multibyte 0 0 1 I/O operations. 0 1 2 1 0 3 Table 48. Streaming Mode (No Addresses Are Skipped) 1 1 Streaming mode Write Mode Address Direction Stop Sequence LSB first Increment 0x230, 0x231, 0x232, stop MSB first Decrement 0x001, 0x000, 0x232, stop Rev. C | Page 51 of 80

AD9516-3 Data Sheet Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLKDON'T CARE DON'T CARE SDIODON'T CARE R/W W1 W0 A12A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA 06422-038 Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data CS SCLK DON’T CARE DON’T CARE SDIO R/WW1W0A12A11A10A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDO DON’T CARE D7 D6 D5D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5D4 D3 D2 D1 D0 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA DCOANR’ET 06422-039 Figure 65. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data tDS tHI CS tS tDH tLO tCLK tC SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 06422-040 Figure 66. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements CS SCLK tDV SSDDIOO DATABITN DATABITN–1 06422-041 Figure 67. Timing Diagram for Serial Control Port Register Read CS SCLKDON'T CARE DON'T CARE SDIODON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10A11A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA 06422-042 Figure 68. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data Rev. C | Page 52 of 80

Data Sheet AD9516-3 tS tC CS tCLK tHI tLO SCLK tDS tDH SDIO BIT N BIT N + 1 06422-043 Figure 69. Serial Control Port Timing—Write Table 50. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between CS falling edge and SCLK rising edge (start of communication cycle) S t Setup time between SCLK rising edge and CS rising edge (end of communication cycle) C t Minimum period that SCLK should be in a logic high state HIGH t Minimum period that SCLK should be in a logic low state LOW t SCLK to valid SDIO and SDO (see Figure 67) DV Rev. C | Page 53 of 80

AD9516-3 Data Sheet THERMAL PERFORMANCE Table 51. Thermal Parameters for the 64-Lead LFCSP Symbol Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board Value (°C/W) θ Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air) 22.0 JA θ Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) 19.2 JMA θ Junction-to-ambient thermal resistance, 2.0 m/sec airflow per JEDEC JESD51-6 (moving air) 17.2 JMA Ψ Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) 11.6 JB and JEDEC JESD51-8 θ Junction-to-case thermal resistance (die-to-heat sink) per MIL-STD-883, Method 1012.1 1.3 JC Ψ Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air) 0.1 JT The AD9516 is specified for a case temperature (T ). To ensure Values of θ are provided for package comparison and PCB CASE JA that T is not exceeded, an airflow source can be used. design considerations. θ can be used for a first-order CASE JA approximation of T by the following equation: Use the following equation to determine the junction J temperature on the application PCB: T = T + (θ × PD) J A JA TJ = TCASE + (ΨJT × PD) where TA is the ambient temperature (°C). where: Values of θ are provided for package comparison and PCB JC T is the junction temperature (°C). design considerations when an external heat sink is required. J T is the case temperature (°C) measured by the user at the CASE Values of Ψ are provided for package comparison and PCB JB top center of the package. design considerations. Ψ is the value from Table 51. JT PD is the power dissipation of the device (see Table 17). Rev. C | Page 54 of 80

Data Sheet AD9516-3 REGISTER MAP OVERVIEW Table 52. Register Map Overview Reg. Default Addr. Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) Serial Port Configuration 0x000 Serial port SDO LSB first Soft reset Long Long Soft reset LSB first SDO active 0x18 configuration active instruction instruction 0x001 Blank 0x002 Reserved 0x003 Part ID Part ID (read only) 0x01 0x004 Readback Blank Read back 0x00 control active registers PLL 0x010 PFD and PFD Charge pump current Charge pump mode PLL power-down 0x7D charge pump polarity 0x011 R counter 14-bit R divider, Bits[7:0] (LSB) 0x01 0x012 Blank 14-bit R divider, Bits[13:8] (MSB) 0x00 0x013 A counter Blank 6-bit A counter 0x00 0x014 B counter 13-bit B counter, Bits[7:0] (LSB) 0x03 0x015 Blank 13-bit B counter, Bits[12:8] (MSB) 0x00 0x016 PLL Control 1 Set CP pin Reset R Reset A and Reset all B counter Prescaler P 0x06 to VCP/2 counter B counters counters bypass 0x017 PLL Control 2 STATUS pin control Antibacklash pulse width 0x00 0x018 PLL Control 3 Reserved Lock detect counter Digital lock Disable VCO calibration divider VCO cal now 0x06 detect digital lock window detect 0x019 PLL Control 4 R, A, B counters SYNC R path delay N path delay 0x00 pin reset 0x01A PLL Control 5 Reserved Reference LD pin control 0x00 frequency monitor threshold 0x01B PLL Control 6 VCO REF2 REF1 (REFIN) REFMON pin control 0x00 frequency (REFIN) frequency monitor frequency monitor monitor 0x01C PLL Control 7 Disable Select Use Reserved Reserved REF2 REF1 Differential 0x00 switchover REF2 REF_SEL pin power-on power-on reference deglitch 0x01D PLL Control 8 Reserved PLL status LD pin Holdover External Holdover 0x00 register comparator enable holdover enable disable enable control 0x01E PLL Control 9 Reserved 0x00 0x01F PLL readback Reserved VCO cal Holdover REF2 VCO REF2 REF1 Digital N/A finished active selected frequency > frequency > frequency > lock detect threshold threshold threshold 0x020 Blank to 0x04F Rev. C | Page 55 of 80

AD9516-3 Data Sheet Reg. Default Addr. Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) Fine Delay Adjust—OUT6 to OUT9 0x0A0 OUT6 delay Blank OUT6 delay 0x01 bypass bypass 0x0A1 OUT6 delay Blank OUT6 ramp capacitors OUT6 ramp current 0x00 full-scale 0x0A2 OUT6 delay Blank OUT6 delay fraction 0x00 fraction 0x0A3 OUT7 delay Blank OUT7 delay 0x01 bypass bypass 0x0A4 OUT7 delay Blank OUT7 ramp capacitors OUT7 ramp current 0x00 full-scale 0x0A5 OUT7 delay Blank OUT7 delay fraction 0x00 fraction 0x0A6 OUT8 delay Blank OUT8 delay 0x01 bypass bypass 0x0A7 OUT8 delay Blank OUT8 ramp capacitors OUT8 ramp current 0x00 full-scale 0x0A8 OUT8 delay Blank OUT8 delay fraction 0x00 fraction 0x0A9 OUT9 delay Blank OUT9 delay 0x01 bypass bypass 0x0AA OUT9 delay Blank OUT9 ramp capacitors OUT9 ramp current 0x00 full-scale 0x0AB OUT9 delay Blank OUT9 delay fraction 0x00 fraction 0x0AC Blank to 0x0EF LVPECL Outputs 0x0F0 OUT0 Blank OUT0 OUT0 LVPECL OUT0 power-down 0x08 invert differential voltage 0x0F1 OUT1 Blank OUT1 OUT1 LVPECL OUT1 power-down 0x0A invert differential voltage 0x0F2 OUT2 Blank OUT2 OUT2 LVPECL OUT2 power-down 0x08 invert differential voltage 0x0F3 OUT3 Blank OUT3 OUT3 LVPECL OUT3 power-down 0x0A invert differential voltage 0x0F4 OUT4 Blank OUT4 OUT4 LVPECL OUT4 power-down 0x08 invert differential voltage 0x0F5 OUT5 Blank OUT5 OUT5 LVPECL OUT5 power-down 0x0A invert differential voltage 0x0F6 Blank to 0x13F LVDS/CMOS Outputs 0x140 OUT6 OUT6 CMOS OUT6 LVDS/ OUT6 OUT6 select OUT6 LVDS OUT6 0x42 output polarity CMOS CMOS B LVDS/CMOS output current power-down output polarity 0x141 OUT7 OUT7 CMOS OUT7 LVDS/ OUT7 OUT7 select OUT7 LVDS OUT7 0x43 output polarity CMOS CMOS B LVDS/CMOS output current power-down output polarity 0x142 OUT8 OUT8 CMOS OUT8 LVDS/ OUT8 OUT8 select OUT8 LVDS OUT8 0x42 output polarity CMOS CMOS B LVDS/CMOS output current power-down output polarity 0x143 OUT9 OUT9 CMOS OUT9 LVDS/ OUT9 OUT9 select OUT9 LVDS OUT9 0x43 output polarity CMOS CMOS B LVDS/CMOS output current power-down output polarity Rev. C | Page 56 of 80

Data Sheet AD9516-3 Reg. Default Addr. Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) 0x144 Blank to 0x18F LVPECL Channel Dividers 0x190 Divider 0 Divider 0 low cycles Divider 0 high cycles 0x00 (PECL) 0x191 Divider 0 Divider 0 Divider 0 Divider 0 Divider 0 phase offset 0x80 bypass no sync force high start high 0x192 Blank Reserved Divider 0 Divider 0 0x00 direct to DCCOFF output 0x193 Divider 1 Divider 1 low cycles Divider 1 high cycles 0xBB (PECL) 0x194 Divider 1 Divider 1 Divider 1 Divider 1 Divider 1 phase offset 0x00 bypass no sync force high start high 0x195 Blank Reserved Divider 1 Divider 1 0x00 direct to DCCOFF output 0x196 Divider 2 Divider 2 low cycles Divider 2 high cycles 0x00 (PECL) 0x197 Divider 2 Divider 2 Divider 2 Divider 2 Divider 2 phase offset 0x00 bypass no sync force high start high 0x198 Blank Reserved Divider 2 Divider 2 0x00 direct to DCCOFF output LVDS/CMOS Channel Dividers 0x199 Divider 3 Low Cycles Divider 3.1 High Cycles Divider 3.1 0x22 (LVDS/CMOS) 0x19A Phase Offset Divider 3.2 Phase Offset Divider 3.1 0x00 0x19B Low Cycles Divider 3.2 High Cycles Divider 3.2 0x11 0x19C Reserved Bypass Bypass Divider 3 Divider 3 Start High Start High 0x00 Divider 3.2 Divider 3.1 no sync force high Divider 3.2 Divider 3.1 0x19D Blank Reserved Divider 3 0x00 DCCOFF 0x19E Divider 4 Low Cycles Divider 4.1 High Cycles Divider 4.1 0x22 (LVDS/CMOS) 0x19F Phase Offset Divider 4.2 Phase Offset Divider 4.1 0x00 0x1A0 Low Cycles Divider 4.2 High Cycles Divider 4.2 0x11 0x1A1 Reserved Bypass Bypass Divider 4 Divider 4 Start High Start High 0x00 Divider 4.2 Divider 4.1 no sync force high Divider 4.2 Divider 4.1 0x1A2 Blank Reserved Divider 4 0x00 DCCOFF 0x1A3 Reserved 0x1A4 Blank to 0x1DF VCO Divider and CLK Input 0x1E0 VCO divider Blank Reserved VCO Divider 0x02 0x1E1 Input CLKs Reserved Power- Power-down Power- Select Bypass VCO 0x00 down VCO clock down VCO VCO or CLK divider clock input interface and CLK section 0x1E2 Blank to 0x22A Rev. C | Page 57 of 80

AD9516-3 Data Sheet Reg. Default Addr. Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex) System 0x230 Power-down Reserved Power- Power- Soft sync 0x00 and sync down sync down distribution reference 0x231 Blank Reserved 0x00 Update All Registers 0x232 Update all Blank Update all 0x00 registers registers (self- clearing bit) Rev. C | Page 58 of 80

Data Sheet AD9516-3 REGISTER MAP DESCRIPTIONS Table 53 through Table 62 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2]. Table 53. Serial Port Configuration Reg. Addr (Hex) Bits Name Description 0x000 [7:4] Mirrored, Bits[3:0] Bits[7:4] should always mirror Bits[3:0] so that it does not matter whether the part is in MSB or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows: Bit 7 = Bit 0. Bit 6 = Bit 1. Bit 5 = Bit 2. Bit 4 = Bit 3. 3 Long instruction Short/long instruction mode. This part uses long instruction mode only, so this bit should always be set to 1. 0: 8-bit instruction (short). 1: 16-bit instruction (long) (default). 2 Soft reset Soft reset. 1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to 0 to complete reset operation. 1 LSB first MSB or LSB data orientation. 0: data-oriented MSB first; addressing decrements (default). 1: data-oriented LSB first; addressing increments. 0 SDO active Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default). 1: SDO used for read, SDIO used for write; unidirectional mode. 0x003 [7:0] Part ID (read only) Uniquely identifies the dash version (-0 through -4) of the AD9516. AD9516-0: 0x01. AD9516-1: 0x41. AD9516-2: 0x81. AD9516-3: 0x43. AD9516-4: 0xC3. 0x004 0 Read back active registers Selects register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers. Rev. C | Page 59 of 80

AD9516-3 Data Sheet Table 54. PLL Reg. Addr. (Hex) Bits Name Description 0x010 7 PFD polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity; Bit 7 = 0. 0: positive; higher control voltage produces higher frequency (default). 1: negative; higher control voltage produces lower frequency. [6:4] CP current Charge pump current (with CPRSET = 5.1 kΩ). 6 5 4 ICP (mA) 0 0 0 0.6 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 (default) [3:2] CP mode Charge pump operating mode. 3 2 Charge Pump Mode 0 0 High impedance state. 0 1 Force source current (pump up). 1 0 Force sink current (pump down). 1 1 Normal operation (default). [1:0] PLL power-down PLL operating mode. 1 0 Mode 0 0 Normal operation. 0 1 Asynchronous power-down (default). 1 0 Normal operation. 1 1 Synchronous power-down. 0x011 [7:0] 14-bit R divider, R divider LSBs—lower eight bits (default = 0x01). Bits[7:0] (LSB) 0x012 [5:0] 14-bit R divider, R divider MSBs—upper six bits (default = 0x00). Bits[13:8] (MSB) 0x013 [5:0] 6-bit A counter A counter (part of N divider) (default = 0x00). 0x014 [7:0] 13-bit B counter, B counter (part of N divider)—lower eight bits (default = 0x03). Bits[7:0] (LSB) 0x015 [4:0] 13-bit B counter, B counter (part of N divider)—upper five bits (default = 0x00). Bits[12:8] (MSB) 0x016 7 Set CP pin to VCP/2 Sets the CP pin to one-half of the VCP supply voltage. 0: CP normal operation (default). 1: CP pin set to VCP/2. 6 Reset R counter Resets R counter (R divider). 0: normal (default). 1: holds the R counter in reset. 5 Reset A, B counters Resets A and B counters (part of N divider). 0: normal (default). 1: holds the A and B counters in reset. 4 Reset all counters Resets R, A, and B counters. 0: normal (default). 1: holds the R, A, and B counters in reset. 3 B counter B counter bypass. This is valid only when operating the prescaler in FD mode. bypass 0: normal (default). 1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. Rev. C | Page 60 of 80

Data Sheet AD9516-3 Reg. Addr. (Hex) Bits Name Description 0x016 [2:0] Prescaler P Prescaler: DM = dual modulus, and FD = fixed divide. 2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 (2/3 mode). 0 1 1 DM Divide-by-4 (4/5 mode). 1 0 0 DM Divide-by-8 (8/9 mode). 1 0 1 DM Divide-by-16 (16/17 mode). 1 1 0 DM Divide-by-32 (32/33 mode) (default). 1 1 1 FD Divide-by-3. 0x017 [7:2] STATUS pin Selects the signal that is connected to the STATUS pin. control Level or Dynamic 7 6 5 4 3 2 Signal Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground (dc) (default). 0 0 0 0 0 1 DYN N divider output (after the delay). 0 0 0 0 1 0 DYN R divider output (after the delay). 0 0 0 0 1 1 DYN A divider output. 0 0 0 1 0 0 DYN Prescaler output. 0 0 0 1 0 1 DYN PFD up pulse. 0 0 0 1 1 0 DYN PFD down pulse. 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified above. The selections that follow are the same as REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency (active high). 1 0 1 0 0 0 LVL Status REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL Digital lock detect (DLD); active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL LD pin comparator output (active high). 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL Digital lock detect (DLD) (active low). 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL LD pin comparator output (active low). Rev. C | Page 61 of 80

AD9516-3 Data Sheet Reg. Addr. (Hex) Bits Name Description 0x017 [1:0] Antibacklash 1 0 Antibacklash Pulse Width (ns) pulse width 0 0 2.9 (default). 0 1 1.3. 1 0 6.0. 1 1 2.9. 0x018 [6:5] Lock detect Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked counter condition. 6 5 PFD Cycles to Determine Lock 0 0 5 (default). 0 1 16. 1 0 64. 1 1 255. 4 Digital lock detect If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock window detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. 0: high range (default). 1: low range. 3 Disable digital Digital lock detect operation. lock detect 0: normal lock detect operation (default). 1: disables lock detect. [2:1] VCO cal VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock. divider 2 1 VCO Calibration Clock Divider 0 0 2. 0 1 4. 1 0 8. 1 1 16 (default). [0] VCO cal now Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. To initiate calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0 (if not zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1, followed by another update bit (Register 0x232, Bit 0). 0x019 [7:6] R, A, B counters 7 6 Action SYNC pin reset 0 0 Does nothing on SYNC (default). 0 1 Asynchronous reset. 1 0 Synchronous reset. 1 1 Does nothing on SYNC. [5:3] R path delay R path delay (default = 0x00) (see Table 2). [2:0] N path delay N path delay (default = 0x00) (see Table 2). 0x01A [6] Reference Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO frequency monitor frequency monitor’s detection threshold (see Table 16: REF1, REF2, and VCO Frequency Status Monitor parameter). threshold 0: frequency valid if frequency is above the higher frequency threshold (default). 1: frequency valid if frequency is above the lower frequency threshold. Rev. C | Page 62 of 80

Data Sheet AD9516-3 Reg. Addr. (Hex) Bits Name Description 0x01A [5:0] LD pin control Selects the signal that is connected to the LD pin. Level or Dynamic 5 4 3 2 1 0 Signal Signal at LD Pin 0 0 0 0 0 0 LVL Digital lock detect (high = lock, low = unlock) (default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ High-Z LD pin. 0 0 0 1 0 0 CUR Current source lock detect (110 µA when DLD is true). 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified above. The selections that follow are the same as REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when indifferential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency (active high). 1 0 1 0 0 0 LVL Status REF2 frequency (active high). 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL Digital lock detect (DLD); active high. 1 0 1 1 1 0 LVL Holdover active (active high). 1 0 1 1 1 1 LVL Not available. Do not use. 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 1 0 0 1 LVL (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 1 0 1 LVL Digital lock detect (DLD); active low. 1 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 1 LVL Not available. Do not use. 0x01B 7 VCO frequency Enables or disables VCO frequency monitor. monitor 0: disables VCO frequency monitor (default). 1: enables VCO frequency monitor. 6 REF2 (REFIN) Enables or disables REF2 frequency monitor. frequency monitor 0: disables REF2 frequency monitor (default). 1: enables REF2 frequency monitor. 5 REF1 (REFIN) REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs frequency monitor (as selected by differential reference mode). 0: disables REF1 (REFIN) frequency monitor (default). 1: enables REF1 (REFIN) frequency monitor. Rev. C | Page 63 of 80

AD9516-3 Data Sheet Reg. Addr. (Hex) Bits Name Description 0x01B [4:0] REFMON Selects the signal that is connected to the REFMON pin. pin control Level or Dynamic 4 3 2 1 0 Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground (dc) (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 LVL Status REF1 frequency (active high). 0 1 0 0 0 LVL Status REF2 frequency (active high). 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 0 1 0 1 1 LVL Status of VCO frequency (active high). 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 0 1 1 0 1 LVL Digital lock detect (DLD); active low. 0 1 1 1 0 LVL Holdover active (active high). 0 1 1 1 1 LVL LD pin comparator output (active high). 1 0 0 0 0 LVL VS (PLL supply). 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 0 1 0 1 LVL Status of selected reference (status of differential reference); active low. 1 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active low. 1 0 1 1 1 LVL Status of REF1 frequency (active low). 1 1 0 0 0 LVL Status of REF2 frequency (active low). 1 1 0 0 1 LVL (Status of REF1 frequency) AND (Status of REF2 frequency). 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (Status of VCO). 1 1 0 1 1 LVL Status of VCO frequency (active low). 1 1 1 0 0 LVL Selected reference (low = REF2, high = REF1). 1 1 1 0 1 LVL Digital lock detect (DLD); active low. 1 1 1 1 0 LVL Holdover active (active low). 1 1 1 1 1 LVL LD pin comparator output (active low). 0x01C 7 Disable Disables or enables the switchover deglitch circuit. switchover 0: enables switchover deglitch circuit (default). deglitch 1: disables switchover deglitch circuit. 6 Select REF2 If Register 0x01C, Bit 5 = 0, select reference for PLL. 0: selects REF1 (default). 1: selects REF2. 5 Use REF_SEL pin Sets method of PLL reference selection. 0: uses Register 0x01C, Bit 6 (default). 1: uses REF_SEL pin. 4 Reserved 0: (default). 3 Reserved 0: (default). 2 REF2 power-on This bit turns the REF2 power on. 0: REF2 power off (default). 1: REF2 power on. 1 REF1 power-on This bit turns the REF1 power on. 0: REF1 power off (default). 1: REF1 power on. 0 Differential Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic reference switchover or REF1 and REF2 to work. 0: single-ended reference mode (default). 1: differential reference mode. Rev. C | Page 64 of 80

Data Sheet AD9516-3 Reg. Addr. (Hex) Bits Name Description 0x01D 4 PLL status Disables the PLL status register readback. register disable 0: PLL status register enable (default). 1: PLL status register disable. 3 LD pin comparator Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When enable in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 53). Otherwise, this function can be used with the REFMON and STATUS pins to monitor the voltage on this pin. 0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default). 1: enables LD pin comparator. 2 Holdover enable Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration. 0: holdover disabled (default). 1: holdover enabled. 1 External Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.) holdover control 0: automatic holdover mode—holdover controlled by automatic holdover circuit. (default) 1: external holdover mode—holdover controlled by SYNC pin. 0 Holdover enable Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration. 0: holdover disabled (default). 1: holdover enabled. 0x01F 6 VCO cal finished Read-only register. Indicates status of the VCO calibration. 0: VCO calibration not finished. 1: VCO calibration finished. 5 Holdover active Read-only register. Indicates if the part is in the holdover state (see Figure 53). This is not the same as holdover enabled. 0: not in holdover. 1: holdover state active. 4 REF2 selected Read-only register. Indicates which PLL reference is selected as the input to the PLL. 0: REF1 selected (or differential reference if in differential mode). 1: REF2 selected. 3 VCO frequency > Read-only register. Indicates if the VCO frequency is greater than the threshold (see Table 16, REF1, REF2, and VCO threshold frequency status monitor). 0: VCO frequency is less than the threshold. 1: VCO frequency is greater than the threshold. 2 REF2 frequency > Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by threshold Register 0x01A, Bit 6. 0: REF2 frequency is less than threshold frequency. 1: REF2 frequency is greater than threshold frequency. 1 REF1 frequency > Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency threshold set by Register 0x01A, Bit 6. 0: REF1 frequency is less than threshold frequency. 1: REF1 frequency is greater than threshold frequency. 0 Digital lock detect Read-only register. Digital lock detect. 0: PLL is not locked. 1: PLL is locked. Rev. C | Page 65 of 80

AD9516-3 Data Sheet Table 55. Fine Delay Adjust—OUT6 to OUT9 Reg. Addr. (Hex) Bits Name Description 0x0A0 0 OUT6 delay bypass Bypasses or uses the delay function. 0: uses delay function. 1: bypasses delay function (default). 0x0A1 [5:3] OUT6 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the number of the capacitors and the ramp current sets the delay full scale. 5 4 3 Number of Capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0] OUT6 ramp current Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 2 1 0 Current (µA) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0A2 [5:0] OUT6 delay fraction Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000 gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00). 0x0A3 0 OUT7 delay bypass Bypasses or uses the delay function. 0: use delay function. 1: bypass delay function (default). 0x0A4 [5:3] OUT7 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the number of the capacitors and the ramp current sets the delay full scale. 5 4 3 Number of Capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 Rev. C | Page 66 of 80

Data Sheet AD9516-3 Reg. Addr. (Hex) Bits Name Description 0x0A4 [2:0] OUT7 ramp current Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 2 1 0 Current (µA) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0A5 [5:0] OUT7 delay fraction Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000 gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00). 0x0A6 0 OUT8 delay bypass Bypasses or uses the delay function. 0: uses delay function. 1: bypasses delay function (default). 0x0A7 [5:3] OUT8 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 5 4 3 Number of Capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0] OUT8 ramp current Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 2 1 0 Current (µA) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0A8 [5:0] OUT8 delay fraction Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000 gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00). Rev. C | Page 67 of 80

AD9516-3 Data Sheet Reg. Addr. (Hex) Bits Name Description 0x0A9 0 OUT9 delay bypass Bypasses or uses the delay function. 0: uses delay function. 1: bypasses delay function (default). 0x0AA [5:3] OUT9 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 5 4 3 Number of Capacitors 0 0 0 4 (default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 [2:0] OUT9 ramp current Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. 2 1 0 Current Value (µA) 0 0 0 200 (default) 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 0x0AB [5:0] OUT9 delay fraction Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000 gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00). Table 56. LVPECL Outputs Reg. Addr. (Hex) Bits Name Description 0x0F0 4 OUT0 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT0 LVPECL Sets the LVPECL output differential voltage (V ). OD differential voltage 3 2 V (mV) OD 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT0 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation (default). On 0 1 Partial power-down, reference on; use only if there are no external Off load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. Off 1 1 Total power-down, reference off; use only if there are no external Off load resistors. Rev. C | Page 68 of 80

Data Sheet AD9516-3 Reg. Addr. (Hex) Bits Name Description 0x0F1 4 OUT1 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT1 LVPECL Sets the LVPECL output differential voltage (V ). OD differential voltage 3 2 V (mV) OD 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT1 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation. On 0 1 Partial power-down, reference on; use only if there are no external load Off resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down (default). Off 1 1 Total power-down, reference off; use only if there are no external load Off resistors. 0x0F2 4 OUT2 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT2 LVPECL Sets the LVPECL output differential voltage (V ). OD differential voltage 3 2 V (mV) OD 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT2 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation (default). On 0 1 Partial power-down, reference on; use only if there are no external load Off resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. Off 1 1 Total power-down, reference off; use only if there are no external load Off resistors. 0x0F3 4 OUT3 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT3 LVPECL Sets the LVPECL output differential voltage (V ). OD differential voltage 3 2 V (mV) OD 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT3 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation. On 0 1 Partial power-down, reference on; use only if there are no external Off load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down (default). Off 1 1 Total power-down, reference off; use only if there are no external Off load resistors. Rev. C | Page 69 of 80

AD9516-3 Data Sheet Reg. Addr. (Hex) Bits Name Description 0x0F4 4 OUT4 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT4 LVPECL Sets the LVPECL output differential voltage (V ). OD differential voltage 3 2 V (mV) OD 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT4 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation (default). On 0 1 Partial power-down, reference on; use only if there are no external load Off resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. Off 1 1 Total power-down, reference off; use only if there are no external load Off resistors. 0x0F5 4 OUT5 invert Sets the output polarity. 0: noninverting (default). 1: inverting. [3:2] OUT5 LVPECL Sets the LVPECL output differential voltage (V ). OD differential voltage 3 2 V (mV) OD 0 0 400 0 1 600 1 0 780 (default) 1 1 960 [1:0] OUT5 power-down LVPECL power-down modes. 1 0 Mode Output 0 0 Normal operation. On 0 1 Partial power-down, reference on; use only if there are no external load Off resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down (default). Off 1 1 Total power-down, reference off; use only if there are no external load Off resistors. Rev. C | Page 70 of 80

Data Sheet AD9516-3 Table 57. LVDS/CMOS Outputs Reg. Addr. (Hex) Bits Name Description 0x140 [7:5] OUT6 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity. 7 6 5 OUT4A (CMOS) OUT4B (CMOS) OUT4 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT6 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT6 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS. [2:1] OUT6 LVDS output current Set output current level in LVDS mode. This has no effect in CMOS mode. 2 1 Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 0 OUT6 power-down Power-down output (LVDS/CMOS). 0: power on (default). 1: power off. 0x141 [7:5] OUT7 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity. 7 6 5 OUT5A (CMOS) OUT5B (CMOS) OUT5 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT7 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode. 0: turns off the CMOS B output (default). 1: turns on the CMOS B output. 3 OUT7 select LVDS/CMOS Select LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS. [2:1] OUT7 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode. 2 1 Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 Rev. C | Page 71 of 80

AD9516-3 Data Sheet Reg. Addr. (Hex) Bits Name Description 0x141 0 OUT7 power-down Power-down output (LVDS/CMOS). 0: power on. 1: power off (default). 0x142 [7:5] OUT8 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity. 7 6 5 OUT6A (CMOS) OUT6B (CMOS) OUT6 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT8 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode. 0: turn off the CMOS B output (default). 1: turn on the CMOS B output. 3 OUT8 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS. [2:1] OUT8 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode. 2 1 Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 0 OUT8 power-down Power-down output (LVDS/CMOS). 0: power on (default). 1: power off. 0x143 [7:5] OUT9 output polarity In CMOS mode, Bits[7:5] select the output polarity of each CMOS output. In LVDS mode, only Bit 5 determines LVDS polarity. 7 6 5 OUT7A (CMOS) OUT7B (CMOS) OUT7 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting (default) 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT9 CMOS B In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode. 0: turn off the CMOS B output (default). 1: turn on the CMOS B output. 3 OUT9 select LVDS/CMOS Selects LVDS or CMOS logic levels. 0: LVDS (default). 1: CMOS. Rev. C | Page 72 of 80

Data Sheet AD9516-3 Reg. Addr. (Hex) Bits Name Description 0x143 [2:1] OUT9 LVDS output current Sets output current level in LVDS mode. This has no effect in CMOS mode. 2 1 Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 (default) 1 0 5.25 50 1 1 7 50 0 OUT9 power-down Power-down output (LVDS/CMOS). 0: power on. 1: power off (default). Table 58. LVPECL Channel Dividers Reg. Addr. (Hex) Bits Name Description 0x190 [7:4] Divider 0 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] Divider 0 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x191 7 Divider 0 bypass Bypasses and powers down the divider; routes input to divider output. 0: uses divider. 1: bypasses divider (default). 6 Divider 0 nosync Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 5 Divider 0 force high Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. 4 Divider 0 start high Selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] Divider 0 phase offset Phase offset (default = 0x0). 0x192 1 Divider 0 direct to output Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK. 0: OUT0 and OUT1 are connected to Divider 0 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1. If Register 0x1E1[1:0] = 01b, there is no effect. 0 Divider 0 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x193 [7:4] Divider 1 low cycles Number of clock cycles of the divider input during which divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] Divider 1 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x194 7 Divider 1 bypass Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: bypasses divider. 6 Divider 1 nosync Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 5 Divider 1 force high Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. Rev. C | Page 73 of 80

AD9516-3 Data Sheet Reg. Addr. (Hex) Bits Name Description 0x194 4 Divider 1 start high Selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] Divider 1 phase offset Phase offset (default = 0x0). 0x195 1 Divider 1 direct to output Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK. 0: OUT2 and OUT3 are connected to Divider 1 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3. If Register 0x1E1[1:0] = 01b, there is no effect. 0 Divider 1 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x196 [7:4] Divider 2 low cycles Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] Divider 2 high cycles Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x197 7 Divider 2 bypass Bypasses and powers down the divider; routes input to divider output. 0: uses divider. 1: bypasses divider (default). 6 Divider 2 nosync Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 5 Divider 2 force high Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. 4 Divider 2 start high Selects clock output to start high or start low. 0: starts low (default). 1: starts high. [3:0] Divider 2 phase offset Phase offset (default = 0x0). 0x198 1 Divider 2 direct to output Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK. 0: OUT4 and OUT5 are connected to Divider 2 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5. If Register 0x1E1[1:0] = 01b, there is no effect. 0 Divider 2 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Table 59. LVDS/CMOS Channel Dividers Reg. Addr. (Hex) Bits Name Description 0x199 [7:4] Low Cycles Divider 3.1 Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] High Cycles Divider 3.1 Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x19A [7:4] Phase Offset Divider 3.2 Refer to LVDS/CMOS channel divider function description (default = 0x0). [3:0] Phase Offset Divider 3.1 Refer to LVDS/CMOS channel divider function description (default = 0x0). 0x19B [7:4] Low Cycles Divider 3.2 Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] High Cycles Divider 3.2 Number of clock cycles (minus 1)of 3.2 divider input during which 3.2 output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). Rev. C | Page 74 of 80

Data Sheet AD9516-3 Reg. Addr. (Hex) Bits Name Description 0x19C 5 Bypass Divider 3.2 Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output. 0: does not bypass (default). 1: bypasses. 4 Bypass Divider 3.1 Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output. 0: does not bypass 3.1 divider logic (default). 1: bypasses 3.1 divider logic. 3 Divider 3 nosync Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 2 Divider 3 force high Force Divider 3 output high. Requires that nosync also be set. 0: forces low (default). 1: forces high. 1 Start High Divider 3.2 Divider 3.2 starts high/low. 0: starts low (default). 1: starts high. 0 Start High Divider 3.1 Divider 3.1 starts high/low. 0: starts low (default). 1: starts high. 0x19D 0 Divider 3 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. 0x19E [7:4] Low Cycles Divider 4.1 Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] High Cycles Divider 4.1 Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x19F [7:4] Phase Offset Divider 4.2 Refer to LVDS/CMOS channel divider function description (default = 0x0). [3:0] Phase Offset Divider 4.1 Refer to LVDS/CMOS channel divider function description (default = 0x0). 0x1A0 [7:4] Low Cycles Divider 4.2 Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). [3:0] High Cycles Divider 4.2 Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). 0x1A1 5 Bypass Divider 4.2 Bypasses (and powers down) 4.2 divider logic; route clock to 4.2 output. 0: does not bypass 4.2 divider logic (default). 1: bypasses 4.2 divider logic. 4 Bypass Divider 4.1 Bypasses (and powers down) 4.1 divider logic; route clock to 4.1 output. 0: does not bypass 4.1 divider logic (default). 1: bypasses 4.1 divider logic. 3 Divider 4 nosync Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. 2 Divider 4 force high Forces Divider 4 output high. Requires that nosync also be set. 0: forces low (default). 1: forces high. 1 Start High Divider 4.2 Divider 4.2 starts high/low. 0: starts low (default). 1: starts high. 0 Start High Divider 4.1 Divider 4.1 starts high/low. 0: starts low (default). 1: starts high. 0x1A2 0 Divider 4 DCCOFF Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Rev. C | Page 75 of 80

AD9516-3 Data Sheet Table 60. VCO Divider and CLK Input Reg. Addr (Hex) Bits Name Description 0x1E0 [2:0] VCO divider 2 1 0 Divide 0 0 0 2. 0 0 1 3. 0 1 0 4 (default). 0 1 1 5. 1 0 0 6. 1 0 1 Output static. Note that setting the VCO divider static should occur only after VCO calibration. 1 1 0 Output static. Note that setting the VCO divider static should occur only after VCO calibration. 1 1 1 Output static. Note that setting the VCO divider static should occur only after VCO calibration. 0x1E1 4 Power down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). 0: normal operation (default). 1: power-down. 3 Power down VCO clock interface Powers down the interface block between VCO and clock distribution. 0: normal operation (default). 1: power-down. 2 Power down VCO and CLK Powers down both VCO and CLK input. 0; normal operation (default). 1: power-down. 0x1E1 1 Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider. 0: selects external CLK as input to VCO divider (default). 1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected. 0 Bypass VCO divider Bypasses or uses the VCO divider. 0: uses VCO divider (default). 1: bypasses VCO divider; cannot select VCO as input when this is selected. Table 61. System Reg. Addr. (Hex) Bits Name Description 0x230 2 Power down SYNC Powers down the SYNC function. 0: normal operation of the SYNC function (default). 1: powers down SYNC circuitry. 1 Power down distribution reference Powers down the reference for distribution section. 0: normal operation of the reference for the distribution section (default). 1: powers down the reference for the distribution section. 0 Soft SYNC The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed. That is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. 0: same as SYNC high (default). 1: same as SYNC low. Table 62. Update All Registers Reg. Addr (Hex) Bits Name Description 0x232 0 Update all registers This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This bit is self-clearing; that is, it does not have to be set back to 0. 1 (self-clearing): updates all active registers to the contents of the buffer registers. Rev. C | Page 76 of 80

Data Sheet AD9516-3 APPLICATIONS INFORMATION FREQUENCY PLANNING USING THE AD9516 Considering an ideal ADC of infinite resolution, where the step size and quantization error can be ignored, the available SNR The AD9516 is a highly flexible PLL. When choosing the PLL can be expressed approximately by settings and version of the AD9516, keep in mind the following guidelines. SNR(dB)=20×log 1  The AD9516 has the following four frequency dividers: the 2πfAtJ  reference (or R) divider, the feedback (or N) divider, the VCO where: divider, and the channel divider. When trying to achieve a f is the highest analog frequency being digitized. A particularly difficult frequency divide ratio requiring a large t is the rms jitter on the sampling clock. J amount of frequency division, some of the frequency division can be done by either the VCO divider or the channel divider, Figure 70 shows the required sampling clock jitter as a function thus allowing a higher phase detector frequency and more of the analog frequency and effective number of bits (ENOB). flexibility in choosing the loop bandwidth. 110 18 1 Within the AD9516 family, lower VCO frequencies generally 100 SNR = 20log 2πfAtJ result in slightly lower jitter. The difference in integrated jitter 16 90 (u(f1sr.uo4am5l lG y1 Hl2e szks Ht tohz 2 at.no9 521 05G 0MH fsHz )o zvo eof rft fhtsheee tA) e fDnotr9i 5rteh1 e6V sfCaaOmm eifl ryoe. uqIftup teuhntec f ydr ereqasuniregened c y is R (dB) 7800 t24J00 00=ff SS100fS 1124 NOB frequency plan can be achieved with a version of the AD9516 SN 1ps E that has a lower VCO frequency, choosing the lower frequency 60 2ps 10 part results in the lowest phase noise and the lowest jitter. However, 50 choosing a higher VCO frequency may result in more flexibility 10ps 8 in frequency planning. 40 6 Choosing a nominal charge pump current in the middle of the 30 adlelocwreaabslee trhaen gceh aasr gae s ptaurmtinpg c puorirnetn atl laonwds, tthheu ds,e asilglonwers ttoh ien dcreesaigsen oerr 10 fA 1(M00Hz) 1k 06422-044 Figure 70. SNR and ENOB vs. Analog Input Frequency to fine-tune the PLL loop bandwidth in either direction. See the AN-756 Application Note, Sampled Systems and the Effects ADIsimCLK is a powerful PLL modeling tool that can be of Clock Phase Noise and Jitter; and the AN-501 Application Note, downloaded from www.analog.com. It is a very accurate tool for Aperture Uncertainty and ADC System Performance, at determining the optimal loop filter for a given application. www.analog.com. USING THE AD9516 OUTPUTS FOR ADC CLOCK Many high performance ADCs feature differential clock inputs APPLICATIONS to simplify the task of providing the required low jitter clock on Any high speed ADC is extremely sensitive to the quality of its a noisy PCB. (Distributing a single-ended clock on a noisy PCB sampling clock. An ADC can be thought of as a sampling mixer, may result in coupled noise on the sample clock. Differential and any noise, distortion, or timing jitter on the clock is combined distribution has inherent common-mode rejection that can with the desired signal at the analog-to-digital output. Clock provide superior clock performance in a noisy environment.) integrity requirements scale with the analog input frequency The AD9516 features both LVPECL and LVDS outputs that and resolution, with higher analog input frequency applications provide differential clock outputs, which enable clock solutions at ≥14-bit resolution being the most stringent. The theoretical that maximize converter SNR performance. The input SNR of an ADC is limited by the ADC resolution and the jitter requirements of the ADC (differential or single-ended, logic on the sampling clock. level, termination) should be considered when selecting the best clocking/converter solution. Rev. C | Page 77 of 80

AD9516-3 Data Sheet LVPECL CLOCK DISTRIBUTION LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode The LVPECL outputs of the AD9516 provide the lowest jitter impedance matching. Even-mode impedance matching is an clock signals that are available from the AD9516. The LVPECL important consideration for closely coupled transmission lines outputs (because they are open emitter) require a dc termination at high frequencies. Its main drawback is that it offers limited to bias the output transistors. The simplified equivalent circuit flexibility for varying the drive strength of the emitter-follower in Figure 59 shows the LVPECL output stage. LVPECL driver. This can be an important consideration when In most applications, an LVPECL far-end Thevenin termination driving long trace lengths but is usually not an issue. In the case (see Figure 71) or Y-termination (see Figure 72) is recommended. shown in Figure 72, where VS_LVPECL = 2.5 V, the 50 Ω In each case, the V of the receiving buffer should match the S termination resistor that is connected to ground should be VS_LVPECL. If it does not, ac coupling is recommended (see changed to 19 Ω. Figure 73). Thevenin-equivalent termination uses a resistor network to provide The resistor network is designed to match the transmission line 50 Ω termination to a dc voltage that is below V of the LVPECL OL impedance (50 Ω) and the switching threshold (V − 1.3 V). S driver. In this case, VS_LVPECL on the AD9516 should equal V S VS_DRV of the receiving buffer. Although the resistor combination shown in Figure 72 results in a dc bias point of VS_LVPECL − 2 V, the VS_LVPECL VS 50Ω 127Ω 127Ω actual common-mode voltage is VS_LVPECL − 1.3 V because additional current flows from the AD9516 LVPECL driver through LVPECL (SNIONTG LCEO-UENPLDEEDD) LVPECL the pull-down resistor. The circuit is identical when VS_LVPECL = 2.5 V, except that 50Ω the pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω. 83Ω 83Ω 06422-145 LVDS CLOCK DISTRIBUTION Figure 71. DC-Coupled 3.3 V LVPECL, Far-End Thevenin Termination The AD9516 provides four clock outputs (OUT6 to OUT9) that are selectable as either CMOS or LVDS level outputs. LVDS is a differential output option that uses a current mode output stage. VS_LVPECL VS = 3.3V The nominal current is 3.5 mA, which yields 350 mV output swing Z0 = 50Ω across a 100 Ω resistor. An output current of 7 mA is also available 50Ω 50Ω LVPECL LVPECL in cases where a larger output swing is required. The LVDS 50Ω Z0 = 50Ω 06422-147 oAu rtepcuotm mmeeetns doerd e txecremedins aatlilo AnN ciSrIc/uTiItA fo/rE ItAhe- 6L4V4D spSe ocuiftipcuattiso ins s. Figure 72. DC-Coupled 3.3 V LVPECL, Y-Termination shown in Figure 74. VS VS VS_LVPECL VS 0.1nF LVDS DIFFERENT1I0A0LΩ (COUPLED)100Ω LVDS LVPECL 0.1nF T1R00AΩN( CSDOMIFUIFSPESLRIEOEDNN) TLIIANLE 100Ω LVPECL 06422-047 Figure 74. LVDS Output Termination 200Ω 200Ω 06422-146 SSpeeee tdh Ae nAaNlo-g5-t8o6- DAipgiptalilc Catoionvne Nrteortse f,o LrV mDoSr eD iantfao rOmuattpiounts o fno rL HViDghS.- Figure 73. AC-Coupled LVPECL with Parallel Transmission Line Rev. C | Page 78 of 80

Data Sheet AD9516-3 CMOS CLOCK DISTRIBUTION Termination at the far-end of the PCB trace is a second option. The CMOS outputs of the AD9516 do not supply enough The AD9516 provides four clock outputs (OUT6 to OUT9) current to provide a full voltage swing with a low impedance that are selectable as either CMOS or LVDS level outputs. resistive, far-end termination, as shown in Figure 76. The far- When selected as CMOS, each output becomes a pair of CMOS end termination network should match the PCB trace impedance outputs, each of which can be individually turned on or off and and provide the desired switching point. The reduced signal set as noninverting or inverting. These outputs are 3.3 V CMOS swing may still meet receiver input requirements in some compatible. applications. This can be useful when driving long trace Whenever single-ended CMOS clocking is used, some of the lengths on less critical nets. following general guidelines should be used. VS Point-to-point nets should be designed such that a driver has only one receiver on the net, if possible. This allows for simple 10Ω 50Ω 100Ω CMOS CMOS tmerismminatacthioend sicmhpeemdeasn acnesd omni tnhiem nizeet.s Sreinrigeisn tge drmuein taot ipoons saitb tleh e 100Ω 06422-077 source is generally required to provide transmission line Figure 76. CMOS Output with Far-End Termination matching and/or to reduce current transients at the driver. Because of the limitations of single-ended CMOS clocking, The value of the resistor is dependent on the board design and consider using differential outputs when driving high speed timing requirements (typically 10 Ω to 100 Ω is used). CMOS signals over long traces. The AD9516 offers both LVPECL and outputs are also limited in terms of the capacitive load or trace LVDS outputs that are better suited for driving long traces length that they can drive. Typically, trace lengths less than where the inherent noise immunity of differential signaling 3 inches are recommended to preserve signal rise/fall times and provides superior performance for clocking converters. preserve signal integrity. 60.4Ω 10Ω (1.0 INCH) CMOS MICROSTRIP CMOS 06422-076 Figure 75. Series Termination of CMOS Output Rev. C | Page 79 of 80

AD9516-3 Data Sheet OUTLINE DIMENSIONS 9.10 0.30 9.00 SQ 0.60 MAX 0.25 8.90 0.60 0.18 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 8.85 0.50 EXPOSED 6.35 8.75 SQ BSC PAD 6.20 SQ 8.65 6.05 0.50 0.40 33 16 32 17 0.30 TOP VIEW BOTTOM VIEW 0.25 MIN 7.50 REF 1.00 12° MAX 0.80 MAX 0.65 TYP 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND SEATING FUNCTION DESCRIPTIONS PLANE 0.20 REF SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-12-2012-C Figure 77. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad CP-64-4 Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9516-3BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9516-3BCPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9516-3/PCBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06422-0-2/13(C) Rev. C | Page 80 of 80

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9516-3BCPZ AD9516-3BCPZ-REEL7 AD9516-3/PCBZ