1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs AD9511 FEATURES FUNCTIONAL BLOCK DIAGRAM Low phase noise phase-locked loop core VS GND RSET CPRSETVCP Reference input frequencies to 250 MHz DISTRIBUTION AD9511 PLL Programmable dual-modulus prescaler REF REF Programmable charge pump (CP) current REFIN R DIVIDER PHASE Separate CP supply (VCPS) extends tuning range REFINB N DIVIDER FDREETQEUCETNOCRY CPHUAMRGPE CP Two 1.6 GHz, differential clock inputs FUNCTION RSEYSNECTBB, 5 programmable dividers, 1 to 32, all integers PDB SETPTLILNGS STATUS Phase select for output-to-output coarse delay adjust CLK1 CLK2 CLK1B CLK2B 3 independent 1.2 GHz LVPECL outputs PROGRAMMABLE DIVIDERS AND Additive output jitter 225 fs rms PHASE ADJUST LVPECL OUT0 /1, /2, /3... /31, /32 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs OUT0B LVPECL Additive output jitter 275 fs rms OUT1 /1, /2, /3... /31, /32 Fine delay adjust on 1 LVDS/CMOS output OUT1B LVPECL Serial control port OUT2 /1, /2, /3... /31, /32 Space-saving 48-lead LFCSP OUT2B SCLK LVDS/CMOS SDIO SERIAL OUT3 CONTROL /1, /2, /3... /31, /32 APPLICATIONS SDO PORT OUT3B CSB LVDS/CMOS OUT4 Low jitter, low phase noise clock distribution /1, /2, /3... /31, /32 ΔT OUT4B CHliogchk pinegrf hoirgmha snpceee wd iAreDleCsss, DtrAanCssc, eDiDveSrss, DDCs, DUCs, MxFEs ADDEJLUASYT 05286-001 High performance instrumentation Figure 1. Broadband infrastructure Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock GENERAL DESCRIPTION output relative to another clock output may be varied by means The AD9511 provides a multi-output clock distribution of a divider phase select function that serves as a coarse timing function along with an on-chip PLL core. The design adjustment. One of the LVDS/CMOS outputs features a emphasizes low jitter and phase noise to maximize data programmable delay element with full-scale ranges up to 10 ns converter performance. Other applications with demanding of delay. This fine tuning delay block has 5-bit resolution, giving phase noise and jitter requirements also benefit from this part. 32 possible delays from which to choose for each full-scale setting. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision The AD9511 is ideally suited for data converter clocking charge pump (CP); and a programmable feedback divider (N). applications where maximum converter performance is By connecting an external VCXO or VCO to the CLK2/CLK2B achieved by encode signals with subpicosecond jitter. pins, frequencies up to 1.6 GHz may be synchronized to the The AD9511 is available in a 48-lead LFCSP and can be input reference. operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by There are five independent clock outputs. Three outputs are connecting the charge pump supply (VCP) to 5.5 V. The LVPECL (1.2 GHz), and two are selectable as either LVDS temperature range is −40°C to +85°C. (800 MHz) or CMOS (250 MHz) levels. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.

AD9511 TABLE OF CONTENTS Specifications.....................................................................................4 A and B Counters...................................................................30 PLL Characteristics......................................................................4 Determining Values for P, A, B, and R................................30 Clock Inputs..................................................................................5 Phase Frequency Detector (PFD) and Charge Pump.......31 Clock Outputs...............................................................................6 Antibacklash Pulse.................................................................31 Timing Characteristics................................................................7 STATUS Pin............................................................................31 Clock Output Phase Noise..........................................................9 PLL Digital Lock Detect........................................................31 Clock Output Additive Time Jitter...........................................12 PLL Analog Lock Detect.......................................................32 PLL and Distribution Phase Noise and Spurious...................14 Loss of Reference....................................................................32 Serial Control Port.....................................................................15 FUNCTION Pin.........................................................................32 FUNCTION Pin.........................................................................15 RESETB: 58h<6:5> = 00b (Default).....................................32 STATUS Pin................................................................................16 SYNCB: 58h<6:5> = 01b.......................................................32 Power............................................................................................16 PDB: 58h<6:5> = 11b............................................................33 Timing Diagrams............................................................................17 Distribution Section...................................................................33 Absolute Maximum Ratings..........................................................18 CLK1 and CLK2 Clock Inputs..................................................33 Thermal Characteristics............................................................18 Dividers........................................................................................33 ESD Caution................................................................................18 Setting the Divide Ratio........................................................33 Pin Configuration and Function Descriptions...........................19 Setting the Duty Cycle...........................................................33 Terminology....................................................................................21 Divider Phase Offset..............................................................37 Typical Performance Characteristics...........................................22 Delay Block.................................................................................38 Typical Modes of Operation..........................................................26 Calculating the Delay............................................................38 PLL with External VCXO/VCO Followed by Clock Outputs........................................................................................38 Distribution.................................................................................26 Power-Down Modes..................................................................39 Clock Distribution Only............................................................26 Chip Power-Down or Sleep Mode—PDB...........................39 PLL with External VCO and Band-Pass Filter Followed by Clock Distribution......................................................................27 PLL Power-Down...................................................................39 Functional Description..................................................................29 Distribution Power-Down....................................................39 Overall..........................................................................................29 Individual Clock Output Power-Down...............................39 PLL Section.................................................................................29 Individual Circuit Block Power-Down................................39 PLL Reference Input—REFIN..............................................29 Reset Modes................................................................................40 VCO/VCXO Clock Input—CLK2........................................29 Power-On Reset—Start-Up Conditions when VS is Applied.................................................................................40 PLL Reference Divider—R....................................................29 Asynchronous Reset via the FUNCTION Pin...................40 VCO/VCXO Feedback Divider—N (P, A, B).....................29 Soft Reset via the Serial Port.................................................40 Rev. A | Page 2 of 60

AD9511 Single-Chip Synchronization.....................................................40 Summary Table............................................................................45 SYNCB—Hardware SYNC....................................................40 Register Map Description..........................................................47 Soft SYNC—Register 58h<2>...............................................40 Power Supply...................................................................................54 Multichip Synchronization........................................................40 Power Management....................................................................54 Serial Control Port..........................................................................41 Applications.....................................................................................55 Serial Control Port Pin Descriptions........................................41 Using the AD9511 Outputs for ADC Clock Applications....55 General Operation of Serial Control Port...............................41 CMOS Clock Distribution.........................................................55 Framing a Communication Cycle with CSB.......................41 LVPECL Clock Distribution......................................................56 Communication Cycle—Instruction Plus Data..................41 LVDS Clock Distribution...........................................................56 Write.........................................................................................41 Power and Grounding Considerations and Power Supply Rejection.......................................................................................56 Read..........................................................................................42 Outline Dimensions........................................................................57 The Instruction Word (16 Bits).................................................42 Ordering Guide...........................................................................57 MSB/LSB First Transfers............................................................42 Register Map and Description.......................................................45 REVISION HISTORY Changes to Divider Phase Offset Section....................................37 6/05—Rev. 0 to Rev. A Changes to Individual Clock Output Power-Down Section.....39 Changes to Features..........................................................................1 Changes to Individual Circuit Block Power-Down Section......39 Changes to General Description.....................................................1 Changes to Soft Reset via the Serial Port Section.......................40 Changes to Table 1 and Table 2.......................................................5 Changes to Multichip Synchronization Section..........................40 Changes to Table 4............................................................................7 Changes to Serial Control Port Section.......................................41 Changes to Table 5............................................................................9 Changes to Serial Control Port Pin Descriptions Section.........41 Changes to Table 6..........................................................................14 Changes to General Operation of Serial Changes to Table 8 and Table 9.....................................................15 Control Port Section.......................................................................41 Changes to Table 11........................................................................16 Added Framing a Communication Cycle with CSB Section....41 Changes to Table 13........................................................................20 Added Communication Cycle—Instruction Plus Changes to Figure 19 to Figure 23................................................24 Data Section.....................................................................................41 Changes to Figure 30 and Figure 31.............................................26 Changes to Write Section...............................................................41 Changes to Figure 32......................................................................27 Changes to Read Section................................................................42 Changes to Figure 33......................................................................28 Changes to Instruction Word (16 Bits) Section..........................42 Changes to VCO/VCXO Clock Input—CLK2 Section..............29 Changes to Table 20........................................................................42 Changes to PLL Reference Divider—P Section...........................29 Changes to MSB/LSB First Transfers Section..............................42 Changes to A and B Counters Section.........................................30 Added Figure 52; Renumbered Sequentially...............................44 Changes to PLL Digital Lock Detect Section..............................31 Changes to Table 23........................................................................45 Changes to PLL Analog Lock Detect Section..............................32 Changes to Table 24........................................................................47 Changes to Loss of Reference Section..........................................32 Changes to Power Supply...............................................................54 Changes to FUNCTION Pin Section...........................................32 Changes to RESETB: 58h<6:5> = 00b (Default) Section...........32 Changes to SYNCB: 58h<6:5> = 01b Section..............................32 Changes to CLK1 and CLK2 Clock Inputs Section....................33 4/05—Revision 0: Initial Version Rev. A | Page 3 of 60

AD9511 SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5%; V ≤ VCP ≤ 5.5 V, T = 25°C, R = 4.12 kΩ, CPR = 5.1 kΩ, unless otherwise noted. S S S A SET SET Minimum (min) and maximum (max) values are given over full V and T (−40°C to +85°C) variation. S A PLL CHARACTERISTICS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUTS (REFIN) Input Frequency 0 250 MHz Input Sensitivity 150 mV p-p Self-Bias Voltage, REFIN 1.45 1.60 1.75 V Self-bias voltage of REFIN1. Self-Bias Voltage, REFINB 1.40 1.50 1.60 V Self-bias voltage of REFINB1. Input Resistance, REFIN 4.0 4.9 5.8 kΩ Self-biased1. Input Resistance, REFINB 4.5 5.4 6.3 kΩ Self-biased1. Input Capacitance 2 pF PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width 0Dh<1:0> = 00b. PFD Input Frequency 100 MHz Antibacklash pulse width 0Dh<1:0> = 01b. PFD Input Frequency 45 MHz Antibacklash pulse width 0Dh<1:0> = 10b. Antibacklash Pulse Width 1.3 ns 0Dh<1:0> = 00b. (This is the default setting.) Antibacklash Pulse Width 2.9 ns 0Dh<1:0> = 01b. Antibacklash Pulse Width 6.0 ns 0Dh<1:0> = 10b. CHARGE PUMP (CP) I Sink/Source Programmable. CP High Value 4.8 mA With CPR = 5.1 kΩ. SET Low Value 0.60 mA Absolute Accuracy 2.5 % V = VCP/2. CP S CPR Range 2.7/10 kΩ SET I Three-State Leakage 1 nA CP Sink-and-Source Current Matching 2 % 0.5 < V < VCP − 0.5 V. CP S I vs. V 1.5 % 0.5 < V < VCP − 0.5 V. CP CP CP S I vs. Temperature 2 % V = VCP/2 V. CP CP S RF CHARACTERISTICS (CLK2)2 Input Frequency 1.6 GHz Frequencies > 1200 MHz (LVPECL) or 800 MHz (LVDS) require a minimum divide-by-2 (see the Distribution Section). Input Sensitivity 150 mV p-p Input Common-Mode Voltage, V 1.5 1.6 1.7 V Self-biased; enables ac coupling. CM Input Common-Mode Range, V 1.3 1.8 V With 200 mV p-p signal applied. CMR Input Sensitivity, Single-Ended 150 mV p-p CLK2 ac-coupled; CLK2B capacitively bypassed to RF ground. Input Resistance 4.0 4.8 5.6 kΩ Self-biased. Input Capacitance 2 pF CLK2 VS. REFIN DELAY 500 ps Difference at PFD. PRESCALER (PART OF N DIVIDER) See the VCO/VCXO Feedback Divider—N (P, A, B) section. Prescaler Input Frequency P = 2 DM (2/3) 600 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 1600 MHz P = 16 DM (16/17) 1600 MHz P = 32 DM (32/33) 1600 MHz CLK2 Input Frequency for PLL 300 MHz A, B counter input frequency. Rev. A | Page 4 of 60

AD9511 Parameter Min Typ Max Unit Test Conditions/Comments NOISE CHARACTERISTICS In-Band Noise of the Charge Pump/ The synthesizer phase noise floor is Phase Frequency Detector (In-Band estimated by measuring the in-band Means Within the LBW of the PLL) phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). @ 50 kHz PFD Frequency −172 dBc/Hz @ 2 MHz PFD Frequency −156 dBc/Hz @ 10 MHz PFD Frequency −149 dBc/Hz @ 50 MHz PFD Frequency −142 dBc/Hz PLL Figure of Merit −218 + dBc/Hz Approximation of the PFD/CP phase noise 10 × log (f ) floor (in the flat region) inside the PLL loop PFD bandwidth. When running closed loop this phase noise is gained up by 20 × log(N)3. PLL DIGITAL LOCK DETECT WINDOW4 Signal available at STATUS pin when selected by 08h<5:2>. Required to Lock Selected by Register ODh. (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns Only) 3.5 ns <5> = 1b. High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns <5> = 0b. High Range (ABP 6 ns) 3.5 ns <5> = 0b. To Unlock After Lock (Hysteresis)4 Selected by Register 0Dh. Low Range (ABP 1.3 ns, 2.9 ns Only) 7 ns <5> = 1b. High Range (ABP 1.3 ns, 2.9 ns) 15 ns <5> = 0b. High Range (ABP 6 ns) 11 ns <5> = 0b. 1 REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition. 2 CLK2 is electrically identical to CLK1; the distribution only input can be used as differential or single-ended input (see the Clock Inputs section). 3 Example: −218 + 10 × log(fPFD) + 20 × log(N) should give the values for the in-band noise at the VCO output. 4 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time. CLOCK INPUTS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK1, CLK2)1 Input Frequency 0 1.6 GHz Input Sensitivity 1502 mV p-p Jitter performance can be improved with higher slew rates (greater swing). Input Level 23 V p-p Larger swings turn on the protection diodes and can degrade jitter performance. Input Common-Mode Voltage, V 1.5 1.6 1.7 V Self-biased; enables ac coupling. CM Input Common-Mode Range, V 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled. CMR Input Sensitivity, Single-Ended 150 mV p-p CLK2 ac-coupled; CLK2B ac bypassed to RF ground. Input Resistance 4.0 4.8 5.6 kΩ Self-biased. Input Capacitance 2 pF 1 CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input. 2 With a 50 Ω termination, this is −12.5 dBm. 3 With a 50 Ω termination, this is +10 dBm. Rev. A | Page 5 of 60

AD9511 CLOCK OUTPUTS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to V − 2 V S OUT0, OUT1, OUT2; Differential Output level 3Dh (3Eh) (3Fh)<3:2> = 10b Output Frequency 1200 MHz See Figure 21 Output High Voltage (V ) V − 1.22 V − 0.98 V − 0.93 V OH S S S Output Low Voltage (V ) V − 2.10 V − 1.80 V − 1.67 V OL S S S Output Differential Voltage (V ) 660 810 965 mV OD LVDS CLOCK OUTPUTS Termination = 100 Ω differential; default OUT3, OUT4; Differential Output level 40h (41h)<2:1> = 01b 3.5 mA termination current Output Frequency 800 MHz See Figure 22 Differential Output Voltage (V ) 250 360 450 mV OD Delta V 25 mV OD Output Offset Voltage (V ) 1.125 1.23 1.375 V OS Delta V 25 mV OS Short-Circuit Current (I , I ) 14 24 mA Output shorted to GND SA SB CMOS CLOCK OUTPUTS OUT3, OUT4 Single-ended measurements; B outputs: inverted, termination open Output Frequency 250 MHz With 5 pF load each output; see Figure 23 Output Voltage High (V ) V-0.1 V @ 1 mA load OH S Output Voltage Low (V ) 0.1 V @ 1 mA load OL Rev. A | Page 6 of 60

AD9511 TIMING CHARACTERISTICS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 50 Ω to V − 2 V S Output level 3Dh (3Eh) (3Fh)<3:2> = 10b Output Rise Time, t 130 180 ps 20% to 80%, measured differentially RP Output Fall Time, t 130 180 ps 80% to 20%, measured differentially FP PROPAGATION DELAY, t , CLK-TO-LVPECL OUT1 PECL Divide = Bypass 335 490 635 ps Divide = 2 − 32 375 545 695 ps Variation with Temperature 0.5 ps/°C OUTPUT SKEW, LVPECL OUTPUTS OUT1 to OUT0 on Same Part, t 2 70 100 140 ps SKP OUT1 to OUT2 on Same Part, t 2 15 45 80 ps SKP OUT0 to OUT2 on Same Part, t 2 45 65 90 Ps SKP All LVPECL OUT Across Multiple Parts, t 3 275 ps SKP_AB Same LVPECL OUT Across Multiple Parts, t 3 130 ps SKP_AB LVDS Termination = 100 Ω differential Output level 40h (41h) <2:1> = 01b 3.5 mA termination current Output Rise Time, t 200 350 ps 20% to 80%, measured differentially RL Output Fall Time, t 210 350 ps 80% to 20%, measured differentially FL PROPAGATION DELAY, t , CLK-TO-LVDS OUT1 Delay off on OUT4 LVDS OUT3 to OUT4 Divide = Bypass 0.99 1.33 1.59 ns Divide = 2 − 32 1.04 1.38 1.64 ns Variation with Temperature 0.9 ps/°C OUTPUT SKEW, LVDS OUTPUTS Delay off on OUT4 OUT3 to OUT4 on Same Part, t 2 −85 +270 ps SKV All LVDS OUTs Across Multiple Parts, t 3 450 ps SKV_AB Same LVDS OUT Across Multiple Parts, t 3 325 ps SKV_AB CMOS B outputs are inverted; termination = open Output Rise Time, t 681 865 ps 20% to 80%; C = 3 pF RC LOAD Output Fall Time, t 646 992 ps 80% to 20%; C = 3 pF FC LOAD PROPAGATION DELAY, t , CLK-TO-CMOS OUT1 Delay off on OUT4 CMOS Divide = Bypass 1.02 1.39 1.71 ns Divide = 2 − 32 1.07 1.44 1.76 ns Variation with Temperature 1 ps/°C OUTPUT SKEW, CMOS OUTPUTS Delay off on OUT4 OUT3 to OUT4 on Same Part, t 2 −140 +145 +300 SKC All CMOS OUT Across Multiple Parts, t 3 650 ps SKC_AB Same CMOS OUT Across Multiple Parts, t 3 500 ps SKC_AB LVPECL-TO-LVDS OUT Everything the same; different logic type Output Skew, t 0.74 0.92 1.14 ns LVPECL to LVDS on same part SKP_V LVPECL-TO-CMOS OUT Everything the same; different logic type Output Skew, t 0.88 1.14 1.43 ns LVPECL to CMOS on same part SKP_C LVDS-TO-CMOS OUT Everything the same; different logic type Output Skew, t 158 353 506 ps LVDS to CMOS on same part SKV_C Rev. A | Page 7 of 60

AD9511 Parameter Min Typ Max Unit Test Conditions/Comments DELAY ADJUST OUT4; LVDS and CMOS Shortest Delay Range4 35h <5:1> 11111b Zero Scale 0.05 0.36 0.68 ns 36h <5:1> 00000b Full Scale 0.72 1.12 1.51 ns 36h <5:1> 11111b Linearity, DNL 0.5 LSB Linearity, INL 0.8 LSB Longest Delay Range4 35h <5:1> 00000b Zero Scale 0.20 0.57 0.95 ns 36h <5:1> 00000b Full Scale 9.0 10.2 11.6 ns 36h <5:1> 11111b Linearity, DNL 0.3 LSB Linearity, INL 0.6 LSB Delay Variation with Temperature Long Delay Range, 10 ns5 Zero Scale 0.35 ps/°C Full Scale −0.14 ps/°C Short Delay Range, 1 ns5 Zero Scale 0.51 ps/°C Full Scale 0.67 ps/°C 1 The measurements are for CLK1. For CLK2, add approximately 25 ps. 2 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. 3 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. 4 Incremental delay; does not include propagation delay. 5 All delays between zero scale and full scale can be estimated by linear interpolation. Rev. A | Page 8 of 60

AD9511 CLOCK OUTPUT PHASE NOISE Table 5. Parameter Min Typ Max Unit Test Conditions/Comments CLK1-TO-LVPECL ADDITIVE PHASE NOISE Distribution Section only; does not include PLL or external VCO/VCXO CLK1 = 622.08 MHz, OUT = 622.08 MHz Input slew rate > 1 V/ns Divide Ratio = 1 @ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −148 dBc/Hz @ 100 kHz Offset −153 dBc/Hz >1 MHz Offset −154 dBc/Hz CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −140 dBc/Hz @ 1 kHz Offset −148 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −161 dBc/Hz CLK1 = 622.08 MHz, OUT = 38.88 MHz Divide Ratio = 16 @ 10 Hz Offset −135 dBc/Hz @ 100 Hz Offset −145 dBc/Hz @ 1 kHz Offset −158 dBc/Hz @ 10 kHz Offset −165 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −166 dBc/Hz CLK1 = 491.52 MHz, OUT = 61.44 MHz Divide Ratio = 8 @ 10 Hz Offset −131 dBc/Hz @ 100 Hz Offset −142 dBc/Hz @ 1 kHz Offset −153 dBc/Hz @ 10 kHz Offset −160 dBc/Hz @ 100 kHz Offset −165 dBc/Hz >1 MHz Offset −165 dBc/Hz CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset −125 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −151 dBc/Hz @ 100 kHz Offset −157 dBc/Hz >1 MHz Offset −158 dBc/Hz CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset −138 dBc/Hz @ 100 Hz Offset −144 dBc/Hz @ 1 kHz Offset −154 dBc/Hz @ 10 kHz Offset −163 dBc/Hz @ 100 kHz Offset −164 dBc/Hz >1 MHz Offset −165 dBc/Hz Rev. A | Page 9 of 60

AD9511 Parameter Min Typ Max Unit Test Conditions/Comments CLK1-TO-LVDS ADDITIVE PHASE NOISE Distribution Section only; does not include PLL or external VCO/VCXO CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset −100 dBc/Hz @ 100 Hz Offset −110 dBc/Hz @ 1 kHz Offset −118 dBc/Hz @ 10 kHz Offset −129 dBc/Hz @ 100 kHz Offset −135 dBc/Hz @ 1 MHz Offset −140 dBc/Hz >10 MHz Offset −148 dBc/Hz CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset −112 dBc/Hz @ 100 Hz Offset −122 dBc/Hz @ 1 kHz Offset −132 dBc/Hz @ 10 kHz Offset −142 dBc/Hz @ 100 kHz Offset −148 dBc/Hz @ 1 MHz Offset −152 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −154 dBc/Hz CLK1 = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 @ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −129 dBc/Hz @ 1 kHz Offset −136 dBc/Hz @ 10 kHz Offset −147 dBc/Hz @ 100 kHz Offset −153 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset −108 dBc/Hz @ 100 Hz Offset −118 dBc/Hz @ 1 kHz Offset −128 dBc/Hz @ 10 kHz Offset −138 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −148 dBc/Hz >10 MHz Offset −155 dBc/Hz CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset −118 dBc/Hz @ 100 Hz Offset −127 dBc/Hz @ 1 kHz Offset −137 dBc/Hz @ 10 kHz Offset −147 dBc/Hz Rev. A | Page 10 of 60

AD9511 Parameter Min Typ Max Unit Test Conditions/Comments @ 100 kHz Offset −154 dBc/Hz @ 1 MHz Offset −156 dBc/Hz >10 MHz Offset −158 dBc/Hz CLK1-TO-CMOS ADDITIVE PHASE NOISE Distribution Section only; does not include PLL or external VCO/VCXO CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset −110 dBc/Hz @ 100 Hz Offset −121 dBc/Hz @ 1 kHz Offset −130 dBc/Hz @ 10 kHz Offset −140 dBc/Hz @ 100 kHz Offset −145 dBc/Hz @ 1 MHz Offset −149 dBc/Hz > 10 MHz Offset −156 dBc/Hz CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −143 dBc/Hz @ 10 kHz Offset −152 dBc/Hz @ 100 kHz Offset −158 dBc/Hz @ 1 MHz Offset −160 dBc/Hz >10 MHz Offset −162 dBc/Hz CLK1 = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 @ 10 Hz Offset −122 dBc/Hz @ 100 Hz Offset −132 dBc/Hz @ 1 kHz Offset −140 dBc/Hz @ 10 kHz Offset −150 dBc/Hz @ 100 kHz Offset −155 dBc/Hz @ 1 MHz Offset −158 dBc/Hz >10 MHz Offset −160 dBc/Hz CLK1 = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 @ 10 Hz Offset −128 dBc/Hz @ 100 Hz Offset −136 dBc/Hz @ 1 kHz Offset −146 dBc/Hz @ 10 kHz Offset −155 dBc/Hz @ 100 kHz Offset −161 dBc/Hz >1 MHz Offset −162 dBc/Hz Rev. A | Page 11 of 60

AD9511 CLOCK OUTPUT ADDITIVE TIME JITTER Table 6. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution Section only; does not include PLL or external VCO/VCXO CLK1 = 622.08 MHz 40 fs rms BW = 12 kHz − 20 MHz (OC-12) Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz 55 fs rms BW = 12 kHz − 20 MHz (OC-3) Any LVPECL (OUT0 to OUT2) = 155.52 MHz Divide Ratio = 4 CLK1 = 400 MHz 215 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 215 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 100 MHz Interferer(s) Both LVDS (OUT3, OUT4) = 100 MHz Interferer(s) CLK1 = 400 MHz 222 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both LVDS (OUT3, OUT4) = 50 MHz Interferer(s) CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off) Interferer(s) CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On) Interferer(s) LVDS OUTPUT ADDITIVE TIME JITTER Distribution Section only; does not include PLL or external VCO/VCXO CLK1 = 400 MHz 264 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN LVDS (OUT3) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 319 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN LVDS (OUT4) = 100 MHz Divide Ratio = 4 Rev. A | Page 12 of 60

AD9511 Parameter Min Typ Max Unit Test Conditions/Comments CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN LVDS (OUT3) = 100 MHz Divide Ratio = 4 LVDS (OUT4) = 50 MHz Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = 50 MHz Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s) CMOS OUTPUT ADDITIVE TIME JITTER Distribution Section only; does not include PLL or external VCO/VCXO CLK1 = 400 MHz 275 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN Both CMOS (OUT3, OUT4) = 100 MHz (B Output On) Divide Ratio = 4 CLK1 = 400 MHz 400 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) LVDS (OUT4) = 50 MHz Interferer(s) CLK1 = 400 MHz 374 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B Output Off) Interferer(s) Rev. A | Page 13 of 60

AD9511 Parameter Min Typ Max Unit Test Conditions/Comments CLK1 = 400 MHz 555 fs rms Calculated from SNR of ADC method; F = 100 MHz with A = 170 MHz C IN CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B Output On) Interferer(s) DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter 100 MHz Output Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000 0.61 ps Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111 0.73 ps Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000 0.71 ps Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111 1.2 ps Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000 0.86 ps Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111 1.8 ps Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000 1.2 ps Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111 2.1 ps Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000 1.3 ps Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111 2.7 ps Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000 2.0 ps Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100 2.8 ps 1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method. PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS Table 7. Parameter Min Typ Max Unit Test Conditions/Comments PHASE NOISE AND SPURIOUS Depends on VCO/VCXO selection. Measured at LVPECL clock outputs; ABP = 6 ns; I = 5 mA; Ref = 30.72 MHz. CP VCXO = 245.76 MHz, VCXO is Toyocom TCO-2112 245.76. F = 1.2288 MHz; R = 25, N = 200 PFD 245.76 MHz Output Divide by 1. Phase Noise @100 kHz Offset <−145 dBc/Hz Dominated by VCXO phase noise. Spurious <−97 dBc First and second harmonics of F . PFD Below measurement floor. 61.44 MHz Output Divide by 4. Phase Noise @100 kHz Offset <−155 dBc/Hz Dominated by VCXO phase noise. Spurious <−97 dBc First and second harmonics of F . PFD Below measurement floor. Rev. A | Page 14 of 60

AD9511 SERIAL CONTROL PORT Table 8. Parameter Min Typ Max Unit Test Conditions/Comments CSB, SCLK (INPUTS) CSB and SCLK have 30 kΩ internal pull-down resistors Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF SDIO (WHEN INPUT) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 10 nA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V TIMING Clock Rate (SCLK, 1/t ) 25 MHz SCLK Pulse Width High, t 16 ns PWH Pulse Width Low, t 16 ns PWL SDIO to SCLK Setup, t 2 ns DS SCLK to SDIO Hold, t 1 ns DH SCLK to Valid SDIO and SDO, t 6 ns DV CSB to SCLK Setup and Hold, t, t 2 ns S H CSB Minimum Pulse Width High, t 3 ns PWH FUNCTION PIN Table 9. Parameter Min Typ Max Unit Test Conditions/Comments INPUT CHARACTERISTICS The FUNCTION pin has a 30 kΩ internal pull-down resistor. This pin should normally be held high. Do not leave NC. Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 110 μA Logic 0 Current 1 μA Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns SYNC TIMING Pulse Width Low 1.5 High speed clock cycles High speed clock is CLK1 or CLK2, whichever is used for distribution. Rev. A | Page 15 of 60

AD9511 STATUS PIN Table 10. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS When selected as a digital output (CMOS); there are other modes in which the STATUS pin is not CMOS digital output. See Figure 37. Output Voltage High (V ) 2.7 V OH Output Voltage Low (V ) 0.4 V OL MAXIMUM TOGGLE RATE 100 MHz Applies when PLL mux is set to any divider or counter output, or PFD up/down pulse. Also applies in analog lock detect mode. Usually debug mode only. Beware that spurs may couple to output when this pin is toggling. ANALOG LOCK DETECT Capacitance 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect readback. Use a pull-up resistor. POWER Table 11. Parameter Min Typ Max Unit Test Conditions/Comments POWER-UP DEFAULT MODE POWER DISSIPATION 550 600 mW Power-up default state; does not include power dissipated in output load resistors. No clock. POWER DISSIPATION 800 mW All outputs on. Three LVPECL outputs @ 800 MHz, two CMOS out @ 62 MHz (5 pF load). Does not include power dissipated in external resistors. 850 mW All outputs on. Three LVPECL outputs @ 800 MHz, two CMOS out @ 125 MHz (5 pF load). Does not include power dissipated in external resistors. Full Sleep Power-Down 35 60 mW Maximum sleep is entered by setting 0Ah<1:0> = 01b and 58h<4> = 1b. This powers off the PLL BG and the distribution BG references. Does not include power dissipated in terminations. Power-Down (PDB) 60 80 mW Set FUNCTION pin for PDB operation by setting 58h<6:5> = 11b. Pull PDB low. Does not include power dissipated in terminations. POWER DELTA CLK1, CLK2 Power-Down 10 15 25 mW Divider, DIV 2 − 32 to Bypass 23 27 33 mW For each divider. LVPECL Output Power-Down (PD2, PD3) 50 65 75 mW For each output. Does not include dissipation in termination (PD2 only). LVDS Output Power-Down 80 92 110 mW For each output. CMOS Output Power-Down (Static) 56 70 85 mW For each output. Static (no clock). CMOS Output Power-Down (Dynamic) 115 150 190 mW For each CMOS output, single-ended. Clocking at 62 MHz with 5 pF load. CMOS Output Power-Down (Dynamic) 125 165 210 mW For each CMOS output, single-ended. Clocking at 125 MHz with 5 pF load. Delay Block Bypass 20 24 60 mW Vs. delay block operation at 1 ns fs with maximum delay; output clocking at 25 MHz. PLL Section Power-Down 5 15 40 mW Rev. A | Page 16 of 60

AD9511 TIMING DIAGRAMS t CLK1 CLK1 DIFFERENTIAL tPECL 80% LVDS tLVDS 20% tCMOS 05286-002 tRL tFL 05286-065 Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode Figure 4. LVDS Timing, Differential DIFFERENTIAL SINGLE-ENDED 80% 80% LVPECL CMOS 3pF LOAD 20% 20% tRP tFP 05286-064 tRC tFC 05286-066 Figure 3. LVPECL Timing, Differential Figure 5. CMOS Timing, Single-Ended, 3 pF Load Rev. A | Page 17 of 60

AD9511 ABSOLUTE MAXIMUM RATINGS Table 12. With Respect Parameter or Pin to Min Max Unit VS GND −0.3 +3.6 V Stresses above those listed under Absolute Maximum Ratings VCP GND −0.3 +5.8 V may cause permanent damage to the device. This is a stress VCP V −0.3 +5.8 V rating only; functional operation of the device at these or any S REFIN, REFINB GND −0.3 V + 0.3 V other conditions above those indicated in the operational S RSET GND −0.3 V + 0.3 V sections of this specification is not implied. Exposure to S CPRSET GND −0.3 V + 0.3 V absolute maximum ratings for extended periods may affect S CLK1, CLK1B, CLK2, CLK2B GND −0.3 V + 0.3 V device reliability. S CLK1 CLK1B −1.2 +1.2 V THERMAL CHARACTERISTICS CLK2 CLK2B −1.2 +1.2 V Thermal Resistance1 SCLK, SDIO, SDO, CSB GND −0.3 V + 0.3 V S OUT0, OUT1, OUT2, OUT3, GND −0.3 V + 0.3 V S 48-Lead LFCSP OUT4 θ = 28.5°C/W FUNCTION GND −0.3 V + 0.3 V JA S STATUS GND −0.3 VS + 0.3 V 1 Thermal impedance measurements were taken on a 4-layer board in still air, Junction Temperature 150 °C in accordance with EIA/JESD51-7. Storage Temperature −65 +150 °C Lead Temperature (10 sec) 300 °C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 18 of 60

AD9511 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T E B S T 00 RDE DTT DD SPNSSNUUSSNN VCGRVGOOVVGG 876543210987 444444444333 REFIN 1 PIN 1 36 VS REFINB 2 INDICATOR 35 OUT3 VS 3 34 OUT3B VCP 4 33 VS CP 5 32 VS AD9511 VS 6 31 OUT4 CLK2 7 TOP VIEW 30 OUT4B CLK2B 8 (Not to Scale) 29 VS VS 9 28 VS CLK1 10 27 OUT1 CLK1B 11 26 OUT1B FUNCTION 12 25 VS 345678901234 111111122222 SKOOBSDB2SSD STATUSCLSDISDCSVGNOUT2OUTVVGN 05286-003 Figure 6. 48-Lead LFCSP Pin Configuration Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND. Rev. A | Page 19 of 60

AD9511 Table 13. Pin Function Descriptions Pin No. Mnemonic Description 1 REFIN PLL Reference Input. 2 REFINB Complementary PLL Reference Input. 3, 6, 9, 18, 22, VS Power Supply (3.3 V). 23, 25, 28, 29, 32, 33, 36, 39, 40, 44, 48 4 VCP Charge Pump Power Supply. It should be greater than or equal to VS. VCP can be set as high as 5.5 V for VCOs, requiring extended tuning range. 5 CP Charge Pump Output. 7 CLK2 Clock Input. Used to connect external VCO/VCXO to feedback divider, N. CLK2 also drives the distribution section of the chip and may be used as a generic clock input when PLL is not used. 8 CLK2B Complementary Clock Input. Used in conjunction with CLK2. 10 CLK1 Clock Input. Drives distribution section of the chip. 11 CLK1B Complementary Clock Input. Used in conjunction with CLK1. 12 FUNCTION Multipurpose Input. May be programmed as a reset (RESETB), sync (SYNCB), or power-down (PDB) pin. This pin is internally pulled down by a 30 kΩ resistor. If this pin is left NC, the part is in reset by default. To avoid this, connect this pin to V with a 1 kΩ resistor. S 13 STATUS Output Used to Monitor PLL Status and Sync Status. 14 SCLK Serial Data Clock. 15 SDIO Serial Data I/O. 16 SDO Serial Data Output. 17 CSB Serial Port Chip Select. 19, 24, 37, GND Ground. 38, 43, 46 20 OUT2B Complementary LVPECL Output. 21 OUT2 LVPECL Output. 26 OUT1B Complementary LVPECL Output. 27 OUT1 LVPECL Output. 30 OUT4B Complementary LVDS/Inverted CMOS Output. OUT4 includes a delay block. 31 OUT4 LVDS/CMOS Output. OUT4 includes a delay block. 34 OUT3B Complementary LVDS/Inverted CMOS Output. 35 OUT3 LVDS/CMOS Output. 41 OUT0B Complementary LVPECL Output. 42 OUT0 LVPECL Output. 45 RSET Current Set Resistor to Ground. Nominal value = 4.12 kΩ. 47 CPRSET Charge Pump Current Set Resistor to Ground. Nominal value = 5.1 kΩ. Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND. Rev. A | Page 20 of 60

AD9511 TERMINOLOGY Phase Jitter and Phase Noise Time Jitter An ideal sine wave can be thought of as having a continuous Phase noise is a frequency domain phenomenon. In the time and even progression of phase with time from 0 degrees to domain, the same effect is exhibited as time jitter. When 360 degrees for each cycle. Actual signals, however, display a observing a sine wave, the time of successive zero crossings is certain amount of variation from ideal phase progression over seen to vary. In a square wave, the time jitter is seen as a time. This phenomenon is called phase jitter. Although many displacement of the edges from their ideal (regular) times of causes can contribute to phase jitter, one major cause is random occurrence. In both cases, the variations in timing from the noise, which is characterized statistically as being Gaussian ideal are the time jitter. Since these variations are random in (normal) in distribution. nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous Time jitter that occurs on a sampling clock for a DAC or an power spectrum. This power spectrum is usually reported as a ADC decreases the SNR and dynamic range of the converter. series of values whose units are dBc/Hz at a given offset in A sampling clock with the lowest possible jitter provides the frequency from the sine wave (carrier). The value is a ratio highest performance from a given converter. (expressed in dB) of the power contained within a 1 Hz Additive Phase Noise bandwidth with respect to the power at the carrier frequency. It is the amount of phase noise that is attributable to the device For each measurement, the offset from the carrier frequency is or subsystem being measured. The phase noise of any external also given. oscillators or clock sources has been subtracted. This makes it It is meaningful to integrate the total power contained within possible to predict the degree to which the device impacts the some interval of offset frequencies (for example, 10 kHz to total system phase noise when used in conjunction with the 10 MHz). This is called the integrated phase noise over that various oscillators and clock sources, each of which contribute frequency offset interval and can be readily related to the time their own phase noise to the total. In many cases, the phase jitter due to the phase noise within that offset frequency noise of one element dominates the system phase noise. interval. Additive Time Jitter Phase noise has a detrimental effect on the performance of It is the amount of time jitter that is attributable to the device ADCs, DACs, and RF mixers. It lowers the achievable dynamic or subsystem being measured. The time jitter of any external range of the converters and mixers, although they are affected oscillators or clock sources has been subtracted. This makes it in somewhat different ways. possible to predict the degree to which the device will impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute their own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. A | Page 21 of 60

AD9511 TYPICAL PERFORMANCE CHARACTERISTICS 0.6 0.7 DEFAULT– 3 LVPECL + 2 LVDS (DIV ON) 0.5 0.6 W) W) 3 LVPECL + 2 CMOS (DIV ON) R ( R ( E E W W O O P 3 LVPECL + 2 LVDS (DIV BYPASSED) P 0.4 0.5 3 LVPECL (DIV ON) 2 LVDS (DIV ON) 0.3 05286-080 0.4 05286-081 0 400 800 0 20 40 60 80 100 120 OUTPUT FREQUENCY (MHz) OUTPUT FREQUENCY (MHz) Figure 7. Power vs. Frequency—LVPECL, LVDS (PLL Off) Figure 10. Power vs. Frequency—LVPECL, CMOS (PLL Off) CLK1 (EVAL BOARD) REFIN (EVAL BOARD) 3GHz 5MHz 5GHz 3GHz 05286-043 05286-062 Figure 8. CLK1 Smith Chart (Evaluation Board) Figure 11. REFIN Smith Chart (Evaluation Board) CLK2 (EVAL BOARD) 5MHz 3GHz 05286-044 Figure 9. CLK2 Smith Chart (Evaluation Board) Rev. A | Page 22 of 60

AD9511 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 ––8900 05286-058 ––8900 05286-059 CENTER 245.75MHz 30kHz/ SPAN 300kHz CENTER 61.44MHz 30kHz/ SPAN 300kHz Figure 12. Phase Noise, LVPECL, DIV 1, FVCXO = 245.76 MHz, Figure 15. Phase Noise, LVPECL, DIV 4, FVCXO = 245.76 MHz, FOUT = 245.76 MHz, FPFD = 1.2288 MHz, R = 25, N = 200 FOUT = 61.44 MHz, FPFD = 1.2288 MHz, R = 25, N = 200 0 –135 z) H –10 c/ B–140 d –20 T ( U P–145 –30 N D I –40 O PF–150 –50 D T RE–155 –60 R E F –70 RE–160 E –80 OIS 1–9000 05286-063 PFD N––117605 05286-057 CENTER 1.5GHz 250kHz/ SPAN 2.5MHz 0.1 1 10 100 PFD FREQUENCY (MHz) Figure 13. PLL Reference Spurs: VCO 1.5 GHz, FPFD = 1 MHz Figure 16. Phase Noise (Referred to CP Output) vs. PFD Frequency 5.0 5.0 4.5 4.5 4.0 4.0 A) A) m m N ( 3.5 N ( 3.5 PI PUMP DOWN PUMP UP PI PUMP DOWN PUMP UP P 3.0 P 3.0 C C M M O 2.5 O 2.5 R R F F T 2.0 T 2.0 N N E E R 1.5 R 1.5 R R U U C 1.0 C 1.0 0.50 05286-041 0.50 05286-042 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOLTAGE ON CP PIN (V) VOLTAGE ON CP PIN (V) Figure 14. Charge Pump Output Characteristics @ VCPS = 3.3 V Figure 17. Charge Pump Output Characteristics @ VCPS = 5.0 V Rev. A | Page 23 of 60

AD9511 1.8 1.7 p) p- V G ( 1.6 N WI S L 1.5 A TI N E R 1.4 E F F DI 1.3 05286-053 1.2100 600 1100 1600 05286-056 VERT 500mV/DIV HORIZ 500ps/DIV OUTPUT FREQUENCY (MHz) Figure 18. LVPECL Differential Output @ 800 MHz Figure 21. LVPECL Differential Output Swing vs. Frequency 750 p) 700 p- V m G ( N 650 WI S L A TI 600 N E R E F F DI 550 05286-054 500 05286-050 VERT 100mV/DIV HORIZ 500ps/DIV 100 300 500 700 900 OUTPUT FREQUENCY (MHz) Figure 19. LVDS Differential Output @ 800 MHz Figure 22. LVDS Differential Output Swing vs. Frequency 3.5 2pF 3.0 2.5 )K 10pF VP 2.0 T ( U P T 1.5 U O 1.0 20pF 0.5 05286-055 0 05286-047 VERT 500mV/DIV HORIZ 1ns/DIV 0 100 200 300 400 500 600 OUTPUT FREQUENCY (MHz) Figure 20. CMOS Single-Ended Output @ 250 MHz with 10 pF Load Figure 23. CMOS Single-Ended Output Swing vs. Frequency and Load Rev. A | Page 24 of 60

AD9511 –110 –110 –120 –120 –130 –130 z) z) H H c/ c/ B–140 B–140 d d L(f) ( L(f) ( –150 –150 –160 –160 –170 05286-051 –170 05286-052 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M OFFSET (Hz) OFFSET (Hz) Figure 24. Additive Phase Noise—LVPECL DIV1, 245.76 MHz Figure 27. Additive Phase Noise—LVPECL DIV1, 622.08 MHz Distribution Section Only –80 –80 –90 –90 –100 –100 –110 –110 z) z) c/H–120 c/H–120 B B d d L(f) (–130 L(f) (–130 –140 –140 –150 –150 ––117600 05286-048 ––117600 05286-049 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M OFFSET (Hz) OFFSET (Hz) Figure 25. Additive Phase Noise—LVDS DIV1, 245.76 MHz Figure 28. Additive Phase Noise—LVDS DIV2, 122.88 MHz –100 –100 –110 –110 –120 –120 z) z) H–130 H–130 c/ c/ B B d d L(f) (–140 L(f) (–140 –150 –150 –160 –160 –170 05286-045 –170 05286-046 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M OFFSET (Hz) OFFSET (Hz) Figure 26. Additive Phase Noise—CMOS DIV1, 245.76 MHz Figure 29. Additive Phase Noise—CMOS DIV4, 61.44 MHz Rev. A | Page 25 of 60

AD9511 TYPICAL MODES OF OPERATION CLOCK DISTRIBUTION ONLY PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION It is possible to use only the distribution section whenever the PLL section is not needed. Some power can be saved by This is the most common operational mode for the AD9511. shutting the PLL block off, as well as by powering down any An external oscillator (shown as VCO/VCXO) is phase locked unused clock channels (see the Register Map Description to a reference input frequency applied to REFIN. The loop filter section). is usually a passive design. A VCO or a VCXO can be used. The CLK2 input is connected internally to the feedback divider, N. In distribution mode, both the CLK1 and CLK2 inputs are The CLK2 input provides the feedback path for the PLL. If the available for distribution to outputs via a low jitter multiplexer VCO/VCXO frequency exceeds maximum frequency of the (mux). output(s) being used, an appropriate divide ratio must be set in the corresponding divider(s) in the Distribution Section. Some power can be saved by shutting off unused functions, as well as VREF AD9511 RPLELF by powering down any unused clock channels (see the Register REFIN R Map and Description section). PFD CHPUAMRGPE N FUNCTION STATUS VREF AD9511 RPELLF CLK1 CLK2 CLOCK CLOCK REFIN INPUT 1 INPUT 2 REFERENCE R INPUT PFD CHPUAMRGPE FLILOTOEPR LVPECL N DIVIDE FUNCTION STATUS LVPECL CLK1 CLK2 VCXO, DIVIDE VCO LVPECL LVPECL DIVIDE DIVIDE CLOCK LVPECL LVDS/CMOS OUTPUTS SERIAL DIVIDE PORT DIVIDE LVPECL LVDS/CMOS SERIAL DIVIDE LVDS/CMOS COLUOTCPUKTS DIVIDE ΔT 05286-011 PORT DIVIDE Figure 31. Clock Distribution Mode LVDS/CMOS DIVIDE ΔT 05286-010 Figure 30. PLL and Clock Distribution Mode Rev. A | Page 26 of 60

AD9511 PLL WITH EXTERNAL VCO AND BAND-PASS FILTER FOLLOWED BY CLOCK DISTRIBUTION An external band-pass filter may be used to try to improve the phase noise and spurious characteristics of the PLL output. This option is most appropriate to optimize cost by choosing a less expensive VCO combined with a moderately priced filter. Note that the BPF is shown outside of the VCO-to-N divider path, with the BP filter outputs routed to CLK1. Some power can be saved by shutting off unused functions, as well as by powering down any unused clock channels (see the Register Map and Description section). VREF AD9511 RPLELF REFIN REFERENCE R INPUT PFD CPHUAMRGPE FLILOTOEPR N FUNCTION STATUS CLK1 CLK2 VCO LVPECL DIVIDE BPF LVPECL DIVIDE LVPECL DIVIDE CLOCK LVDS/CMOS OUTPUTS SERIAL PORT DIVIDE LVDS/CMOS DIVIDE ΔT 05286-012 Figure 32. AD9511 with VCO and BPF Filter Rev. A | Page 27 of 60

AD9511 VS GND RSET CPRSETVCP DISTRIBUTION AD9511 PLL REF REF REFIN 250MHz R DIVIDER PHASE REFINB FDREETQEUCETNOCRY CPHUAMRGPE CP N DIVIDER SYNCB, FUNCTION RESETB PDB PLL STATUS SETTINGS CLK1 CLK2 1.6GHz 1.6GHz CLK1B CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST LVPECL OUT0 /1, /2, /3... /31, /32 OUT0B LVPECL OUT1 1.2GHz /1, /2, /3... /31, /32 LVPECL OUT1B LVPECL OUT2 /1, /2, /3... /31, /32 OUT2B SCLK LVDS/CMOS SDIO SERIAL OUT3 CONTROL /1, /2, /3... /31, /32 SDO PORT OUT3B 800MHz LVDS CSB LVDS/CMOS 250MHz OUT4 CMOS /1, /2, /3... /31, /32 ΔT OUT4B ADDEJLUASYT 05286-004 Figure 33. Functional Block Diagram Showing Maximum Frequencies Rev. A | Page 28 of 60

AD9511 FUNCTIONAL DESCRIPTION OVERALL capacitor to a quiet ground. Figure 34 shows the equivalent circuit of REFIN. Figure 33 shows a block diagram of the AD9511. The chip combines a programmable PLL core with a configurable clock VS distribution system. A complete PLL requires the addition of a 10kΩ 12kΩ suitable external VCO (or VCXO) and loop filter. This PLL can REFIN 150Ω lock to a reference input signal and produce an output that is related to the input frequency by the ratio defined by the REFINB 150Ω 10kΩ 10kΩ programmable R and N dividers. The PLL cleans up some jitter fbraonmd wthide tehx atenrdn athl ere pfehraesnec ne osiisgen pale,r dfoerpmenadnicneg o of nth teh eV lCoOop 05286-033 (VCXO). Figure 34. REFIN Equivalent Circuit VCO/VCXO Clock Input—CLK2 The output from the VCO (VCXO) can be applied to the clock The CLK2 differential input is used to connect an external VCO distribution section of the chip, where it can be divided by any or VCXO to the PLL. Only the CLK2 input port has a integer value from 1 to 32. The duty cycle and relative phase of connection to the PLL N divider. This input can receive up to the outputs can be selected. There are three LVPECL outputs 1.6 GHz. These inputs are internally self-biased and must be ac- (OUT0, OUT1, and OUT2) and two outputs that can be either coupled via capacitors. LVDS or CMOS level outputs (OUT3 or OUT4). OUT4 can also make use of a variable delay block. Alternatively, CLK2 may be used as an input to the distribution section. This is accomplished by setting Register 45h<0> = 0b. Alternatively, the clock distribution section can be driven The default condition is for CLK1 to feed the distribution section. directly by an external clock signal, and the PLL can be powered off. Whenever the clock distribution section is used alone, there CLOCK INPUT is no clock clean-up. The jitter of the input clock signal is STAGE VS passed along directly to the distribution section and may dominate at the clock outputs. CLK PLL SECTION CLKB The AD9511 consists of a PLL section and a distribution 2.5kΩ 2.5kΩ section. If desired, the PLL section can be used separately from 5kΩ tThhee d AisDtr9ib5u1t1i ohna ss eac ctioomn.p lete PLL core on-chip, requiring only 5kΩ 05286-016 Figure 35. CLK1, CLK2 Equivalent Input Circuit an external loop filter and VCO/VCXO. This PLL is based on the ADF4106, a PLL noted for its superb low phase noise PLL Reference Divider—R performance. The operation of the AD9511 PLL is nearly The REFIN/REFINB inputs are routed to reference divider, R, identical to that of the ADF4106, offering an advantage to those which is a 14-bit counter. R may be programmed to any value with experience with the ADF series of PLLs. Differences from 1 to 16383 (a value of 0 results in a divide by 1) via its include the addition of differential inputs at REFIN and CLK2, control register (OBh<5:0>, OCh<7:0>). The output of the R and a different control register architecture. Also, the prescaler divider goes to one of the phase/frequency detector inputs. The has been changed to allow N as low as 1. The AD9511 PLL maximum allowable frequency into the phase, frequency implements the digital lock detect feature somewhat differently detector (PFD) must not be exceeded. This means that the than the ADF4106 does, offering improved functionality at REFIN frequency divided by R must be less than the maximum higher PFD rates. See the Register Map Description section. allowable PFD frequency. See Figure 34. PLL Reference Input—REFIN VCO/VCXO Feedback Divider—N (P, A, B) The REFIN/REFINB pins can be driven by either a differential The N divider is a combination of a prescaler, P, (3 bits) and two or a single-ended signal. These pins are internally self-biased so counters, A (6 bits) and B (13 bits). Although the AD9511’s PLL that they can be ac-coupled via capacitors. It is possible to dc- is similar to the ADF4106, the AD9511 has a redesigned couple to these inputs. If REFIN is driven single-ended, the prescaler that allows lower values of N. The prescaler has both a unused side (REFINB) should be decoupled via a suitable dual modulus (DM) and a fixed divide (FD) mode. The AD9511 prescaler modes are shown in Table 14. Rev. A | Page 29 of 60

AD9511 Table 14. PLL Prescaler Modes A and B Counters Mode The AD9511 B counter has a bypass mode (B = 1), which is not (FD = Fixed Divide DM = Dual Modulus) Value in 0Ah<4:2> Divide By available on the ADF4106. The B counter bypass mode is valid only when using the prescaler in FD mode. The B counter is FD 000 1 bypassed by writing 1 to the B counter bypass bit (0Ah<6> = FD 001 2 1b). The valid range of the B counter is 3 to 8191. The default P = 2 DM 010 P/P + 1 = 2/3 after a reset is 0, which is invalid. P = 4 DM 011 P/P + 1 = 4/5 P = 8 DM 100 P/P + 1 = 8/9 Note that the A counter is not used when the prescaler is in P = 16 DM 101 P/P + 1 = 16/17 FD mode. P = 32 DM 110 P/P + 1 = 32/33 FD 111 3 Note also that the A/B counters have their own reset bit, which is primarily intended for testing. The A and B counters When using the prescaler in FD mode, the A counter is not can also be reset using the R, A, and B counters’ shared reset bit used, and the B counter may need to be bypassed. The DM (09h<0>). prescaler modes set some upper limits on the frequency, which can be applied to CLK2. See Table 15. Determining Values for P, A, B, and R When operating the AD9511 in a dual-modulus mode, the Table 15. Frequency Limits of Each Prescaler Mode input reference frequency, F , is related to the VCO output REF Mode (DM = Dual Modulus) CLK2 frequency, F VCO. P = 2 DM (2/3) <600 MHz F = (F /R) × (PB + A) = F × N/R P = 4 DM (4/5) <1000 MHz VCO REF REF P = 8 DM (8/9) <1600 MHz When operating the prescaler in fixed divide mode, the A P = 16 DM <1600 MHz counter is not used and the equation simplifies to P = 32 DM <1600 MHz F = (F /R) × (PB) = F × N/R VCO REF REF By using combinations of dual modulus and fixed divide modes, the AD9511 can achieve values of N all the way down to N = 1. Table 16 shows how a 10 MHz reference input may be locked to any integer multiple of N. Note that the same value of N may be derived in different ways, as illustrated by N = 12. Table 16. P, A, B, R—Smallest Values for N F R P A B N F Mode Notes REF VCO 10 1 1 X 1 1 10 FD P = 1, B = 1 (Bypassed) 10 1 2 X 1 2 20 FD P = 2, B = 1 (Bypassed) 10 1 1 X 3 3 30 FD P = 1, B = 3 10 1 1 X 4 4 40 FD P = 1, B = 4 10 1 1 X 5 5 50 FD P = 1, B = 5 10 1 2 X 3 6 60 FD P = 2, B = 3 10 1 2 0 3 6 60 DM P/P + 1 = 2/3, A = 0, B = 3 10 1 2 1 3 7 70 DM P/P + 1 = 2/3, A = 1, B = 3 10 1 2 2 3 8 80 DM P/P + 1 = 2/3, A = 2, B = 3 10 1 2 1 4 9 90 DM P/P + 1 = 2/3, A = 1, B = 4 10 1 2 X 5 10 100 FD P = 2, B = 5 10 1 2 0 5 10 100 DM P/P + 1 = 2/3, A = 0, B = 5 10 1 2 1 5 11 110 DM P/P + 1 = 2/3, A = 1, B = 5 10 1 2 X 6 12 120 FD P = 2, B = 6 10 1 2 0 6 12 120 DM P/P + 1 = 2/3, A = 0, B = 6 10 1 4 0 3 12 120 DM P/P + 1 = 4/5, A = 0, B = 3 10 1 4 1 3 13 130 DM P/P + 1 = 4/5, A = 1, B = 3 Rev. A | Page 30 of 60

AD9511 Phase Frequency Detector (PFD) and Charge Pump Antibacklash Pulse The PFD takes inputs from the R counter and the N counter The PLL features a programmable antibacklash pulse width that (N = BP + A) and produces an output proportional to the phase is set by the value in Register 0Dh<1:0>. The default and frequency difference between them. Figure 36 is a antibacklash pulse width is 1.3 ns (0Dh<1:0> = 00b) and simplified schematic. The PFD includes a programmable delay normally should not need to be changed. The antibacklash element that controls the width of the antibacklash pulse. This pulse eliminates the dead zone around the phase-locked pulse ensures that there is no dead zone in the PFD transfer condition and thereby reduces the potential for certain spurs function and minimizes phase noise and reference spurs. Two that could be impressed on the VCO signal. bits in Register 0Dh <1:0> control the width of the pulse. STATUS Pin VP The output multiplexer on the AD9511 allows access to various CHARGE PUMP signals and internal points on the chip at the STATUS pin. HI D1 Q1 UP Figure 37 shows a block diagram of the STATUS pin section. U1 The function of the STATUS pin is controlled by Register R DIVIDER CLR1 08h<5:2>. PLL Digital Lock Detect PROGRAMMABLE U3 CP DELAY The STATUS pin can display two types of PLL lock detect: ANTIBACKLASH digital (DLD) and analog (ALD). Whenever digital lock detect PULSE WIDTH is desired, the STATUS pin provides a CMOS level signal, which CLR2 DOWN can be active high or active low. HI D2 Q2 U2 The digital lock detect has one of two time windows, as selected N DIVIDER by Register 0Dh<5>. The default (ODh<5> = 0b) requires the GND 05286-014 s9i.g5n nasl teod gseets tohne tDheL Din ptruutes ,t wo hthiceh P tFhDen t om bues tc soeipnacirdateen bt yw aitth liena st Figure 36. PFD Simplified Schematic and Timing (In Lock) 15 ns to give DLD = false. The other setting (ODh<5> = 1b) makes these coincidence times 3.5 ns for DLD = true and 7 ns for DLD = false. The DLD may be disabled by writing 1 to Register 0Dh<6>. If the signal at REFIN goes away while DLD is true, the DLD will not necessarily indicate loss-of-lock. See the Loss of Reference section for more information. OFF (LOW) (DEFAULT) SYNC DIGITAL LOCK DETECT (ACTIVE HIGH) DETECT VS N DIVIDER OUTPUT DIGITAL LOCK DETECT (ACTIVE LOW) G R DIVIDER OUTPUT LODE ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN) AO NM PRESCAAL ECRO UONUTTEPRU TO (UNTCPLUKT) OR AECT STATUS PFD UP PULSE FT PIN PFD DOWN PULSE OL DE LOSS OF REFERENCE (ACTIVE HIGH) RK TC TRI-STATE NO OL ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN) C LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH) GND LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW) SYNC DETECT ENABLE LOSS OF REFERENCE (ACTIVE LOW) 58h <0> PLL M0U8hX <C5O:2N>TROL 05286-015 Figure 37. STATUS Pin Circuit CLK1 Clock Input Rev. A | Page 31 of 60

AD9511 PLL Analog Lock Detect User intervention is required to take the part out of this state. First, 07h<2> = 0b must be written in order to disable the loss- An analog lock detect (ALD) signal may be selected. When of-reference circuit, taking the charge pump out of tri-state and ALD is selected, the signal at the STATUS pin is either an open- causing LREF to go false. A second write of 07h<2> = 1b is drain P-channel (08h<5:2> = 1100b) or an open-drain N- required to re-enable the loss-of-reference circuit. channel (08h<5:2> = 0101b). The analog lock detect signal is true (relative to the selected PLL LOOP LOCKS mode) with brief false pulses. These false pulses get shorter as DLLRDE GF OISEFSA TLRSUEE the inputs to the PFD are nearer to coincidence and longer as WRITE 07h<2> = 0 LREF SETFALSE they are further from coincidence. CHARGE PUMP COMES OUT OF TRI-STATE n PFD CYCLES WITH WRITE 07h<2> = 1 DLD TRUE To extract a usable analog lock detect signal, an external RC LOR ENABLED (n SET BY 07h<6:5>) network is required to provide an analog filter with the appropriate RC constant to allow for the discrimination of a CHARGE PUMP CHECK FOR PRESENCE lock condition by an external voltage comparator. A 1 kΩ GOES INTO TRI-STATE. OF REFERENCE. LREF SET TRUE. LREF STAYSFALSE IF resistor in parallel with a small capacitance usually fulfills this REFERENCE IS DETECTED. requirement. However, some experimentation may be required RDEMEFTIESERSCEINTNEGCDE 05286-034 to get the desired operation. Figure 38. Loss of Reference Sequence of Events The analog lock detect function may introduce some spurious FUNCTION PIN energy into the clock outputs. It is prudent to limit the use of The FUNCTION pin (12) has three functions that are selected the ALD when the best possible jitter/phase noise performance by the value in Register 58h<6:5>. This pin is internally pulled is required on the clock outputs. down by a 30 kΩ resistor. If this pin is left NC, the part is in Loss of Reference reset by default. To avoid this, connect this pin to VS with a 1 kΩ resistor. The AD9511 PLL can warn of a loss-of-reference signal at REFIN. The loss-of-reference monitor internally sets a flag RESETB: 58h<6:5> = 00b (Default) called LREF. Externally, this signal can be observed in several In its default mode, the FUNCTION pin acts as RESETB, which ways on the STATUS pin, depending on the PLL MUX control generates an asynchronous reset or hard reset when pulled low. settings in Register 08h<5:2>. The LREF alone can be observed The resulting reset writes the default values into the serial as an active high signal by setting 08h<5:2> = <1010b> or as an control port buffer registers as well as loading them into the active low signal by setting 08h<5:2> = <1111b>. chip control registers. When the RESETB signal goes high The loss-of-reference circuit is clocked by the signal from the again, a synchronous sync is issued (see the SYNCB: 58h<6:5> VCO, which means that there must be a VCO signal present to = 01b section) and the AD9511 resumes operation according to detect a loss of reference. the default values of the registers. SYNCB: 58h<6:5> = 01b The digital lock detect (DLD) block of the AD9511 requires a PLL reference signal to be present for the digital lock detect The FUNCTION pin may be used to cause a synchronization or output to be valid. It is possible to have a digital lock detect alignment of phase among the various clock outputs. The indication (DLD = true) that remains true even after a loss-of- synchronization applies only to clock outputs that: reference signal. For this reason, the digital lock detect signal • are not powered down alone cannot be relied upon if the reference has been lost. There is a way to combine the DLD and the LREF into a single signal • the divider is not masked (no sync = 0b) at the STATUS pin. Set 08h<5:2> = <1101b> to get a signal that • are not bypassed (bypass = 0b) is the logical OR of the loss-of-lock (inverse of DLD) and the loss-of-reference (LREF) active high. If an active low version of SYNCB is level and rising edge sensitive. When SYNCB is low, this same signal is desired, set 08h<5:2> = <1110b>. the set of affected outputs are held in a predetermined state, defined by each divider’s start high bit. On a rising edge, the The reference monitor is enabled only after the DLD signal has dividers begin after a predefined number of fast clock cycles been high for the number of PFD cycles set by the value in (fast clock is the selected clock input, CLK1 or CLK2) as 07h<6:5>. This delay is measured in PFD cycles. The delay determined by the values in the divider’s phase offset bits. ranges from 3 PFD cycles (default) to 24 PFD cycles. When the reference goes away, LREF goes true and the charge pump goes The SYNCB application of the FUNCTION pin is always active, into tri-state. regardless of whether the pin is also assigned to perform reset Rev. A | Page 32 of 60

AD9511 or power-down. When the SYNCB function is selected, the Each divider can be configured for divide ratio, phase, and duty FUNCTION pin does not act as either RESETB or PDB. cycle. The phase and duty cycle values that can be selected depend on the divide ratio that is chosen. PDB: 58h<6:5> = 11b Setting the Divide Ratio The FUNCTION pin may also be programmed to work as an asynchronous full power-down, PDB. Even in this full power- The divide ratio is determined by the values written via the SCP down mode, there is still some residual V current because to the registers that control each individual output, OUT0 to S some on-chip references continue to operate. In PDB mode, the OUT4. These are the even numbered registers beginning at 4Ah FUNCTION pin is active low. The chip remains in a power- and going through 52h. Each of these registers is divided into down state until PDB is returned to logic high. The chip returns bits that control the number of clock cycles the divider output to the settings programmed prior to the power-down. stays high (high_cycles <3:0>) and the number of clock cycles the divider output stays low (low_cycles <7:4>). Each value is 4 See the Chip Power-Down or Sleep Mode—PDB section for bits and has the range of 0 to 15. more details on what occurs during a PDB initiated power- down. The divide ratio is set by DISTRIBUTION SECTION Divide Ratio = (high_cycles + 1) + (low_cycles + 1) As previously mentioned, the AD9511 is partitioned into two Example 1: operational sections: PLL and distribution. The PLL Section was discussed previously. If desired, the distribution section can Set the Divide Ratio = 2 be used separately from the PLL section. high_cycles = 0 CLK1 AND CLK2 CLOCK INPUTS low_cycles = 0 Either CLK1 or CLK2 may be selected as the input to the distribution section. The CLK1 input can be connected to drive Divide Ratio = (0 + 1) + (0 + 1) = 2 the distribution section only. CLK1 is selected as the source for Example 2: the distribution section by setting Register 45h<0> = 1. This is the power-up default state. Set Divide Ratio = 8 CLK1 and CLK2 work for inputs up to 1600 MHz. The jitter high_cycles = 3 performance is improved by a higher input slew rate. The input level should be between approximately 150 mV p-p to no more low_cycles = 3 than 2 V p-p. Anything greater may result in turning on the Divide Ratio = (3 + 1) + (3 + 1) = 8 protection diodes on the input pins, which could degrade the jitter performance. Note that a Divide Ratio of 8 may also be obtained by setting: See Figure 35 for the CLK1 and CLK2 equivalent input circuit. high_cycles = 2 These inputs are fully differential and self-biased. The signal should be ac-coupled using capacitors. If a single-ended input low_cycles = 4 must be used, this can be accommodated by ac coupling to one Divide Ratio = (2 + 1) + (4 + 1) = 8 side of the differential input only. The other side of the input should be bypassed to a quiet ac ground by a capacitor. Although the second set of settings produce the same divide ratio, the resulting duty cycle is not the same. The unselected clock input (CLK1 or CLK2) should be powered down to eliminate any possibility of unwanted crosstalk Setting the Duty Cycle between the selected clock input and the unselected clock input. The duty cycle and the divide ratio are related. Different divide DIVIDERS ratios have different duty cycle options. For example, if Divide Ratio = 2, the only duty cycle possible is 50%. If the Divide Each of the five clock outputs of the AD9511 has its own Ratio = 4, the duty cycle may be 25%, 50%, or 75%. divider. The divider can be bypassed to get an output at the same frequency as the input (1×). When a divider is bypassed, it The duty cycle is set by is powered down to save power. Duty Cycle = (high_cycles + 1)/[(high_cycles + 1) + (low_cycles + 1)] All integer divide ratios from 1 to 32 may be selected. A divide ratio of 1 is selected by bypassing the divider. See Table 17 for the values of the available duty cycles for each divide ratio. Rev. A | Page 33 of 60

AD9511 Table 17. Duty Cycle and Divide Ratio 4Ah to 52h 4Ah to 52h Divide Ratio Duty Cycle (%) LO<7:4> HI<3:0> Divide Ratio Duty Cycle (%) LO<7:4> HI<3:0> 2 50 0 0 11 27 7 2 3 67 0 1 11 82 1 8 3 33 1 0 11 18 8 1 4 50 1 1 11 91 0 9 4 75 0 2 11 9 9 0 4 25 2 0 12 50 5 5 5 60 1 2 12 58 4 6 5 40 2 1 12 42 6 4 5 80 0 3 12 67 3 7 5 20 3 0 12 33 7 3 6 50 2 2 12 75 2 8 6 67 1 3 12 25 8 2 6 33 3 1 12 83 1 9 6 83 0 4 12 17 9 1 6 17 4 0 12 92 0 A 7 57 2 3 12 8 A 0 7 43 3 2 13 54 5 6 7 71 1 4 13 46 6 5 7 29 4 1 13 62 4 7 7 86 0 5 13 38 7 4 7 14 5 0 13 69 3 8 8 50 3 3 13 31 8 3 8 63 2 4 13 77 2 9 8 38 4 2 13 23 9 2 8 75 1 5 13 85 1 A 8 25 5 1 13 15 A 1 8 88 0 6 13 92 0 B 8 13 6 0 13 8 B 0 9 56 3 4 14 50 6 6 9 44 4 3 14 57 5 7 9 67 2 5 14 43 7 5 9 33 5 2 14 64 4 8 9 78 1 6 14 36 8 4 9 22 6 1 14 71 3 9 9 89 0 7 14 29 9 3 9 11 7 0 14 79 2 A 10 50 4 4 14 21 A 2 10 60 3 5 14 86 1 B 10 40 5 3 14 14 B 1 10 70 2 6 14 93 0 C 10 30 6 2 14 7 C 0 10 80 1 7 15 53 6 7 10 20 7 1 15 47 7 6 10 90 0 8 15 60 5 8 10 10 8 0 15 40 8 5 11 55 4 5 15 67 4 9 11 45 5 4 15 33 9 4 11 64 3 6 15 73 3 A 11 36 6 3 15 27 A 3 11 73 2 7 15 80 2 B Rev. A | Page 34 of 60

AD9511 4Ah to 52h 4Ah to 52h Divide Ratio Duty Cycle (%) LO<7:4> HI<3:0> Divide Ratio Duty Cycle (%) LO<7:4> HI<3:0> 15 20 B 2 19 53 8 9 15 87 1 C 19 47 9 8 15 13 C 1 19 58 7 A 15 93 0 D 19 42 A 7 15 7 D 0 19 63 6 B 16 50 7 7 19 37 B 6 16 56 6 8 19 68 5 C 16 44 8 6 19 32 C 5 16 63 5 9 19 74 4 D 16 38 9 5 19 26 D 4 16 69 4 A 19 79 3 E 16 31 A 4 19 21 E 3 16 75 3 B 19 84 2 F 16 25 B 3 19 16 F 2 16 81 2 C 20 50 9 9 16 19 C 2 20 55 8 A 16 88 1 D 20 45 A 8 16 13 D 1 20 60 7 B 16 94 0 E 20 40 B 7 16 6 E 0 20 65 6 C 17 53 7 8 20 35 C 6 17 47 8 7 20 70 5 D 17 59 6 9 20 30 D 5 17 41 9 6 20 75 4 E 17 65 5 A 20 25 E 4 17 35 A 5 20 80 3 F 17 71 4 B 20 20 F 3 17 29 B 4 21 52 9 A 17 76 3 C 21 48 A 9 17 24 C 3 21 57 8 B 17 82 2 D 21 43 B 8 17 18 D 2 21 62 7 C 17 88 1 E 21 38 C 7 17 12 E 1 21 67 6 D 17 94 0 F 21 33 D 6 17 6 F 0 21 71 5 E 18 50 8 8 21 29 E 5 18 56 7 9 21 76 4 F 18 44 9 7 21 24 F 4 18 61 6 A 22 50 A A 18 39 A 6 22 55 9 B 18 67 5 B 22 45 B 9 18 33 B 5 22 59 8 C 18 72 4 C 22 41 C 8 18 28 C 4 22 64 7 D 18 78 3 D 22 36 D 7 18 22 D 3 22 68 6 E 18 83 2 E 22 32 E 6 18 17 E 2 22 73 5 F 18 89 1 F 22 27 F 5 18 11 F 1 23 52 A B Rev. A | Page 35 of 60

AD9511 4Ah to 52h 4Ah to 52h Divide Ratio Duty Cycle (%) LO<7:4> HI<3:0> Divide Ratio Duty Cycle (%) LO<7:4> HI<3:0> 23 48 B A 26 46 D B 23 57 9 C 26 58 A E 23 43 C 9 26 42 E A 23 61 8 D 26 62 9 F 23 39 D 8 26 38 F 9 23 65 7 E 27 52 C D 23 35 E 7 27 48 D C 23 70 6 F 27 56 B E 23 30 F 6 27 44 E B 24 50 B B 27 59 A F 24 54 A C 27 41 F A 24 46 C A 28 50 D D 24 58 9 D 28 54 C E 24 42 D 9 28 46 E C 24 63 8 E 28 57 B F 24 38 E 8 28 43 F B 24 67 7 F 29 52 D E 24 33 F 7 29 48 E D 25 52 B C 29 55 C F 25 48 C B 29 45 F C 25 56 A D 30 50 E E 25 44 D A 30 53 D F 25 60 9 E 30 47 F D 25 40 E 9 31 52 E F 25 64 8 F 31 48 F E 25 36 F 8 32 50 F F 26 50 C C 26 54 B D Rev. A | Page 36 of 60

AD9511 Divider Phase Offset In general, by combining the 4-bit phase offset and the Start H/L bit, there are 32 possible phase offset states (see Table 18). The phase of each output may be selected, depending on the divide ratio chosen. This is selected by writing the appropriate Table 18. Phase Offset—Start H/L Bit values to the registers, which set the phase and start high/low Phase Offset 4Bh to 53h (Fast Clock bit for each output. These are the odd numbered registers from Rising Edges) Phase Offset <3:0> Start H/L <4> 4Bh to 53h. Each divider has a 4-bit phase offset <3:0> and a 0 0 0 start high or low bit <4>. 1 1 0 Following a sync pulse, the phase offset word determines how 2 2 0 many fast clock (CLK1 or CLK2) cycles to wait before initiating 3 3 0 a clock output edge. The Start H/L bit determines if the divider 4 4 0 output starts low or high. By giving each divider a different 5 5 0 phase offset, output-to-output delays can be set in increments of 6 6 0 the fast clock period, t . 7 7 0 CLK 8 8 0 Figure 39 shows three dividers, each set for DIV = 4, 50% duty 9 9 0 cycle. By incrementing the phase offset from 0 to 2, each output 10 10 0 is offset from the initial edge by a multiple of t . CLK 11 11 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 12 12 0 CLOCK INPUT 13 13 0 CLK tCLK 14 14 0 DIVIDER OTUPUTS DIV = 4, DUTY = 50% 15 15 0 START = 0, 16 0 1 PHASE = 0 17 1 1 START = 0, PHASE = 1 18 2 1 19 3 1 START = 0, PHASE = 2 20 4 1 2×tCLK tCLK 05286-091 2212 56 11 Figure 39. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 2 23 7 1 24 8 1 For example: 25 9 1 CLK1 = 491.52 MHz 26 10 1 27 11 1 t = 1/491.52 = 2.0345 ns CLK1 28 12 1 For DIV = 4 29 13 1 30 14 1 Phase Offset 0 = 0 ns 31 15 1 Phase Offset 1 = 2.0345 ns The resolution of the phase offset is set by the fast clock period (t ) at CLK1 or CLK2. As a result, every divide ratio does not CLK Phase Offset 2 = 4.069 ns have 32 unique phase offsets available. For any divide ratio, the number of unique phase offsets is numerically equal to the The three outputs may also be described as: divide ratio (see Table 18): OUT1 = 0° DIV = 4 OUT2 = 90° Unique Phase Offsets Are Phase = 0, 1, 2, 3 OUT3 = 180° DIV= 7 Setting the phase offset to Phase = 4 results in the same relative Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6 phase as the first channel, Phase = 0° or 360°. Rev. A | Page 37 of 60

AD9511 DIV = 18 This path adds some jitter greater than that specified for the nondelay outputs. This means that the delay function should be Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, used primarily for clocking digital chips, such as FPGA, ASIC, 11, 12, 13, 14, 15, 16, 17 DUC, and DDC, rather than for data converters. The jitter is higher for long full scales (~10 ns). This is because the delay Phase offsets may be related to degrees by calculating the phase block uses a ramp and trip points to create the variable delay. A step for a particular divide ratio: longer ramp means more noise may be introduced. Phase Step = 360°/(Divide Ratio) = 360°/DIV Calculating the Delay Using some of the same examples, The following values and equations are used to calculate the delay of the delay block. DIV = 4 Value of Ramp Current Control Bits (Register 35h or Register 39h Phase Step = 360°/4 = 90° <2:0>) = Iramp_bits Unique Phase Offsets in Degrees Are Phase = 0°, 90°, I (μA) = 200 × (Iramp_bits + 1) 180°, 270° RAMP No. of Caps = No. of 0s + 1 in Ramp Control Capacitor DIV = 7 (Register 35h or Register 39h <5:3>), that is, 101 = 1 + 1 = 2; 110 Phase Step = 360°/7 = 51.43° = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1) Unique Phase Offsets in Degrees Are Phase = 0°, 51.43°, Delay_Range (ns) = 200 × [(No. of Caps + 3)/(IRAMP)] × 1.3286 102.86°, 154.29°, 205.71°, 257.15°, 308.57° ⎛No.ofCaps−1⎞ DELAY BLOCK Offset(ns)=0.34+(1600−IRAMP)×10−4+⎜⎜⎝ IRAMP ⎟⎟⎠×6 OUT4 (LVDS/CMOS) includes an analog delay element that can be programmed (Register 34h to Register 36h) to give Delay_Full_Scale (ns) = Delay_Range + Offset variable time delays (ΔT) in the clock signal passing through Fine_Adj = Value of Delay Fine Adjust (Register 36h or that output. Register 3Ah <5:1>), that is, 11111 = 31 CLOCK INPUT Delay (ns) = Offset + Delay_Range × Fine_adj × (1/31) OUT4 ONLY OUTPUTS ÷N ∅SELECT The AD9511 offers three different output level choices: X LVDS MU LVPECL, LVDS, and CMOS. OUT0 to OUT2 are LVPECL only. ΔT CMOS OUTPUT OUT3 and OUT4 can be selected as either LVDS or CMOS. DRIVER Each output can be enabled or turned off as needed to save FUFLILN-SEC (D3AE2L LSEAT:Y E1 PnAsSD )TJOUS 1T0ns 05286-092 power. Figure 40. Analog Delay (OUT4) The simplified equivalent circuit of the LVPECL outputs is shown in Figure 41. The amount of delay that can be used is determined by the frequency of the clock being delayed. The amount of delay can 3.3V approach one-half cycle of the clock period. For example, for a 10 MHz clock, the delay can extend to the full 10 ns maximum of which the delay element is capable. However, for a 100 MHz clock (with 50% duty cycle), the maximum delay is less than 5 ns (or half of the period). OUT OUT4 allows a full-scale delay in the range 1 ns to 10 ns. The OUTB full-scale delay is selected by choosing a combination of ramp current and the number of capacitors by writing the appropriate values into Register 35h. There are 32 fine delay settings for e ach full scale, set by Register 36h. GND 05286-037 Figure 41. LVPECL Output Simplified Equivalent Circuit Rev. A | Page 38 of 60

AD9511 Table 19. Register 0Ah: PLL Power-Down 3.5mA <1> <0> Mode 0 0 Normal Operation 0 1 Asynchronous Power-Down OUT 1 0 Normal Operation OUTB 1 1 Synchronous Power-Down In asynchronous power-down mode, the device powers down as soon as the registers are updated. 3.5mA 05286-038 In synchronous power-down mode, the PLL power-down is Figure 42. LVDS Output Simplified Equivalent Circuit gated by the charge pump to prevent unwanted frequency jumps. The device goes into power-down on the occurrence of POWER-DOWN MODES the next charge pump event after the registers are updated. Chip Power-Down or Sleep Mode—PDB Distribution Power-Down The PDB chip power-down turns off most of the functions and currents in the AD9511. When the PDB mode is enabled, a chip The distribution section can be powered down by writing to power-down is activated by taking the FUNCTION pin to a Register 58h<3> = 1. This turns off the bias to the distribution logic low level. The chip remains in this power-down state until section. If the LVPECL power-down mode is normal operation PDB is brought back to logic high. When woken up, the <00>, it is possible for a low impedance load on that LVPECL AD9511 returns to the settings programmed into its registers output to draw significant current during this power-down. If prior to the power-down, unless the registers are changed by the LVPECL power-down mode is set to <11>, the LVPECL new programming while the PDB mode is active. output is not protected from reverse bias, and can be damaged under certain termination conditions. The PDB power-down mode shuts down the currents on the chip, except the bias current necessary to maintain the LVPECL When combined with the PLL power-down, this mode results in outputs in a safe shutdown mode. This is needed to protect the the lowest possible power-down current for the AD9511. LVPECL output circuitry from damage that could be caused by Individual Clock Output Power-Down certain termination and load configurations when tri-stated. Any of the five clock distribution outputs can be powered down Because this is not a complete power-down, it can be called sleep mode. individually by writing to the appropriate registers via the SCP. The register map details the individual power-down settings for When the AD9511 is in a PDB power-down or sleep mode, the each output. The LVDS/CMOS outputs may be powered down, chip is in the following state: regardless of their output load configuration. • The PLL is off (asynchronous power-down). The LVPECL outputs have multiple power-down modes (see Register 3Dh, Register 3Eh, and Register 3Fh in Table 24). • All clocks and sync circuits are off. These give some flexibility in dealing with various output termination conditions. When the mode is set to <10b>, the • All dividers are off. LVPECL output is protected from reverse bias to 2 V + 1 V. If BE • All LVDS/CMOS outputs are off. the mode is set to <11b>, the LVPECL output is not protected from reverse bias and can be damaged under certain • All LVPECL outputs are in safe off mode. termination conditions. This setting also affects the operation when the distribution block is powered down with Register • The serial control port is active, and the chip responds to 58h<3> = 1b (see the Distribution Power-Down section). commands. Individual Circuit Block Power-Down If the AD9511 clock outputs must be synchronized to each Many of the AD9511 circuit blocks (CLK1, CLK2, and REFIN, other, a SYNC (see the Single-Chip Synchronization section) is and so on) can be powered down individually. This gives required upon exiting power-down mode. flexibility in configuring the part for power savings whenever PLL Power-Down certain chip functions are not needed. The PLL section of the AD9511 can be selectively powered down. There are three PLL power-down modes, set by the values in Register 0Ah<1:0>, as shown in Table 19. Rev. A | Page 39 of 60

AD9511 RESET MODES Synchronization of two or more AD9511s requires a fast clock and a slow clock. The fast clock can be up to 1 GHz and may be The AD9511 has several ways to force the chip into a reset the clock driving the master AD9511 CLK1 input or one of the condition. outputs of the master. The fast clock acts as the input to the Power-On Reset—Start-Up Conditions when VS is distribution section of the slave AD9511 and is connected to its Applied CLK1 input. The PLL may be used on the master, but the slave A power-on reset (POR) is issued when the VS power supply is PLL is not used. turned on. This initializes the chip to the power-on conditions The slow clock is the clock that is synchronized across the two that are determined by the default register settings. These are chips. This clock must be no faster than one-fourth of the fast indicated in the default value column of Table 23. clock, and no greater than 250 MHz. The slow clock is taken Asynchronous Reset via the FUNCTION Pin from one of the outputs of the master AD9511 and acts as the REFIN (or CLK2) input to the slave AD9511. One of the As mentioned in the FUNCTION Pin section, a hard reset, outputs of the slave must provide this same frequency back to RESETB: 58h<6:5> = 00b (Default), restores the chip to the the CLK2 (or REFIN) input of the slave. default settings. Soft Reset via the Serial Port Multichip synchronization is enabled by writing to Register 58h<0> = 1b on the slave AD9511. When this bit is set, the The serial control port allows a soft reset by writing to STATUS pin becomes the output for the SYNC signal. A low Register 00h<5> = 1b. When this bit is set, the chip executes a signal indicates an in-sync condition, and a high indicates an soft reset. This restores the default values to the internal out-of-sync condition. registers, except for Register 00h itself. Register 58h<1> selects the number of fast clock cycles that are This bit is not self-clearing. The bit must be written to the maximum separation of the slow clock edges that are 00h<5> = 0b for the operation of the part to continue. considered synchronized. When 58h<1> = 0b (default), the SINGLE-CHIP SYNCHRONIZATION slow clock edges must be coincident within 1 to 1.5 high speed clock cycles. If the coincidence of the slow clock edges is closer SYNCB—Hardware SYNC than this amount, the SYNC flag stays low. If the coincidence of The AD9511 clocks can be synchronized to each other at any the slow clock edges is greater than this amount, the SYNC flag time. The outputs of the clocks are forced into a known state is set high. When Register 58h<1> = 1b, the amount of with respect to each other and then allowed to continue coincidence required is 0.5 fast clock cycles to 1 fast clock clocking from that state in synchronicity. Before a cycles. synchronization is done, the FUNCTION Pin must be set as the SYNCB: 58h<6:5> = 01b input (58h<6:5> = 01b). Whenever the SYNC flag is set (high), indicating an out-of-sync Synchronization is done by forcing the FUNCTION pin low, condition, a SYNCB signal applied simultaneously at the creating a SYNCB signal and then releasing it. FUNCTION pins of both AD9511s brings the slow clocks into synchronization. See the SYNCB: 58h<6:5> = 01b section for a more detailed description of what happens when the SYNCB: 58h<6:5> = 01b AD9511 signal is issued. MASTER FAST CLOCK OUTN Soft SYNC—Register 58h<2> <1GHz A soft SYNC may be issued by means of a bit in the Register FU(NSYCNTICOBN) SLOW CLOCK OUTM 58h<2>. This soft SYNC works the same as the SYNCB, except <250MHz FSYNC that the polarity is reversed. A 1 written to this bit forces the clock outputs into a known state with respect to each other. SYNCB When a 0 is subsequently written to this bit, the clock outputs CLK2 REFIN AD9511 continue clocking from that state in synchronicity. SLAVE CSLLOOCWK FSYNC MULTICHIP SYNCHRONIZATION <250MHz OUTY FAST CLOCK The AD9511 provides a means of synchronizing two or more CLK1 <1GHz DSEYTNECCT AD9511s. This is not an active synchronization; it requires user msyonnchitroorninizge adn ids sahcotiwonn. iTnh Fei gaurrraen 4g3e.m ent of two AD9511s to be FU(NSYCNTICOBN) S(STYANTCU)S 05286-093 Figure 43. Multichip Synchronization Rev. A | Page 40 of 60

AD9511 SERIAL CONTROL PORT The AD9511 serial control port is a flexible, synchronous, serial not brought high at the end of each write or read cycle (on a communications port that allows an easy interface with many byte boundary), the last byte is not loaded into the register industry-standard microcontrollers and microprocessors. The buffer. AD9511 serial control port is compatible with most CSB stall high is supported in modes where three or fewer bytes synchronous transfer formats, including both the Motorola SPI® of data (plus instruction data) are transferred (W1:W0 must be and Intel® SSR protocols. The serial control port allows set to 00, 01, or 10, see Table 20). In these modes, CSB can read/write access to all registers that configure the AD9511. temporarily return high on any byte boundary, allowing time Single or multiple byte transfers are supported, as well as MSB for the system controller to process the next byte. CSB can go first or LSB first transfer formats. The AD9511 serial control high on byte boundaries only and can go high during either port can be configured for a single bidirectional I/O pin (SDIO part (instruction or data) of the transfer. During this period, the only) or for two unidirectional I/O pins (SDIO/SDO). serial control port state machine enters a wait state until all data SERIAL CONTROL PORT PIN DESCRIPTIONS has been sent. If the system controller decides to abort the transfer before all of the data is sent, the state machine must be SCLK (serial clock) is the serial shift clock. This pin is an input. reset by either completing the remaining transfer or by SCLK is used to synchronize serial control port reads and returning the CSB low for at least one complete SCLK cycle (but writes. Write data bits are registered on the rising edge of this less than eight SCLK cycles). Raising the CSB on a nonbyte clock, and read data bits are registered on the falling edge. This boundary terminates the serial transfer and flushes the buffer. pin is internally pulled down by a 30 kΩ resistor to ground. In the streaming mode (W1:W0 = 11b), any number of data SDIO (serial data input/output) is a dual-purpose pin and acts bytes can be transferred in a continuous stream. The register as either an input only or as both an input/output. The AD9511 address is automatically incremented or decremented (see the defaults to two unidirectional pins for I/O, with SDIO used as MSB/LSB First Transfers section). CSB must be raised at the an input and SDO as an output. Alternatively, SDIO can be used end of the last byte to be transferred, thereby ending the as a bidirectional I/O pin by writing to the SDO enable register stream mode. at 00h<7> = 1b. Communication Cycle—Instruction Plus Data SDO (serial data out) is used only in the unidirectional I/O mode (00h<7> = 0b, default) as a separate output pin for There are two parts to a communication cycle with the AD9511. reading back data. The AD9511 defaults to this I/O mode. The first writes a 16-bit instruction word into the AD9511, Bidirectional I/O mode (using SDIO as both input and output) coincident with the first 16 SCLK rising edges. The instruction may be enabled by writing to the SDO enable register at word provides the AD9511 serial control port with information 00h<7> = 1b. regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether CSB (chip select bar) is an active low control that gates the read the upcoming data transfer is a read or a write, the number of and write cycles. When CSB is high, SDO and SDIO are in a bytes in the data transferred, and the starting register address high impedance state. This pin is internally pulled down by a for the first byte of the data transfer. 30 kΩ resistor to ground. It should not be left NC or tied low. See the Framing a Communication Cycle with CSB section on Write the use of the CSB in a communication cycle. If the instruction word is for a write operation (I15 = 0b), the SCLK (PIN 14) second part is the transfer of data into the serial control port AD9511 SDIO (PIN 15) buffer of the AD9511. The length of the transfer (1, 2, 3 bytes or SERIAL SCDSOB ((PPIINN 1167)) COPNOTRRTOL 05286-094 sintrsetarumcitniogn m boydtee.) C isS Bin cdaicna bteed r baiys etwd oa fbteitrs e(aWch1 :sWeq0u)e innc eth oef eight bits to stall the bus (except after the last byte, where it ends the Figure 44. Serial Control Port cycle). When the bus is stalled, the serial transfer resumes when GENERAL OPERATION OF SERIAL CONTROL PORT CSB is lowered. Stalling on nonbyte boundaries resets the serial Framing a Communication Cycle with CSB control port. Each communication cycle (a write or a read operation) is gated Since data is written into a serial control port buffer area, not by the CSB line. CSB must be brought low to initiate a directly into the AD9511’s actual control registers, an additional communication cycle. CSB must be brought high at the operation is needed to transfer the serial control port buffer completion of a communication cycle (see Figure 52). If CSB is contents to the actual control registers of the AD9511, thereby causing them to take effect. This update command consists of Rev. A | Page 41 of 60

AD9511 writing to Register 5Ah<0> = 1b. This update bit is self-clearing For a write, the instruction word is followed by the number of (it is not required to write 0 to it to clear it). Since any number bytes of data indicated by Bits W1:W0, which is interpreted of bytes of data can be changed before issuing an update according to Table 20. command, the update simultaneously enables all register Table 20. Byte Transfer Count changes since any previous update. W1 W0 Bytes to Transfer Phase offsets or divider synchronization is not effective until a 0 0 1 SYNC is issued (see the Single-Chip Synchronization section). 0 1 2 1 0 3 Read 1 1 4 If the instruction word is for a read operation (I15 = 1b), the A12:A0: These 13 bits select the address within the register map next N × 8 SCLK cycles clock out the data from the address that is written to or read from during the data transfer portion specified in the instruction word, where N is 1 to 4 as of the communications cycle. The AD9511 does not use all of determined by W1:W0. The readback data is valid on the falling the 13-bit address space. Only Bits A6:A0 are needed to cover edge of SCLK. the range of the 5Ah registers used by the AD9511. Bits A12:A7 The default mode of the AD9511 serial control port is must always be 0b. For multibyte transfers, this address is the unidirectional mode; therefore, the requested data appears on starting byte address. In MSB first mode, subsequent bytes the SDO pin. It is possible to set the AD9511 to bidirectional increment the address. mode by writing the SDO enable register at 00h<7> = 1b. In MSB/LSB FIRST TRANSFERS bidirectional mode, the readback data appears on the SDIO pin. The AD9511 instruction word and byte data may be MSB first A readback request reads the data that is in the serial control or LSB first. The default for the AD9511 is MSB first. The LSB port buffer area, not the active data in the AD9511’s actual first mode may be set by writing 1b to Register 00h<6>. This control registers. takes effect immediately (since it only affects the operation of the serial control port) and does not require that an update be executed. Immediately after the LSB first bit is set, all serial S control port operations are changed to LSB first order. S R R E E T SCLK UFF GIS When MSB first mode is active, the instruction and data bytes SDIO B E must be written from MSB to LSB. Multibyte data transfers in SCDSOB STER UPDATE ROL R MSB first format start with an instruction byte that includes the REGI RE5GAIhS <T0E>RS ONT rdeagtias tbeyrt easd dmruessst foofl tlohwe mino ostr dsiegrn firfoicman hti gdhat aad bdyrtees. sS tuob lsoewqu ent SCPEOORRNITTARLOL C ADCO9R5E11 05286-095 aaddddrreessss . gIenn MerSatBo rfi drsetc mreomdeen, ttsh feo sre eraiaclh c doanttar obly pteo rotf itnhtee rnal Figure 45. Relationship Between Serial Control Port Register Buffers and multibyte transfer cycle. Control Registers of the AD9511 When LSB_First = 1b (LSB first), the instruction and data bytes The AD9511 uses Address 00h to Address 5Ah. Although the must be written from LSB to MSB. Multibyte data transfers in AD9511 serial control port allows both 8-bit and 16-bit LSB first format start with an instruction byte that includes the instructions, the 8-bit instruction mode provides access to five register address of the least significant data byte followed by address bits (A4 to A0) only, which restricts its use to the multiple data bytes. The serial control port internal byte address address space 00h to 01F. The AD9511 defaults to 16-bit generator increments for each byte of the multibyte transfer instruction mode on power-up. The 8-bit instruction mode cycle. (although defined for this serial control port) is not useful for the AD9511; therefore, it is not discussed further in this data The AD9511 serial control port register address decrements sheet. from the register address just written toward 0000h for multibyte I/O operations if the MSB first mode is active THE INSTRUCTION WORD (16 BITS) (default). If the LSB first mode is active, the serial control port The MSB of the instruction word is R/W, which indicates register address increments from the address just written whether the instruction is a read or a write. The next two bits, toward 1FFFh for multibyte I/O operations. W1:W0, indicate the length of the transfer in bytes. The final 13 bits are the addresses (A12:A0) at which to begin the read or Unused addresses are not skipped during multibyte I/O write operation. operations; therefore, it is important to avoid multibyte I/O operations that would include these addresses. Rev. A | Page 42 of 60

AD9511 Table 21. Serial Control Port, 16-Bit Instruction Word, MSB First MSB LSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R/W W1 W0 A12 = 0 A11 = 0 A10 = 0 A9 = 0 A8 = 0 A7 = 0 A6 A5 A4 A3 A2 A1 A0 CSB SCLKDON'T CARE DON'T CARE SDIODON'T CARE R/W W1 W0 A12A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N– 1) DATA 05286-019 Figure 46. Serial Control Port Write—MSB First, 16-Bit Instruction, 2 Bytes of Data CSB SCLK DON'T CARE DON'T CARE SDIO R/WW1W0A12A11A10A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDO DON'T CARE D7 D6 D5D4 D3 D2D1 D0 D7 D6 D5D4 D3 D2D1 D0 D7 D6 D5D4 D3 D2D1 D0 D7 D6 D5D4 D3 D2D1 D0 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N– 1) DATA REGISTER (N– 2) DATA REGISTER (N– 3) DATA DCOANR'ET 05286-020 Figure 47. Serial Control Port Read—MSB First, 16-Bit Instruction, 4 Bytes od Data t DS t tS t HI tCLK tH DH t CSB LO SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 05286-021 Figure 48. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements CSB SCLK t DV SSDDIOO DATA BIT N DATA BIT N– 1 05286-022 Figure 49. Timing Diagram for Serial Control Port Register Read CSB SCLKDON'T CARE DON'T CARE SDIODON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10A11A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA 05286-023 Figure 50. Serial Control Port Write—LSB First, 16-Bit Instruction, 2 Bytes Data Rev. A | Page 43 of 60

AD9511 t t S H CSB t CLK t t HI LO t DS SCLK t DH SDIO BI N BI N + 1 05286-040 Figure 51. Serial Control Port Timing—Write Table 22. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between CSB and SCLK S t Hold time between CSB and SCLK H t Minimum period that SCLK should be in a logic high state HI t Minimum period that SCLK should be in a logic low state LO CSBTOGGLE INDICATES CYCLE COMPLETE CSB tPWH 16 INSTRUCTION BITS + 8 DATA BITS 16 INSTRUCTION BITS + 8 DATA BITS SCLK SDIO COMMUNICATION CYCLE 1 COMMUNICATION CYCLE 2 TBIEMTINOGG DGILAEGDR HAIMG HFOARN DT WTHOE SNU LCOCWESASTI VTEH EC OCMOMMPULNEICTAIOTINO ON FC AY CCLOEMSM. NUONITCEA TTHIOANT CCYSCBL MEU.ST 05286-067 Figure 52. Use of CSB to Define Communications Cycles Rev. A | Page 44 of 60

AD9511 REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 23. AD9511 Register Map Def. Addr Bit 0 Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Notes 00 Serial SDO Inactive LSB Soft Long Not Used 10 Control Port (Bidirectional First Reset Instruction Configuration Mode) 01, Not Used 02, 03 PLL PLL Starts in Power- Down 04 A Counter Not Used 6-Bit A Counter <5:0> 00 N Divider (A) 05 B Counter Not Used 13-Bit B Counter Bits 12:8 (MSB) <4:0> 00 N Divider (B) 06 B Counter 13-Bit B Counter Bits 7:0 (LSB) <7:0> 00 N Divider (B) 07 PLL 1 Not LOR Lock_Del Not Used LOR Not Used 00 Used <6:5> Enable 08 PLL 2 Not PFD PLL Mux Select <5:2> CP Mode <1:0> 00 Used Polarity Signal on STATUS pin 09 PLL 3 Not CP Current <6:4> Not Reset R Reset N Reset All 00 Used Used Counter Counter Counters 0A PLL 4 Not B Not Prescaler P <4:2> Power-Down <1:0> 01 N Divider Used Bypass Used (P) 0B R Divider Not Used 14-Bit R Divider Bits 13:8 (MSB) <5:0> 00 R Divider 0C R Divider 14-Bit R Divider Bits 13:8 (MSB) <7:0> 00 R Divider 0D PLL 5 Not Digital Digital Not Used Antibacklash 00 Used Lock Lock Pulse Width <1:0> Det Det Enable Window OE- Not Used 33 FINE DELAY Fine ADJUST Delays Bypassed 34 Delay Bypass 4 Not Used Bypass 01 Bypass Delay 35 Delay Not Used Ramp Capacitor <5:3> Ramp Current <2:0> 00 Max. Full-Scale 4 Delay Full-Scale 36 Delay Fine Not Used 5-Bit Fine Delay <5:1> Not 00 Min. Delay Adjust 4 Used Value 37, Not Used 38, 39, 3A, 3B, 3C Rev. A | Page 45 of 60

AD9511 Def. Addr Bit 0 Value (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Notes OUTPUTS 3D LVPECL OUT0 Not Used Output Level Power-Down <1:0> 08 ON <3:2> 3E LVPECL OUT1 Not Used Output Level Power-Down <1:0> 08 ON <3:2> 3F LVPECL OUT2 Not Used Output Level Power-Down <1:0> 08 ON <3:2> 40 LVDS_CMOS Not Used CMOS Logic Output Level Output 02 LVDS, ON OUT 3 Inverted Select <2:1> Power Driver On 41 LVDS_CMOS Not Used CMOS Logic Output Level Output 02 LVDS, ON OUT 4 Inverted Select <2:1> Power Driver On 42, Not Used 43, 44 CLK1 AND Input CLK2 Receivers 45 Clocks Select, Not Used CLKs in REFIN PD CLK CLK2 CLK1 Select 01 All Clocks Power-Down PD to PD PD CLK IN ON, Select (PD) Options PLL CLK1 PD 46, Not Used 47, 48, 49 DIVIDERS 4A Divider 0 Low Cycles <7:4> High Cycles <3:0> 00 Divide by 2 4B Divider 0 Bypass No Force Start H/L Phase Offset <3:0> 00 Phase = 0 Sync 4C Divider 1 Low Cycles <7:4> High Cycles <3:0> 11 Divide by 4 4D Divider 1 Bypass No Force Start H/L Phase Offset <3:0> 00 Phase = 0 Sync 4E Divider 2 Low Cycles <7:4> High Cycles <3:0> 33 Divide by 8 4F Divider 2 Bypass No Force Start H/L Phase Offset <3:0> 00 Phase = 0 Sync 50 Divider 3 Low Cycles <7:4> High Cycles <3:0> 00 Divide by 2 51 Divider 3 Bypass No Force Start H/L Phase Offset <3:0> 00 Phase = 0 Sync 52 Divider 4 Low Cycles <7:4> High Cycles <3:0> 11 Divide by 4 53 Divider 4 Bypass No Force Start H/L Phase Offset <3:0> 00 Phase = 0 Sync 54, Not Used 55, 56, 57 FUNCTION 58 FUNCTION Not Set FUNCTION Pin PD Sync PD All Sync Sync Sync 00 FUNCTION Pin and Sync Used Ref Reg Select Enable Pin = RESETB 59 Not Used 5A Update Not Used Update 00 Self- Registers Registers Clearing Bit END Rev. A | Page 46 of 60

AD9511 REGISTER MAP DESCRIPTION Table 24 lists the AD9511 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 24 describes the functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 23. Table 24. AD9511 Register Descriptions Reg. Addr. (Hex) Bit(s) Name Description Serial Control Port Any changes to this register takes effect immediately. Register 5Ah<0> Update Registers does not Configuration have to be written. 00 <3:0> Not Used. 00 <4> Long Instruction When this bit is set (1), the instruction phase is 16 bits. When clear (0), the instruction phase is 8 bits. The default, and only, mode for this part is long instruction (Default = 1b). 00 <5> Soft Reset When this bit is set (1), the chip executes a soft reset, restoring default values to the internal registers, except for this register, 00h. This bit is not self-clearing. A clear (0) has to be written to it to clear it. 00 <6> LSB First When this bit is set (1), the input and output data is oriented as LSB first. Additionally, register addressing increments. If this bit is clear (0), data is oriented as MSB first and register addressing decrements. (Default = 0b, MSB first). 00 <7> SDO Inactive When set (1), the SDO pin is tri-state and all read data goes to the SDIO pin. When clear (0), the (Bidirectional SDO is active (unidirectional mode). (Default = 0b). Mode) Not Used 01 <7:0> Not Used. 02 <7:0> Not Used. 03 <7:0> Not Used. PLL Settings 04 <5:0> A Counter 6-Bit A Counter <5:0>. 04 <7:6> Not Used. 05 <4:0> B Counter MSBs 13-Bit B Counter (MSB) <12:8>. 05 <7:5> Not Used. 06 <7:0> B Counter LSBs 13-Bit B Counter (LSB) <7:0>. 07 <1:0> Not Used. 07 <2> LOR Enable 1 = Enables the Loss-of-Reference (LOR) Function; (Default = 0b). 07 <4:3> Not Used. 07 <6:5> LOR Initial Lock LOR Initial Lock Detect Delay. Once a lock detect is indicated, this is the number of phase frequency Detect Delay detector (PFD) cycles that occur prior to turning on the LOR monitor. <6> <5> LOR Initial Lock Detect Delay 0 0 3 PFD Cycles (Default) 0 1 6 PFD Cycles 1 0 12 PFD Cycles 1 1 24 PFD Cycles 07 <7> Not Used 08 <1:0> Charge Pump Mode <1> <0> Charge Pump Mode 0 0 Tri-Stated (Default) 0 1 Pump-Up 1 0 Pump-Down 1 1 Normal Operation Rev. A | Page 47 of 60

AD9511 Reg. Addr. (Hex) Bit(s) Name Description 08 <5:2> PLL Mux Control <5> <4> <3> <2> MUXOUT—Signal on STATUS Pin 0 0 0 0 Off (Signal Goes Low) (Default) 0 0 0 1 Digital Lock Detect (Active High) 0 0 1 0 N Divider Output 0 0 1 1 Digital Lock Detect (Active Low) 0 1 0 0 R Divider Output 0 1 0 1 Analog Lock Detect (N Channel, Open-Drain) 0 1 1 0 A Counter Output 0 1 1 1 Prescaler Output (NCLK) 1 0 0 0 PFD Up Pulse 1 0 0 1 PFD Down Pulse 1 0 1 0 Loss-of-Reference (Active High) 1 0 1 1 Tri-State 1 1 0 0 Analog Lock Detect (P Channel, Open-Drain) 1 1 0 1 Loss-of-Reference or Loss-of-Lock (Inverse of DLD) (Active High) 1 1 1 0 Loss-of-Reference or Loss-of-Lock (Inverse of DLD) (Active Low) 1 1 1 1 Loss-of-Reference (Active Low) MUXOUT is the PLL portion of the STATUS output MUX. 08 <6> Phase-Frequency 0 = Negative (Default), 1 = Positive. Detector (PFD) Polarity 08 <7> Not Used. 09 <0> Reset All Counters 0 = Normal (Default), 1 = Reset R, A, and B Counters. 09 <1> N-Counter Reset 0 = Normal (Default), 1 = Reset A and B Counters. 09 <2> R-Counter Reset 0 = Normal (Default), 1 = Reset R Counter. 09 <3> Not Used. 09 <6:4> Charge Pump (CP) Current Setting <6> <5> <4> I (mA) CP 0 0 0 0.60 0 0 1 1.2 0 1 0 1.8 0 1 1 2.4 1 0 0 3.0 1 0 1 3.6 1 1 0 4.2 1 1 1 4.8 Default = 000b. These currents assume: CPR = 5.1 kΩ. SET Actual current can be calculated by: CP_lsb = 3.06/CPR . SET 09 <7> Not Used. Rev. A | Page 48 of 60

AD9511 Reg. Addr. (Hex) Bit(s) Name Description 0A <1:0> PLL Power-Down 01 = Asynchronous Power-Down (Default). <1> <0> Mode 0 0 Normal Operation 0 1 Asynchronous Power-Down 1 0 Normal Operation 1 1 Synchronous Power-Down 0A <4:2> Prescaler Value (P/P+1) <4> <3> <2> Mode Prescaler Mode 0 0 0 FD Divide by 1 0 0 1 FD Divide by 2 0 1 0 DM 2/3 0 1 1 DM 4/5 1 0 0 DM 8/9 1 0 1 DM 16/17 1 1 0 DM 32/33 1 1 1 FD Divide by 3 DM = Dual Modulus, FD = Fixed Divide. 0A <5> Not Used. 0A <6> B Counter Bypass Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is divided by 1. This allows the prescaler setting to determine the divide for the N divider. 0A <7> Not Used. 0B <5:0> 14-Bit Reference R Divider (MSB) <13:8>. Counter, MSBs 0C <7:0> 14-Bit Reference R Divider (MSB) <7:0>. Counter, R LSBs 0D <1:0> Antibacklash Pulse-Width <1> <0> Antibacklash Pulse Width (ns) 0 0 1.3 (Default) 0 1 2.9 1 0 6.0 1 1 1.3 0D <4:2> Not Used. 0D <5> Digital Lock Detect Window <5> Digital Lock Detect Window (ns) Digital Lock Detect Loss-of-Lock Threshold (ns) 0 (Default) 9.5 15 1 3.5 7 Digital Lock If the time difference of the rising edges at the inputs to the PFD are less than the lock detect Detect Window window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. 0D <6> Lock Detect 0 = Normal Lock Detect Operation (Default). Disable 1 = Disable Lock Detect. 0D <7> Not Used. Unused 0E-33 Not Used. Rev. A | Page 49 of 60

AD9511 Reg. Addr. (Hex) Bit(s) Name Description Fine Delay Adjust 34 <0> Delay Control Delay Block Control Bit. OUT4 Bypasses Delay Block and Powers It Down (Default = 1b). 34 <7:1> Not Used. 35 <2:0> Ramp Current The slowest ramp (200 μs) sets the longest full scale of approximately 10 ns. OUT4 <2> <1> <0> Ramp Current (μs) 0 0 0 200 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 35 <5:3> Ramp Capacitor Selects the Number of Capacitors in Ramp Generation Circuit. OUT4 More Capacitors => Slower Ramp. <5> <4> <3> Number of Capacitors 0 0 0 4 (Default) 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 35 <7:6> Not Used. 36 <0> Not Used. 36 <5:1> Delay Fine Adjust Sets Delay Within Full Scale of the Ramp; There Are 32 Steps. OUT4 00000b => Zero Delay (Default). 11111b => Maximum Delay. 36 <7:6> Not Used. 37 (38) (39) <7:0> Not Used. (3A) (3B) (3C) 3D (3E) (3F) <1:0> Power-Down LVPECL OUT0 (OUT1) (OUT2) Mode <1> <0> Description Output ON 0 0 Normal Operation ON PD1 0 1 Test Only—Do Not Use OFF PD2 1 0 Safe Power-Down OFF Partial Power-Down; Use If Output Has Load Resistors PD3 1 1 Total Power-Down OFF Use Only If Output Has No Load Resistors Rev. A | Page 50 of 60

AD9511 Reg. Addr. (Hex) Bit(s) Name Description 3D (3E) (3F) <3:2> Output Level Output Single-Ended Voltage Levels for LVPECL Outputs. LVPECL OUT0 (OUT1) (OUT2) <3> <2> Output Voltage (mV) 0 0 490 0 1 330 1 0 805 (Default) 1 1 650 3D (3E) (3F) <7:4> Not Used 40 (41) <0> Power-Down Power-Down Bit for Both Output and LVDS Driver. LVDS/CMOS 0 = LVDS/CMOS on (Default). OUT3 1 = LVDS/CMOS Power-Down. (OUT4) 40 (41) <2:1> Output Current Level LVDS OUT3 (OUT4) <2> <1> Current (mA) Termination (Ω) 0 0 1.75 100 0 1 3.5 (Default) 100 1 0 5.25 50 1 1 7 50 40 (41) <3> LVDS/CMOS 0 = LVDS (Default). Select 1 = CMOS. OUT3 (OUT4) 40 (41) <4> Inverted CMOS Affects Output Only when in CMOS Mode. Driver 0 = Disable Inverted CMOS Driver (Default). OUT3 1 = Enable Inverted CMOS Driver. (OUT4) 40 (41) <7:5> Not Used. 42 (43) (44) <7:0> Not Used. 45 <0> Clock Select 0: CLK2 Drives Distribution Section. 1: CLK1 Drives Distribution Section (Default). 45 <1> CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b). 45 <2> CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b). 45 <3> Prescaler Clock 1 = Shut Down Clock Signal to PLL Prescaler (Default = 0b). Power-Down 45 <4> REFIN Power- 1 = Power-Down REFIN (Default = 0b). Down 45 <5> All Clock Inputs 1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree; Power-Down (Default = 0b). 45 <7:6> Not Used. 46 (47) <7:0> Not Used. (48) (49) Rev. A | Page 51 of 60

AD9511 Reg. Addr. (Hex) Bit(s) Name Description <3:0> Divider High Number of Clock Cycles Divider Output Stays High. 4A OUT0 (4C) (OUT1) (4E) (OUT2) (50) (OUT3) (52) (OUT4) <7:4> Divider Low Number of Clock Cycles Divider Output Stays Low. 4A OUT0 (4C) (OUT1) (4E) (OUT2) (50) (OUT3) (52) (OUT4) <3:0> Phase Offset Phase Offset (Default = 0000b). 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <4> Start Selects Start High or Start Low. 4B OUT0 (Default = 0b). (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <5> Force Forces Individual Outputs to the State Specified in Start (Above). This Function Requires That Nosync (Below) Also Be Set (Default = 0b). 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <6> Nosync Ignore Chip-Level Sync Signal (Default = 0b). 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) <7> Bypass Divider Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b). 4B OUT0 (4D) (OUT1) (4F) (OUT2) (51) (OUT3) (53) (OUT4) 54 (55) <7:0> Not Used. (56) (57) 58 <0> SYNC Detect 1 = Enable SYNC Detect (Default = 0b). Enable 58 <1> SYNC Select 1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles. 0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles. Rev. A | Page 52 of 60

AD9511 Reg. Addr. (Hex) Bit(s) Name Description 58 <2> Soft SYNC Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s polarity is reversed. That is, a high level forces selected outputs into a known state, and a high > low transition triggers a sync (Default = 0b). 58 <3> Dist Ref Power- 1 = Power-Down the References for the Distribution Section (Default = 0b). Down 58 <4> SYNC Power- 1 = Power-Down the SYNC (Default = 0b). Down 58 <6:5> FUNCTION Pin Select <6> <5> Function 0 0 RESETB (Default) 0 1 SYNCB 1 0 Test Only; Do Not Use 1 1 PDB 58 <7> Not Used 59 <7:0> Not Used 5A <0> Update Registers 1 written to this bit updates all registers and transfers all serial control port register buffer contents to the control registers on the next rising SCLK edge. This is a self-clearing bit. 0 does not have to be written to clear it. 5A <7:1> Not Used. END Rev. A | Page 53 of 60

AD9511 POWER SUPPLY The AD9511 requires a 3.3 V ± 5% power supply for V. POWER MANAGEMENT S The tables in the Specifications section give the performance The power usage of the AD9511 can be managed to use only the expected from the AD9511 with the power supply voltage power required for the functions that are being used. Unused within this range. The absolute maximum range of −0.3 V to features and circuitry can be powered down to save power. The +3.6 V, with respect to GND, must never be exceeded on following circuit blocks can be powered down, or are powered the VS pin. down when not selected (see the Register Map and Description section): Good engineering practice should be followed in the layout of power supply traces and ground plane of the PCB. The power • The PLL section can be powered down if not needed. supply should be bypassed on the PCB with adequate capacitance (>10 μF). The AD9511 should be bypassed with • Any of the dividers are powered down when bypassed— adequate capacitors (0.1 μF) at all power pins, as close as equivalent to divide-by-one. possible to the part. The layout of the AD9511 evaluation board (AD9511/PCB or AD9511-VCO/PCB) is a good example. • The adjustable delay block on OUT4 is powered down when not selected. The AD9511 is a complex part that is programmed for its desired operating configuration by on-chip registers. These • Any output may be powered down. However, LVPECL registers are not maintained over a shutdown of external power. outputs have both a safe and an off condition. When the This means that the registers can lose their programmed values LVPECL output is terminated, only the safe shutdown if V is lost long enough for the internal voltages to collapse. should be used to protect the LVPECL output devices. This S Careful bypassing should protect the part from memory loss still consumes some power. under normal conditions. Nonetheless, it is important that the • The entire distribution section can be powered down when V power supply not become intermittent, or the AD9511 risks S not needed. losing its programming. Powering down a functional block does not cause the The internal bias currents of the AD9511 are set by the R and SET programming information for that block (in the registers) to be CPR resistors. These resistors should be as close as possible to SET lost. This means that blocks can be powered on and off without the values given as conditions in the Specifications section otherwise having to reprogram the AD9511. However, (R = 4.12 kΩ and CPR = 5.1 kΩ). These values are standard SET SET synchronization is lost. A SYNC must be issued to 1% resistor values and should be readily obtainable. The bias resynchronize (see the Single-Chip Synchronization section). currents set by these resistors determine the logic levels and operating conditions of the internal blocks of the AD9511. The performance figures given in the Specifications section assume that these resistor values are used. The VCP pin is the supply pin for the charge pump (CP). The voltage at this pin (V ) may be from V up to 5.5 V, as required CP S to match the tuning voltage range of a specific VCO/VCXO. This voltage must never exceed the absolute maximum of 6 V. V should also never be allowed to be less than −0.3 V below CP V or GND, whichever is lower. S The exposed metal paddle on the AD9511 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The PCB acts as a heat sink for the AD9511; therefore, this GND connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the PCB. See the layout of the AD9511 evaluation board (AD9511/PCB or AD9511-VCO/PCB) for a good example. Rev. A | Page 54 of 60

AD9511 APPLICATIONS USING THE AD9511 OUTPUTS FOR ADC CLOCK level, termination) should be considered when selecting the best clocking/converter solution. APPLICATIONS Any high speed analog-to-digital converter (ADC) is extremely CMOS CLOCK DISTRIBUTION sensitive to the quality of the sampling clock provided by the The AD9511 provides two clock outputs (OUT3 and OUT4), user. An ADC can be thought of as a sampling mixer; any noise, which are selectable as either CMOS or LVDS levels. When distortion, or timing jitter on the clock is combined with the selected as CMOS, these outputs provide for driving devices desired signal at the A/D output. Clock integrity requirements requiring CMOS level logic at their clock inputs. scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution Whenever single-ended CMOS clocking is used, some of the being the most stringent. The theoretical SNR of an ADC is following general guidelines should be followed. limited by the ADC resolution and the jitter on the sampling Point-to-point nets should be designed such that a driver has clock. Considering an ideal ADC of infinite resolution where one receiver only on the net, if possible. This allows for simple the step size and quantization error can be ignored, the available termination schemes and minimizes ringing due to possible SNR can be expressed approximately by mismatched impedances on the net. Series termination at the ⎡ 1 ⎤ source is generally required to provide transmission line SNR=20×log⎢ ⎥ matching and/or to reduce current transients at the driver. The ⎢⎣2πftj⎥⎦ value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS where f is the highest analog frequency being digitized, and t is j outputs are limited in terms of the capacitive load or trace the rms jitter on the sampling clock. Figure 53 shows the length that they can drive. Typically, trace lengths less than required sampling clock jitter as a function of the analog 3 inches are recommended to preserve signal rise/fall times and frequency and effective number of bits (ENOB). preserve signal integrity. tj = 50fs 1 60.4Ω 120 SNR = 20log10 2πftj 10Ω 1.0 INCH 18 CMOS tj = 0.1ps MICROSTRIP 100 16 R (dB) 80 tjt =j = 1 01ppss 1124 NOB 50pFGND 05286-096 N E Figure 54. Series Termination of CMOS Output S 10 60 Termination at the far end of the PCB trace is a second option. tj = 100ps 8 The CMOS outputs of the AD9511 do not supply enough 40 6 current to provide a full voltage swing with a low impedance 20 tj = 1ns 4 05286-024 erensdis tteivrem, ifnara-teionnd nteertmwoinrkat siohno,u alds smhoatwchn tinhe F PigCuBre t r5a5c. eT he far- 1 3 10 30 100 impedance and provide the desired switching point. The FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz) reduced signal swing can still meet receiver input requirements Figure 53. ENOB and SNR vs. Analog Input Frequency in some applications. This may be useful when driving long trace lengths on less critical nets. See Application Notes AN-756 and AN-501 on the ADI website at www.analog.com. VPULLUP = 3.3V Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on 10Ω 50Ω 100Ω CMOS a noisy PCB. (Distributing a single-ended clock on a noisy PCB OUT3, OUT4 100Ω 3pF can result in coupled noise on the sample clock. Differential SELECTED AS CMOS dprisotvriidbue tsiuopne hriaosr i nclhoecrke npte rcfoomrmmaonnc-em ino dae n roeijseyc teinovni,r wonhmichen cta.)n 05286-097 The AD9511 features both LVPECL and LVDS outputs that Figure 55. CMOS Output with Far-End Termination provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or single-ended, logic Rev. A | Page 55 of 60

AD9511 Because of the limitations of single-ended CMOS clocking, LVDS CLOCK DISTRIBUTION consider using differential outputs when driving high speed Low voltage differential signaling (LVDS) is a second signals over long traces. The AD9511 offers both LVPECL and differential output option for the AD9511. LVDS uses a current LVDS outputs, which are better suited for driving long traces mode output stage with several user-selectable current levels. where the inherent noise immunity of differential signaling The normal value (default) for this current is 3.5 mA, which provides superior performance for clocking converters. yields 350 mV output swing across a 100 Ω resistor. The LVDS LVPECL CLOCK DISTRIBUTION outputs meet or exceed all ANSI/TIA/EIA—644 specifications. The low voltage, positive emitter-coupled, logic (LVPECL) A recommended termination circuit for the LVDS outputs is outputs of the AD9511 provide the lowest jitter clock signals shown in Figure 58. available from the AD9511. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output 3.3V 3.3V transistors. A simplified equivalent circuit in Figure 41 shows the LVPECL output stage. 100Ω LVDS 100Ω LVDS DIFFERENTIAL (COUPLED) In most applications, a standard LVPECL far-end termination is recommended, as shown in Figure 56. The resistor network is dthees idgenseidre tdo smwaittcchhi nthge t htrraensshmolidss (i1o.n3 lVin)e. impedance (50 Ω) and 05286-032 3.3V Figure 58. LVDS Output Termination See Application Note AN-586 on the ADI website at 3.3V 3.3V 50Ω 127Ω 127Ω www.analog.com for more information on LVDS. POWER AND GROUNDING CONSIDERATIONS AND SINGLE-ENDED LVPECL LVPECL (NOT COUPLED) POWER SUPPLY REJECTION Many applications seek high speed and performance under less 50Ω than ideal operating conditions. In these application circuits, VT = VCC– 1.3V 83Ω 83Ω 05286-030 timhep iomrtpalnemt aesn tthaeti coinrc aunidt dceosnigstnr.u Pcrtoiopne ro Rf tFh tee PchCnBi qisu eass must be Figure 56. LVPECL Far-End Termination used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance. 3.3V 3.3V 0.1nF DIFFERENTIAL LVPECL 100Ω LVPECL 0.1nF (COUPLED) 200Ω 200Ω 05286-031 Figure 57. LVPECL with Parallel Transmission Line Rev. A | Page 56 of 60

AD9511 OUTLINE DIMENSIONS 0.30 7.00 0.60 MAX 0.23 BSC SQ 0.60 MAX 0.18 PIN 1 INDICATOR 37 48 PIN 1 36 1 INDICATOR EXPOSED TOP 6.75 5.25 VIEW BSC SQ PAD 5.10 SQ (BOTTOM VIEW) 4.95 0.50 0.40 25 12 24 13 0.30 0.25 MIN 5.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM 0.50 BSC COPLANARITY 0.20REF 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 59. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9511BCPZ1 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 AD9511BCPZ-REEL71 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1 AD9511/PCB Evaluation Board without VCO, VCXO, or Loop Filter AD9511-VCO/PCB Evaluation Board with 245.76 MHz VCXO, Loop Filter 1 Z = Pb-free part. Rev. A | Page 57 of 60

AD9511 NOTES Rev. A | Page 58 of 60

AD9511 NOTES Rev. A | Page 59 of 60

AD9511 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05286–0–6/05(A) Rev. A | Page 60 of 60