16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9266 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD AGND SDIOSCLK CSB DRVDD 1.8 V to 3.3 V output supply SNR RBIAS SPI AD9266 77.6 dBFS at 9.7 MHz input VCM ER OR F 71.1 dBFS at 200 MHz input VIN+ PROGRAMMING DATA SUF D15_D14 SFDR CAODRCE MOT B 8 VIN– CPU D1_D0 93 dBc at 9.7 MHz input UT O 80 dBc at 200 MHz input DCO VREF Low power SENSE 56 mW at 20 MSPS REF 113 mW at 80 MSPS SELECT Differential input with 700 MHz bandwidth DIVIDE DUTY CYCLE MODE 1TO 8 STABILIZER CONTROLS On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input CLK+CLK– PDWNDFS MODE 08678-001 DNL = −0.6/+1.1 LSB Figure 1. Interleaved data output for reduced pin-count interface Serial port control options Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer PRODUCT HIGHLIGHTS Integer 1-to-8 input clock divider Built-in selectable digital test pattern generation 1. The AD9266 operates from a single 1.8 V analog power Energy-saving power-down modes supply and features a separate digital output driver supply Data clock output (DCO) with programmable clock and to accommodate 1.8 V to 3.3 V logic families. data alignment 2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is APPLICATIONS designed for low cost, low power, and ease of use. 3. A standard serial port interface supports various product Communications features and functions, such as data output formatting, Diversity radio systems internal clock divider, power-down, DCO and data output Multimode digital receivers (D15_D14 to D1_D0) timing and offset adjustments, and GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA voltage reference modes. Smart antenna systems Battery-powered instruments 4. The AD9266 is packaged in a 32-lead RoHS-compliant Handheld scope meters LFCSP that is pin compatible with the AD9609 10-bit Portable medical imaging ADC, the AD9629 12-bit ADC, and the AD9649 14-bit Ultrasound ADC, enabling a simple migration path between 10-bit and Radar/LIDAR 16-bit converters sampling from 20 MSPS to 80 MSPS. PET/SPECT imaging Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD9266 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 19 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 20 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 22 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 22 Revision History ............................................................................... 2 Timing ......................................................................................... 23 General Description ......................................................................... 3 Output Test ...................................................................................... 24 Specifications ..................................................................................... 4 Output Test Modes ..................................................................... 24 DC Specifications ......................................................................... 4 Serial Port Interface (SPI) .............................................................. 25 AC Specifications .......................................................................... 5 Configuration Using the SPI ..................................................... 25 Digital Specifications ................................................................... 6 Hardware Interface ..................................................................... 26 Switching Specifications .............................................................. 7 Configuration Without the SPI ................................................ 26 Timing Specifications .................................................................. 8 SPI Accessible Features .............................................................. 26 Absolute Maximum Ratings ............................................................ 9 Memory Map .................................................................................. 27 Thermal Characteristics .............................................................. 9 Reading the Memory Map Register Table ............................... 27 ESD Caution .................................................................................. 9 Open Locations .......................................................................... 27 Pin Configuration and Function Descriptions ........................... 10 Default Values ............................................................................. 27 Typical Performance Characteristics ........................................... 11 Memory Map Register Table ..................................................... 28 AD9266-80 .................................................................................. 11 Memory Map Register Descriptions ........................................ 30 AD9266-65 .................................................................................. 13 Applications Information .............................................................. 31 AD9266-40 .................................................................................. 14 Design Guidelines ...................................................................... 31 AD9266-20 .................................................................................. 15 Outline Dimensions ....................................................................... 32 Equivalent Circuits ......................................................................... 16 Ordering Guide .......................................................................... 32 Theory of Operation ...................................................................... 17 Analog Input Considerations .................................................... 17 REVISION HISTORY 3/16—Rev. A to Rev. B Change to Product Highlights Section .......................................... 1 Changes to Pipeline Delay (Latency) Parameter, Table 4 ............ 7 Changes to Figure 3 and Table 8 ................................................... 10 Changes to Clock Input Options Section .................................... 20 Changes to Data Clock Output Section ....................................... 23 6/12—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 4 Changes to Table 4 ............................................................................ 7 Changed Built-In Self-Test (BIST) and Output Test Section to Output Test Section ........................................................................ 24 Changes to Output Test Section; Deleted Built-In Self-Test (BIST) Section ................................................................................. 24 Changes to Table 16 ........................................................................ 28 4/10—Revision 0: Initial Version Rev. B | Page 2 of 32

Data Sheet AD9266 GENERAL DESCRIPTION The AD9266 is a monolithic, single-channel 1.8 V supply, A differential clock input with a selectable internal 1-to-8 divide 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital ratio controls all internal conversion cycles. An optional duty cycle converter (ADC). It features a high performance sample-and- stabilizer (DCS) compensates for wide variations in the clock duty hold circuit and on-chip voltage reference. cycle while maintaining excellent overall ADC performance. The product uses multistage differential pipeline architecture The interleaved digital output data is presented in offset binary, with output error correction logic to provide 16-bit accuracy at gray code, or twos complement format. A DCO is provided to 80 MSPS data rates and to guarantee no missing codes over the ensure proper latch timing with receiving logic. Both 1.8 V and full operating temperature range. 3.3 V CMOS levels are supported. The ADC contains several features designed to maximize The AD9266 is available in a 32-lead RoHS-compliant LFCSP flexibility and minimize system cost, such as programmable and is specified over the industrial temperature range (−40°C clock and data alignment and programmable digital test pattern to +85°C). generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). Rev. B | Page 3 of 32

AD9266 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 1. AD9266-20/AD9266-40 AD9266-65 AD9266-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 16 16 16 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full +0.05 ±0.30 +0.05 ±0.30 +0.05 ±0.30 % FSR Gain Error1 Full −2.5/−2.0 −1.0 +1.0 % FSR Differential Nonlinearity Full −0.9/+1.2 −0.9/+1.7 −0.9/+1.7 LSB (DNL)2 25°C −0.5/+0.6 −0.5/+1.0 −0.6/+1.1 LSB Integral Nonlinearity Full ±5.5 ±6.5 ±6.2 LSB (INL)2 25°C ±1.8 ±2.4 ±3.5 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.983 0.995 1.007 0.983 0.995 1.007 0.983 0.995 1.007 V Load Regulation Error Full 2 2 2 mV at 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V 25°C 2.8 2.8 2.8 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 Full 6.5 6.5 6.5 pF Input Common-Mode Full 0.9 0.9 0.9 V Voltage Input Common-Mode Full 0.5 1.3 0.5 1.3 0.5 1.3 V Range REFERENCE INPUT Full 7.5 7.5 7.5 kΩ RESISTANCE POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current IAVDD2 Full 31.4/40.7 33.2/42.5 54.5 57.6 62.5 65.7 mA IDRVDD2 (1.8 V) Full 1.7/3.3 5.2 6.3 mA IDRVDD2 (3.3 V) Full 3.0/5.9 9.3 11.6 mA POWER CONSUMPTION DC Input Full 57/73 98 113 mW Sine Wave Input2 Full 60/79 63/82 107 113 124 130 mW (DRVDD = 1.8 V) Sine Wave Input2 Full 66/93 129 151 mW (DRVDD = 3.3 V) Standby Power4 Full 40 44 44 mW Power-Down Power Full 0.5 0.5 0.5 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between the differential inputs. 4 Standby power is measured with a dc input and the CLK active. Rev. B | Page 4 of 32

Data Sheet AD9266 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 2. AD9266-20/AD9266-40 AD9266-65 AD9266-80 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 78.2 77.9 77.6 dBFS IN f = 30.5 MHz 25°C 77.6 77.5 77.3 dBFS IN Full 76.7 76.6 dBFS f = 70 MHz 25°C 75.8/76.4 76.6 76.6 dBFS IN Full 75.5 dBFS f = 200 MHz 25°C 72.1 dBFS IN SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) f = 9.7 MHz 25°C 78.0 77.7 77.4 dBFS IN f = 30.5 MHz 25°C 77.5 77.3 77.1 dBFS IN Full 76.2 76.2 dBFS f = 70 MHz 25°C 75.7/76.3 76.5 76.6 dBFS IN Full 75.5 dBFS f = 200 MHz 25°C 69.4 dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) f = 9.7 MHz 25°C 12.7 12.6 12.6 Bits IN f = 30.5 MHz 25°C 12.6 12.5 12.5 Bits IN f = 70 MHz 25°C 12.3/12.4 12.4 12.4 Bits IN f = 200 MHz 25°C 11.2 Bits IN WORST SECOND OR THIRD HARMONIC f = 9.7 MHz 25°C −97 −96 −95 dBc IN f = 30.5 MHz 25°C −96/−93 −94 −93 dBc IN Full −80 −80 dBc f = 70 MHz 25°C −97/−95 −98 −95 dBc IN Full −80 dBc f = 200 MHz 25°C −80 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 9.7 MHz 25°C 95 95 94 dBc IN f = 30.5 MHz 25°C 93 92 92 dBc IN Full 80 80 dBc f = 70 MHz 25°C 93 95 93 dBc IN Full 80 dBc f = 200 MHz 25°C 80 dBc IN WORST OTHER (HARMONIC OR SPUR) f = 9.7 MHz 25°C −102 −101 −99 dBc IN f = 30.5 MHz 25°C −102 −101 −98 dBc IN Full −89 −89 dBc f = 70 MHz 25°C −101 −100 −98 dBc IN Full −89 dBc f = 200 MHz 25°C −86 dBc IN TWO-TONE SFDR f = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc IN ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. B | Page 5 of 32

AD9266 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 3. AD9266-20/AD9266-40/AD9266-65/AD9266-80 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (CSB)2 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 135 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, I = 50 µA Full 3.29 V OH High Level Output Voltage, I = 0.5 mA Full 3.25 V OH Low Level Output Voltage, I = 1.6 mA Full 0.2 V OL Low Level Output Voltage, I = 50 µA Full 0.05 V OL DRVDD = 1.8 V High Level Output Voltage, I = 50 µA Full 1.79 V OH High Level Output Voltage, I = 0.5 mA Full 1.75 V OH Low Level Output Voltage, I = 1.6 mA Full 0.2 V OL Low Level Output Voltage, I = 50 µA Full 0.05 V OL 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. B | Page 6 of 32

Data Sheet AD9266 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. Table 4. AD9266-20/AD9266-40 AD9266-65 AD9266-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 80/320 520 625 MHz Conversion Rate1 Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (t ) Full 50/25 15.38 12.5 ns CLK CLK Pulse Width High (t ) 25.0/12.5 7.69 6.25 ns CH Aperture Delay (t ) Full 1.0 1.0 1.0 ns A Aperture Uncertainty (Jitter, t) Full 0.1 0.1 0.1 ps rms J DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 1.84 3 3.90 1.84 3 3.90 1.84 3 3.90 ns DCO Propagation Delay (tDCO) Full 1.86 3 4.04 1.86 3 4.04 1.86 3 4.04 ns DCO to Data Skew (tSKEW) Full −0.53 0.1 0.72 −0.53 0.1 0.72 −0.53 0.1 0.72 ns Pipeline Delay (Latency) Full 8 8 8 Cycles Wake-Up Time2 Full 350 350 350 μs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. t A N N + 6 N – 1 N + 7 N + 1 N + 5 VIN N + 8 t N + 2 N + 3 CLK CLK+ CLK– t DCO DCO tSKEW tSKEW D1_D0 D1N–9 D0N–9 D1N–8 D0N–8 D1N–7 D0N–7 D1N–6 D0N–6 D1N–5 D0N–5 D1N–4 D0N–4 t PD D15_D14 D15N–9 D14N–9 D15N–8 D14N–8 D15N–7 D14N–7 D15N–6 D14N–6 D15N–5 D14N–5 D15N–4 D14N–4 08678-002 Figure 2. CMOS Output Data Timing Rev. B | Page 7 of 32

AD9266 Data Sheet TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK 2 ns DS t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S t Hold time between CSB and SCLK 2 ns H t SCLK pulse width high 10 ns HIGH t SCLK pulse width low 10 ns LOW t Time required for the SDIO pin to switch from an input to an output 10 ns EN_SDIO relative to the SCLK falling edge t Time required for the SDIO pin to switch from an output to an input 10 ns DIS_SDIO relative to the SCLK rising edge Rev. B | Page 8 of 32

Data Sheet AD9266 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating The exposed paddle is the only ground connection for the chip. AVDD to AGND −0.3 V to +2.0 V The exposed paddle must be soldered to the AGND plane of the DRVDD to AGND −0.3 V to +3.9 V user’s circuit board. Soldering the exposed paddle to the user’s VIN+, VIN− to AGND −0.3 V to AVDD + 0.2 V board also increases the reliability of the solder joints and CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V maximizes the thermal capability of the package. VREF to AGND −0.3 V to AVDD + 0.2 V Table 7. Thermal Resistance SENSE to AGND −0.3 V to AVDD + 0.2 V VCM to AGND −0.3 V to AVDD + 0.2 V Airflow Velocity RBIAS to AGND −0.3 V to AVDD + 0.2 V Package Type (m/sec) θ 1, 2 θ 1, 3 θ 1, 4 Ψ 1, 2 Unit JA JC JB JT CSB to AGND −0.3 V to DRVDD + 0.3 V 32-Lead LFCSP, 0 37.1 3.1 20.7 0.3 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V 5 mm × 5 mm SDIO/PDWN to AGND −0.3 V to DRVDD + 0.3 V 1.0 32.4 0.5 °C/W MODE/OR to AGND −0.3 V to DRVDD + 0.3 V 2.5 29.1 0.8 °C/W D1_D0 Through D15_D14 to AGND −0.3 V to DRVDD + 0.3 V 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. DCO to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Operating Temperature Range (Ambient) −40°C to +85°C 3 Per MIL-Std 883, Method 1012.1. Maximum Junction Temperature Under Bias 150°C 4 Per JEDEC JESD51-8 (still air). Storage Temperature Range (Ambient) −65°C to +150°C Typical θ is specified for a 4-layer PCB with a solid ground JA plane. As shown in Table 7, airflow improves heat dissipation, which reduces θ . In addition, metal in direct contact with the Stresses at or above those listed under Absolute Maximum JA package leads from metal traces, through holes, ground, and Ratings may cause permanent damage to the product. This is a power planes reduces the θ . stress rating only; functional operation of the product at these JA or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond ESD CAUTION the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 9 of 32

AD9266 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DDVA+NIV–NIVDDVASAIBRMCVESNESFERV 21098765 33322222 CLK+ 1 24 AVDD CLK– 2 23 MODE/OR AVDD 3 22 DCO CSB 4 AD9266 21 (MSB) D15_D14 SCLK/DFS 5 TOP VIEW 20 D13_D12 SDIO/PDWN 6 (Not to Scale) 19 D11_D10 DNC 7 18 D9_D8 DNC 8 17 D7_D6 910111213141516 CNDCNDCNDCNDDDVRD)BSL( 02D_3D4D_5D D _ 1 D NOTES 1. DNC = DO NOT CONNECT. 2 . TBHHEEEA S TEO DXLPIDSOESSRIPEEADDTPITOAOND T,D NHLOEEIA SISNE A,TALHNOEDG O MGNELRYCO HGUARNNODIC UOANFDL T SCHTOERN PENCNEBGCTTTHOIO. ENN OSNU RTEH EP RDOEPVEICRE F. IUTN MCUTSIOTNALITY, 08678-003 Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 0 EPAD Exposed Paddle. The exposed paddle is the only ground connection on the device. It must be soldered to the analog ground of the PCB to ensure proper functionality, heat dissipation, noise, and mechanical strength. 1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs. 3, 24, 29, 32 AVDD 1.8 V Supply Pin for ADC Core Domain. 4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up. 5 SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down. Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down. DFS high = twos complement output; DFS low = offset binary output. 6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down. Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull- down. See Table 14 for details. 7 to 12 DNC Do Not Connect. 14 to 21 D1_D0 (LSB) to ADC Digital Outputs. (MSB) D15_D14 13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain. 22 DCO Data Clock Digital Output. 23 MODE/OR Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR). Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1). Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0). Chip power-down (SPI Register 0x08, Bits[7:5] = 100b). Chip standby (SPI Register 0x08, Bits[7:5] = 101b). Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b). Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b). Out-of-range (OR) digital output only in non-SPI mode. 25 VREF 1.0 V Voltage Reference Input/Output. See Table 10. 26 SENSE Reference Mode Selection. See Table 10. 27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs. 28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs. Rev. B | Page 10 of 32

Data Sheet AD9266 TYPICAL PERFORMANCE CHARACTERISTICS AD9266-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 0 80MSPS 80MSPS 9.7MHz @ –1dBFS 30.6MHz @ –1dBFS –20 SNR = 76.8dB (77.8dBFS) –20 SNR = 76.5dB (77.5dBFS) SFDR = 94.3dBc SFDR = 85.7dBc –40 –40 S) S) F F B B E (d –60 E (d –60 D D U U LIT –80 LIT –80 P P M M A A –100 –100 –120 –120 –1400 5 10 F1R5EQUE2N0CY (MH25z) 30 35 40 08678-033 –1400 5 10 F1R5EQUE2N0CY (MH25z) 30 35 40 08678-034 Figure 4. AD9266-80 Single-Tone FFT with fIN = 9.7 MHz Figure 7. AD9266-80 Single-Tone FFT with fIN = 30.6 MHz 0 0 80MSPS 80MSPS 69MHz @ –1dBFS 210MHz @ –1dBFS –20 SNR = 75.1dB (76.1dBFS) –20 SNR = 70dB (71dBFS) SFDR = 89.5dBc SFDR = 79.7dBc –40 –40 S) S) F F B B E (d –60 E (d –60 D D U U LIT –80 LIT –80 P P M M A A –100 –100 –120 –120 –1400 5 10 F1R5EQUE2N0CY (MH25z) 30 35 40 08678-035 –1400 5 10 F1R5EQUE2N0CY (MH25z) 30 35 40 08678-036 Figure 5. AD9266-80 Single-Tone FFT with fIN = 69 MHz Figure 8. AD9266-80 Single-Tone FFT with fIN = 210 MHz 0 10 80MSPS –15 28.3MHz @ –7dBFS –10 30.6MHz @ –7dBFS SFDR (dBc) –30 SFDR = 89.5dBc (96.5dBFS) S) –30 dBFS) –45 c/dBF –50 IMD3 (dBc) E ( –60 dB AMPLITUD ––9705 F2–F1 2F2+F21F1+F2 F1+F22F2– F1 2F1– F2 SFDR/IMD3 ( ––7900 SFDR (dBFS) –105 –110 –120 IMD3 (dBFS) –135 4 8 12 FR1E6QUE2N0CY (M24Hz) 28 32 36 08678-053 –130–95 –85 –75 IN–P6U5T AM–5P5LITU–D4E5 (dB–F3S5) –25 –15 08678-054 Figure 6. AD9266-80 Two-Tone FFT with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Rev. B | Page 11 of 32

AD9266 Data Sheet AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 100 1.5 90 SFDR (dBc) 1.0 80 c) 70 S/dB 60 SNR (dBFS) LSB) 0.5 BF R ( SFDR (d 5400 L ERRO 0 SNR/ 30 DN–0.5 20 –1.0 10 00 50 INPUT FREQ10U0ENCY (MHz) 150 200 08678-057 –1.50 16,384 OUTP3U2,T7 6C8ODE 49,152 65,536 08678-038 Figure 10. AD9266-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale Figure 13. DNL Error with fIN = 9.7 MHz 100 6 90 SFDR (dBc) 4 80 c)70 dB SNR (dBFS) B) 2 R (dBFS/5600 ROR (LS 0 D R SNR/SF3400 INL E –2 20 –4 10 010 20 30SAMP4L0E RATE5 (0MSPS)60 70 80 08678-055 –60 16,384 OUTP32U,T7 6C8ODE 49,152 65,536 08678-037 Figure 11. AD9266-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz Figure 14. INL with fIN = 9.7 MHz 120 4.0M SFDRFS 3.5M 2.8 LSB RMS 100 3.0M c) B 80 S S/d SNRFS HIT 2.5M DR (dBF 60 SFDR BER OF 2.0M NR/SF 40 SNR NUM 1.5M S 1.0M 20 500k 0–65 –60 –50 INPU–T4 0AMPLIT–U30DE (dBF–2S0) –10 0 08678-061 0 N – 12N – 11N – 10N – 9N – 8N – 7N – 6N – 5N – 4OUN – 3TN – 2PUN – 1T CNON + 1DEN + 2N + 3N + 4N + 5N + 6N + 7N + 8N + 9N + 10 08678-048 Figure 12. AD9266-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 15. Grounded Input Histogram Rev. B | Page 12 of 32

Data Sheet AD9266 AD9266-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 120 65MSPS 9.7MHz @ –1dBFS SFDRFS –20 SNR = 76.9dB (77.9dBFS) 100 SFDR = 95.9dBc S) –40 Bc) 80 F d LITUDE (dB ––8600 FDR (dBFS/ 60 SNRFS SFDR AMP NR/S 40 SNR –100 S –120 20 –1400 5 10 FREQU15ENCY (M2H0z) 25 30 08678-030 0–65 –60 –50 INPU–T4 0AMPLIT–U30DE (dBF–2S0) –10 0 08678-060 Figure 16. AD9266-65 Single-Tone FFT with fIN = 9.7 MHz Figure 19. AD9266-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 100 65MSPS SFDR (dBc) 69MHz @ –1dBFS 90 –20 SNR = 75.5dB (76.5dBFS) SFDR = 87.4dBc 80 S) –40 Bc) 70 SNR (dBFS) PLITUDE (dBF ––8600 SFDR (dBFS/d 654000 AM –100 SNR/ 30 20 –120 10 –1400 5 10 FREQU15ENCY (M2H0z) 25 30 08678-032 00 50 INPUT FREQ10U0ENCY (MHz) 150 200 08678-056 Figure 17. AD9266-65 Single-Tone FFT with fIN = 69 MHz Figure 20. AD9266-65 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 0 65MSPS 30.6MHz @ –1dBFS –20 SNR = 76.6dB (77.6dBFS) SFDR = 89.9dBc –40 S) F B E (d –60 D U LIT –80 P M A –100 –120 –1400 5 10 FREQU15ENCY (M2H0z) 25 30 08678-031 Figure 18. AD9266-65 Single-Tone FFT with fIN = 30.6 MHz Rev. B | Page 13 of 32

AD9266 Data Sheet AD9266-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 120 40MSPS 9.7MHz @ –1dBFS SFDRFS –20 SNR = 76.9dB (77.9dBFS) 100 SFDR = 95.1dBc S) –40 Bc) 80 F d LITUDE (dB ––8600 FDR (dBFS/ 60 SNRFS SFDR AMP NR/S 40 SNR –100 S –120 20 –1400 2 4 6 FR8EQUE1N0CY (M12Hz) 14 16 18 20 08678-028 0–65 –60 –50 INPU–T4 0AMPLIT–U30DE (dBF–2S0) –10 0 08678-059 Figure 21. AD9266-40 Single-Tone FFT with fIN = 9.7 MHz Figure 23. AD9266-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 40MSPS 30.6MHz @ –1dBFS –20 SNR = 76.6dB (77.6dBFS) SFDR = 88.8dBc –40 S) F B E (d –60 D U LIT –80 P M A –100 –120 –1400 2 4 6 FR8EQUE1N0CY (M12Hz) 14 16 18 20 08678-029 Figure 22. AD9266-40 Single-Tone FFT with fIN = 30.6 MHz Rev. B | Page 14 of 32

Data Sheet AD9266 AD9266-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted. 0 120 20MSPS SFDRFS –20 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) 100 SFDR = 95.6dBc FS) –40 dBc) 80 SNRFS LITUDE (dB ––8600 FDR (dBFS/ 60 SFDR (dBc) P S AM NR/ 40 –100 S SNR (dBc) –120 20 –1400 1 2 3 FR4EQUEN5CY (M6Hz) 7 8 9 10 08678-024 0–90 –80 –70 I–N6P0UT A–M50PLIT–U4D0E (d–B3F0S) –20 –10 0 08678-058 Figure 24. AD9266-20 Single-Tone FFT with fIN = 9.7 MHz Figure 26. AD9266-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 20MSPS –20 30.6MHz @ –1dBFS SNR = 76.7dB (77.7dBFS) SFDR = 90.7dBc –40 S) F B E (d –60 D U LIT –80 P M A –100 –120 –1400 1 2 3 FR4EQUEN5CY (M6Hz) 7 8 9 10 08678-026 Figure 25. AD9266-20 Single-Tone FFT with fIN = 30.6 MHz Rev. B | Page 15 of 32

AD9266 Data Sheet EQUIVALENT CIRCUITS AVDD DRVDD VIN± D1_D0TO D15_D14, OR 08678-039 08678-042 Figure 27. Equivalent Analog Input Circuit Figure 31. Equivalent D1_D0 to D15_D14 and OR Digital Output Circuit DRVDD AVDD SCLK/DFS, 350Ω MODE, VREF 375Ω SDIO/PDWN 30kΩ 7.5kΩ 08678-047 08678-043 Figure 28. Equivalent VREF Circuit Figure 32. Equivalent SCLK/DFS, MODE, and SDIO/PDWN Input Circuit AVDD DRVDD AVDD 30kΩ 375Ω 350Ω SENSE CSB 08678-046 08678-045 Figure 29. Equivalent SENSE Circuit Figure 33. Equivalent CSB Input Circuit AVDD 5Ω CLK+ AVDD 15kΩ 0.9V AVDD 15kΩ RBIAS 375Ω AND VCM 5Ω CLK– 08678-040 08678-044 Figure 30. Equivalent Clock Input Circuit Figure 34. Equivalent RBIAS and VCM Circuit Rev. B | Page 16 of 32

Data Sheet AD9266 THEORY OF OPERATION high IF frequencies. Either a shunt capacitor or two single-ended The AD9266 architecture consists of a multistage, pipelined ADC. capacitors can be placed on the inputs to provide a matching Each stage provides sufficient overlap to correct for flash errors in passive network. This ultimately creates a low-pass filter at the the preceding stage. The quantized outputs from each stage are input to limit unwanted broadband noise. See the AN-742 combined into a final 16-bit result in the digital correction logic. Application Note, the AN-827 Application Note, and the Analog The pipelined architecture permits the first stage to operate with Dialogue article “Transformer-Coupled Front-End for Wideband a new input sample, whereas the remaining stages operate with A/D Converters” (Volume 39, April 2005) for more information. In preceding samples. Sampling occurs on the rising edge of the clock. general, the precise values depend on the application. Each stage of the pipeline, excluding the last, consists of a low Input Common Mode resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying The analog inputs of the AD9266 are not internally dc-biased. digital-to-analog converter (MDAC)). The residue amplifier Therefore, in ac-coupled applications, the user must provide magnifies the difference between the reconstructed DAC output a dc bias externally. Setting the device so that VCM = AVDD/2 and the flash input for the next stage in the pipeline. One bit of is recommended for optimum performance, but the device can redundancy is used in each stage to facilitate digital correction function over a wider range with reasonable performance, as of flash errors. The last stage simply consists of a flash ADC. shown in Figure 36. The output staging block aligns the data, corrects errors, and 100 passes the data to the CMOS output buffers. The output buffers 95 are powered from a separate (DRVDD) supply, allowing adjust- SFDR (dBc) 90 ment of the output voltage swing. During power-down, the c) B output buffers go into a high impedance state. S/d 85 F ANALOG INPUT CONSIDERATIONS R (dB 80 SNR (dBFS) The analog input to the AD9266 is a differential switched- FD S 75 capacitor circuit designed for processing differential input R/ N S signals. This circuit can support a wide common-mode range 70 while maintaining excellent performance. By using an input 65 common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. 60 0.5 0.6 IN0P.7UT CO0M.8MON-M0.O9DE V1O.0LTAGE1. 1(V) 1.2 1.3 08678-049 Figure 36. SNR/SFDR vs. Input Common-Mode Voltage, H fIN = 32.5 MHz, fS = 80 MSPS C An on-board, common-mode voltage reference is included in PAR H VIN+ the design and is available from the VCM pin. The VCM pin C SAMPLE must be decoupled to ground by a 0.1 μF capacitor, as described S S in the Applications Information section. S S C SAMPLE Differential Input Configurations VIN– C H PAR Optimum performance is achieved while driving the AD9266 in a H 08678-006 dAiDff8er1e3n8t,i AalD inAp4u9t3 c7o-2n,f aignudr AatDioAn4. 9F3o8r- b2 adsieffbearnendt iaapl pdlriicvaetriso nprso, vthidee Figure 35. Switched-Capacitor Input Circuit excellent performance and a flexible interface to the ADC. The clock signal alternately switches the input circuit between The output common-mode voltage of the ADA4938-2 is easily sample-and-hold mode (see Figure 35). When the input circuit set with the VCM pin of the AD9266 (see Figure 37), and the is switched to sample mode, the signal source must be capable driver can be configured in a Sallen-Key filter topology to of charging the sample capacitors and settling within one-half provide band limiting of the input signal. of a clock cycle. A small resistor in series with each input can 200Ω help reduce the peak transient current injected from the output 33Ω VIN 76.8Ω VIN– AVDD stage of the driving source. In addition, low Q inductors or ferrite 90Ω beads can be placed on each leg of the input to reduce high differ- ADA4938-2 10pF ADC ential capacitance at the analog inputs and, therefore, achieve 0.1µF 120Ω 33Ω tohre f emrraitxei mbeuamds bisa nredqwuiidrethd owfh thene AdrDivCin. gS uthceh cuosnev oefr ltoewr f rQo nint deuncdt oatr s 200Ω VIN+ VCM 08678-007 Figure 37. Differential Input Configuration Using the ADA4938-2 Rev. B | Page 17 of 32

AD9266 Data Sheet For baseband applications less than approximately 10 MHz In any configuration, the value of Shunt Capacitor C is dependent where SNR is a key parameter, differential transformer coupling is on the input frequency and source impedance and may need to the recommended input configuration. An example is shown in be reduced or removed. Table 9 displays the suggested values to set Figure 38. To bias the analog input, the VCM voltage can be the RC network. However, these values are dependent on the connected to the center tap of the secondary winding of the input signal and should be used only as a starting guide. transformer. Table 9. Example RC Network VIN+ R Series R Frequency Range (MHz) (Ω Each) C Differential (pF) 2V p-p 49.9Ω C ADC 0 to 70 33 22 R VIN– VCM 70 to 200 125 Open 0.1µF 08678-008 Single-Ended Input Configuration Figure 38. Differential Transformer-Coupled Configuration A single-ended input can provide adequate performance in The signal characteristics must be considered when selecting cost-sensitive applications. In this configuration, SFDR and a transformer. Most RF transformers saturate at frequencies distortion performance degrade due to the large input common- below a few megahertz (MHz). Excessive signal power can also mode swing. If the source impedances on each input are matched, cause core saturation, which leads to distortion. there should be little effect on SNR performance. Figure 39 shows a typical single-ended input configuration. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve 10µF AVDD the true SNR performance of the AD9266. For applications greater 1kΩ R VIN+ than approximately 10 MHz where SNR is a key parameter, 1Vp-p 49.9Ω 0.1µF 1kΩ differential double balun coupling is the recommended input AVDD C ADC configuration (see Figure 40). 1kΩ R VIN– Ainn t haelt esrencoatnivde N toy quusiisntg z ao ntrea inss tfoo rumsee rt-hceo AupDle8d3 5in2p duitf faetr fernetqiaule dnrciiveesr . 10µF 0.1µF 1kΩ 08678-009 An example is shown in Figure 41. See the AD8352 data sheet Figure 39. Single-Ended Input Configuration for more information. 0.1µF 0.1µF R 2V p-p VIN+ 25Ω PA S S P C ADC 25Ω 0.1µF 0.1µF R VIN– VCM 08678-010 Figure 40. Differential Double Balun Input Configuration VCC 0.1µF ANALOG INPUT 0Ω 161 8, 1311 0.1µF 0.1µF R VIN+ 2 200Ω CD RD RG34 AD835210 0.1µF 200Ω R C VIN– ADCVCM ANALOG INPUT 0.1µF 0Ω 5 104.1µF 0.1µF 08678-011 Figure 41. Differential Input Configuration Using the AD8352 Rev. B | Page 18 of 32

Data Sheet AD9266 VOLTAGE REFERENCE 0 A stable and accurate 1.0 V voltage reference is built into the %)–0.5 AD9266. The VREF can be configured using either the internal R ( O 1.0 V reference or an externally applied 1.0 V reference voltage. R R–1.0 The various reference modes are summarized in the sections that GE E INTERNAL VREF = 0.995V follow. The Reference Decoupling section describes the best A T–1.5 L practices for PCB layout of VREF. O V E Internal Reference Connection NC–2.0 E R A comparator within the AD9266 detects the potential at the E F SENSE pin and configures the reference into two possible modes, RE–2.5 which are summarized in Table 10. If SENSE is grounded, the rdeifveirdeenrc (es eaem Fpilgiufireer s4w2i)t,c she titsi ncgo nVnReEctFe dto t o1 .t0h Ve .i n ternal resistor –3.00 0.2 0.4 0.6LOA0.D8 CUR1.R0ENT1 .(2mA)1.4 1.6 1.8 2.0 08678-014 Figure 43. VREF Accuracy vs. Load Current VIN+ VIN– External Reference Operation The use of an external reference may be necessary to enhance ADC the gain accuracy of the ADC or improve thermal drift charac- CORE teristics. Figure 44 shows the typical drift characteristics of the internal reference in 1.0 V mode. VREF 4 1.0µF 0.1µF SELECT 3 LOGIC SENSE 2 VREF ERROR (mV) 0.5V 1 V) ADC 08678-012 ERROR (m –10 Figure 42. Internal Reference Configuration EF –2 R V If the internal reference of the AD9266 is used to drive multiple –3 converters to improve gain matching, the loading of the reference –4 by the other converters must be considered. Figure 43 shows –5 how the internal reference voltage is affected by loading. –6 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 08678-052 Figure 44. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 28). The internal buffer generates the posi- tive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. Table 10. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Rev. B | Page 19 of 32

AD9266 Data Sheet CLOCK INPUT CONSIDERATIONS The back-to-back Schottky diodes across the transformer/ balun secondary limit clock excursions into the AD9266 to For optimum performance, clock the AD9266 sample clock inputs, approximately 0.8 V p-p differential. CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or This limit helps prevent the large voltage swings of the clock capacitors. These pins are biased internally (see Figure 45) and from feeding through to other portions of the AD9266 while require no external bias. preserving the fast rise and fall times of the signal that are AVDD critical to a low jitter performance. If a low jitter clock source is not available, another option is to 0.9V ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 48. The AD9510/AD9511/AD9512/ CLK+ CLK– AD9513/AD9514/AD9515/AD9516-0/AD9516-1/AD9516-2/ 2pF 2pF AD9516-3/AD9516-4/AD9516-5/AD9517-0/AD9517-1/ AD9517-2/AD9517-3/AD9517-4 clock drivers offer excellent 08678-016 jitter performance. Figure 45. Equivalent Clock Input Circuit Clock Input Options 0.1µF 0.1µF CLOCK CLK+ INPUT The AD9266 has a very flexible clock input structure. The clock AD951x 100Ω ADC input can be a CMOS, LVDS, LVPECL, or sine wave signal. 0.1µF PECL DRIVER 0.1µF CLOCK CLK– Rofe ggraeradtl ecossn ocef rtnh,e a tsy dpees corfi bseigdn ianl tbheei nJigtt uers eCdo, nclsoidcker saotiuorncse sjeitctteiro nis. INPUT50kΩ 50kΩ 240Ω 240Ω 08678-019 Figure 46 and Figure 47 show two preferred methods for clock- Figure 48. Differential PECL Sample Clock (Up to 625 MHz) ing the AD9266 (at clock rates up to 625 MHz when using the A third option is to ac couple a differential LVDS signal to the internal clock divider). A low jitter clock source is converted from sample clock input pins, as shown in Figure 49. The AD9510/ a single-ended signal to a differential signal using either an RF AD9511/AD9512/AD9513/AD9514/AD9515/AD9516-0/ transformer or an RF balun. AD9516-1/AD9516-2/AD9516-3/AD9516-4/AD9516-5/ AD9517-0/AD9517-1/AD9517-2/AD9517-3/AD9517-4 clock Mini-Circuits® ADT1-1WT, 1:1 Z drivers offer excellent jitter performance. 0.1µF 0.1µF CLOCK XFMR CLK+ INPUT 50Ω 100Ω 0.1µF ADC 0.1µF 0.1µF CLK– CILNOPCUKT CLK+ 0.1µF SHCDSHIMOOSDT2ET8SK2:2Y 08678-017 CLOCK 0.1µF LVDASD 9D5R1IxVER 100.01ΩµF CLKA–DC Figure 46. Transformer-Coupled Differential Clock (Up to 200 MHz) INPUT50kΩ 50kΩ 08678-020 Figure 49. Differential LVDS Sample Clock (Up to 625 MHz) 1nF 0.1µF In some applications, it may be acceptable to drive the sample CLOCK CLK+ INPUT clock inputs with a single-ended 1.8 V CMOS signal. In such 50Ω ADC 0.1µF applications, drive the CLK+ pin directly from a CMOS gate, and 1nF CLK– bypass the CLK− pin to ground with a 0.1 μF capacitor (see SHDCSIHMOOSDT2ET8SK2:2Y 08678-018 Figure 50). Figure 47. Balun-Coupled Differential Clock (Up to 625 MHz) VCC The RF balun configuration is recommended for clock frequencies 0.1µF 1kΩ AD951x OP1T0IO0ΩNAL0.1µF between 125 MHz and 625 MHz, and the RF transformer is recom- CILNOPCUKT CMOS DRIVER CLK+ 50Ω1 1kΩ mended for clock frequencies from 10 MHz to 200 MHz. ADC CLK– 0.1µF 150Ω RESISTOR IS OPTIONAL. 08678-021 Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Rev. B | Page 20 of 32

Data Sheet AD9266 Input Clock Divider Jitter Considerations The AD9266 contains an input clock divider with the ability High speed, high resolution ADCs are sensitive to the quality of to divide the input clock by integer values between 1 and 8. the clock input. The degradation in SNR from the low frequency Optimum performance can be obtained by enabling the internal SNR (SNR ) at a given input frequency (f ) due to jitter LF INPUT duty cycle stabilizer (DCS) when using divide ratios other than (tJRMS) can be calculated by 1, 2, or 4. SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10(−SNRLF/10)] Clock Duty Cycle In the previous equation, the rms aperture jitter represents the Typical high speed ADCs use both clock edges to generate clock input jitter specification. IF undersampling applications a variety of internal timing signals and, as a result, may be are particularly sensitive to jitter, as illustrated in Figure 52. sensitive to clock duty cycle. Commonly, a ±5% tolerance is 80 required on the clock duty cycle to maintain dynamic performance characteristics. 75 0.05ps The AD9266 contains a duty cycle stabilizer (DCS) that retimes 70 the nonsampling (falling) edge, providing an internal clock 0.2ps signal with a nominal 50% duty cycle. This allows the user to FS)65 B provide a wide range of clock input duty cycles without affecting d R ( the performance of the AD9266. Noise and distortion perform- N60 0.5ps S ance are nearly flat for a wide range of duty cycles with the DCS on, 55 as shown in Figure 51. 1.0ps 80 50 1.5ps DCS OFF 2.0ps 79 DCS ON 3.0ps 2.5ps 45 7787 1 10FREQUENCY (MHz1)00 1k 08678-022 Figure 52. SNR vs. Input Frequency and Jitter S) 76 F Treat the clock input as an analog signal when aperture jitter may B R (d 75 affect the dynamic range of the AD9266. To avoid modulating the N S 74 clock signal with digital noise, keep power supplies for clock 73 drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources. If the 72 clock is generated from another type of source (by gating, dividing, 71 or another method), it should be retimed by the original clock at 7030 35 40POSI4T5IVE DU5T0Y CYC5L5E (%)60 65 70 08678-064 tFhoer lmasot rset eipn.f ormation, see the AN-501 Application Note and Figure 51. SNR vs. DCS On/Off the AN-756 Application Note. Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 µs to 5 µs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. Rev. B | Page 21 of 32

AD9266 Data Sheet POWER DISSIPATION AND STANDBY MODE down mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent As shown in Figure 53, the analog core power dissipated by the in power-down mode, and shorter power-down cycles result in AD9266 is proportional to its sample rate. The digital power proportionally shorter wake-up times. dissipation of the CMOS outputs are determined primarily by the strength of the digital drivers and the load on each output bit. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows The maximum DRVDD current (IDRVDD) can be calculated as the user to keep the internal reference circuitry powered when IDRVDD = V × C × f × N DRVDD LOAD CLK faster wake-up times are required. See the Memory Map section where N is the number of output bits (nine, in the case of the for more details. AD9266). DIGITAL OUTPUTS This maximum current occurs when every output bit switches The AD9266 output drivers can be configured to interface with on every clock cycle, that is, a full-scale square wave at the Nyquist 1.8 V to 3.3 V CMOS logic families. Output data can also be frequency of f /2. In practice, the DRVDD current is estab- CLK multiplexed onto a single output bus to reduce the total number lished by the average number of output bits switching, which of traces required. is determined by the sample rate and the characteristics of the The CMOS output drivers are sized to provide sufficient output analog input signal. current to drive a wide variety of logic families. However, large Reducing the capacitive load presented to the output drivers can drive currents tend to cause current glitches on the supplies and minimize digital power consumption. The data in Figure 53 was may affect converter performance. taken using the same operating conditions as those used for the Applications requiring the ADC to drive large capacitive loads Typical Performance Characteristics, with a 5 pF load on each or large fanouts may require external buffers or latches. output driver. The output data format can be selected to be either offset binary 115 AD9266-80 or twos complement by setting the SCLK/DFS pin when operating 105 in the external pin mode (see Table 11). W) AD9266-65 As detailed in the AN-877 Application Note, Interfacing to High R (m 95 Speed ADCs via SPI, the data format can be selected for offset E W O 85 binary, twos complement, or gray code when using the SPI control. P E R G CO 75 AD9266-40 T(Eaxbtleer 1n1a.l SPCinL KM/oDdFeS) and SDIO/PDWN Mode Selection O AL 65 Voltage at Pin SCLK/DFS SDIO/PDWN N A AD9266-20 AGND Offset binary (default) Normal operation 55 (default) DRVDD Twos complement Outputs disabled 4510 20 30 CLOC4K0 RATE 5(M0SPS) 60 70 80 08678-067 Digital Output Enable Function (OEB) Figure 53. Analog Core Power vs. Clock Rate When using the SPI interface, the data outputs and DCO can be In SPI mode, the AD9266 can be placed in power-down mode independently three-stated by using the programmable external directly via the SPI port, or by using the programmable external MODE pin. The MODE pin (OEB) function is enabled via Bits[6:5] MODE pin. In non-SPI mode, power-down is achieved by assert- of Register 0x08. ing the PDWN pin high. In this state, the ADC typically dissipates If the MODE pin is configured to operate in traditional OEB 500 µW. During power-down, the output drivers are placed in mode and the MODE pin is low, the output data drivers and a high impedance state. Asserting PDWN low (or the MODE pin DCOs are enabled. If the MODE pin is high, the output data in SPI mode) returns the AD9266 to its normal operating mode. drivers and DCOs are placed in a high impedance state. This Note that PDWN is referenced to the digital output driver OEB function is not intended for rapid access to the data bus. supply (DRVDD) and should not exceed that supply voltage. Note that the MODE pin is referenced to the digital output Low power dissipation in power-down mode is achieved by driver supply (DRVDD) and should not exceed that supply shutting down the reference, reference buffer, biasing networks, voltage. and clock. Internal capacitors are discharged when entering power- Rev. B | Page 22 of 32

Data Sheet AD9266 TIMING The lowest typical conversion rate of the AD9266 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance may degrade. The AD9266 provides latched data with a pipeline delay of eight clock cycles. Data outputs are available one propagation Data Clock Output (DCO) delay (tPD) after the rising edge of the clock signal. The AD9266 provides a DCO signal that is intended for Minimize the length of the output data lines and loads placed capturing the data in an external register. The CMOS data outputs on them to reduce transients within the AD9266. These are valid on the rising and falling edge of DCO. See Figure 2 for transients can degrade converter dynamic performance. a graphical timing description. Table 12. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000 1 VIN+ − VIN− = −VREF 0000 0000 0000 0000 1000 0000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 1111 0111 1111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 1111 0111 1111 1111 1111 1 Rev. B | Page 23 of 32

AD9266 Data Sheet OUTPUT TEST The AD9266 includes various output test options to place the test patterns are subject to output formatting, and some are predictable values on the outputs of the AD9266. not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be OUTPUT TEST MODES performed with or without an analog signal (if present, the analog The output test options are described in Table 16 at Address 0x0D. signal is ignored), but they do require an encode clock. For more When an output test mode is enabled, the analog section of the information, see the AN-877 Application Note, Interfacing to ADC is disconnected from the digital back end blocks and the High Speed ADCs via SPI. test pattern is run through the output formatting block. Some of Rev. B | Page 24 of 32

Data Sheet AD9266 SERIAL PORT INTERFACE (SPI) The AD9266 serial port interface (SPI) allows the user to con- The falling edge of CSB, in conjunction with the rising edge of figure the converter for specific functions or operations through SCLK, determines the start of the framing. An example of the a structured register space provided inside the ADC. The SPI gives serial timing and its definitions can be found in Figure 54 and the user added flexibility and customization, depending on the Table 5. application. Addresses are accessed via the serial port and can Other modes involving the CSB pin are available. CSB can be be written to or read from via the port. Memory is organized held low indefinitely, which permanently enables the device; into bytes that can be further divided into fields, which are this is called streaming. CSB can stall high between bytes to documented in the Memory Map section. For more detailed allow for additional external timing. When CSB is tied high, operational information, see the AN-877 Application Note, SPI functions are placed in high impedance mode. This mode Interfacing to High Speed ADCs via SPI. turns on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Three pins define the SPI of this ADC: SCLK, SDIO, and CSB Data follows the instruction phase, and its length is determined (see Table 13). The SCLK (a serial clock) is used to synchronize by the W0 and W1 bits, as shown in Figure 54. the read and write data presented from and to the ADC. SDIO All data is composed of 8-bit words. The first bit of the first byte in (serial data input/output) is a dual-purpose pin that allows data to a multibyte serial data transfer frame indicates whether a read be sent and read from the internal ADC memory map registers. command or a write command is issued. This allows the serial The CSB (chip select bar) is an active-low control that enables data input/output (SDIO) pin to change direction from an input or disables the read and write cycles. to an output at the appropriate point in the serial frame. Table 13. Serial Port Interface Pins In addition to word length, the instruction phase determines Pin Function whether the serial frame is a read or write operation, allowing SCLK Serial clock. The serial shift clock input, which is used to the serial port to be used both to program the chip and to read synchronize serial interface reads and writes. the contents of the on-chip memory. If the instruction is a readback SDIO Serial data input/output. A dual-purpose pin that operation, performing a readback causes the serial data input/ typically serves as an input or an output, depending on output (SDIO) pin to change direction from an input to an output the instruction being sent and the relative position in the at the appropriate point in the serial frame. timing frame. CSB Chip select bar. An active-low control that gates the read Data can be sent in MSB-first mode or in LSB-first mode. MSB and write cycles. first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tDS tHIGH tCLK tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 08678-023 Figure 54. Serial Port Interface Timing Diagram Rev. B | Page 25 of 32

AD9266 Data Sheet HARDWARE INTERFACE this mode, connect the CSB chip select to DRVDD, which disables the serial port interface. The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port Table 14. Mode Selection of the AD9266. The SCLK pin and the CSB pin function as inputs External when using the SPI interface. The SDIO pin is bidirectional, Pin Voltage Configuration functioning as an input during write phases and as an output SDIO/PDWN DRVDD Chip power-down mode during readback. AGND (default) Normal operation (default) The SPI interface is flexible enough to be controlled by either SCLK/DFS DRVDD Twos complement enabled FPGAs or microcontrollers. One method for SPI configuration AGND (default) Offset binary enabled is described in detail in the AN-812 Application Note, Micro- SPI ACCESSIBLE FEATURES controller-Based Serial Port Interface (SPI) Boot Circuit. Table 15 provides a brief description of the general features that The SPI port should not be active during periods when the full are accessible via the SPI. These features are described in detail dynamic performance of the converter is required. Because the in the AN-877 Application Note, Interfacing to High Speed ADCs SCLK signal, the CSB signal, and the SDIO signal are typically via SPI. The AD9266 part-specific features are described in asynchronous to the ADC clock, noise from these signals can detail in Table 16. degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between Table 15. Features Accessible Using the SPI this bus and the AD9266 to prevent these signals from transi- Feature Description tioning at the converter inputs during critical sampling periods. Modes Allows the user to set either power-down mode or standby mode SDIO/PDWN and SCLK/DFS serve a dual function when the Clock Allows the user to access the DCS via the SPI SPI interface is not being used. When the pins are strapped to Offset Allows the user to digitally adjust the converter DRVDD or ground during device power-on, they are associated offset with a specific function. The Digital Outputs section describes Test I/O Allows the user to set test modes to have known the strappable functions supported on the AD9266. data on output bits CONFIGURATION WITHOUT THE SPI Output Mode Allows the user to set up outputs Output Phase Allows the user to set the output clock polarity In applications that do not interface to the SPI control registers, Output Delay Allows the user to vary the DCO delay the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the power-down and output data format feature control. In Rev. B | Page 26 of 32

Data Sheet AD9266 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 16) After the AD9266 is reset, critical registers are loaded with contains eight bit locations. The memory map is roughly default values. The default values for the registers are given in divided into four sections: the chip configuration registers the memory map register table (see Table 16). (Address 0x00 to Address 0x02); the device index and transfer Logic Levels register (Address 0xFF); the program registers, including setup, An explanation of logic level terminology follows: control, and test (Address 0x08 to Address 0x2A); and the AD9266-specific customer SPI control register (Address 0x101).  “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Table 16 documents the default hexadecimal value for each hexadecimal address shown. The column with the heading  “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x2A, the OR/MODE select register, Transfer Register Map has a hexadecimal default value of 0x01. This means that in Address 0x08 to Address 0x18 are shadowed. Writes to these Address 0x2A, Bits[7:1] = 0, and Bit 0 = 1. This setting is the addresses do not affect part operation until a transfer command default OR/MODE setting. The default value results in the is issued by writing 0x01 to Address 0xFF, setting the transfer bit. programmable external MODE/OR pin (Pin 23) functioning This allows these registers to be updated internally and simulta- as an out-of-range digital output. For more information on this neously when the transfer bit is set. The internal update takes function and others, see the AN-877 Application Note, Interfacing place when the transfer bit is set, and then the bit autoclears. to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining register, Register 0x101, is documented in the Memory Map Register Descriptions section that follows Table 16. OPEN LOCATIONS All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these loca- tions is required only when part of an address location is open (for example, Address 0x2A). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. Rev. B | Page 27 of 32

AD9266 Data Sheet MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Default Addr Bit 7 Bit 0 Value (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB Soft 1 1 Soft LSB first 0 0x18 The nibbles are configuration first reset reset mirrored so that LSB- or MSB-first mode registers correctly, regardless of shift mode. 0x01 Chip ID 8-bit chip ID, Bits[7:0] Read Unique chip ID AD9266 = 0x78 only used to differentiate devices; read only. 0x02 Chip grade Open Speed grade ID, Bits[6:4] (identify Open Read Unique speed device variants of chip ID) only grade ID used 20 MSPS = 000 to differentiate 40 MSPS = 001 devices; read only. 65 MSPS = 010 80 MSPS = 011 Device Index and Transfer Register 0xFF Transfer Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave. Program Registers 0x08 Modes External External Pin 23 Open 00 = chip run 0x00 Determines various Pin 23 mode function when high 01 = full power-down generic modes of input enable 00 = full power- 10 = standby chip operation. down 11 = chip wide digital 01 = standby reset 10 = normal mode: output disabled 11 = normal mode: output enabled 0x09 Clock Open Duty cycle 0x01 Enable internal stabilize duty cycle stabilizer (DCS). 0x0B Clock divide Open Clock divider, Bits[2:0] 0x00 The divide ratio is Clock divide ratio: the value plus 1. 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0D Test mode User test mode Reset PN Reset PN Output test mode, Bits[3:0] (local) 0x00 When set, the test 00 = single long gen short gen 0000 = off (default) data is placed on 01 = alternate 0001 = midscale short the output pins in 10 = single once 0010 = positive FS place of normal data. 11 = alternate once 0011 = negative FS 0100 = alternating checkerboard 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = 1/0 word toggle 1000 = user input 1001 = 1/0 bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 0x10 Offset adjust 8-bit device offset adjustment, Bits[7:0] (local) 0x00 Device offset trim. Offset adjust in LSBs from +127 to −128 (twos complement format) 0x14 Output mode 00 = 3.3 V CMOS Open Output Open Output 00 = offset binary 0x00 Configures the 10 = 1.8 V CMOS disable invert 01 = twos complement outputs and the 10 = gray code format of the data. 11 = offset binary Rev. B | Page 28 of 32

Data Sheet AD9266 Default Addr Bit 7 Bit 0 Value (Hex) Register Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x15 Output adjust 3.3 V DCO 1.8 V DCO 3.3 V data 1.8 V data drive strength 0x22 Determines CMOS drive strength drive strength drive strength 00 = 1 stripe output drive 00 = 1 stripe (default) 00 = 1 stripe 00 = 1 stripe (default) 01 = 2 stripes strength properties. 01 = 2 stripes 01 = 2 stripes 01 = 2 stripes 10 = 3 stripes (default) 10 = 3 stripes 10 = 3 stripes (default) 10 = 3 stripes 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 0x16 Output phase DCO output Open Input clock phase adjust, Bits[2:0] 0x00 On devices that use polarity (Value is number of input clock global clock divide, 0 = normal cycles of phase delay) determines which 1 = inverted 000 = no delay phase of the divider 001 = 1 input clock cycle output is used to 010 = 2 input clock cycles supply the output 011 = 3 input clock cycles clock; internal 100 = 4 input clock cycles latching is 101 = 5 input clock cycles unaffected. 110 = 6 input clock cycles 111 = 7 input clock cycles 0x17 Output delay Enable DCO Open Enable Open DCO/data delay[2:0] (typical values) 0x00 Sets the fine delay data 000 = 0.56 ns output delay of the delay 001 = 1.12 ns output clock but 010 = 1.68 ns does not change 011 = 2.24 ns internal timing. 100 = 2.80 ns (Typical values) 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB. 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB. 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB. 0x2A OR/MODE select Open 0 = MODE 0x01 Selects I/O 1 = OR functionality in (default) conjunction with Address 0x08 for MODE (input) or OR (output) on External Pin 23. AD9266-Specific Customer SPI Control Register 0x10 USR2 Open Enable Run Open Disable 0x08 Enables internal 1 GCLK GCLK SDIO pull- oscillator for clock detect down rates of <5 MHz. Rev. B | Page 29 of 32

AD9266 Data Sheet MEMORY MAP REGISTER DESCRIPTIONS Bit 2—Run GCLK For additional information about functions that are controlled This bit enables the GCLK oscillator. For some applications in Register 0x00 to Register 0xFF, see the AN-877 Application with encode rates below 10 MSPS, it may be preferable to set Note, Interfacing to High Speed ADCs via SPI. this bit high to supersede the GCLK detector. USR2 (Register 0x101) Bit 0—Disable SDIO Pull-Down Bit 3—Enable GCLK Detect This bit can be set high to disable the internal 30 kΩ pull-down Normally set high, this bit enables a circuit that detects encode on the SDIO pin, which can be used to limit the loading when rates below about 5 MSPS. When a low encode rate is detected, many devices are connected to the SPI bus. an internal oscillator, GCLK, is enabled, ensuring the proper operation of several circuits. If set low, the detector is disabled. Rev. B | Page 30 of 32

Data Sheet AD9266 APPLICATIONS INFORMATION DESIGN GUIDELINES To maximize the coverage and adhesion between the ADC and the PCB, overlay a silkscreen to partition the continuous plane on Before starting design and layout of the AD9266 as a system, the PCB into several uniform sections. This provides several tie it is recommended that the designer become familiar with these points between the ADC and the PCB during the reflow process. guidelines, which discuss the special circuit connections and Using one continuous plane with no partitions guarantees only one layout requirements needed for certain pins. tie point between the ADC and the PCB. For detailed information Power and Ground Recommendations about packaging and PCB layout of chip scale packages, see the When connecting power to the AD9266, it is strongly recom- AN-772 Application Note, A Design and Manufacturing Guide mended that two separate supplies be used. Use one 1.8 V supply for the Lead Frame Chip Scale Package (LFCSP). for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the Encode Clock digital output supply (DRVDD). If a common 1.8 V AVDD and For optimum dynamic performance, use a low jitter encode DRVDD supply must be used, the AVDD and DRVDD domains clock source with a 50% duty cycle ± 5% to clock the AD9266. must be isolated with a ferrite bead or filter choke and separate VCM decoupling capacitors. Several different decoupling capacitors can be used to cover both high and low frequencies. Locate The VCM pin should be decoupled to ground with a 0.1 μF these capacitors close to the point of entry at the PCB level capacitor, as shown in Figure 38. and close to the pins of the part, with minimal trace length. RBIAS A single PCB ground plane should be sufficient when using the The AD9266 requires that a 10 kΩ resistor be placed between AD9266. With proper decoupling and smart partitioning of the the RBIAS pin and ground. This resistor sets the master current PCB analog, digital, and clock sections, optimum performance reference of the ADC core and should have at least a 1% tolerance. is easily achieved. Reference Decoupling Exposed Paddle Thermal Heat Sink Recommendations Externally decouple the VREF pin to ground with a low ESR, The exposed paddle (Pin 0) is the only ground connection for 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic the AD9266; therefore, it must be connected to analog ground capacitor. (AGND) on the PCB. To achieve the best electrical and thermal SPI Port performance, mate an exposed (no solder mask) continuous copper plane on the PCB to the AD9266 exposed paddle, Pin 0. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the The copper plane should have several vias to achieve the SCLK, CSB, and SDIO signals are typically asynchronous to the lowest possible resistive thermal path for heat dissipation to ADC clock, noise from these signals can degrade converter flow through the bottom of the PCB. Fill or plug these vias performance. If the on-board SPI bus is used for other devices, with nonconductive epoxy. it may be necessary to provide buffers between this bus and the AD9266 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. B | Page 31 of 32

AD9266 Data Sheet OUTLINE DIMENSIONS 5.10 0.30 5.00SQ 0.25 PIN1 4.90 0.18 INDICATOR PIN1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED *3.75 PAD 3.60SQ 3.55 17 8 0.50 16 9 0.25MIN TOPVIEW 0.40 BOTTOMVIEW 0.30 FORPROPERCONNECTIONOF 0.80 THEEXPOSEDPAD,REFERTO 0.75 THEPINCONFIGURATIONAND 0.05MAX FUNCTIONDESCRIPTIONS 0.70 0.02NOM SECTIONOFTHISDATASHEET. COPLANARITY 0.08 SEATING 0.20REF PLANE *CWOITMHPELXIACNETPTTOIOJNETDOECEXSPTOASNEDDARPDASDMDIOM-E22N0S-IWOHNH.D-5 08-16-2010-B Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9266BCPZ-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266BCPZRL7-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266BCPZ-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266BCPZRL7-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266BCPZ-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266BCPZRL7-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266BCPZ-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266BCPZRL7-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12 AD9266-80EBZ Evaluation Board AD9266-65EBZ Evaluation Board AD9266-40EBZ Evaluation Board AD9266-20EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2010–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08678-0-3/16(B) Rev. B | Page 32 of 32