14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter Data Sheet AD9245 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 3 V supply operation (2.7 V to 3.6 V) AVDD DRVDD SNR = 72.7 dBc to Nyquist AD9245 SFDR = 83.0 dBc to Nyquist Low power VVIINN+– SHA MDAC1 1 1/2-8B-SITT PAIGPEELINE A/D 366 mW at 80 MSPS 4 16 3 300 mW at 65 MSPS REFT A/D 165 mW at 40 MSPS REFB 90 mW at 20 MSPS CORRECTION LOGIC OTR Differential input with 500 MHz bandwidth 14 On-chip reference and sample-and-hold OUTPUT BUFFERS DNL = ±0.5 LSB D13 (MSB) VREF Flexible analog input: 1 V p-p to 2 V p-p range D0 (LSB) Offset binary or twos complement data format SENSE 0.5V CLOCK MODE Clock duty-cycle stabilizer REF DSUTTAYB ICLYIZCELRE SELECT A PPLICATIONS SELECT 03583-001 AGND CLK PDWN MODE DGND Medical imaging equipment Figure 1. IF sampling in communications receivers WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA A single-ended clock input is used to control all internal con- Battery-powered instruments version cycles. A duty cycle stabilizer (DCS) compensates for Hand-held scopemeters wide variations in the clock duty cycle while maintaining Spectrum analyzers excellent overall ADC performance. The digital output data is Power-sensitive military applications presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that GENERAL DESCRIPTION can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the The AD9245 is a monolithic, single 3 V supply, 14-bit, AD9245 is available in a 32-lead LFCSP and is specified over 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital the industrial temperature range (–40°C to +85°C). converter (ADC) featuring a high performance sample-and- PRODUCT HIGHLIGHTS hold amplifier (SHA) and voltage reference. The AD9245 uses a multistage differential pipelined architecture with output error 1. The AD9245 operates from a single 3 V power supply and correction logic to provide 14-bit accuracy and guarantee no features a separate digital output driver supply to missing codes over the full operating temperature range. accommodate 2.5 V and 3.3 V logic families. 2. The patented SHA input maintains excellent performance for The wide bandwidth, truly differential SHA allows a variety of input frequencies up to 100 MHz and can be configured for user-selectable input ranges and common modes, including single-ended or differential operation. single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and 3. The AD9245 is pin-compatible with the AD9215, AD9235, for sampling single-channel inputs at frequencies well beyond and AD9236. This allows a simplified migration from 10 bits the Nyquist rate. Combined with power and cost savings over to 14 bits and 20 MSPS to 80 MSPS. previously available analog-to-digital converters, the AD9245 is 4. The clock DCS maintains overall ADC performance over a suitable for applications in communications, imaging, and wide range of clock pulse widths. medical ultrasound. 5. The OTR output bit indicates when the signal is beyond the selected input range. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD9245 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 13 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 18 General Description ......................................................................... 1 Analog Input and Reference Overview ................................... 18 Functional Block Diagram .............................................................. 1 Clock Input Considerations ...................................................... 19 Product Highlights ........................................................................... 1 Jitter Considerations .................................................................. 20 Revision History ............................................................................... 2 Power Dissipation and Standby Mode .................................... 20 Specifications ..................................................................................... 3 Digital Outputs ........................................................................... 20 DC Specifications ......................................................................... 3 Timing.......................................................................................... 21 AC Specifications .......................................................................... 5 Voltage Reference ....................................................................... 21 Digital Specifications ................................................................... 7 Internal Reference Connection ................................................ 21 Switching Specifications .............................................................. 8 External Reference Operation .................................................. 22 Absolute Maximum Ratings ............................................................ 9 Operational Mode Selection ..................................................... 22 Thermal Resistance ...................................................................... 9 Evaluation Board ........................................................................ 22 ESD Caution .................................................................................. 9 Outline Dimensions ....................................................................... 29 Terminology .................................................................................... 10 Ordering Guide .......................................................................... 29 Pin Configuration and Function Descriptions ........................... 11 Equivalent Circuits ......................................................................... 12 REVISION HISTORY 5/13—Rev. D to Rev. E Changes to Table 5 ............................................................................. 7 Changed CP-32-2 to CP-32-7 ........................................... Universal Changes to Table 6 ............................................................................. 8 Changes to Figure 3 and Table 9 ................................................... 11 Deleted Explanation of Test Levels Table ....................................... 8 Changes to Figure 40 ...................................................................... 19 Added Figure 26 to Figure 31; Renumbered Sequentially ........ 16 Changes to Ordering Guide .......................................................... 29 Added Figure 32 to Figure 37; Renumbered Sequentially ........ 17 Changes to Figure 39 ...................................................................... 18 1/06—Rev. C to Rev. D Changes to Clock Input Consideration Section ......................... 19 Changes to Differential Input Configurations Section and Changes to Figure 44 ...................................................................... 20 Figure 40 .......................................................................................... 19 Changes to Table 10 ....................................................................... 21 Changes to Internal Reference Connection Section .................. 21 Changes to Figure 51 ...................................................................... 25 Changes to Figure 49 ...................................................................... 23 Changes to Table 12 ....................................................................... 28 Changes to Figure 50 ...................................................................... 24 Changes to Ordering Guide .......................................................... 29 Changes to Table 12 ........................................................................ 28 Updated Outline Dimensions ....................................................... 29 Updated Outline Dimensions ....................................................... 29 10/03—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 29 Changes to Figure 33 ...................................................................... 17 8/05—Rev. B to Rev. C 5/03—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Figure 30 ...................................................................... 15 Changes to Features, Applications, General Description, and Changes to Figure 37 ...................................................................... 19 Product Highlights ........................................................................... 1 Changes to Figure 38 ...................................................................... 20 Added Table 1; Renumbered Sequentially .................................... 3 Changes to Figure 39 ...................................................................... 21 Changes to Table 2 ............................................................................ 4 Changes to Table 10 ....................................................................... 24 Added Table 3; Renumbered Sequentially .................................... 5 Changes to the Ordering Guide ................................................... 25 Changes to Table 4 ............................................................................ 6 Rev. E | Page 2 of 32

Data Sheet AD9245 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted. Table 1. AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 14 14 14 Bits ACCURACY No Missing Codes Guaranteed 14 14 14 Bits Offset Error ±0.30 ±1.60 ±0.50 ±1.75 ±0.50 ±1.75 % FSR Gain Error1 ±0.30 ±3.25 ±0.50 ±3.25 ±0.50 ±6.90 % FSR Differential Nonlinearity (DNL)2 ±0.50 ±1.00 ±0.50 ±1.00 ±0.50 ±1.00 LSB Integral Nonlinearity (INL)2 ±1.20 ±3.10 ±1.40 ±3.40 ±1.60 ±5.55 LSB TEMPERATURE DRIFT1 Offset Error ±2 ±2 ±3 ppm/°C Gain Error ±12 ±12 ±12 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) ±5 ±35 ±5 ±35 ±5 ±35 mV Load Regulation @ 1.0 mA 0.8 0.8 0.8 mV Output Voltage Error (0.5 V Mode) ±2.5 ±2.5 ±2.5 mV Load Regulation @ 0.5 mA 0.1 0.1 0.1 mV INPUT REFERRED NOISE VREF = 0.5 V 2.28 2.28 2.28 LSB rms VREF = 1.0 V 1.08 1.08 1.08 LSB rms ANALOG INPUT Input Span, VREF = 0.5 V 1 1 1 V p-p Input Span, VREF = 1.0 V 2 2 2 V p-p Input Capacitance3 7 7 7 pF REFERENCE INPUT RESISTANCE 7 7 7 kΩ POWER SUPPLIES Supply Voltages AVDD 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V Supply Current IAVDD2 30 55 100 mA IDRVDD2 2 5 7 mA PSRR ±0.01 ±0.01 ±0.01 % FSR POWER CONSUMPTION DC Input4 90 165 300 mW Sine Wave Input2 95 120 180 220 320 375 mW Standby Power5 1.0 1.0 1.0 mW 1 Gain errors and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with a dc input, the CLK pin inactive (that is, set to AVDD or AGND). Rev. E | Page 3 of 32

AD9245 Data Sheet AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted. Table 2. AD9245BCP-80 Parameter Min Typ Max Unit RESOLUTION 14 Bits ACCURACY No Missing Codes Guaranteed Offset Error1 ±0.30 ±1.2 % FSR Gain Error ±0.28 % FSR Gain Error1 ±0.70 ±4.16 % FSR Differential Nonlinearity (DNL)2 ±0.5 ±1.0 LSB Integral Nonlinearity (INL)2 ±1.4 ±5.15 LSB TEMPERATURE DRIFT Offset Error1 ±10 ppm/°C Gain Error ±12 ppm/°C Gain Error1 ±17 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) ±3 ±34 mV Load Regulation @ 1.0 mA ±2 mV Output Voltage Error (0.5 V Mode) ±6 mV Load Regulation @ 0.5 mA ±1 mV INPUT REFERRED NOISE VREF = 0.5 V 1.86 LSB rms VREF = 1.0 V 1.17 LSB rms ANALOG INPUT Input Span, VREF = 0.5 V 1 V p-p Input Span, VREF = 1.0 V 2 V p-p Input Capacitance3 7 pF REFERENCE INPUT RESISTANCE 7 kΩ POWER SUPPLIES Supply Voltage AVDD 2.7 3.0 3.6 V DRVDD 2.25 2.5 3.6 V Supply Current IAVDD2 122 138 mA IDRVDD2 9 mA PSRR ±0.01 % FSR POWER CONSUMPTION Low Frequency Input4 366 mW Standby Power5 1.0 mW 1 With a 1.0 V internal reference. 2 Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure. 4 Measured at ac specification conditions without output drivers. 5 Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND). Rev. E | Page 4 of 32

Data Sheet AD9245 AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 3. AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 Parameter Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.4 MHz 73.5 73.5 73.1 dBc INPUT f = 9.7 MHz 70.6 73.3 dBc INPUT f = 19.6 MHz 70.5 73.4 dBc INPUT f = 32.5 MHz 70.3 72.7 dBc INPUT f = 100 MHz 70.8 71.3 70.2 dBc INPUT SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD) f = 2.4 MHz 73.4 73.4 73.0 dBc INPUT f = 9.7 MHz 69.4 73.2 dBc INPUT f = 19.6 MHz 70.0 73.2 dBc INPUT f = 32.5 MHz 68.4 72.6 dBc INPUT f = 100 MHz 69.5 69.1 67.9 dBc INPUT EFFECTIVE NUMBER OF BITS (ENOB) f = 9.7 MHz 11.9 Bits INPUT f = 19.6 MHz 11.8 Bits INPUT f = 32.5 MHz 11.7 Bits INPUT WORST HARMONIC (SECOND OR THIRD) f = 9.7 MHz –89 –80 dBc INPUT f = 19.6 MHz –89 –80 dBc INPUT f = 32.5 MHz –83 –74 dBc INPUT SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz 92.0 92.0 92.0 dBc INPUT f = 9.7 MHz 80.0 89.0 dBc INPUT f = 19.6 MHz 80.0 89.0 dBc INPUT f = 32.5 MHz 74.0 83.0 dBc INPUT f = 100 MHz 84.0 85.0 80.5 dBc INPUT Rev. E | Page 5 of 32

AD9245 Data Sheet AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 4. AD9245BCP-80 Parameter Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.4 MHz 71.1 73.3 dB IN f = 40 MHz 72.7 dB IN f = 70 MHz 70.5 71.7 dB IN f = 100 MHz 70.2 dB IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) f = 2.4 MHz 70.7 73.2 dB IN f = 40 MHz 72.5 dB IN f = 70 MHz 69.9 71.2 dB IN f = 100 MHz 69.6 dB IN EFFECTIVE NUMBER OF BITS (ENOB) f = 2.4 MHz 11.5 11.9 Bits IN f = 40 MHz 11.8 Bits IN f = 70 MHz 11.3 11.5 Bits IN f = 100 MHz 11.3 Bits IN WORST HARMONIC (SECOND OR THIRD) f = 2.4 MHz −92.8 –76.5 dBc IN f = 40 MHz –87.6 dBc IN f = 70 MHz −81.6 –75.7 dBc IN f = 100 MHz –79.0 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 2.4 MHz 76.5 92.8 dBc IN f = 40 MHz 87.6 dBc IN f = 70 MHz 75.7 81.6 dBc IN f = 100 MHz 79.0 dBc IN Rev. E | Page 6 of 32

Data Sheet AD9245 DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted. Table 5. AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-801 Parameter Min Typ Max Unit LOGIC INPUTS (CLK, PDWN) High Level Input Voltage 2.0 V Low Level Input Voltage 0.8 V High Level Input Current –10 +10 µA Low Level Input Current –10 +10 µA Input Capacitance 2 pF DIGITAL OUTPUT BITS (D0 to D13, OTR)2 DRVDD = 3.3 V High Level Output Voltage (IOH = 50 µA) 3.29 V High Level Output Voltage (IOH = 0.5 mA) 3.25 V Low Level Output Voltage (IOH = 1.6 mA) 0.2 V Low Level Output Voltage (IOH = 50 µA) 0.05 V DRVDD = 2.5 V High Level Output Voltage (IOH = 50 µA) 2.49 V High Level Output Voltage (IOH = 0.5 mA) 2.45 V Low Level Output Voltage (IOH = 1.6 mA) 0.2 V Low Level Output Voltage (IOH = 50 µA) 0.05 V 1 AD9245BCP-80 performance measured with 1.0 V external reference. 2 Output voltage levels measured with 5 pF load on each output. Rev. E | Page 7 of 32

AD9245 Data Sheet SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted. Table 6. AD9245BCP-20 AD9245BCP-40 AD9245BCP-65 AD9245BCP-80 Unit Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS Maximum Conversion Rate 20 40 65 80 MSPS Minimum Conversion Rate 1 1 1 1 MSPS CLK Period 50.0 25.0 15.4 12.5 ns CLK Pulse Width High1 15.0 8.8 6.2 4.6 ns CLK Pulse Width Low1 15.0 8.8 6.2 4.6 ns DATA OUTPUT PARAMETERS Output Delay2 (t ) 3.5 3.5 3.5 4.2 ns PD Pipeline Delay (Latency) 7 7 7 7 Cycles Aperture Delay (t ) 1.0 1.0 1.0 1.0 ns A Aperture Uncertainty Jitter (t) 0.5 0.5 0.5 0.3 ps rms J Wake-Up Time3 3.0 3.0 3.0 7.0 ms OUT-OF-RANGE RECOVERY TIME 1 1 2 2 Cycles 1 For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40 models. 2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. N+1 N N+2 N+8 N–1 N+3 t ANALOG A INPUT N+4 N+7 N+5 N+6 CLK DATA N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N OUT tPD = 62..00nnss MMAINX 03583-002 Figure 2. Timing Diagram Rev. E | Page 8 of 32

Data Sheet AD9245 ABSOLUTE MAXIMUM RATINGS Table 7. THERMAL RESISTANCE Parameter With Respect to Min Max Unit θ is specified for the worst-case conditions on a 4-layer board ELECTRICAL JA in still air, in accordance with EIA/JESD51-1. AVDD AGND –0.3 +3.9 V DRVDD DGND –0.3 +3.9 V Table 8. Thermal Resistance AGND DGND –0.3 +0.3 V Package Type θJA θJC Unit AVDD DRVDD –3.9 +3.9 V 32-Lead LFCSP 32.5 32.71 °C/W D0 to D13 DGND –0.3 DRVDD + 0.3 V CLK, MODE AGND –0.3 AVDD + 0.3 V Airflow increases heat dissipation, effectively reducing θ . JA VIN+, VIN– AGND –0.3 AVDD + 0.3 V In addition, more metal directly in contact with the package VREF AGND –0.3 AVDD + 0.3 V leads from metal traces, through holes, ground, and power SENSE AGND –0.3 AVDD + 0.3 V planes reduces the θ . It is recommended that the exposed JA REFT, REFB AGND –0.3 AVDD + 0.3 V paddle be soldered to the ground plane for the LFCSP package. PDWN AGND –0.3 AVDD + 0.3 V There is an increased reliability of the solder joints, and ENVIRONMENTAL maximum thermal capability of the package is achieved with Storage Temperature Range –65 +125 °C the exposed paddle soldered to the customer board. Operating Temperature Range –40 +85 °C Lead Temperature 300 °C (Soldering 10 sec) Junction Temperature 150 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. E | Page 9 of 32

AD9245 Data Sheet TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) Signal-to-Noise and Distortion (SINAD)1 The analog input frequency at which the spectral power of the The ratio of the rms input signal amplitude to the rms value of fundamental frequency (as determined by the FFT analysis) is the sum of all other spectral components below the Nyquist reduced by 3 dB. frequency, including harmonics but excluding dc. Aperture Delay (t ) Effective Number of Bits (ENOB) A The delay between the 50% point of the rising edge of the clock The effective number of bits for a sine wave input at a given and the instant at which the analog input is sampled. input frequency can be calculated directly from its measured SINAD using the following formula: Aperture Uncertainty (Jitter, t) J The sample-to-sample variation in aperture delay. (SINAD−1.76) ENOB= 6.02 Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from Signal-to-Noise Ratio (SNR)1 negative full scale through positive full scale. The point used as The ratio of the rms input signal amplitude to the rms value of negative full scale occurs ½ LSB before the first code transition. the sum of all other spectral components below the Nyquist Positive full scale is defined as a level 1½ LSB beyond the last frequency, excluding the first six harmonics and dc. code transition. The deviation is measured from the middle of Spurious-Free Dynamic Range (SFDR)1 each particular code to the true straight line. The difference in dB between the rms input signal amplitude Differential Nonlinearity (DNL, No Missing Codes) and the peak spurious signal. The peak spurious component An ideal ADC exhibits code transitions that are exactly 1 LSB may or may not be a harmonic. apart. DNL is the deviation from this ideal value. Guaranteed Two-Tone SFDR1 no missing codes to 14-bit resolution indicates that all 16,384 The ratio of the rms value of either input tone to the rms value codes must be present over all operating ranges. of the peak spurious component. The peak spurious component Offset Error may or may not be an IMD product. The major carry transition should occur for an analog value Clock Pulse Width and Duty Cycle ½ LSB below VIN+ = VIN–. Offset error is defined as the Pulse width high is the minimum amount of time that the clock deviation of the actual transition from that point. pulse should be left in the Logic 1 state to achieve rated Gain Error performance. Pulse width low is the minimum time the clock The first code transition should occur at an analog value ½ LSB pulse should be left in the Logic 0 state. At a given clock rate, above negative full scale. The last transition should occur at an these specifications define an acceptable clock duty cycle. analog value 1½ LSB below the positive full scale. Gain error is Minimum Conversion Rate the deviation of the actual difference between first and last code The clock rate at which the SNR of the lowest analog signal transitions and the ideal difference between first and last code frequency drops by no more than 3 dB below the guaranteed limit. transitions. Maximum Conversion Rate Temperature Drift The clock rate at which parametric testing is performed. The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value Output Propagation Delay (t ) PD at T or T . MIN MAX The delay between the clock rising edge and the time when all bits are within valid logic levels. Power Supply Rejection Ratio The change in full scale from the value with the supply at the Out-of-Range Recovery Time minimum limit to the value with the supply at its maximum limit. The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% Total Harmonic Distortion (THD)1 above negative full scale, or from 10% below negative full scale The ratio of the rms input signal amplitude to the rms value of to 10% below positive full scale. the sum of the first six harmonic components. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. E | Page 10 of 32

Data Sheet AD9245 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DDVADNGA–NIV+NIVDNGADDVATFERBFER 21098765 33322222 DNC 1 24 VREF CLK 2 23 SENSE DNC 3 22 MODE AD9245 PDWN 4 21 OTR (LSB) D0 5 TOP VIEW 20 D13 (MSB) (Not to Scale) D1 6 19 D12 D2 7 18 D11 D3 8 17 D10 910111213141516 456789DD DDDDDDND GV DR D NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS RECOMMENDED THAT THE EXPOSED PADDLE BE SOLDERED TO THE GROUND PLANE FAEOXNPDRO TTSHHEEED ML PFAACXDSIDMPL UPEMA S CTOKHLAEDGREEMR.A ETLDH CETAROPE TA IHSBE IAL CNITU YISN OTCOFR METAEHSREE BPDAO RCAEKRLADIGA.BEI LISIT AYC OHFIE TVHEED SWOITLHD ETRH EJOINTS, 03583-022 Figure 3. LFCSP Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic Description 1, 3 DNC Do Not Connect 2 CLK Clock Input Pin 4 PDWN Power-Down Function Select 5 to 14, 17 to 20 D0 (LSB) to D13 (MSB) Data Output Bits 15 DGND Digital Output Ground 16 DRVDD Digital Output Driver Supply 21 OTR Out-of-Range Indicator 22 MODE Data Format Select and DCS Mode Selection (See Table 11) 23 SENSE Reference Mode Selection (See Table 10) 24 VREF Voltage Reference Input/Output 25 REFB Differential Reference (–) 26 REFT Differential Reference (+) 27, 32 AVDD Analog Power Supply 28, 31 AGND Analog Ground 29 VIN+ Analog Input Pin (+) 30 VIN– Analog Input Pin (–) EPAD Exposed Pad. It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board. Rev. E | Page 11 of 32

AD9245 Data Sheet EQUIVALENT CIRCUITS AVDD DRVDD VIN+, VIN– D13-D0, OTR 03583-003 03583-005 Figure 4. Equivalent Analog Input Circuit Figure 6. Equivalent Digital Output Circuit AVDD AVDD CLK, MODE PDWN 20k 03583-004 03583-006 Figure 5. Equivalent MODE Input Circuit Figure 7. Equivalent Digital Input Circuit Rev. E | Page 12 of 32

Data Sheet AD9245 TYPICAL PERFORMANCE CHARACTERISTICS DUT = AD9245-80, AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, DCS disabled, T = 25°C, 2 V p-p differential input, A AIN = −0.5 dBFS, VREF = 1.0 V external, unless otherwise noted. 0 100 AIN =–0.5dBFS SFDR (dBFS) –10 SNR = 73.2dBc ENOB = 11.8 BITS –20 SFDR = 92.8dBc 90 SFDR (dBc) –30 S) F S) –40 dB 80 SNR (dBFS) DE (dBF ––5600 Bc AND 70 MPLITU ––7800 FDR (d 60 SRFEDFRER =E 9N0CdEB cLINE A –90 NR/S SNR (dBc) S –100 50 ––112100 03583-032 40 03583-033 0 5 10 15 20 25 30 35 40 –30 –25 –20 –15 –10 –5 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 8. Single Tone 8K FFT @ 2.5 MHz Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz 0 100 AIN =–0.5dBFS SFDR (dBFS) –10 SNR = 72.7dBc ENOB = 11.8 BITS –20 SFDR = 87.6dBc 90 SFDR (dBc) –30 S) F S) –40 dB 80 SNR (dBFS) DE (dBF ––5600 Bc AND 70 MPLITU ––7800 FDR (d 60 SRFEDFRER =E 9N0CdEB cLINE A –90 NR/S SNR (dBc) S –100 50 ––112100 03583-023 40 03583-034 0 5 10 15 20 25 30 35 40 –30 –25 –20 –15 –10 –5 0 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 9. Single Tone 8K FFT @ 39 MHz Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz 0 100 AIN =–0.5dBFS –10 SNR = 71.7dBc SFDR (DIFF) ENOB = 11.5 BITS –20 SFDR = 81.6dBc 90 –30 BFS) ––4500 Bc) 80 SFDR (SE) SNR (DIFF) d d E ( –60 R ( D D U F LIT –70 R/S 70 MP –80 SN A SNR (SE) –90 60 –100 ––112100 03583-024 50 03583-025 0 5 10 15 20 25 30 35 40 0 20 40 60 80 100 FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 10. Single Tone 8K FFT @ 70 MHz Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz Rev. E | Page 13 of 32

AD9245 Data Sheet 0 100 AIN =–6.5dBFS SFDR (dBFS) –10 SNR = 73.4dBFS SFDR = 86.0dBFS –20 90 SFDR (dBc) –30 S) F –40 B 80 S) d BF –50 ND E (d –60 c A 70 D B U d SNR (dBFS) AMPLIT ––8700 R/SFDR ( 60 SRFEDFRER =E 9N0CdEB cLINE –90 SN SNR (dBc) –100 50 ––112100 03583-029 40 03583-031 0 5 10 15 20 25 30 35 40 –30 –27 –24 –21 –18 –15 –12 –9 –6 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz 0 100 AIN =–6.5dBFS SFDR (dBFS) –10 SNR = 72.7dBFS –20 SFDR = 78.8dBFS 90 SFDR (dBc) –30 S) F –40 B 80 FS) D d B –50 N d A E ( –60 c 70 LITUD –70 DR (dB SNR (dBFS) AMP –80 R/SF 60 SRFEDFRER =E 9N0CdEB cLINE –90 N SNR (dBc) S –100 50 ––112100 03583-030 40 03583-027 0 5 10 15 20 25 30 35 40 –30 –27 –24 –21 –18 –15 –12 –9 –6 FREQUENCY (MHz) INPUT AMPLITUDE (dBFS) Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz 1.5 1.0 0.8 1.0 0.6 0.4 0.5 0.2 INL (LSB) 0 DNL (LSB) –0.02 –0.5 –0.4 –0.6 –1.0 –1.5 03583-026 ––10..08 03583-028 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 16. Typical INL Figure 19. Typical DNL Rev. E | Page 14 of 32

Data Sheet AD9245 75 100 74 –40C 95 73 +25C 72 90 71 Bc) +85C Bc) R (d 70 R (d 85 –40C SN 69 SFD 80 68 +25C 67 +85C 75 6656 03583-036 70 03583-038 0 25 50 75 100 125 0 25 50 75 100 125 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) Figure 20. SNR vs. Input Frequency Figure 23. SFDR vs. Input Frequency 90 0 SFDR (DCS ON) –10 88 –20 86 –30 84 S) –40 Bc) 82 SFDR (DCS OFF) dBF –50 R (d 80 DE ( –60 D U R/SF 78 PLIT –70 N M –80 S 76 A –90 74 SNR (DCS OFF) –100 770230 35 40 45 SNR5 (0DCS O5N5) 60 65 7003583-037 ––1121000 9.6 19.2 28.8 38.03583-0604 DUTY CYCLE (%) FREQUENCY (MHz) Figure 21. SNR/SFDR vs. Clock Duty Cycle Figure 24. Two 32K FFT CDMA-2000 Carriers @ FIN = 46.08 MHz; Sample Rate = 61.44 MSPS 0 0 –10 –10 –20 –20 –30 –30 S) –40 S) –40 F F B B d –50 d –50 E ( E ( D –60 D –60 U U LIT –70 LIT –70 P P M –80 M –80 A A –90 –90 –100 –100 ––112100 03583-059 ––112100 03583-061 0 9.6 19.2 28.8 38.4 0 9.6 19.2 28.8 38.4 FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. 32K FFT WCDMA Carrier @ FIN = 96 MHz; Sample Rate = 76.8 MSPS Figure 25. Two 32K FFT WCDMA Carriers @ FIN = 76.8 MHz; Sample Rate = 61.44 MSPS Rev. E | Page 15 of 32

AD9245 Data Sheet 0 0 AIN =–0.5dBFS AIN =–0.5dBFS SNR = 72.7dBc SNR = 73.4dBc –20 ENOB = 11.7 BITS –20 ENOB = 11.9 BITS SFDR = 81.3dBc SFDR = 88.3dBc S) –40 S)–40 F F B B d d E ( E ( D –60 D–60 U U T T LI LI P P AM –80 AM–80 –100 –100 –120 03583-062 –120 03583-065 0 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) FREQUENCY (MHz) Figure 26. AD9245-65 Single Tone 16K FFT @ 35 MHz Figure 29. AD9245-40 Single Tone 16K FFT @ 19.7 MHz 2.0 1.0 0.8 1.5 0.6 1.0 0.4 0.5 B) B) 0.2 S S L (L 0 L (L 0 N N I D–0.2 –0.5 –0.4 –1.0 –0.6 ––12..50 03583-063 ––01..80 03583-066 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 27. AD9245-65 Typical INL Figure 30. AD9245-65 Typical DNL 2.0 1.0 1.5 0.8 0.6 1.0 0.4 0.5 B) B) 0.2 S S L (L 0 L (L 0 N N I–0.5 D–0.2 –0.4 –1.0 –0.6 ––12..50 03583-064 ––01..80 03583-067 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 28. AD9245-40 Typical INL Figure 31. AD9245-40 Typical DNL Rev. E | Page 16 of 32

Data Sheet AD9245 2.0 1.0 1.5 0.8 0.6 1.0 0.4 0.5 B) B) 0.2 S S NL (L 0 NL (L 0 I D–0.2 –0.5 –0.4 –1.0 –0.6 ––12..50 ––01..80 03583-071 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 32. AD9245-20 Typical INL Figure 35. AD9245-20 Typical DNL 0 0 AIN =–0.5dBFS AIN =–0.5dBFS SNR = 73.4dBc SNR = 73.3dBc –20 ENOB = 11.9 BITS –20 ENOB = 11.9 BITS SFDR = 95.0dBc SFDR = 92.6dBc BFS)–40 BFS)–40 E (d E (d UD–60 UD–60 PLIT PLIT AM–80 AM–80 –100 –100 –120 03583-069 –120 03583-072 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. AD9245-20 Single Tone 16K FFT @ 5 MHz Figure 36. AD9245-20 Single Tone 16K FFT @ 9.7 MHz 75 –0.5dBFS 10004707 70 7996189 –6dBFS 7281624 c)65 B S d T D ( HI A N SI60 3167101 1755666 55 50 –20dBFS 03583-070 25N3–6325 N–2 N–1 N N+1 N+2 54N7+4398 03583-073 1 10 100 CODE INPUT FREQUENCY (MHz) Figure 34. AD9245-20 SINAD vs. Input Frequency Figure 37. AD9245-20 Grounded-Input Histogram Rev. E | Page 17 of 32

AD9245 Data Sheet THEORY OF OPERATION The AD9245 architecture consists of a front-end sample-and- Referring to Figure 39, the clock signal alternately switches the hold amplifier (SHA) followed by a pipelined switched capacitor SHA between sample mode and hold mode. When the SHA is ADC. The pipelined ADC is divided into three sections switched into sample mode, the signal source must be capable consisting of a 4-bit first stage followed by eight 1.5-bit stages, of charging the sample capacitors and settling within one-half and a final 3-bit flash. Each stage provides sufficient overlap to of a clock cycle. A small resistor in series with each input can correct for flash errors in the preceding stages. The quantized help reduce the peak transient current required from the output outputs from each stage are combined into a final 14-bit result stage of the driving source. In addition, a small shunt capacitor in the digital correction logic. The pipelined architecture can be placed across the inputs to provide dynamic charging permits the first stage to operate on a new input sample, while currents. This passive network creates a low-pass filter at the the remaining stages operate on preceding samples. Sampling ADC’s input; therefore, the precise values are dependent upon occurs on the rising edge of the clock. the application. In IF undersampling applications, any shunt capacitors should be reduced or removed. In combination with Each stage of the pipeline, excluding the last, consists of a low the driving source impedance, they would limit the input resolution flash ADC connected to a switched capacitor DAC bandwidth. and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output H and the flash input for the next stage in the pipeline. One bit of T T redundancy is used in each stage to facilitate digital correction 5pF of flash errors. The last stage simply consists of a flash ADC. VIN+ CPAR The input stage contains a differential SHA that can be ac-coupled or dc-coupled in differential or single-ended modes. T The output staging block aligns the data, carries out the error 5pF VIN– correction, and passes the data to the output buffers. The output CPAR buffers are powered from a separate supply, allowing adjustment of T tbhuef foeurst pguot ivnotolt aag he isgwhi inmg.p Deduarnincge sptoawtee. r -down, the output H 03583-012 Figure 39. Switched-Capacitor SHA Input ANALOG INPUT AND REFERENCE OVERVIEW For best dynamic performance, the source impedances driving The analog input to the AD9245 is a differential switched- VIN+ and VIN– should be matched such that common-mode capacitor SHA that has been designed for optimum performance settling errors are symmetrical. These errors are reduced by the while processing a differential input signal. The SHA input can common-mode rejection of the ADC. support a wide common-mode range (VCM) and maintain excellent performance, as shown in Figure 38. An input An internal differential reference buffer creates positive and common-mode voltage of midsupply minimizes signal- negative reference voltages, REFT and REFB, that define the dependent errors and provides optimum performance. span of the ADC core. The output common mode of the 100 reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as: 95 90 SFDR (2.5MHz) REFT = ½ (AVDD + VREF) REFB = ½ (AVDD − VREF) 85 SFDR (39MHz) Bc) 80 Span = 2 × (REFT − REFB) = 2 × VREF d DR ( 75 SNR (2.5MHz) The previous equations show that the REFT and REFB voltages F R/S 70 SNR (39MHz) are symmetrical about the midsupply voltage, and, by definition, N S 65 the input span is twice the value of the VREF voltage. 60 The internal voltage reference can be pin strapped to fixed 5505 03583-039 vdaislucuess soefd 0 i.n5 tVh eo rIn 1t.e0r nVa, lo Rr eafdejruesntecde Cwoitnhnine ctthioe ns asmecet iroann.g e as 0.5 1.0 1.5 2.0 2.5 3.0 Maximum SNR performance is achieved with the AD9245 set COMMON-MODE LEVEL (V) to the largest input span of 2 V p-p. The relative SNR degradation Figure 38. AD9245-80 SNR/SFDR vs. Common-Mode Level is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. Rev. E | Page 18 of 32

Data Sheet AD9245 The SHA can be driven from a source that keeps the signal peaks within the allowable range for the selected reference 33Ω AVDD voltage. The minimum and maximum common-mode input VIN+ levels are defined as 2V p-p 49.9Ω 20pF AD9245 VREF VCMMIN = 33Ω 2 VIN– (AVDD+VREF) AGND VCMMAX = 1kΩ 2 Tachceo mmminoimdautme g croomunmdo rne-fmeroendcee idn pinupt uletsv.e l allows the AD9245 to 0.1µF 1kΩ 03583-014 Figure 41. Differential Transformer-Coupled Configuration Although optimum performance is achieved with a differential input, a single-ended source can be applied to VIN+ or VIN–. The signal characteristics must be considered when selecting In this configuration, one input accepts the signal, while the a transformer. Most RF transformers saturate at frequencies opposite input is set to midscale by connecting it to an below a few MHz, and excessive signal power can also cause appropriate reference. For example, a 2 V p-p signal can be core saturation, which leads to distortion. applied to VIN+ while a 1 V reference is applied to VIN–. The Single-Ended Input Configuration AD9245 then accepts an input signal varying between 2 V and A single-ended input can provide adequate performance in 0 V. In the single-ended configuration, distortion performance cost-sensitive applications. In this configuration, there is a can degrade significantly as compared to the differential case. degradation in SFDR and distortion performance due to the However, the effect is less noticeable at lower input frequencies. large input common-mode swing (see Figure 13). However, if Differential Input Configurations the source impedances on each input are matched, there should As previously detailed, optimum performance is achieved while be little effect on SNR performance. Figure 42 details a typical driving the AD9245 in a differential input configuration. For single-ended input configuration. baseband applications, the AD8351 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8351 is easily set to 1kΩ 33Ω AVDD VIN+ AVDD/2, and the driver can be configured in a Sallen-Key filter 2V p-p 49.9Ω 0.33µF 1kΩ topology to provide band limiting of the input signal. 20pF AD9245 1kΩ 33Ω + VIN– 0.1µF 1.2kΩ 1kΩ33Ω VIN+AVDD 10µF 0.1µF 1kΩ AGND 03583-015 2V p-p 50Ω 25Ω AD8351 20pF AD9245 Figure 42. Single-Ended Input Configuration 33Ω 25Ω 0.1mF VIN– CLOCK INPUT CONSIDERATIONS 1kΩ AGND 03583-013 Typical high speed ADCs use both clock edges to generate a Figure 40. Differential Input Configuration Using the AD8351 variety of internal timing signals, and as a result can be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the At input frequencies in the second Nyquist zone and above, the clock duty cycle to maintain dynamic performance characteristics. performance of most amplifiers is not adequate to achieve the The AD9245-80 and AD9245-65 contain a clock duty cycle true performance of the AD9245. This is especially true in IF stabilizer (DCS) that retimes the nonsampling edge, providing an undersampling applications where frequencies in the 70 MHz to internal clock signal with a nominal 50% duty cycle. This allows a 100 MHz range are being sampled. For these applications, wide range of clock input duty cycles without affecting the differential transformer coupling is the recommended input performance of the AD9245. As shown in Figure 21, noise and configuration. The value of the shunt capacitor is dependent on distortion performance is nearly flat for a 30% to 70% duty cycle the input frequency and source impedance and should be with the DCS on. reduced or removed. An example is shown in Figure 41. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. Rev. E | Page 19 of 32

AD9245 Data Sheet JITTER CONSIDERATIONS which is determined by the sample rate and the characteristics of the analog input signal. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input 450 frequency (f ) due only to aperture jitter (t) can be INPUT J calculated with the following equation: 400 AD9245-80 SNR = −20log10[2π fINPUT × tj] 350 W) Imne tahne seqquuaarteio onf ,a tlhl eji trtmers saopuerrcteusr,e w jihttiecrh rienpcrluesdeen tths eth celo rcoko tin-put, ER (m300 AD9245-65 analog input signal, and ADC aperture jitter specification. IF OW250 P undersampling applications are particularly sensitive to jitter L A200 (see Figure 43). TOT AD9245-40 150 The clock input should be treated as an analog signal in cases wAfrohDme9r2 et4 ha5ep. eAProDtuwCree r oj isututtpeprup ctli adensr ifavofefrre ccsltuo tpchpke ld idersyi vnteoar mas vsioch iordau nmldgo ebd oeu fsl atehtpiena rga tthede 10500 AD9245-20 03583-074 0 10 20 30 40 50 60 70 80 clock signal with digital noise. Low jitter, crystal-controlled SAMPLE RATE (MSPS) oscillators make the best clock sources. If the clock is generated Figure 44. AD9245 Power vs. Sample Rate @ 2.5 MHz from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 44 was 75 taken with the same operating conditions as those reported in 0.2ps the Typical Performance Characteristics section, and with a 70 5 pF load on each output driver. MEASURED SNR 65 By asserting the PDWN pin high, the AD9245 is placed in 0.5ps standby mode. In this state, the ADC typically dissipates 60 c) 1.0ps 1 mW if the CLK and analog inputs are static. During standby, B R (d 55 1.5ps the output drivers are placed in a high impedance state. N Reasserting the PDWN pin low returns the AD9245 to its S 2.0ps 2.5ps normal operational mode. 50 3.0ps Low power dissipation in standby mode is achieved by shutting 45 down the reference, reference buffer, and biasing networks. The 40 03583-041 denetceoruinpgli nstga ncadpbayc imtoords eo nan RdE tFhTen a nmdu RstE bFeB r eacrhe adrigsecdh awrgheedn w hen 1 10 100 1000 INPUT FREQUENCY (MHz) returning to normal operation. As a result, the wake-up time is Figure 43. SNR vs. Input Frequency and Jitter related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the POWER DISSIPATION AND STANDBY MODE recommended 0.1 μF and 10 μF decoupling capacitors on REFT As shown in Figure 44, the power dissipated by the AD9245 is and REFB, it takes approximately 1 second to fully discharge the proportional to its sample rate. The digital power dissipation is reference buffer decoupling capacitors and 7 ms to restore full determined primarily by the strength of the digital drivers and operation. the load on each output bit. The maximum DRVDD current DIGITAL OUTPUTS (I ) can be calculated as DRVDD The AD9245 output drivers can be configured to interface with I V C f N DRVDD DRVDD LOAD CLK 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to where N is the number of output bits, 14 in the case of the provide sufficient output current to drive a wide variety of logic AD9245. This maximum current occurs when every output bit families. However, large drive currents tend to cause current switches on every clock cycle, that is, a full-scale square wave at glitches on the supplies, which can affect converter performance. the Nyquist frequency, f /2. In practice, the DRVDD current CLK Applications requiring the ADC to drive large capacitive loads or is established by the average number of output bits switching, large fanouts can require external buffers or latches. Rev. E | Page 20 of 32

Data Sheet AD9245 As detailed in Table 11, the data format can be selected for either In all reference configurations, REFT and REFB drive the A/D offset binary or twos complement. conversion core and establish its input span. The input range of TIMING the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. The AD9245 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to VIN+ Figure 2 for a detailed timing diagram. VIN– REFT The length of the output data lines and the loads placed on 0.1F ADC + them should be minimized to reduce transients within the CORE 0.1F 10F AD9245. These transients can degrade the converter’s dynamic REFB performance. 0.1F VREF The lowest typical conversion rate of the AD9245 is 1 MSPS. At 10F+ 0.1F SELECT clock rates below 1 MSPS, dynamic performance can degrade. LOGIC VOLTAGE REFERENCE SENSE A stable and accurate 0.5 V voltage reference is built into the 0.5V AD9245. The input range can be adjusted by varying the rinefteerrennacl er evfoelrteangcee a oprp aline de xtote trhnea lAlyD a9p2p4li5e du srienfge reeinthceer v tohleta ge. AD9245 03583-017 The input span of the ADC tracks reference voltage changes Figure 45. Internal Reference Configuration linearly. The various reference modes are summarized in Table 10 and described in the following sections. If the internal reference of the AD9245 is used to drive multiple converters to improve gain matching, the loading of the reference If the ADC is being driven differentially through a transformer, by the other converters must be considered. Figure 46 depicts the reference voltage can be used to bias the center tap how the internal reference voltage is affected by loading. A (common-mode voltage). 2 mA load is the maximum recommended load. INTERNAL REFERENCE CONNECTION 0.05 A comparator within the AD9245 detects the potential at the SENSE pin and configures the reference into one of four 0 possible states, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the –0.05 0.5V ERROR (%) internal resistor divider (see Figure 45), setting VREF to 1 V. %) Connecting the SENSE pin to VREF switches the reference OR ( –0.10 amplifier output to the SENSE pin, completing the loop and RR E 1.0V ERROR (%) providing a 0.5 V reference output. If a resistor divider is –0.15 connected as shown in Figure 47, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting –0.20 mode with the VREF output defined as VREF0.51R2 –0.250 0.5 1.0 1.5 2.0 2.5 3.003583-019  R1 LOAD (mA) Figure 46. VREF Accuracy vs. Load Table 10. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference AVDD N/A 2 × External Reference Internal Fixed Reference VREF 0.5 1.0 Programmable Reference 0.2 V to VREF 0.51 R2 (See Figure 47) 2 × VREF  R1 Internal Fixed Reference AGND to 0.2 V 1.0 2.0 Rev. E | Page 21 of 32

AD9245 Data Sheet OPERATIONAL MODE SELECTION VIN+ As discussed earlier, the AD9245 can output data in either VIN– REFT offset binary or twos complement format. There is also a provision for enabling or disabling the clock DCS. The 0.1F ADC + CORE 0.1F 10F MODE pin is a multilevel input that controls the data format REFB and DCS state. The input threshold values and corresponding 0.1F mode selections are outlined in Table 11. VREF + Table 11. Mode Selection 10F 0.1F SELECT R2 LOGIC MODE Voltage Data Format Duty Cycle Stabilizer SENSE AVDD Twos Complement Disabled 2/3 AVDD Twos Complement Enabled R1 0.5V 1/3 AVDD Offset Binary Enabled AGND (Default) Offset Binary Disabled AD9245 03583-018 EVALUATION BOARD Figure 47. Programmable Reference Configuration The AD9245 evaluation board provides the support circuitry EXTERNAL REFERENCE OPERATION required to operate the ADC in its various modes and configurations. Complete schematics and layout plots follow The use of an external reference can be necessary to enhance and demonstrate the proper routing and grounding techniques the gain accuracy of the ADC or improve thermal drift char- that should be applied at the system level. acteristics. When multiple ADCs track one another, a single reference (internal or external) can be necessary to reduce It is critical that signal sources with very low phase noise gain matching errors to an acceptable level. Figure 48 shows (<1 ps rms jitter) be used to realize the ultimate performance of the typical drift characteristics of the internal reference in both the converter. Proper filtering of the input signal, to remove 1.0 V and 0.5 V modes. harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal The AD9245 can be driven single-ended or differentially reference buffer loads the external reference with an equivalent through a transformer. Separate power pins are provided to 7 kΩ load. The internal buffer still generates the positive and isolate the DUT from the support circuitry. Each input negative full-scale references, REFT and REFB, for the ADC configuration can be selected by proper connection of core. The input span is always twice the value of the reference various jumpers (refer to the schematics). voltage; therefore, the external reference must be limited to a maximum of 1.0 V. An alternative differential analog input path using an AD8351 op amp is included in the layout but is not populated 1.0 in production. Designers interested in evaluating the op amp 0.9 with the ADC should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 0.8 outputs and the AD9245 allows the user to optimize the 0.7 frequency response of the op amp for the application. %) 0.6 R ( O R 0.5 R E F 0.4 E R V 0.3 VREF = 1.0V 0.2 0.01 VREF = 0.5V 03583-040 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) Figure 48. Typical VREF Drift Rev. E | Page 22 of 32

Data Sheet AD9245 LE6 LE6 LE6 LE6 DRXD13X D12XD11XD10XD9X D8XD7X D6XD5X D4XD3XD2XD1X D0X O O O O H H H H H1MT H2MT H3MT H4MT 16 1514131211 109 16 1514131211 109 LT) U A GND 1234562P PDDDLDDMDNNDVVVGGARAVD VVVV0550....3225 OVERRANGE BITΩRP2 220(MSB) 1 23456 78RVDDND 1 23456 78(LSB) ΩRP1 220 SENSE PIN SOLDERABLE JUMPER:E TO A:EXTERNAL VOLTAGE DIVIDERE TO B:INTERNAL 1V REFERENCE (DEFE TO C:EXTERNAL REFERENCEE TO D:INTERNAL 0.5V REFERENCE MODE PIN SOLDERABLE JUMPER:5 TO 1:TWOS COMPLEMENT/DCS OFF5 TO 2:TWOS COMPLEMENT/DCS ON5 TO 3:OFFSET BINARY/DCS ON5 TO 4:OFFSET BINARY/DCS OFF DG 16 1514131211 109 7101D DVDDDGNDD9D8D7D6 D5D4 3D8 GND C8µ0.1F D 98112111DD 45 21DD67 R8Ω1k GN 1022R31TDO AD92U4 NWD0DP45 P13 DE P5 3222EESDNOEMS CKNLDC23 LK P14 D MO2 42FERV REFBREFT AVDDAGNDVIN+VIN– AGNDAVDD CND1 C AVD 25 2627282930 3132 GND 1P6 R5Ω1k 2P1 R7Ω1k 3P3 R6Ω1k 4P4 D AVDDGNDVIN+VIN– GNDAVDD R25Ω1k N D G AVDD C22µ10F ND GN R26Ω1k C2110pF GND C19OR L1FOR FILTERGND C2310pF DDR13Ω1k G pF AV EXTREF1V MAX E1 AVDDGNDP11R1P9P8C13Ω10kµ0.10FCDBP7AEGND P10 µ0.1FR9ΩC1210k C9GNDGNDµ0.10FµC290.1Fµ10FC11 GND C7FOR SINGLE ENDED INPUTµ0.1FPLACE R18, R19, R42, C6, AND C18.REMOVE R3, R12, C15, C17, AND C27GND R42C6R12, R42, C17Ωµ00.1FONLY ONE SHOULD BEAVDDON BOARD AT A TIMER36Ω1kAMPIN R12Ω0 R4XOUTΩ33 T 1L1ADT1–1WTR10J110nHΩ3661XFRIN1C26E 452510pFCTC15GNDNCµ430.1FAMPGNDC16R2GND20µ0.1FC5DNPPRISECGNDµ0.1FR11ΩGND36OPTIONAL XFRT2XBOUTFT C1–1–1351R3XX FRINOUTΩ20CT34AMPINBR15GNDBXOUTΩ33PRISECC18µ0.10FR18ΩR SINGLE ENDED25R3, R16, C18ONLY ONE SHOULD BEON BOARD AT A TIMEGND03583-050 Figure 49. LFCSP Evaluation Board Schematic—Analog Inputs and DUT Rev. E | Page 23 of 32

AD9245 Data Sheet D N G 1 35 7 91 3 5 7 91 3 57 9 1 35 7 9 1 11 1 12 2 2 2 23 3 33 3 1 35 7 91 3 5 7 91 3 57 9 1 35 7 9 1 11 1 12 2 2 2 23 3 33 3 2 1 P 0 2 46 8 02 4 6 8 02 4 68 0 2 46 8 1 1 11 1 22 2 2 2 33 3 33 4 0 2 46 8 02 4 6 8 02 4 68 0 2 46 8 1 1 11 1 22 2 2 2 33 3 33 4 B N N PI PI M M A A D N F F ND R ND DRY G C27µ0.1 C17µ0.1 G D G B S M 16Ω 17Ω GND GND R0 R0 D GN C24µ10F C45µ0.1F 4Ω R39Ω1k VAMP R125 D N G R38Ω1k C44µ0.1F VOCM10 VPOS98OPHI 7OPLO COMM6 RY 1 D P 5 Ω VAM ND U3D83 R341.2k G A GND24 2322GND21 20 19DRVDD1817 16GND1514 13 12 11GND109 8DRVDD76 5GND4 3 2GND1 O USE AMPLIFIERLACE ALL COMPONENTSHOWN HERE (RIGHT)XCEPT R40 OR R41.EMOVE R12, R3, R18, R42,6, C15, AND C18. PWDN 1RGP1 2 INHI 3 INLO 4 RPG2 5R33Ω25 74LVTH162374 U1 2CLK2OE252DB2QB262D72Q727GNDGND282D62Q6292D52Q530VVCCCC312D42Q4322D32Q333GNDGND342D22Q2352D12Q1361Q81D8371D71Q738GGNDND391D61Q6401D51Q541VVCCCC421D41Q4431Q31D344GNDGND451D21Q2461D11Q1471OE1CLK148 INOUT POWER DOWNUSE R40 OR R41TPGNDVAMPSERR40R41CΩΩ10k10k C28MP INµ0.1FMP R19C35Ω50µ0.10F R35Ω25GND GNDGND DAC DAC A A CLKAT/ DRXD13X GNDD12X D11X RVDD D10XD9X GNDD8X D7XD6X D5X GND D4XD3X RVDDD2XD1X GNDD0X CLKLAT/ D D MSB LSB 03583-051 Figure 50. LFCSP Evaluation Board Schematic—Digital Path Rev. E | Page 24 of 32

Data Sheet AD9245 C40µ1F 0 0 0. C37µ1F C46µ10F 0. C20µ10F VAMP GND L D D N V C49µ0.001F G GG UP.D R R22Ω0 C48C38C1C47C39µ0.001Fµµµµ0.001F0.1F0.1F0.001F LATCH BYPASSINLATCH BYPASSIN SCHEMATIC SHOWS TWO GATE DELAY SETFOR ONE DELAY, REMOVE R22 AND R37 ANΩATTACH Rx (Rx = 0). R23ΩRx0R37CLKLAT/DACDNPΩ0D C36µ0.1F ENCX GND VDL C34µ0.1F 3 67 8D11 14R N W G P C31µ0.1F CX86 1Y 2Y 3Y 4Y U5 NG 74V SI C30µ0.001F L BYPAS 1A12B14A2B529A310B312A413B4 A C2µF GIT 10 DI DRVDD C41µ0.1F GND R32Ω1k ND 53 R20Ω1kGND R21Ω1k GND R24Ω1k GND G E 5 4 3 4 AVDD C32C33C14C25µµµµ0.001F0.1F0.001F10F GND ANALOG BYPASSING CLOCK TIMINGADJUSTMENTS FOR A BUFFERED ENCODE USE R28FOR A DIRECT ENCODE USE R27 CLKR28Ω0ENCX ENCENCE51E50R27Ω0 VDL VDLE52 VDLR31C43Ω1kµ0.1F R30R29E31EΩΩ1k50 GNDVDLGNDE43E VDL E DDAVDD C3µ10F GND SING ENCOD J2 GND V S DRVDL C4C10µ10Fµ10F DUT BYPA 03583-052 Figure 51. LFCSP Evaluation Board Schematic—Clock Input Rev. E | Page 25 of 32

AD9245 Data Sheet 03583-053 03583-055 Figure 52. LFCSP Evaluation Board Layout, Primary Side Figure 54. LFCSP Evaluation Board Layout, Ground Plane 03583-054 03583-056 Figure 53. LFCSP Evaluation Board Layout, Secondary Side Figure 55. LFCSP Evaluation Board Layout, Power Plane Rev. E | Page 26 of 32

Data Sheet AD9245 03583-057 03583-058 Figure 56. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 57. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev. E | Page 27 of 32

AD9245 Data Sheet Table 12. LFCSP Evaluation Board Bill of Materials Recommended Supplied Item Qty. Omit1 Reference Designator Device Package Value Vendor/Part No. by ADI 1 18 C1, C5, C7, C8, C9, C11, C12, Chip Capacitors 0603 0.1 µF C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 8 C6, C17, C18, C27, C28, C35, C45, C44 2 8 C2, C3, C4, C10, C20, Tantalum Capacitors TAJC 10 µF C22, C25, C29 2 C24, C46 3 8 C14, C30, C32, C38, Chip Capacitors 0603 0.001 µF C39, C40, C48, C49 4 1 C19 Chip Capacitors 0603 20 pF 5 1 C26 Chip Capacitors 0603 10 pF 2 C21, C23 6 9 E31, E35, E43, E44, Headers EHOLE Jumper Blocks E50, E51, E52, E53 2 E1, E45 7 2 J1, J2 SMA Connectors/50 Ω SMA 8 1 L1 Inductor 0603 10 nH Coilcraft/ 0603CS-10NXGBU 9 1 P2 Terminal Block TB6 Wieland/25.602.2653.0, z5-530-0625-0 10 1 P12 Header Dual 20-Pin RT Angle HEADER40 Digi-Key S2131-20-ND 11 5 R3, R12, R23, R28, Rx Chip Resistors 0603 0 Ω 6 R16, R17, R22, R27, R42, R37 12 2 R4, R15 Chip Resistors 0603 33 Ω 13 14 R5, R6, R7, R8, R13, R20, R21, Chip Resistors 0603 1 kΩ R24, R25, R26, R30, R31, R32, R36 14 2 R10, R11 Chip Resistors 0603 36 Ω 15 1 R29 Chip Resistors 0603 50 Ω 1 R19 16 2 RP1, RP2 Resistor Packs R_742 220 Ω Digi-Key CTS/742C163221JTR 17 1 T1 ADT1-1WT AWT1-1T Mini-Circuits 18 1 U1 74LVTH162374 CMOS Register TSSOP-48 19 1 U4 AD9245BCP ADC (DUT) LFCSP-32 Analog Devices, Inc. X 20 1 U5 74VCX86M SOIC-14 Fairchild 21 1 PCB AD92XXBCP/PCB PCB Analog Devices, Inc. X 22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. X 23 1 T2 M/A-COM Transformer ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13 24 5 R1, R2, R9, R38, R39 Chip Resistors 0603 SELECT 25 3 R14, R18, R35 Chip Resistors 0603 25 Ω 26 2 R40, R41 Chip Resistors 0603 10 kΩ 27 1 R34 Chip Resistor 1.2 kΩ 28 1 R33 Chip Resistor 25 Ω Total 81 35 1 These items are included in the PCB design, but are omitted at assembly. Rev. E | Page 28 of 32

Data Sheet AD9245 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN 1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.25 PAD 3.10 SQ 2.95 17 8 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A Figure 58. 32-Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9245BCPZ-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9245BCPZRL7-80 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9245BCPZ-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9245BCPZRL7-65 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9245BCPZ-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9245BCPZRL7-40 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9245BCPZ-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9245BCPZRL7-20 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 1 Z = RoHS-Compliant Part. Rev. E | Page 29 of 32

AD9245 Data Sheet NOTES Rev. E | Page 30 of 32

Data Sheet AD9245 NOTES Rev. E | Page 31 of 32

AD9245 Data Sheet NOTES © 2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03583-0-5/13(E) Rev. E | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9245BCPZRL7-20 AD9245BCPZRL7-80 AD9245BCPZ-65 AD9245BCPZ-20 AD9245BCPZ-40 AD9245BCPZRL7-65 AD9245BCPZ-80 AD9245BCPZRL7-40