12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9231 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD GND SDIOSCLK CSB 1.8 V to 3.3 V output supply SNR SPI 71.3 dBFS at 9.7 MHz input ER ORA F 69.0 dBFS at 200 MHz input VIN+A PROGRAMMING DATA SUF D11A OB SFDR VIN–A ADC CMPUT D0A 93 dBc at 9.7 MHz input UT O 83 dBc at 200 MHz input VREF ON DCOA Low power TI SENSE OP DRVDD 32 mW per channel at 20 MSPS AD9231 X 71 mW per channel at 80 MSPS VCM SERLEEFCT MU Differential input with 700 MHz bandwidth RBIAS FER ORB On-chip voltage reference and sample-and-hold circuit VIN–B OSBUF D11B ADC MT 2 V p-p differential analog input VIN+B CPU D0B T DNL = ±0.40 LSB OU DCOB Serial port control options Offset binary, gray code, or twos complement data format DIVIDE DUTY CYCLE MODE 1TO 8 STABILIZER CONTROLS OInptetigoenra 1l -ctloo-c8k i dnputuyt ccylocclek sdtiavbidileizre r CLK+CLK– SYNC DCS PDWNDFS OEB 08121-001 Data output multiplex option Figure 1. Built-in selectable digital test pattern generation Energy-saving power-down modes PRODUCT HIGHLIGHTS Data clock out with programmable clock and data alignment 1. The AD9231 operates from a single 1.8 V analog power supply and features a separate digital output driver supply APPLICATIONS to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent Communications performance for input frequencies up to 200 MHz and is Diversity radio systems designed for low cost, low power, and ease of use. Multimode digital receivers 3. A standard serial port interface supports various product GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA features and functions, such as data output formatting, I/Q demodulation systems internal clock divider, power-down, DCO/DATA timing Smart antenna systems Battery-powered instruments and offset adjustments, and voltage reference modes. Hand held scope meters 4. The AD9231 is packaged in a 64-lead RoHS compliant Portable medical imaging LFCSP that is pin compatible with the AD9268 16-bit Ultrasound ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC, Radar/LIDAR and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD9231 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 22 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 23 Functional Block Diagram .............................................................. 1 Channel/Chip Synchronization ................................................ 25 Product Highlights ........................................................................... 1 Power Dissipation and Standby Mode .................................... 25 Revision History ............................................................................... 2 Digital Outputs ........................................................................... 26 General Description ......................................................................... 3 Timing ......................................................................................... 26 Specifications ..................................................................................... 4 Built-In Self-Test (BIST) and Output Test .................................. 27 DC Specifications ......................................................................... 4 Built-In Self-Test (BIST) ............................................................ 27 AC Specifications .......................................................................... 5 Output Test Modes ..................................................................... 27 Digital Specifications ................................................................... 6 Serial Port Interface (SPI) .............................................................. 28 Switching Specifications .............................................................. 7 Configuration Using the SPI ..................................................... 28 Timing Specifications .................................................................. 8 Hardware Interface ..................................................................... 29 Absolute Maximum Ratings ............................................................ 9 Configuration Without the SPI ................................................ 29 Thermal Characteristics .............................................................. 9 SPI Accessible Features .............................................................. 29 ESD Caution .................................................................................. 9 Memory Map .................................................................................. 30 Pin Configuration and Function Descriptions ........................... 10 Reading the Memory Map Register Table ............................... 30 Typical Performance Characteristics ........................................... 12 Open Locations .......................................................................... 30 AD9231-80 .................................................................................. 12 Default Values ............................................................................. 30 AD9231-65 .................................................................................. 14 Memory Map Register Table ..................................................... 31 AD9231-40 .................................................................................. 15 Memory Map Register Descriptions ........................................ 33 AD9231-20 .................................................................................. 16 Applications Information .............................................................. 34 Equivalent Circuits ......................................................................... 17 Design Guidelines ...................................................................... 34 Theory of Operation ...................................................................... 19 Outline Dimensions ....................................................................... 35 ADC Architecture ...................................................................... 19 Ordering Guide .......................................................................... 35 Analog Input Considerations .................................................... 19 REVISION HISTORY 9/2016—Rev. A to Rev. B Changes to Figure 3 .......................................................................... 7 6/2010—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 10/2009—Revision 0: Initial Version Rev. B | Page 2 of 36

Data Sheet AD9231 GENERAL DESCRIPTION The AD9231 is a monolithic, dual-channel, 1.8 V supply, 12-bit, A differential clock input controls all internal conversion cycles. 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital conver- An optional duty cycle stabilizer (DCS) compensates for wide ter (ADC). It features a high performance sample-and-hold variations in the clock duty cycle while maintaining excellent circuit and on-chip voltage reference. overall ADC performance. The product uses multistage differential pipeline architecture The digital output data is presented in offset binary, gray code, with output error correction logic to provide 12-bit accuracy at or twos complement format. A data output clock (DCO) is 80 MSPS data rates and to guarantee no missing codes over the provided for each ADC channel to ensure proper latch timing full operating temperature range. with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single The ADC contains several features designed to maximize output bus. flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern The AD9231 is available in a 64-lead RoHS compliant LFCSP generation. The available digital test patterns include built-in and is specified over the industrial temperature range (−40°C deterministic and pseudorandom patterns, along with custom to +85°C). user-defined test patterns entered via the serial port interface (SPI). Rev. B | Page 3 of 36

AD9231 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. AD9231-20/AD9231-40 AD9231-65 AD9231-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full 12 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full 0.05 ±0.5 0.05 ±0.5 0.05 ±0.5 % FSR Gain Error1 Full −1.5 −1.5 −1.5 % FSR Differential Nonlinearity (DNL)2 Full ±0.30 ±0.40 ±0.40 LSB 25°C ±0.12 ±0.17 ±0.2 LSB Integral Nonlinearity (INL)2 Full ±0.45 ±0.50 ±0.65 LSB 25°C ±0.15 ±0.17 ±0.2 LSB MATCHING CHARACTERISTICS Offset Error 25°C ±0.0 ±0.70 ±0.0 ±0.60 ±0.0 ±0.60 % FSR Gain Error1 25°C 0.3 0.3 0.4 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.981 0.993 1.005 0.981 0.993 1.005 0.981 0.993 1.005 V Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT-REFERRED NOISE VREF = 1.0 V 25°C 0.25 0.25 0.25 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V Input Common-Mode Range Full 0.5 1.3 0.5 1.3 0.5 1.3 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 3.6 1.7 3.6 1.7 3.6 V Supply Current IAVDD2 Full 35.7/49.0 37.7/52.2 69 72.4 80.0 83.4 mA IDRVDD2 (1.8 V) Full 3.0/5.1 7.4 9.1 mA IDRVDD2 (3.3 V) Full 5.9/10.1 14.9 18.3 mA POWER CONSUMPTION DC Input Full 63.5/87.1 122.9 141.8 mW Sine Wave Input2 (DRVDD = 1.8 V) Full 69.7/97.3 73.3/103.0 138.0 143.8 160.4 166.5 mW Sine Wave Input2 (DRVDD = 3.3 V) Full 83.7/121.5 173.4 204 mW Standby Power4 Full 37/37 37 37 mW Power-Down Power Full 2.2 2.2 2.2 mW 1 Measured with 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK active. Rev. B | Page 4 of 36

Data Sheet AD9231 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. AD9231-20/AD9231-40 AD9231-65 AD9231-80 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 9.7 MHz 25°C 70.7/71.5 71.4 71.3 dBFS IN f = 30.5 MHz 25°C 70.6/71.3 71.3 71.2 dBFS IN Full 70.1/70.7 70.5 dBFS f = 70 MHz 25°C 70.5/71.0 71.0 70.9 dBFS IN Full 70.1 dBFS f = 200 MHz 25°C 69.0 69.0 69.0 dBFS IN SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) f = 9.7 MHz 25°C 70.6/71.4 71.3 71.2 dBFS IN f = 30.5 MHz 25°C 70.6/71.2 71.2 71.1 dBFS IN Full 70.1/70.6 70.0 dBFS f = 70 MHz 25°C 70.4/70.9 70.9 70.8 dBFS IN Full 70.0 dBFS f = 200 MHz 25°C 68 68 68 dBFS IN EFFECTIVE NUMBER OF BITS (ENOB) f = 9.7 MHz 25°C 11.4/11.6 11.6 11.5 Bits IN f = 30.5 MHz 25°C 11.4/11.5 11.5 11.5 Bits IN f = 70 MHz 25°C 11.4/11.5 11.5 11.5 Bits IN f = 200 MHz 25°C 11.0 11.0 11.0 Bits IN WORST SECOND OR THIRD HARMONIC f = 9.7 MHz 25°C −95 −95 −93 dBc IN f = 30.5 MHz 25°C −95 −95 −93 dBc IN Full −81 −81 dBc f = 70 MHz 25°C −92/−94 −94 −92 dBc IN Full −81 dBc f = 200 MHz 25°C −83 −83 −83 dBc IN SPURIOUS-FREE DYNAMIC RANGE (SFDR) f = 9.7 MHz 25°C 95 95 93 dBc IN f = 30.5 MHz 25°C 95 95 93 dBc IN Full 81 81 dBc f = 70 MHz 25°C 92/94 94 92 dBc IN Full 81 dBc f = 200 MHz 25°C 83 83 83 dBc IN WORST OTHER (HARMONIC OR SPUR) f = 9.7 MHz 25°C −98 −98 −97 dBc IN f = 30.5 MHz 25°C −97/−98 −98 −97 dBc IN Full −90 −90 dBc f = 70 MHz 25°C −97/−98 −98 −95 dBc IN Full −89 dBc f = 200 MHz 25°C −92 −92 −92 dBc IN TWO-TONE SFDR f = 28.3 MHz (−7 dBFS), 30.6 MHz (−7 dBFS) 25°C 90 90 90 dBc IN CROSSTALK2 Full −110 −110 −110 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. B | Page 5 of 36

AD9231 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. AD9231-20/AD9231-40/AD9231-65/AD9231-80 Parameter Temp Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 µA Low Level Input Current Full −10 +10 µA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (CSB)2 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 135 µA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO1/DCS2) High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 µA Low Level Input Current Full 40 130 µA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, I = 50 µA Full 3.29 V OH High Level Output Voltage, I = 0.5 mA Full 3.25 V OH Low Level Output Voltage, I = 1.6 mA Full 0.2 V OL Low Level Output Voltage, I = 50 µA Full 0.05 V OL DRVDD = 1.8 V High Level Output Voltage, I = 50 µA Full 1.79 V OH High Level Output Voltage, I = 0.5 mA Full 1.75 V OH Low Level Output Voltage, I = 1.6 mA Full 0.2 V OL Low Level Output Voltage, I = 50 µA Full 0.05 V OL 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. Rev. B | Page 6 of 36

Data Sheet AD9231 SWITCHING SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. AD9231-20/AD9231-40 AD9231-65 AD9231-80 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate1 Full 3 20/40 3 65 3 80 MSPS CLK Period—Divide-by-1 Mode (t ) Full 50/25 15.38 12.5 ns CLK CLK Pulse Width High (t ) 25.0/12.5 7.69 6.25 ns CH Aperture Delay (t ) Full 1.0 1.0 1.0 ns A Aperture Uncertainty (Jitter, t) Full 0.1 0.1 0.1 ps rms J DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 3 3 ns DCO Propagation Delay (tDCO) Full 3 3 3 ns DCO to Data Skew (tSKEW) Full 0.1 0.1 0.1 ns Pipeline Delay (Latency) Full 9 9 9 Cycles Wake-Up Time2 Full 350 350 350 µs Standby Full 600/400 300 260 ns OUT-OF-RANGE RECOVERY TIME Full 2 2 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors. N – 1 tA N + 4 N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CHA/CH B DATA N – 9 N – 8 N – 7 N – 6 N – 5 tPD 08121-002 Figure 2. CMOS Output Data Timing N – 1 tA N + 4 N + 5 N N + 3 VIN N + 1 N + 2 tCH tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CH A/CH B DATA CHA AS OAUPTPPEUATR SP IONNS tPD CNH – A9 CNH – B9 NC H– A8 CNH – B8 CNH – A7 CNH – B7 NC H– A6 CNH – B6 CNH – A5 08121-003 Figure 3. CMOS Interleaved Output Timing, Output as Appears on Channel A Output Pins Rev. B | Page 7 of 36

AD9231 Data Sheet TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK setup time 0.24 ns SSYNC t SYNC to rising edge of CLK hold time 0.40 ns HSYNC SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK 2 ns DS t Hold time between the data and the rising edge of SCLK 2 ns DH t Period of the SCLK 40 ns CLK t Setup time between CSB and SCLK 2 ns S t Hold time between CSB and SCLK 2 ns H t SCLK pulse width high 10 ns HIGH t SCLK pulse width low 10 ns LOW t Time required for the SDIO pin to switch from an input to an 10 ns EN_SDIO output relative to the SCLK falling edge t Time required for the SDIO pin to switch from an output to an 10 ns DIS_SDIO input relative to the SCLK rising edge CLK+ tSSYNC tHSYNC SYNC 08121-004 Figure 4. SYNC Input Timing Requirements Rev. B | Page 8 of 36

Data Sheet AD9231 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Rating The exposed paddle is the only ground connection for the chip. AVDD to AGND −0.3 V to +2.0 V The exposed paddle must be soldered to the AGND plane of the DRVDD to AGND −0.3 V to +3.9 V user’s circuit board. Soldering the exposed paddle to the user’s VIN+A, VIN+B, VIN−A, VIN−B to AGND −0.3 V to AVDD + 0.2 V board also increases the reliability of the solder joints and CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V maximizes the thermal capability of the package. SYNC to AGND −0.3 V to DRVDD + 0.3 V Table 7. Thermal Resistance VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V Airflow Velocity VCM to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V Package Type (m/sec) θJA1, 2 θJC1, 3 θJB1, 4 Unit 64-Lead LFCSP 0 23 2.0 °C/W CSB to AGND −0.3 V to DRVDD + 0.3 V SCLK/DFS to AGND −0.3 V to DRVDD + 0.3 V 9 mm × 9 mm 1.0 20 12 °C/W (CP-64-4) SDIO/DCS to AGND −0.3 V to DRVDD + 0.3 V 2.5 18 °C/W OEB to AGND −0.3 V to DRVDD + 0.3 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. PDWN to AGND −0.3 V to DRVDD + 0.3 V 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. D0A/D0B through D11A/D11B to AGND −0.3 V to DRVDD + 0.3 V 4 Per JEDEC JESD51-8 (still air). DCOA/DCOB to AGND −0.3 V to DRVDD + 0.3 V Operating Temperature Range (Ambient) −40°C to +85°C Typical θJA is specified for a 4-layer PCB with a solid ground Maximum Junction Temperature Under Bias 150°C plane. As shown in Table 7, airflow improves heat dissipation, Storage Temperature Range (Ambient) −65°C to +150°C which reduces θ . In addition, metal in direct contact with the JA package leads from metal traces, through holes, ground, and power planes, reduces the θ . Stresses at or above those listed under Absolute Maximum JA Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these ESD CAUTION or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 9 of 36

AD9231 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDDAVDDVIN+BVIN–BAVDDAVDDRBIASVCMSENSEVREFAVDDAVDDVIN–AVIN+AAVDDAVDD 4321098765432109 6666655555555554 CLK+ 1 PIN 1 48PDWN CLK– 2 INDICATOR 47OEB SYNC 3 46CSB NC 4 45SCLK/DFS NC 5 44SDIO/DCS NC 6 43ORA NC 7 AD9231 42D11A (MSB) (LSB) D0B 8 41D10A TOP VIEW D1B 9 40D9A (Not to Scale) DRVDD10 39D8A D2B 11 38D7A D3B12 37DRVDD D4B13 36D6A D5B14 35D5A D6B15 34D4A D7B16 33D3A 7890123456789012 1112222222222333 BBDBBBBACCCDCAAA D8D9DRVDD10(MSB) D11ORDCODCONNNDRVDN(LSB) D0D1D2 08121-005 NOTES 1. NC = NO CONNECT. 2. THE EXPOSEDPADDLE MUST BE SOLDEREDTO THE PCB GROUNDTO ENSURE PROPER HEAT DISSIPATION, NOISE,AND MECHANICAL STRENGTH BENEFITS. Figure 5. Pin Configuration Table 8. Pin Function Description Pin No. Mnemonic Description 0 GND Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 4, 5, 6, 7, 25, 26, 27, 29 NC Do Not Connect. 8 to 9, 11 to 18, 20, 21 D0B to D11B Channel B Digital Outputs. D11B = MSB. 10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. 30 to 36, 38 to 42 D0A to D11A Channel A Digital Outputs. D11A = MSB. 43 ORA Channel A Out-of-Range Digital Output. 44 SDIO/DCS SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull- down in SPI mode. Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal pull-up in non-SPI (DCS) mode. 45 SCLK/DFS SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down. Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down. DFS high = twos complement output. DFS low = offset binary output. 46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up. 47 OEB Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high. 30 kΩ internal pull-down. 48 PDWN Digital Input. 30 kΩ internal pull-down. PDWN high = power-down device. PDWN low = run device, normal operation. Rev. B | Page 10 of 36

Data Sheet AD9231 Pin No. Mnemonic Description 49, 50, 53, 54, 59, 60, 63, 64 AVDD 1.8 V Analog Supply Pins. 51, 52 VIN+A, VIN−A Channel A Analog Inputs. 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog output voltage at midsupply to set common mode of the analog inputs. 58 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 61, 62 VIN−B, VIN+B Channel B Analog Inputs. Rev. B | Page 11 of 36

AD9231 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9231-80 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 0 –15 80MSPS –15 80MSPS 9.7MHz @ –1dBFS 100.3MHz @ –1dBFS –30 SSNFDRR = =7 09.32.d6BdB (c71.2dBFS) –30 SSNFDRR = =6 98.75.d7BdB (c70.5dBFS) S) –45 S) –45 F F B B d d E ( –60 E ( –60 D D U U T –75 T –75 LI LI AMP –90 2 + AMP –90 3 + 2 6 3 5 4 4 5 6 –105 –105 –120 –120 –1350 4 8 12 FR1E6QUE2N0CY (M24Hz) 28 32 36 4008121-054 –1350 4 8 12 FR1E6QUE2N0CY (M24Hz) 28 32 36 4008121-057 Figure 6. AD9231-80 Single-Tone FFT with fIN = 9.7 MHz Figure 9. AD9231-80 Single-Tone FFT with fIN = 100.3 MHz 0 0 –15 80MSPS –15 80MSPS 30.6MHz @ –1dBFS 210.3MHz @ –1dBFS –30 SSNFDRR = =7 09.41.d4BdB (c71.1dBFS) –30 SSNFDRR = =6 78.39.d2BdB (c68.9dBFS) S) –45 S) –45 F F B B d d E ( –60 E ( –60 D D U U T –75 T –75 LI LI AMP –90 + AMP –90 3 2 + 5 3 2 6 4 5 6 4 –105 –105 –120 –120 –1350 4 8 12 FR1E6QUE2N0CY (M24Hz) 28 32 36 4008121-055 –1350 4 8 12 FR1E6QUE2N0CY (M24Hz) 28 32 36 4008121-058 Figure 7. AD9231-80 Single-Tone FFT with fIN = 30.6 MHz Figure 10. AD9231-80 Single-Tone FFT with fIN = 210.3 MHz 0 0 80MSPS 80MSPS –15 –15 69MHz @ –1dBFS 28.3 @ –7dBFS SNR = 69.9dB (70.9dBFS) 30.6 @ –7dBFS –30 SFDR = 94.3dBc –30 SFDR = 90dBc S) –45 S) –45 F F B B d d E ( –60 E ( –60 D D U U T –75 T –75 LI LI P P AM –90 + AM –90 F2 – F1 2F2 – F1 F1 + F22F2 – F1 2F1 – F2 6 2 5 3 4 2F1 + F2 –105 –105 –120 –120 –1350 4 8 12 FR1E6QUE2N0CY (M24Hz) 28 32 36 4008121-056 –1350 4 8 12 FR1E6QUE2N0CY (M24Hz) 28 32 36 4008121-059 Figure 8. AD9231-80 Single-Tone FFT with fIN = 69 MHz Figure 11. AD9231-80 Two-Tone FFT with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Rev. B | Page 12 of 36

Data Sheet AD9231 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 100 90 SFDR –20 80 D3 (dBc/dBFS) ––6400 SIMFDD3R ( (ddBBcc)) R (dBFS/dBc) 567000 SNRFS M D DR/I S/SF 40 SF –80 RF N 30 S SFDR (dBFS) 20 –100 10 IMD3 (dBFS) –120–70 –60 –I5N0PUT AM–4P0LITUDE– (3d0BFS) –20 –10 08121-060 010 20 30 SAM40PLE RA5T0E (MHz)60 70 80 08121-062 Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with Figure 15. AD9231-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz fIN1 = 28.3 MHz and fIN2 = 30.6 MHz 100 100 SFDR 90 90 SFDRFS 80 80 SNR S) SNRFS BFS/dBc) 6700 AND dBF 6700 SFDR d c R ( 50 dB 50 SFD 40 DR ( 40 SNR SNR/ 30 R/SF 30 N S 20 20 10 10 00 50 INPUT FREQ10U0ENCY (MHz)150 200 08121-061 0–70 –60 –50INPUT– 4A0MPLIT–U3D0E (dBc–)20 –10 0 08121-064 Figure 13. AD9231-80 SNR/SFDR vs. Input Frequency (AIN) with Figure 16. AD9231-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 2 V p-p Full Scale 0.3 0.4 0.2 0.2 B) 0.1 B) S S R (L R (L RO 0 RO 0 R R E E DNL –0.1 INL –0.2 –0.2 –0.30 500 1000 150O0UTP20U0T0 CO2D5E00 3000 3500 4000 08121-063 0.40 500 1000 150O0UTP20U0T0 CO2D5E00 3000 3500 4000 08121-066 Figure 14. AD9231-80 DNL Error with fIN = 9.7 MHz Figure 17. AD9231-80 INL with fIN = 9.7 MHz Rev. B | Page 13 of 36

AD9231 Data Sheet AD9231-65 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 120 65MSPS –15 9.7MHz @ –1dBFS SFDRFS SNR =70.3 (71.3dBFS) 100 –30 SFDR = 94.2dBc S) F S) –45 dB 80 DE (dBF –60 Bc AND 60 SNRFS PLITU –75 DR (d SFDR AM –90 6 + 5 2 4 3 NR/SF 40 –105 S SNR 20 –120 –1350 3 6 9 F12REQ1U5ENC1Y8 (MH2z1) 24 27 30 3308121-067 0–70 –60 –50INPUT– 4A0MPLIT–U3D0E (dBc–)20 –10 0 08121-070 Figure 18. AD9231-65 Single-Tone FFT with fIN = 9.7 MHz Figure 21. AD9231-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 100 –15 65MSPS 90 SFDR 30.6MHz @ –1dBFS 80 –30 SSNFDRR = =7 09.42.d1BdB (7c1.2dBFS) c) 70 SNR S) –45 dB LITUDE (dBF ––6705 SFDR (dBFS/ 456000 AMP –90 2 + 5 3 SNR/ 30 4 6 –105 20 –120 10 –1350 3 6 9 F12REQ1U5ENC1Y8 (MH2z1) 24 27 30 3308121-069 00 50 INPUT F1R00EQUENCY (M1H50z) 200 08121-071 Figure 19. AD9231-65 Single-Tone FFT with fIN = 30.6 MHz Figure 22. AD9231-65 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 0 65MSPS –15 69MHz @ –1dBFS SNR = 69.9dB (70.9dBFS) –30 SFDR = 92.0dBc S) –45 F B E (d –60 D U T –75 LI P AM –90 2 + 3 4 5 6 –105 –120 –1350 3 6 9 F12REQ1U5ENC1Y8 (MH2z1) 24 27 30 3308121-068 Figure 20. AD9231-65 Single-Tone FFT with fIN = 69 MHz Rev. B | Page 14 of 36

Data Sheet AD9231 AD9231-40 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 120 40MSPS –15 9.7MHz @ –1dBFS SFDRFS SNR = 70.3dB (71.3dBFS) 100 –30 SFDR = 93.8dBc S) F S) –45 dB 80 E (dBF –60 c AND SNRFS D B 60 U d AMPLIT–1––079550 4 5 3 + 6 2 SNR/SFDR ( 40 SSFNDRR 20 –120 –1350 2 4 6 FRE8QUE1N0CY (M12Hz) 14 16 18 2008121-072 0–70 –60 –50INPUT– A40MPLIT–U3D0E (dBc–)20 –10 0 08121-074 Figure 23. AD9231-40 Single-Tone FFT with fIN = 9.7 MHz Figure 25. AD9231-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 –15 40MSPS 30.6MHz @ –1dBFS –30 SNR = 70.2dB (71.2dBFS) SFDR = 95.4dBc S) –45 F B d E ( –60 D U T –75 LI P AM –90 + –105 4 5 3 6 2 –120 –1350 2 4 6 FRE8QUE1N0CY (M12Hz) 14 16 18 2008121-073 Figure 24. AD9231-40 Single-Tone FFT with fIN = 30.6 MHz Rev. B | Page 15 of 36

AD9231 Data Sheet AD9231-20 AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 120 –15 20MSPS 9.7MHz @ –1dBFS 100 SFDRFS –30 SNR = 70.3dB (71.3dBFS) SFDR = 94.1dBc S) F S) –45 dB 80 DE (dBF –60 Bc AND 60 SNRFS AMPLITU ––7950 2 4 + 5 3 NR/SFDR (d 40 SSFNDRR –105 6 S 20 –120 –1350 0.95 1.90 2.85 3F.R8E0QU4.E7N5CY5. 7(M0Hz6).65 7.60 8.55 9.50 08121-075 0–70 –60 –50INPUT– 4A0MPLITU–3D0E (dBc–)20 –10 0 08121-077 Figure 26. AD9231-20 Single-Tone FFT with fIN = 9.7 MHz Figure 28. AD9231-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 0 –15 20MSPS 30.6MHz @ –1dBFS SNR = 70.2dB (71.2dBFS) –30 SFDR = 94.6dBc S) –45 F B d E ( –60 D U T –75 LI P AM –90 + 2 4 6 5 3 –105 –120 –1350 0.95 1.90 2.85 3F.R8E0QU4.E7N5CY5. 7(M0Hz6).65 7.60 8.55 9.50 08121-076 Figure 27. AD9231-20 Single-Tone FFT with fIN = 30.6 MHz Rev. B | Page 16 of 36

Data Sheet AD9231 EQUIVALENT CIRCUITS AVDD DRVDD VIN±x 08121-039 08121-042 Figure 29. Equivalent Analog Input Circuit Figure 32. Equivalent Digital Output Circuit 5Ω CLK+ 15kΩ 0.9V 15kΩ DRVDD 5Ω CLK– SCLK/DFS, SYNC, 350Ω OEB,AND PDWN 30kΩ 08121-040 08121-043 Figure 33. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Figure 30. Equivalent Clock Input Circuit AVDD AVDD DRVDD 30kΩ 350Ω SDIO/DCS RBIAS 375Ω AND VCM 30kΩ 08121-041 08121-044 Figure 34. Equivalent RBIAS and VCM Circuit Figure 31. Equivalent SDIO/DCS Input Circuit Rev. B | Page 17 of 36

AD9231 Data Sheet DRVDD AVDD AVDD 30kΩ 350Ω CSB 375Ω VREF 7.5kΩ 08121-045 08121-047 Figure 35. Equivalent CSB Input Circuit Figure 37. Equivalent VREF Circuit AVDD 375Ω SENSE 08121-046 Figure 36. Equivalent SENSE Circuit Rev. B | Page 18 of 36

Data Sheet AD9231 THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS The AD9231 dual ADC design can be used for diversity recep- tion of signals, where the ADCs are operating identically on the The analog input to the AD9231 is a differential switched- same carrier but from two separate antennae. The ADCs can capacitor circuit designed for processing differential input also be operated with independent analog inputs. The user can signals. This circuit can support a wide common-mode range sample any fS/2 frequency segment from dc to 200 MHz, using while maintaining excellent performance. By using an input appropriate low-pass or band-pass filtering at the ADC inputs common-mode voltage of midsupply, users can minimize with little loss in ADC performance. Operation to 300 MHz signal-dependent errors and achieve optimum performance. analog input is permitted but occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9231 can be used as a base- H band or direct downconversion receiver, where one ADC is C PAR H used for I input data and the other is used for Q input data. VIN+x C SAMPLE Synchronization capability is provided to allow synchronized S S timing between multiple channels or multiple devices. S S C SAMPLE Programming and control of the AD9231 is accomplished using VIN–x C H a 3-bit SPI-compatible serial interface. PAR ADC ARCHITECTURE H 08121-006 The AD9231 architecture consists of a multistage, pipelined ADC. Figure 38. Switched-Capacitor Input Circuit Each stage provides sufficient overlap to correct for flash errors The clock signal alternately switches the input circuit between in the preceding stage. The quantized outputs from each stage are sample-and-hold mode (see Figure 38). When the input circuit combined into a final 12-bit result in the digital correction logic. is switched to sample mode, the signal source must be capable The pipelined architecture permits the first stage to operate with of charging the sample capacitors and settling within one-half a new input sample while the remaining stages operate with of a clock cycle. A small resistor in series with each input can preceding samples. Sampling occurs on the rising edge of help reduce the peak transient current injected from the output the clock. stage of the driving source. In addition, low Q inductors or ferrite Each stage of the pipeline, excluding the last, consists of a low beads can be placed on each leg of the input to reduce high resolution flash ADC connected to a switched-capacitor DAC differential capacitance at the analog inputs and, therefore, and an interstage residue amplifier (for example, a multiplying achieve the maximum bandwidth of the ADC. Such use of low digital-to-analog converter (MDAC)). The residue amplifier Q inductors or ferrite beads is required when driving the converter magnifies the difference between the reconstructed DAC output front end at high IF frequencies. Either a shunt capacitor or two and the flash input for the next stage in the pipeline. One bit of single-ended capacitors can be placed on the inputs to provide a redundancy is used in each stage to facilitate digital correction matching passive network. This ultimately creates a low-pass of flash errors. The last stage simply consists of a flash ADC. filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the The output staging block aligns the data, corrects errors, and Analog Dialogue article “Transformer-Coupled Front-End for passes the data to the CMOS output buffers. The output buffers Wideband A/D Converters” (Volume 39, April 2005) for more are powered from a separate (DRVDD) supply, allowing adjust- information. In general, the precise values depend on the ment of the output voltage swing. During power-down, the application. output buffers go into a high impedance state. Rev. B | Page 19 of 36

AD9231 Data Sheet Input Common Mode The output common-mode voltage of the ADA4938-2 is easily The analog inputs of the AD9231 are not internally dc-biased. set with the VCM pin of the AD9231 (see Figure 41), and the Therefore, in ac-coupled applications, the user must provide a driver can be configured in a Sallen-Key filter topology to dc bias externally. Setting the device so that VCM = AVDD/2 is provide band limiting of the input signal. recommended for optimum performance, but the device can 200Ω 33Ω function over a wider range with reasonable performance, as VIN 76.8Ω VIN–x AVDD 90Ω shown in Figure 39 and Figure 40. ADA4938 10pF ADC An on-board, common-mode voltage reference is included in 0.1µF 120Ω 33Ω tmhue sdt ebseig dne acnoudp ilse adv taoil agbroleu fnrdo mby t ha e0 .V1C μMF c paipna.c Tithoer, VasC dMes pcirnib ed 200Ω VIN+x VCM 08121-007 Figure 41. Differential Input Configuration Using the ADA4938-2 in the Applications Information section. For baseband applications below ~10 MHz where SNR is a key 100 parameter, differential transformer-coupling is the recommended SFDR (dBc) input configuration. An example is shown in Figure 42. To bias 90 the analog input, the VCM voltage can be connected to the c) center tap of the secondary winding of the transformer. B d FS/ 80 VIN+x dB R DR ( SNR (dBFS) 2V p-p 49.9Ω C ADC SF 70 NR/ R VIN–x VCM S 60 0.1µF 08121-008 Figure 42. Differential Transformer-Coupled Configuration 500.5 0.6 IN0P.U7T CO0M.8MON-M0.O9DE V1O.0LTAGE1. 1(V) 1.2 1.3 08121-149 Ta htrea nsisgfnoarml cehra. rMacotsetr iRstFi ctsr amnusfsotr bmee crosn ssaitduerraetde awt hfreenq sueelnecctiiensg Figure 39. SNR/SFDR vs. Input Common-Mode Voltage, below a few megahertz (MHz). Excessive signal power can also fIN = 32.1 MHz, fS = 80 MSPS cause core saturation, which leads to distortion. 100 At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve SFDR (dBc) 90 the true SNR performance of the AD9231. For applications above c) ~10 MHz where SNR is a key parameter, differential double balun B S/d 80 coupling is the recommended input configuration (see Figure 44). F B d R ( SNR (dBFS) An alternative to using a transformer-coupled input at frequencies D SF 70 in the second Nyquist zone is to use the AD8352 differential driver. NR/ An example is shown in Figure 45. See the AD8352 data sheet S for more information. 60 In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to 500.5 0.6 IN0P.U7T CO0M.8MON-M0.O9DE V1O.0LTAGE1. 1(V) 1.2 1.3 08121-150 bthee r eRdCu cneedt woro rrekm. Hovoewde. vTearb, lteh 9es dei svpallauyess t ahree s duegpgeesntedde nvta olune st htoe set Figure 40. SNR/SFDR vs. Input Common-Mode Voltage, input signal and should be used only as a starting guide. fIN = 10.3 MHz, fS = 20 MSPS Differential Input Configurations Table 9. Example RC Network Optimum performance is achieved while driving the AD9231 in a R Series Frequency Range (MHz) (Ω Each) C Differential (pF) differential input configuration. For baseband applications, the 0 to 70 33 22 AD8138, ADA4937-2, and ADA4938-2 differential drivers provide 70 to 200 125 Open excellent performance and a flexible interface to the ADC. Rev. B | Page 20 of 36

Data Sheet AD9231 Single-Ended Input Configuration 10µF AVDD 1kΩ A single-ended input can provide adequate performance in R VIN+x cost-sensitive applications. In this configuration, SFDR and 1Vp-p 49.9Ω 0.1µF 1kΩ distortion performance degrade due to the large input common- AVDD C ADC mode swing. If the source impedances on each input are matched, 1kΩ R VIN–x tshheorwe ss hao tuylpdi cbael lsiitntlgel eef-feencdt eodn iSnNpuRt pcoernffoirgmuraanticoen. .F igure 43 10µF 0.1µF 1kΩ 08121-009 Figure 43. Single-Ended Input Configuration 0.1µF 0.1µF R 2V p-p VIN+x 25Ω PA S S P C ADC 25Ω 0.1µF 0.1µF R VIN–x VCM 08121-010 Figure 44. Differential Double Balun Input Configuration VCC 0.1µF ANALOG INPUT 0Ω 161 8, 1311 0.1µF 0.1µF R VIN+x 2 200Ω CD RD RG34 AD835210 0.1µF 200Ω R C VIN–xADCVCM ANALOG INPUT 0.1µF 0Ω 5 104.1µF 0.1µF 08121-011 Figure 45. Differential Input Configuration Using the AD8352 Rev. B | Page 21 of 36

AD9231 Data Sheet VOLTAGE REFERENCE If the internal reference of the AD9231 is used to drive multiple converters to improve gain matching, the loading of the reference A stable and accurate 1.0 V voltage reference is built into the by the other converters must be considered. Figure 47 shows AD9231. The VREF can be configured using either the internal how the internal reference voltage is affected by loading. 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections 0 that follow. The Reference Decoupling section describes the best practices PCB layout of the reference. %)–0.5 Internal Reference Connection OR ( R R–1.0 A comparator within the AD9231 detects the potential at the GE E INTERNAL VREF = 0.993V SENSE pin and configures the reference into two possible modes, A T–1.5 L which are summarized in Table 10. If SENSE is grounded, the O V reference amplifier switch is connected to the internal resistor CE N–2.0 divider (see Figure 46), setting VREF to 1.0 V. E R E F RE–2.5 VIN+A/VIN+B –3.0 VIN–A/VIN–B 0 0.2 0.4 0.6LOA0.D8 CUR1.R0ENT1 .(2mA)1.4 1.6 1.8 2.0 08121-014 Figure 47. VREF Accuracy vs. Load Current ADC CORE VREF 1.0µF 0.1µF SELECT LOGIC SENSE 0.5V ADC 08121-012 Figure 46. Internal Reference Configuration Table 10. Reference Configuration Summary Selected Mode SENSE Voltage (V) Resulting VREF (V) Resulting Differential Span (V p-p) Fixed Internal Reference AGND to 0.2 1.0 internal 2.0 Fixed External Reference AVDD 1.0 applied to external VREF pin 2.0 Rev. B | Page 22 of 36

Data Sheet AD9231 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance The AD9231 has a very flexible clock input structure. The clock the gain accuracy of the ADC or improve thermal drift charac- input can be a CMOS, LVDS, LVPECL, or sine wave signal. teristics. Figure 48 shows the typical drift characteristics of the Regardless of the type of signal being used, clock source jitter internal reference in 1.0 V mode. is of the most concern, as described in the Jitter Considerations section. 4 3 Figure 50 and Figure 51 show two preferred methods for clock- ing the AD9231 (at clock rates up to 625 MHz). A low jitter clock 2 VREF ERROR (mV) source is converted from a single-ended signal to a differential 1 V) signal using either an RF transformer or an RF balun. R (m 0 The RF balun configuration is recommended for clock frequencies O R –1 R between 125 MHz and 625 MHz, and the RF transformer is recom- E EF –2 mended for clock frequencies from 10 MHz to 200 MHz. The R V –3 back-to-back Schottky diodes across the transformer/balun –4 secondary limit clock excursions into the AD9231 to approx- imately 0.8 V p-p differential. –5 –6 This limit helps prevent the large voltage swings of the clock –40 –20 0TEMPER2A0TURE (°4C0) 60 80 08121-052 fprroemse rfveiendgi nthg et hfarostu grihs et oa notdh fearl pl toirmtieosn os fo tfh teh sei gAnDal9 t2h3a1t warhei le Figure 48. Typical VREF Drift critical to a low jitter performance. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal Mini-Circuits® reference buffer loads the external reference with an equivalent ADT1-1WT, 1:1 Z 0.1µF 0.1µF 7.5 kΩ load (see Figure 37). The internal buffer generates the CLOCK XFMR CLK+ positive and negative full-scale references for the ADC core. INPUT 50Ω 100Ω ADC 0.1µF Therefore, the external reference must be limited to a maximum CLK– oCfL 1O.0C VK. INPUT CONSIDERATIONS 0.1µF SHDCSIHMOOSDT2ET8SK2:2Y 08121-017 Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz) For optimum performance, clock the AD9231 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally 1nF 0.1µF CLOCK CLK+ (see Figure 49) and require no external bias. INPUT 50Ω ADC 0.1µF AVDD 1nF CLK– 0.9V SHDCSIHMOOSDT2ET8SK2:2Y 08121-018 Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz) CLK+ CLK– 2pF 2pF 08121-016 Figure 49. Equivalent Clock Input Circuit Rev. B | Page 23 of 36

AD9231 Data Sheet If a low jitter clock source is not available, another option is to Input Clock Divider ac couple a differential PECL signal to the sample clock input The AD9231 contains an input clock divider with the ability pins, as shown in Figure 52. The AD9510/AD9511/AD9512/ to divide the input clock by integer values between 1 and 8. AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer Optimum performance is obtained by enabling the internal excellent jitter performance. duty cycle stabilizer (DCS) when using divide ratios other than 1, 2, or 4. 0.1µF 0.1µF The AD9231 clock divider can be synchronized using the CILNOPCUKT CLK+ external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow AD951x 100Ω ADC the clock divider to be resynchronized on every SYNC signal PECL DRIVER CLOCK 0.1µF 0.1µF CLK– or only on the first SYNC signal after the register is written. A INPUT 50kΩ 50kΩ 240Ω 240Ω 08121-019 vTahliisd sSyYnNchCr ocnaiuzsaetsio tnh ef ecalotucrke dailvloidwesr mtou rletispelte t poa irttss i ntoit hiaalv set a te. Figure 52. Differential PECL Sample Clock (Up to 625 MHz) their clock dividers aligned to guarantee simultaneous input sampling. A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 53. The AD9510/ Clock Duty Cycle AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 Typical high speed ADCs use both clock edges to generate clock drivers offer excellent jitter performance. a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic 0.1µF 0.1µF CLOCK CLK+ performance characteristics. INPUT AD951x 100Ω ADC The AD9231 contains a duty cycle stabilizer (DCS) that retimes LVDS DRIVER 0.1µF 0.1µF CLOCK CLK– the nonsampling (falling) edge, providing an internal clock INPUT 50kΩ 50kΩ 08121-020 spirgonvaidl ew ait wh iad en roamngine aolf 5c0lo%c kd iuntpyu cty dculety. Tcyhcilse as lwloiwthso tuht ea fufescetri ntog Figure 53. Differential LVDS Sample Clock (Up to 625 MHz) the performance of the AD9231. Noise and distortion perform- In some applications, it may be acceptable to drive the sample ance are nearly flat for a wide range of duty cycles with the DCS clock inputs with a single-ended 1.8 V CMOS signal. In such on, as shown in Figure 55. applications, drive the CLK+ pin directly from a CMOS gate, and Jitter in the rising edge of the input is still of concern and is not bypass the CLK− pin to ground with a 0.1 μF capacitor (see easily reduced by the internal stabilization circuit. The duty Figure 54). cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated VCC with it that must be considered in applications in which the 0.1µF 1kΩ AD951x OP1T0IO0ΩNAL0.1µF clock rate can change dynamically. A wait time of 1.5 μs to 5 μs CLOCK CMOS DRIVER CLK+ INPUT 50Ω1 1kΩ ADC is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. CLK– 80 0.1µF 150Ω RESISTOR IS OPTIONAL. 08121-021 75 DCS ON Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) 70 S) 65 F B R (d 60 DCS OFF N S 55 50 4405 08121-078 10 20 30 40 50 60 70 80 POSITIVE DUTY CYCLE (%) Figure 55. SNR vs. DCS On/Off Rev. B | Page 24 of 36

Data Sheet AD9231 Jitter Considerations POWER DISSIPATION AND STANDBY MODE High speed, high resolution ADCs are sensitive to the quality As shown in Figure 57, the analog core power dissipated by of the clock input. The degradation in SNR from the low fre- the AD9231 is proportional to its sample rate. The digital quency SNR (SNRLF) at a given input frequency (fINPUT) due to power dissipation of the CMOS outputs are determined jitter (tJRMS) can be calculated by primarily by the strength of the digital drivers and the load SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10(−SNRLF/10)] on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as In the previous equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications IDRVDD = VDRVDD × CLOAD × fCLK × N are particularly sensitive to jitter, as illustrated in Figure 56. where N is the number of output bits (26, in the case of the 80 AD9231). This maximum current occurs when every output bit switches 75 0.05ps on every clock cycle, that is, a full-scale square wave at the Nyquist 70 frequency of f /2. In practice, the DRVDD current is estab- CLK 0.2ps lished by the average number of output bits switching, which BFS)65 is determined by the sample rate and the characteristics of the d R ( analog input signal. N60 0.5ps S Reducing the capacitive load presented to the output drivers can 55 1.0ps minimize digital power consumption. The data in Figure 57 was 50 1.5ps taken using the same operating conditions as those used for the 2.0ps Typical Performance Characteristics, with a 5 pF load on each 3.0ps 2.5ps 45 output driver. 1 10FREQUENCY (MHz1)00 1k 08121-022 150 Figure 56. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases in mW)130 AD9231-80 which aperture jitter may affect the dynamic range of the AD9231. R ( E To avoid modulating the clock signal with digital noise, keep OW110 P power supplies for clock drivers separate from the ADC output E driver supplies. Low jitter, crystal-controlled oscillators make the COR 90 AD9231-65 G best clock sources. If the clock is generated from another type of O L A source (by gating, dividing, or another method), it should be N A 70 AD9231-40 retimed by the original clock at the last step. AFoNr -m75o6r eA ipnpfolircmataiotino nN, osetee atvhaei lAabNle-5 o0n1 wAwppwl.iacnatailoong .Ncoomte. and the 500 10 AD290231-2030 40 50 60 70 8008121-079 CHANNEL/CHIP SYNCHRONIZATION CLOCK RATE (MSPS) Figure 57. Analog Core Power vs. Clock Rate The AD9231 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. Drive the SYNC input using a single-ended CMOS-type signal. Rev. B | Page 25 of 36

AD9231 Data Sheet The AD9231 is placed in power-down mode either by the SPI As detailed in the AN-877 Application Note, Interfacing to High port or by asserting the PDWN pin high. In this state, the ADC Speed ADCs via SPI, the data format can be selected for offset typically dissipates 2.2 mW. During power-down, the output binary, twos complement, or gray code when using the SPI control. drivers are placed in a high impedance state. Asserting the Table 11. SCLK/DFS Mode Selection (External Pin Mode) PDWN pin low returns the AD9231 to its normal operating Voltage at Pin SCLK/DFS SDIO/DCS mode. Note that PDWN is referenced to the digital output AGND Offset binary (default) DCS disabled(default) driver supply (DRVDD) and should not exceed that supply DRVDD Twos complement DCS enabled voltage. Low power dissipation in power-down mode is achieved by Digital Output Enable Function (OEB) shutting down the reference, reference buffer, biasing networks, The AD9231 has a flexible three-state ability for the digital and clock. Internal capacitors are discharged when entering power- output pins. The three-state mode is enabled using the OEB pin down mode and then must be recharged when returning to normal or through the SPI interface. If the OEB pin is low, the output operation. As a result, wake-up time is related to the time spent data drivers and DCOs are enabled. If the OEB pin is high, the in power-down mode, and shorter power-down cycles result in output data drivers and DCOs are placed in a high impedance proportionally shorter wake-up times. state. This OEB function is not intended for rapid access to the When using the SPI port interface, the user can place the ADC data bus. Note that OEB is referenced to the digital output in power-down mode or standby mode. Standby mode allows driver supply (DRVDD) and should not exceed that supply the user to keep the internal reference circuitry powered when voltage. faster wake-up times are required. See the Memory Map section When using the SPI interface, the data outputs and DCO of for more details. each channel can be independently three-stated by using the DIGITAL OUTPUTS output disable (OEB) bit (Bit 4) in Register 0x14. The AD9231 output drivers can be configured to interface with TIMING 1.8 V to 3.3 V CMOS logic families. Output data can also be The AD9231 provides latched data with a pipeline delay of multiplexed onto a single output bus to reduce the total number 9 clock cycles. Data outputs are available one propagation of traces required. delay (t ) after the rising edge of the clock signal. PD The CMOS output drivers are sized to provide sufficient output Minimize the length of the output data lines and loads placed current to drive a wide variety of logic families. However, large on them to reduce transients within the AD9231. These drive currents tend to cause current glitches on the supplies transients can degrade converter dynamic performance. and may affect converter performance. The lowest typical conversion rate of the AD9231 is 3 MSPS. At Applications requiring the ADC to drive large capacitive loads clock rates below 3 MSPS, dynamic performance can degrade. or large fanouts may require external buffers or latches. Data Clock Output (DCO) The output data format can be selected to be either offset binary or twos complement by setting the SCLK/DFS pin when operating The AD9231 provides two data clock output (DCO) signals in the external pin mode (see Table 11). intended for capturing the data in an external register. The CMOS data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description. Table 12. Output Data Format Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode OR VIN+ − VIN− < −VREF − 0.5 LSB 0000 0000 0000 1000 0000 0000 1 VIN+ − VIN− = −VREF 0000 0000 0000 1000 0000 0000 0 VIN+ − VIN− = 0 1000 0000 0000 0000 0000 0000 0 VIN+ − VIN− = +VREF − 1.0 LSB 1111 1111 1111 0111 1111 1111 0 VIN+ − VIN− > +VREF − 0.5 LSB 1111 1111 1111 0111 1111 1111 1 Rev. B | Page 26 of 36

Data Sheet AD9231 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of The AD9231 includes a built-in self-test feature designed to the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN enable verification of the integrity of each channel as well as to sequence can be continued from its last value by writing a 0 in facilitate board level debugging. A built-in self-test (BIST) feature Bit 2 of Register 0x0E. However, if the PN sequence is not reset, that verifies the integrity of the digital datapath of the AD9231 the signature calculation does not equal the predetermined is included. Various output test options are also provided to place value at the end of the test. At that point, the user needs to rely predictable values on the outputs of the AD9231. on verifying the output data. BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES The BIST is a thorough test of the digital portion of the selected The output test options are described in Table 16 at Address AD9231 signal path. Perform the BIST test after a reset to ensure 0x0D. When an output test mode is enabled, the analog section the part is in a known state. During BIST, data from an internal of the ADC is disconnected from the digital back-end blocks pseudorandom noise (PN) source is driven through the digital and the test pattern is run through the output formatting block. datapath of both channels, starting at the ADC block output. Some of the test patterns are subject to output formatting, and At the datapath output, CRC logic calculates a signature from some are not. The PN generators from the PN sequence tests the data. The BIST sequence runs for 512 cycles and then stops. can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These Once completed, the BIST compares the signature results with a tests can be performed with or without an analog signal (if pre-determined value. If the signatures match, the BIST sets Bit 0 present, the analog signal is ignored), but they do require of Register 0x24, signifying the test passed. If the BIST test failed, an encode clock. For more information, see the AN-877 Bit 0 of Register 0x24 is cleared. The outputs are connected Application Note, Interfacing to High Speed ADCs via SPI. during this test, so the PN sequence can be observed as it runs. Writing the value 0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence Rev. B | Page 27 of 36

AD9231 Data Sheet SERIAL PORT INTERFACE (SPI) The falling edge of CSB, in conjunction with the rising edge of The AD9231 serial port interface (SPI) allows the user to configure SCLK, determines the start of the framing. An example of the the converter for specific functions or operations through a serial timing and its definitions can be found in Figure 58 and structured register space provided inside the ADC. The SPI Table 5. gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port Other modes involving the CSB are available. The CSB can be and can be written to or read from via the port. Memory is held low indefinitely, which permanently enables the device; organized into bytes that can be further divided into fields, this is called streaming. The CSB can stall high between bytes to which are documented in the Memory Map section. For allow for additional external timing. When CSB is tied high, SPI detailed operational information, see the AN-877 Application functions are placed in high impedance mode. This mode turns Note, Interfacing to High Speed ADCs via SPI. on any SPI pin secondary functions. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined Three pins define the SPI of this ADC: the SCLK, the SDIO, by the W0 and W1 bits as shown in Figure 58. and the CSB (see Table 13). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to All data is composed of 8-bit words. The first bit of the first byte the ADC. The SDIO (serial data input/output) is a dual-purpose in a multibyte serial data transfer frame indicates whether a read pin that allows data to be sent and read from the internal ADC command or a write command is issued. This allows the serial memory map registers. The CSB (chip select bar) is an active- data input/output (SDIO) pin to change direction from an input low control that enables or disables the read and write cycles. to an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines Table 13. Serial Port Interface Pins whether the serial frame is a read or write operation, allowing Pin Function the serial port to be used both to program the chip and to read SCLK Serial Clock. The serial shift clock input, which is used to the contents of the on-chip memory. If the instruction is a readback synchronize serial interface reads and writes. operation, performing a readback causes the serial data input/ SDIO Serial Data Input/Output. A dual-purpose pin that typically serves as an input or an output, depending on output (SDIO) pin to change direction from an input to an output the instruction being sent and the relative position in the at the appropriate point in the serial frame. timing frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB CSB Chip Select Bar. An active-low control that gates the read first is the default on power-up and can be changed via the SPI and write cycles. port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tDS tHIGH tCLK tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 08121-023 Figure 58. Serial Port Interface Timing Diagram Rev. B | Page 28 of 36

Data Sheet AD9231 HARDWARE INTERFACE Table 14. Mode Selection The pins described in Table 13 constitute the physical interface External between the programming device of the user and the serial port Pin Voltage Configuration of the AD9231. The SCLK pin and the CSB pin function as inputs SDIO/DCS DRVDD Duty cycle stabilizer enabled when using the SPI interface. The SDIO pin is bidirectional, AGND(default) Duty cycle stabilizer disabled functioning as an input during write phases and as an output SCLK/DFS DRVDD Twos complement enabled during readback. AGND (default) Offset binary enabled OEB DRVDD Outputs in high impedance The SPI interface is flexible enough to be controlled by AGND (default) Outputs enabled either FPGAs or microcontrollers. One method for SPI PDWN DRVDD Chip in power-down or standby configuration is described in detail in the AN-812 Appli- AGND (default) Normal operation cation Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. SPI ACCESSIBLE FEATURES The SPI port should not be active during periods when the full Table 15 provides a brief description of the general features that dynamic performance of the converter is required. Because the are accessible via the SPI. These features are described in detail SCLK signal, the CSB signal, and the SDIO signal are typically in the AN-877 Application Note, Interfacing to High Speed ADCs asynchronous to the ADC clock, noise from these signals can via SPI. The AD9231 part-specific features are described in degrade converter performance. If the on-board SPI bus is used detail in Table 16. for other devices, it may be necessary to provide buffers between this bus and the AD9231 to prevent these signals from transi- Table 15. Features Accessible Using the SPI tioning at the converter inputs during critical sampling periods. Feature Description Mode Allows the user to set either power-down mode SDIO/DCS and SCLK/DFS serve a dual function when the or standby mode SPI interface is not being used. When the pins are strapped to Clock Allows the user to access the DCS via the SPI DRVDD or ground during device power-on, they are associated Offset Allows the user to digitally adjust the with a specific function. The Digital Outputs section describes converter offset the strappable functions supported on the AD9231. Test I/O Allows the user to set test modes to have known CONFIGURATION WITHOUT THE SPI data on output bits Output Mode Allows the user to set up outputs In applications that do not interface to the SPI control registers, Output Phase Allows the user to set the output clock polarity the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the Output Delay Allows the user to vary the DCO delay PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power- down feature control. In this mode, connect the CSB chip select to DRVDD, which disables the serial port interface. Rev. B | Page 29 of 36

AD9231 Data Sheet MEMORY MAP READING THE MEMORY MAP REGISTER TABLE DEFAULT VALUES Each row in the memory map register table (see Table 16) has After the AD9231 is reset, critical registers are loaded with eight bit locations. The memory map is roughly divided into default values. The default values for the registers are given four sections: the chip configuration registers (Address 0x00 in the memory map register table (see Table 16). to Address 0x02); the device index and transfer registers Logic Levels (Address 0x05 and Address 0xFF); the program registers, An explanation of logic level terminology follows: including setup, control, and test (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 • “Bit is set” is synonymous with “bit is set to Logic 1” or and Address 0x101). “writing Logic 1 for the bit.” • “Clear a bit” is synonymous with “bit is set to Logic 0” or Table 16 documents the default hexadecimal value for each “writing Logic 0 for the bit.” hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For Transfer Register Map example, Address 0x05, the channel index register, has a hexade- Address 0x08 to Address 0x18 are shadowed. Writes to these cimal default value of 0x03. This means that in Address 0x05 addresses do not affect part operation until a transfer command Bit[7:2] = 0, and the remaining Bits[1:0] = 1. This setting is the is issued by writing 0x01 to Address 0xFF, setting the transfer bit. default channel index setting. The default value results in both This allows these registers to be updated internally and simulta- ADC channels receiving the next write command. For more neously when the transfer bit is set. The internal update takes information on this function and others, see the AN-877 place when the transfer bit is set, and then the bit autoclears. Application Note, Interfacing to High Speed ADCs via SPI. This Channel-Specific Registers application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers, Register 0x100 and Some channel setup functions can be programmed differently Register 0x101, are documented in the Memory Map Register for each channel. In these cases, channel address locations are Descriptions section following Table 16. internally duplicated for each channel. These registers and bits OPEN LOCATIONS are designated in the memory map register table as local. These local registers and bits can be accessed by setting the appropriate All address and bit locations that are not included in the SPI Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. map are not currently supported for this device. Unused bits of If both bits are set, the subsequent write affects the registers of a valid address location should be written with 0s. Writing to these both channels. In a read cycle, set only Channel A or Channel B locations is required only when part of an address location is to read one of the two registers. If both bits are set during an open (for example, Address 0x05). If the entire address location SPI read cycle, the part returns the value for Channel A. is open, it is omitted from the SPI map (for example, Address 0x13) Registers and bits designated as global in the memory map and should not be written. register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev. B | Page 30 of 36

Data Sheet AD9231 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 16 are not currently supported for this device. Table 16. Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Chip Configuration Registers 0x00 SPI port 0 LSB Soft reset 1 1 Soft LSB 0 0x18 The nibbles are configuration first reset first mirrored so that (global) LSB- or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID (global) 8-bit chip ID bits [7:0] Unique chip ID used AD9231 = 0x24 to differentiate devices; read only 0x02 Chip grade Open Speed grade ID [6:4] Open Unique speed (global) 20 MSPS = 000 grade ID used to 40 MSPS = 001 differentiate 65 MSPS = 010 devices; read only 80 MSPS = 011 Device Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open ADC B ADC A 0x03 Bits are set to default default determine which device on chip receives the next write command; the default is all devices on chip 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave Program Registers (May or May Not Be Indexed by Device Index) 0x08 Modes External External pin function Open Open 00 = chip run 0x80 Determines various power- 0x00 full power-down 01 = full power- generic modes of down 0x01 standby down chip operation enable (local) 10 = standby (local) 11 = chip wide digital reset (local) 0x09 Clock (global) Open Open Open Open Open Duty 0x00 cycle stabilize 0x0B Clock divide Open Clock divider [2:0] 0x00 The divide ratio is (global) Clock divide ratio the value plus 1 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0D Test mode (local) User test mode Reset PN Reset Output test mode [3:0] (local) 0x00 When set, the test (local) long gen PN 0000 = off (default) data is placed on 00 = single short 0001 = midscale short the output pins in 01 = alternate gen 0010 = positive FS place of normal 10 = single once 0011 = negative FS data 11 = alternate 0100 = alternating checkerboard once 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency Rev. B | Page 31 of 36

AD9231 Data Sheet Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments 0x0E BIST enable Open Open Open Open Open BIST Open BIST 0x00 When Bit 0 is set, INIT enable the BIST function is initiated 0x10 Offset adjust 8-bit device offset adjustment [7:0] (local) 0x00 Device offset trim (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 0x14 Output mode 00 = 3.3 V CMOS Output mux Output Open Output 00 = offset binary 0x00 Configures the 10 = 1.8 V CMOS enable disable invert 01 = twos outputs and the (interleaved) (local) (local) complement format of the data 10 = gray code 11 = offset binary (local) 0x15 OUTPUT_ADJUST 3.3 V DCO 1.8 V DCO 3.3 V data 1.8 V data 0x22 Determines drive strength drive strength drive strength drive strength CMOS output drive 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe 00 = 1 stripe strength properties (default) 01 = 2 stripes (default) 01 = 2 stripes 01 = 2 stripes 10 = 3 stripes (default) 01 = 2 stripes 10 = 3 stripes 10 = 3 stripes 11 = 4 stripes 10 = 3 stripes (default) 11 = 4 stripes 11 = 4 stripes 11 = 4 stripes 0x16 OUTPUT_PHASE DCO Open Open Open Open Input clock phase adjust [2:0] 0x00 On devices that output (Value is number of input clock utilize global clock polarity cycles of phase delay) divide, this register 0 = 000 = no delay determines which normal 001 = 1 input clock cycle phase of the divider 1 = 010 = 2 input clock cycles output is used to inverted 011 = 3 input clock cycles supply the output (local) 100 = 4 input clock cycles clock; internal 101 = 5 input clock cycles latching is 110 = 6 input clock cycles unaffected 111 = 7 input clock cycles 0x17 OUTPUT_DELAY Enable Open Enable Open Open DCO/Data delay[2:0] 0x00 This sets the fine DCO data 000 = 0.56 ns output delay of the delay delay 001 = 1.12 ns output clock but does not change 010 = 1.68 ns internal timing 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB 0x24 BIST signature LSB BIST signature [7:0] 0x00 Least significant byte of BIST signature, read only 0x2A Features Open Open Open Open Open Open Open OR OE 0x01 Disable the OR pin (local) for the indexed channel 0x2E Output assign Open Open Open Open Open Open Open 0 = Ch A = Assign an ADC to an ADC A 0x00 output channel 1 = Ch B = ADC B 0x01 (local) Rev. B | Page 32 of 36

Data Sheet AD9231 Default Addr Register Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments Digital Feature Control 0x100 Sync control Open Open Open Open Open Clock Clock Master 0x01 (global) divider divider sync next sync enable sync enable only 0x101 USR2 Enable Open Open Open Enable Run Open Disable 0x88 Enables internal OEB GCLK GCLK SDIO oscillator for clock Pin 47 detect pull- rates < 5 MHz (local) down USR2 (Register 0x101) MEMORY MAP REGISTER DESCRIPTIONS Bit 7—Enable OEB Pin 47 For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Normally set high, this bit allows Pin 47 to function as the Note, Interfacing to High Speed ADCs via SPI. output enable. If it is set low, it disables Pin 47. Sync Control (Register 0x100) Bit 3—Enable GCLK Detect Bits[7:3]—Reserved Normally set high, this bit enables a circuit that detects encode Bit 2—Clock Divider Next Sync Only rates below about 5 MSPS. When a low encode rate is detected an internal oscillator, GCLK, is enabled ensuring the proper If the master sync enable bit (Address 0x100, Bit 0) and the operation of several circuits. If set low the detector is disabled. clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it Bit 2—Run GCLK receives and to ignore the rest. The clock divider sync enable This bit enables the GCLK oscillator. For some applications bit (Address 0x100, Bit 1) resets after it syncs. with encode rates below 10 MSPS, it may be preferable to set Bit 1—Clock Divider Sync Enable this bit high to supersede the GCLK detector. Bit 1 gates the sync pulse to the clock divider. The sync signal Bit 0—Disable SDIO Pull-Down is enabled when Bit 1 and Bit 0 are high and the device is This bit can be set high to disable the internal 30 kΩ pull-down operating in continuous sync mode as long as Bit 2 of the on the SDIO pin, which can be used to limit the loading when sync control is low. many devices are connected to the SPI bus. Bit 0—Master Sync Enable Bit 0 must be high to enable any of the sync functions. Rev. B | Page 33 of 36

AD9231 Data Sheet APPLICATIONS INFORMATION DESIGN GUIDELINES The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to Before starting design and layout of the AD9231 as a system, flow through the bottom of the PCB. Fill or plug these vias it is recommended that the designer become familiar with these with nonconductive epoxy. guidelines, which discuss the special circuit connections and To maximize the coverage and adhesion between the ADC and layout requirements needed for certain pins. the PCB, a silkscreen should be overlaid to partition the continuous Power and Ground Recommendations plane on the PCB into several uniform sections. This provides When connecting power to the AD9231, it is strongly several tie points between the ADC and the PCB during the reflow recommended that two separate supplies be used. Use one 1.8 V process. Using one continuous plane with no partitions guarantees supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for only one tie point between the ADC and the PCB. For detailed the digital output supply (DRVDD). If a common 1.8 V AVDD information about packaging and PCB layout of chip scale and DRVDD supply must be used, the AVDD and DRVDD packages, see the AN-772 Application Note, A Design and domains must be isolated with a ferrite bead or filter choke and Manufacturing Guide for the Lead Frame Chip Scale Package separate decoupling capacitors. Several different decoupling (LFCSP), at www.analog.com. capacitors can be used to cover both high and low frequencies. VCM Locate these capacitors close to the point of entry at the PCB The VCM pin should be decoupled to ground with a 0.1 μF level and close to the pins of the part, with minimal trace length. capacitor, as shown in Figure 42. A single PCB ground plane should be sufficient when using the RBIAS AD9231. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance The AD9231 requires that a 10 kΩ resistor be placed between is easily achieved. the RBIAS pin and ground. This resistor sets the master current Exposed Paddle Thermal Heat Sink Recommendations reference of the ADC core and should have at least a 1% tolerance. Reference Decoupling The exposed paddle (Pin 0) is the only ground connection for the AD9231; therefore, it must be connected to analog ground Externally decoupled the VREF pin to ground with a low ESR, (AGND) on the customer’s PCB. To achieve the best electrical 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic and thermal performance, mate an exposed (no solder mask) capacitor. continuous copper plane on the PCB to the AD9231 exposed SPI Port paddle, Pin 0. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9231 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. B | Page 34 of 36

Data Sheet AD9231 OUTLINE DIMENSIONS 9.10 0.60 0.30 9.00 SQ 0.42 0.23 0.60 8.90 0.24 0.18 0.42 PIN 1 0.24 INDICATOR 49 64 1 48 PIN 1 INDICATOR 8.85 0.50 EXPOSED 6.35 8.75 SQ BSC PAD 6.20 SQ 8.65 6.05 0.50 0.40 33 16 32 17 0.30 0.25 MIN TOP VIEW BOTTOM VIEW 7.50 REF 1.00 12° MAX 0.80 MAX 0.65 NOM 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND SEATING FUNCTION DESCRIPTIONS PLANE 0.20 REF SECTION OF THIS DATA SHEET. PKG-1184 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 01-22-2015-D Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters ORDERING GUIDE Model1 Notes Temperature Range Package Description Package Option AD9231BCPZ-80 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9231BCPZRL7-80 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9231BCPZ-65 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9231BCPZRL7-65 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9231BCPZ-40 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9231BCPZRL7-40 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9231BCPZ-20 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9231BCPZRL7-20 2 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-4 AD9231-80EBZ Evaluation Board AD9231-65EBZ Evaluation Board AD9231-40EBZ Evaluation Board AD9231-20EBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. Rev. B | Page 35 of 36

AD9231 Data Sheet NOTES ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08121-0-9/16(B) Rev. B | Page 36 of 36

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9231BCPZRL7-80 AD9231BCPZ-20 AD9231BCPZ-65 AD9231BCPZRL7-65 AD9231BCPZ-40 AD9231BCPZRL7-40 AD9231BCPZ-80 AD9231BCPZRL7-20