10-Bit, 65/80/105 MSPS, 3 V A/D Converter Data Sheet AD9215 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 3 V supply operation (2.7 V to 3.3 V) AVDD DRVDD SNR = 58 dBc (to Nyquist) VIN+ SFDR = 77 dBc (to Nyquist) SHA APDIPCE CLOINREE Low power ADC core: 96 mW at 65 MSPS, 104 mW VIN– @ 80 MSPS, 120 mW at 105 MSPS REFT AD9215 Differential input with 300 MHz bandwidth REFB On-chip reference and sample-and-hold amplifier CORRECTION LOGIC DNL = ±0.25 LSB 10 Flexible analog input: 1 V p-p to 2 V p-p range OUTPUT BUFFERS OR Offset binary or twos complement data format D9 (MSB) Clock duty cycle stabilizer D0 VREF APPLICATIONS CLOCK DUTY CYCLE MODE SENSE STABLIZER SELECT Ultrasound equipment REF IBFa statemryp-lpinogw ienr ceodm inmsturnuimcaetniotsn s receivers SELECT AGND0.5V CLK PDWN MODE DGND 02874-A-001 Hand-held scopemeters Figure 1. Low cost digital oscilloscopes PRODUCT DESCRIPTION The AD9215 is a family of monolithic, single 3 V supply, 10-bit, Fabricated on an advanced CMOS process, the AD9215 is avail- 65/80/105 MSPS analog-to-digital converters (ADC). This family able in both a 28-lead surface-mount plastic package and a features a high performance sample-and-hold amplifier (SHA) 32-lead chip scale package and is specified over the industrial and voltage reference. The AD9215 uses a multistage differential temperature range of −40°C to +85°C. pipelined architecture with output error correction logic to pro- PRODUCT HIGHLIGHTS vide 10-bit accuracy at 105 MSPS data rates and to guarantee no missing codes over the full operating temperature range. 1. The AD9215 operates from a single 3 V power supply and features a separate digital output driver supply to accom- The wide bandwidth, truly differential sample-and-hold ampli- modate 2.5 V and 3.3 V logic families. fier (SHA) allows for a variety of user-selectable input ranges 2. Operating at 105 MSPS, the AD9215 core ADC consumes and offsets including single-ended applications. It is suitable for a low 120 mW; at 80 MSPS, the power dissipation is 104 multiplexed systems that switch full-scale voltage levels in mW; and at 65 MSPS, the power dissipation is 96 mW. successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with pow- 3. The patented SHA input maintains excellent performance er and cost savings over previously available ADCs, the AD9215 for input frequencies up to 200 MHz and can be config- is suitable for applications in communications, imaging, and ured for single-ended or differential operation. medical ultrasound. 4. The AD9215 is part of several pin compatible 10-, 12-, and 14-bit low power ADCs. This allows a simplified upgrade A single-ended clock input is used to control all internal conversion from 10 bits to 12 bits for systems up to 80 MSPS. cycles. A duty cycle stabilizer compensates for wide variations in the 5. The clock duty cycle stabilizer maintains converter per- clock duty cycle while maintaining excellent performance. The digital formance over a wide range of clock pulse widths. output data is presented in straight binary or twos complement for- 6. The out of range (OR) output bit indicates when the signal mats. An out-of-range signal indicates an overflow condition, which is beyond the selected input range. can be used with the MSB to determine low or high overflow. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD9215 Data Sheet TABLE OF CONTENTS Specifications ..................................................................................... 3 REVISION HISTORY Absolute Maximum Ratings1 .......................................................... 6 2/13—Data Sheet Changed from a REV. A to a REV. B Explanation of Test Levels ........................................................... 6 Changes to Figure 4 and Added EPAD Note to Pin Configura- tions and Function Descriptions Section ..................................... 7 ESD Caution .................................................................................. 6 Changes to Voltage Reference Section ........................................ 17 Pin Configurations and Function Descriptions ........................... 7 Changes to Evaluation Board Section......................................... 18 Equivalent Circuits ....................................................................... 8 Updated Outline Dimensions ...................................................... 33 Definitions of Specifications ....................................................... 8 Changes to Ordering Guide ......................................................... 34 Typical Performance Characteristics ........................................... 10 2/04—Data Sheet Changed from a REV. 0 to a REV. A Applying the AD9215 Theory of Operation ............................... 14 Renumbered Figures and Tables ..............................UNIVERSAL Clock Input and Considerations .............................................. 15 Changes to Product Title ................................................................ 1 Evaluation Board ........................................................................ 18 Changes to Features ........................................................................ 1 Outline Dimensions ....................................................................... 33 Changes to Product Description ................................................... 1 Ordering Guide ........................................................................... 34 Changes to Product Highlights ..................................................... 1 Changes to Specifications ............................................................... 2 Changes to Figure 2 ......................................................................... 4 Changes to Figures 9 to 11 ........................................................... 10 Added Figure 14 ............................................................................ 10 Added Figures 16 and 18 .............................................................. 11 Changes to Figures 21 to 24 and 25 to 26 ................................... 12 Deleted Figure 25 ........................................................................... 12 Changes to Figures 28 and 29 ...................................................... 13 Changes to Figure 31 ..................................................................... 14 Changes t0 Figure 35 ..................................................................... 16 Changes to Figures 50 through 58............................................... 26 Added Table 11 .............................................................................. 31 Updated Outline Dimensions ...................................................... 32 Changes to Ordering Guide ......................................................... 33 5/03—Revision 0: Initial Version Rev. B | Page 2 of 36

Data Sheet AD9215 SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted. Table 1. DC Specifications AD9215BRU-65/ AD9215BRU-80/ AD9215BRU-105/ AD9215BCP-65 AD9215BCP-80 AD9215BCP-105 Test Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION Full VI 10 10 10 Bits ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Offset Error1 Full VI ±0.3 ±2.0 ±0.3 ±2.0 ±0.3 ±2.0 % FSR Gain Error1 Full VI 0 +1.5 +4.0 +1.5 +4.0 +1.5 +4.0 % FSR Differential Nonlinearity (DNL)2 Full VI −1.0 ±0.5 +1.0 −1.0 ±0.5 +1.0 −1.0 ±0.6 +1.2 LSB Integral Nonlinearity (INL)2 Full VI ±0.5 ±1.2 ±0.5 ±1.2 ±0.65 ±1.2 LSB TEMPERATURE DRIFT Offset Error1 Full V +15 +15 +15 ppm/°C Gain Error1 Full V +30 +30 +30 ppm/°C Reference Voltage (1 V Mode) Full V ±230 ±230 ±230 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Full VI ±2 ±35 ±2 ±35 ±2 ±35 mV Load Regulation @ 1.0 mA Full V 0.2 0.2 0.2 mV Output Voltage Error (0.5 V Mode) Full V ± 1 ±1 ±1 mV Load Regulation @ 0.5 mA Full V 0.2 0.2 0.2 mV INPUT REFERRED NOISE VREF = 0.5 V 25°C V 0.8 0.8 0.8 LSB rms VREF = 1.0 V 25°C V 0.4 0.4 0.4 LSB rms ANALOG INPUT Input Span, VREF = 0.5 V Full IV 1 1 1 V p-p Input Span, VREF = 1.0 V Full IV 2 2 2 V p-p Input Capacitance3 Full V 2 2 2 pF REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ POWER SUPPLIES Supply Voltage AVDD Full IV 2.7 3.0 3.3 2.7 3.0 3.3 2.7 3.0 3.3 V DRVDD Full IV 2.25 2.5 3.6 2.25 2.5 3.6 2.25 2.5 3.6 V Supply Current I 2 Full VI 32 35 34.5 39 40 44 mA AVDD I 2 25°C V 7.0 8.6 11.3 mA DRVDD PSRR Full V ± 0.1 ± 0.1 ± 0.1 % FSR POWER CONSUMPTION Sine Wave Input2 I 2 Full VI 96 104 120 mW AVDD I 2 25°C V 18 20 25 mW DRVDD Standby Power4 25°C V 1.0 1.0 1.0 mW 1 With a 1.0 V internal reference. 2 Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure. 4 Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND). Rev. B | Page 3 of 36

AD9215 Data Sheet AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted. Table 2. AC Specifications AD9215BRU-65/ AD9215BRU-80/ AD9215BRU-105/ AD9215BCP-65 AD9215BCP-80 AD9215BCP-105 Test Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) f = 2.4 MHz Full VI 56.0 58.5 56.0 58.5 57.5 dB IN 25°C I 57.0 59.0 57.0 59.0 56.6 58.5 dB f = Nyquist1 Full VI 56.0 58.0 56.0 58.0 57.5 dB IN 25°C I 56.5 58.5 56.5 58.5 56.4 58.0 dB f = 70 MHz 25°C V 58.0 57.8 dB IN f = 100 MHz 25°C V 57.5 57.7 dB IN SIGNAL-TO-NOISE AND DISTORTION (SINAD) f = 2.4 MHz Full VI 55.8 58.5 55.7 58.5 57.6 dB IN 25°C I 56.5 59.0 56.8 58.5 56.5 58.2 dB f = Nyquist1 Full VI 55.8 58.0 55.5 58.0 57.3 dB IN 25°C I 56.3 58.5 56.3 58.5 56.1 57.8 dB f = 70 MHz 25°C V 56.0 57.7 dB IN f = 100 MHz 25°C V 55.5 57.4 dB IN EFFECTIVE NUMBER OF BITS (ENOB) f = 2.4 MHz Full VI 9.1 9.5 9.0 9.5 9.3 Bits IN 25°C I 9.2 9.6 9.3 9.5 9.2 9.5 Bits f = Nyquist1 Full VI 9.1 9.4 9.0 9.4 9.4 Bits IN 25°C I 9.1 9.5 9.0 9.5 9.1 9.4 Bits f = 70 MHz 25°C V 9.1 9.4 Bits IN f = 100 MHz 25°C V 9.0 9.3 Bits IN WORST HARMONIC (Second or Third) f = 2.4 MHz Full VI −78 −64 −78 −64 −78 dBc IN 25°C I −80 −65 −80 −65 −84 −70 dBc f = Nyquist1 Full VI −77 −64 −76 −63 −74 dBc IN 25°C I −78 −65 −78 −65 −75 −61 dBc f = 70 MHz 25°C V −70 −75 dBc IN f = 100 MHz 25°C V −70 −74 dBc IN WORST OTHER (Excluding Second or Third) f = 2.4 MHz Full VI −77 −67 −77 −66 −73 dBc IN 25°C I −78 −68 −77 −68 −75 −66 dBc f = Nyquist1 Full VI −77 −67 −77 −66 −71 dBc IN 25°C I −78 −68 −77 −68 −75 −63 dBc f = 70 MHz 25°C V −80 -75 dBc IN f = 100 MHz 25°C V −80 −75 dBc IN TWO-TONE SFDR (AIN = –7 dBFS) f = 70.3 MHz, f = 71.3 MHz 25°C V 75 75 dBc IN1 IN2 f = 100.3 MHz, f = 101.3 MHz 25°C V 74 74 dBc IN1 IN2 ANALOG BANDWIDTH 25°C V 300 300 300 MHz 1 Tested at fIN = 35 MHz for AD9215-65; fIN = 39 MHz for AD9215-80; and fIN = 50 MHz for AD9215-105. Rev. B | Page 4 of 36

Data Sheet AD9215 Table 3. Digital Specifications AD9215BRU-65/ AD9215BRU-80/ AD9215BRU-105/ AD9215BCP-65 AD9215BCP-80 AD9215BCP-105 Test Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit LOGIC INPUTS (CLK, PDWN) High Level Input Voltage Full IV 2.0 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 0.8 V High Level Input Current Full IV −650 +10 −650 +10 −650 +10 µA Low Level Input Current Full IV −70 +10 −70 +10 −70 +10 µA Input Capacitance Full V 2 2 2 pF LOGIC OUTPUTS1 DRVDD = 2.5 V High Level Output Voltage Full IV 2.45 2.45 2.45 V Low Level Output Voltage Full IV 0.05 0.05 0.05 V 1 Output voltage levels measured with a 5 pF load on each output. Table 4. Switching Specifications AD9215BRU-65/ AD9215BRU-80/ AD9215BRU-105/ AD9215BCP-65 AD9215BCP-80 AD9215BCP-105 Test Unit Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max CLOCK INPUT PARAMETERS Maximum Conversion Rate Full VI 65 80 105 MSPS Minimum Conversion Rate Full V 5 5 5 MSPS CLOCK Period Full V 15.4 12.5 9.5 ns DATA OUTPUT PARAMETERS Output Delay1 (t ) Full VI 2.5 4.8 6.5 2.5 4.8 6.5 2.5 4.8 6.5 ns OD Pipeline Delay (Latency) Full V 5 5 5 Cycles Aperture Delay 25°C V 2.4 2.4 2.4 ns Aperture Uncertainty (Jitter) 25°C V 0.5 0.5 0.5 ps rms Wake-Up Time2 25°C V 7 7 7 ms OUT-OF-RANGE RECOVERY TIME 25°C V 1 1 1 Cycles N+1 N N+2 N+8 N–1 N+3 ANALOG tA INPUT N+4 N+7 N+5 N+6 CLK DATA OUT N–7 N–6 N–5 N–4 N–3 N–2 N–1 N tPD N+1 N+2 02874-A-002 Figure 2. Timing Diagram 1 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 2 Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. Rev. B | Page 5 of 36

AD9215 Data Sheet ABSOLUTE MAXIMUM RATINGS1 Table 5. EXPLANATION OF TEST LEVELS With Test Level Mnemonic Respect to Min Max Unit ELECTRICAL I 100% production tested. AVDD AGND −0.3 +3.9 V DRVDD DRGND −0.3 +3.9 V II 100% production tested at 25°C and sample tested at spec- AGND DRGND −0.3 +0.3 V ified temperatures. AVDD DRVDD −3.9 +3.9 V III Sample tested only. Digital Outputs DRGND −0.3 DRVDD + 0.3 V CLK, MODE AGND −0.3 AVDD + 0.3 V IV Parameter is guaranteed by design and characterization VIN+, VIN− AGND −0.3 AVDD + 0.3 V testing. VREF AGND −0.3 AVDD + 0.3 V SENSE AGND −0.3 AVDD + 0.3 V V Parameter is a typical value only. REFB, REFT AGND −0.3 AVDD + 0.3 V VI 100% production tested at 25°C; guaranteed by design and PDWN AGND −0.3 AVDD + 0.3 V characterization testing for industrial temperature range; ENVIRONMENTAL2 100% production tested at temperature extremes for mili- Operating Temperature −40 +85 °C tary devices. Junction Temperature 150 °C Lead Temperature (10 sec) 300 °C Storage Temperature −65 +150 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances 28-lead TSSOP: θJA = 67.7°C/W, 32-lead LFCSP: θJA = 32.7°C/W; heat sink soldered down to ground plane. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 36

Data Sheet AD9215 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DDVANGAD–NIV+NVINGADDDVATFERBFER 21098765 OR 1 28 D9 (MSB) 33322222 MODE 2 27 D8 DNC 1 24 VREF SENSE 3 26 D7 CLK 2 23 SENSE VREF 4 25 D6 DNC 3 AD9215 22 MODE PDWN 4 21 OR REFB 5 24 DRVDD DNC 5 TOP VIEW 20 D9 (MSB) (Not to Scale) REFT 6 AD9215 23 DRGND DNC 6 19 D8 DNC 7 18 D7 AVDD 7 (NToOt Pto V SIEcaWle)22 D5 DNC 8 17 D6 AGND 8 21 D4 90123456 VIN+ 9 20 D3 1111111 0D1D2D3D4D5DDNDD AVGINND– 1101 1198 DD21 )BSL GRDVRD ( AVDD 12 17 D0 (LSB) NOTES 1. DNC = DO NOT CONNECT. CLK 13 16 DNC 2.IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. THERE IS PDWDNFNiCg14 u=r De O3 .N TOSTS OCPO N(RN1UE5-C2DT8N) C 02874-A-003 ATACHNCUE HSIN TIMECOVARMEXEEDIAMR WSU BEMITOD HTA R HRTEEDHFLR.EiIgAM EuBAXrILeLP IO4CT.AYS L PEOFADCF BPS TIPALH ID(TEC Y SSP OOO-3LFL2D DT-EE7HRR)E E JPDOA TICNOKT TASHG, EAEN IDS 02874-A-004 Table 6. Pin Function Descriptions TSSOP Pin No. LFCSP Pin No. Mnemonic Description 1 21 OR Out-of-Range Indicator. 2 22 MODE Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection. 3 23 SENSE Reference Mode Selection. 4 24 VREF Voltage Reference Input/Output. 5 25 REFB Differential Reference (Negative). 6 26 REFT Differential Reference (Positive). 7, 12 27, 32 AVDD Analog Power Supply. 8, 11 28, 31 AGND Analog Ground. 9 29 VIN+ Analog Input Pin (+). 10 30 VIN− Analog Input Pin (−). 13 2 CLK Clock Input Pin. 14 4 PDWN Power-Down Function Selection (Active High). 15 to 16 1, 3, 5 to 8 DNC Do not connect, recommend floating this pin. 17 to 22, 9 to 14, D0 (LSB) to Data Output Bits. 25 to 28 17 to 20 D9 (MSB) 23 15 DRGND Digital Output Ground. 24 16 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF. N/A 33 EP Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed pad soldered to the customer board. Rev. B | Page 7 of 36

AD9215 Data Sheet EQUIVALENT CIRCUITS AVDD no missing codes to 10-bit resolution indicate that all 1024 codes, respectively, must be present over all operating ranges. Effective Number of Bits (ENOB) MODE For a sine wave, SINAD can be expressed in terms of the num- 02874-A-005 bmeera osfu breit so.f Upseirnfogr tmhea nfoclel oewxpinregs fsoerdm aus lNa,, itth ies pefofesscitbivlee tnou ombbtaeirn o af Figure 5. Equivalent Analog Input Circuit bits AVDD N = (SINAD – 1.76)/6.02 Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly MODE 20kΩ 02874-A-006 Gfroamin iEtsr rmoera sured SINAD. Figure 6. Equivalent MODE Input Circuit The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at DRVDD an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between the first D9–D0, and last code transitions and the ideal difference between the OR 02874-A-007 fInirtset ganradl l Nasot ncolidnee tarraintsyi t(iIoNnLs.) Figure 7. Equivalent Digital Output Circuit INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” AVDD The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 2.6kΩ LSB beyond the last code transition. The deviation is measured CLK from the middle of each particular code to the true straight line. 2.6kΩ 02874-A-008 MThaex cilmocukm ra Cteo antv wehrsiciho np aRraamtee tric testing is performed. Figure 8. Equivalent Digital Input Circuit Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal DEFINITIONS OF SPECIFICATIONS frequency drops by no more than 3 dB below the guaranteed Aperture Delay limit. Aperture delay is a measure of the sample-and-hold amplifier Offset Error (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN−. Zero error is defined as the deviation Aperture Jitter of the actual transition from that point. Aperture jitter is the variation in aperture delay for successive Out-of-Range Recovery Time samples and can be manifested as frequency-dependent noise on the input to the ADC. Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above Clock Pulse Width and Duty Cycle positive full scale to 10% above negative full scale, or from 10% Pulse width high is the minimum amount of time that the clock below negative full scale to 10% below positive full scale. pulse should be left in the Logic 1 state to achieve rated perfor- Output Propagation Delay mance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these speci- The delay between the clock logic threshold and the time when fications define an acceptable clock duty cycle. all bits are within valid logic levels. Differential Nonlinearity (DNL, No Missing Codes) Power Supply Rejection An ideal ADC exhibits code transitions that are exactly 1 LSB The specification shows the maximum change in full scale from apart. DNL is the deviation from this ideal value. Guaranteed the value with the supply at the minimum limit to the value Rev. B | Page 8 of 36

Data Sheet AD9215 with the supply at its maximum limit. Spurious-Free Dynamic Range (SFDR) Signal-to-Noise and Distortion (SINAD) Ratio SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. SINAD is the ratio of the rms value of the measured input sig- nal to the rms sum of all other spectral components below the Temperature Drift Nyquist frequency, including harmonics but excluding dc. The The temperature drift for zero error and gain error specifies the value for SINAD is expressed in decibels. maximum change from the initial (25°C) value to the value at Signal-to-Noise Ratio (SNR) T or T . MIN MAX SNR is the ratio of the rms value of the measured input signal to Total Harmonic Distortion (THD) the rms sum of all other spectral components below the Nyquist THD is the ratio of the rms sum of the first six harmonic com- frequency, excluding the first six harmonics and dc. The value ponents to the rms value of the measured input signal and is for SNR is expressed in decibels. expressed as a percentage or in decibels. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It may be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. B | Page 9 of 36

AD9215 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.0 V, DRVDD = 2.5 V with DCS enabled, T = 25°C, 2 V differential input, A = −0.5 dBFS, VREF = 1.0 V, unless A IN otherwise noted. 0 80 2V p-p SFDR (dBc) AIN =–0.5dBFS AIN =–0.5dBFS SNR = 58.0 –20 ENOB = 9.4 BITS 75 SFDR = 75.5dB S)–40 70 BF 1V p-p SFDR (dBc) d UDE (–60 dB65 T LI P AM–80 60 2V p-p SNR (dB) ––112000 02874-A-062 5550 1V p-p SNR (dB) 02874-A-012 0 6.56 13.13 19.69 26.25 32.81 39.38 45.94 52.50 5 15 25 35 45 55 65 75 85 FREQUENCY (MHz) ENCODE (MSPS) Figure 9. Single-Tone 32k FFT with fIN = 10.3 MHZ, fSAMPLE = 105 MSPS Figure 12. AD9215-80 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz 0 80 AIN =–0.5dBFS 2V p-p SFDR (dBc) AIN =–0.5dBFS SNR = 57.8 –20 ENOB = 9.4 BITS 75 SFDR = 75.0dB S)–40 70 1V p-p SFDR (dBc) F B d DE (–60 dB 65 U T LI P AM–80 60 2V p-p SNR (dB) ––112000 02874-A-063 5550 1V p-p SNR (dB) 02874-A-013 0 6.56 13.13 19.69 26.25 32.81 39.38 45.94 52.50 5 15 25 35 45 55 65 FREQUENCY (MHz) ENCODE (MSPS) Figure 10. Single-Tone 32k FFT with fIN = 70.3 MHz, fSAMPLE = 105 MSPS Figure 13. AD9215-65 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz 0 85 AIN =–0.5dBFS 2V p-p SFDR SNR = 57.7 –20 ENOB = 9.3 BITS 80 SFDR = 75dB S)–40 F 75 B d E ( TUD–60 dB 70 LI P M A–80 65 ––1120000 6.56 13.13 19.69 26.25 32.81 39.38 45.94 52.5002874-A-065 5650 2V p-p SNR 02874-A-066 0 20 40 60 80 100 FREQUENCY (MHz) fSAMPLE (MSPS) Figure 11. Single-Tone 32k FFT with fIN = 100.3 MHz, fSAMPLE = 105 MSPS Figure 14. AD9215-105 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz Rev. B | Page 10 of 36

Data Sheet AD9215 80 80 70 75 60 SFDR 50 80dB REFERENCE LINE 1V p-p SFDR (dBc) 70 dB 40 dB 65 30 2V p-p SNR (dB) 60 20 1V p-p SNR (dB) SNR 100 2V p-p SFDR (dBc) 02874-A-014 5505 02874-A-072 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 0 50 100 150 200 250 300 ANALOG INPUT LEVEL FREQUENCY (MHz) Figure 15. AD9215-80 SNR/SFDR vs. Figure 18. AD9215-105 SNR/SFDR vs. Analog Input Drive Level, fSAMPLE = 80 MSPS, fIN = 39.1 MHz fIN, AIN = −0.5 dBFS, fSAMPLE = 105 MSPS 85 80 80 70 2 SFDR dBc 75 60 70 50 dB 2V p-p SFDR (dBc) dB 40 65 –70dBFS REFERENCE LINE 30 60 1V p-p SFDR (dBc) 2V p-p SNR (dB) 21000–90 –80 –720SVN pR-–p60 –50 –40 1V– 3p0-p SN–R20 –10 0 02874-A-067 55050 50 100 fIN1 (5M0Hz) 200 250 300 02874-A-016 ANALOG INPUT LEVEL (–dBFS) Figure 16. AD9215-105 SNR/SFDR vs. Figure 19. AD9215-80 SNR/SFDR vs. Analog Input Drive Level, fSAMPLE = 105 MSPS, fIN = 50.3 MHz fIN, AIN = −0.5 dBFS, fSAMPLE = 80 MSPS 80 80 1V p-p SFDR (dBc) 70 75 60 80dB REFERENCE LINE 2V p-p SFDR (dBc) 50 2V p-p SNR (dB) 70 dB 40 B d 65 30 1V p-p SNR (dB) 20 60 2V p-p SFDR (dBc) 100–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 02874-A-015 5505 2V p-p SNR (dB) 02874-A-017 ANALOG INPUT LEVEL 0 50 100 150 200 250 300 Figure 17. AD9215-65 SNR/SFDR vs. ANALOG INPUT (MHz) Figure 20. AD9215-65 SNR/SFDR vs. Analog Input Drive Level, fSAMPLE = 65 MSPS, fIN = 30.3 MHz fIN, AIN = −0.5 dBFS, fSAMPLE = 65 MSPS Rev. B | Page 11 of 36

AD9215 Data Sheet 0 AIN1, AIN2 =–7dBFS 80 SFDR = 74dBc –20 70 60 –40 SFDR 50 dB–60 dB 40 80dBFS REFERENCE LINE –80 30 20 ––1120000 13.125 26.250 39.375 52.5002874-A-0600 100 02874-A-073 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 FREQUENCY (MHz) 0 Figurea n2d1. f TINw2 =o- 7To1.n1e M 32Hkz ,F fFSATM wPLiEt =h f1IN015 = M 7S0P.1S MHz, Figure 24. AD9215-801 0Tw1.o3 -MToHnze, SfASFAINDM P(RLdE Bv =sF .S1 A)0IN5, MfINS1 P=S 1 00.3 MHz, and fIN2 = AIN1, AIN2 =–7dBFS 80 SFDR DCS ON SFDR = 74dBc 75 –20 70 SFDR DCS OFF –40 65 SNR DCS ON 60 dB–60 dB 55 50 –80 45 SNR DCS OFF ––1120000 13.125 26.250 39.375 52.5002874-A-0610 343005 02874-A-069 20 30 40 50 60 70 80 FREQUENCY (MHz) Figure 22. Two-Tone 32k FFT with fIN1 = 100.3 MHz, CLOCK DUTY CYCLE HIGH (%) Figure 25. SINAD, SFDR vs. 80 and fIN2 = 101.3 MHz, fSAMPLE = 105 MSPS Clock Duty Cycle, fSAMPLE = 105 MSPS, fIN = 50.3 MH 80 70 2V p-p SFDR (dBc) 75 60 50 70 SFDR dB 40 c 1V p-p SFDR (dBc) B 65 d 80dBFS REFERENCE LINE 30 60 20 2V p-p SINAD 100–65 –55 –45 –35 –25 –15 –502874-A-068 5505 1V p-p SINAD 02874-A-070 AIN1, AIN2 (dBFS) –40 –20 0 20 40 60 80 Figure 23. AD9215-105 Two-Tone SFDR vs. AIN, Figure 26. SINTAEDM,P SEFRDART UvRs.E T e(mC)perature, fIN1 = 70.1 MHz, and fIN2 = 71.1 MHz, fSAMPLE = 105 MSPS fSAMPLE = 105 MSPS, fIN = 50 MHz Rev. B | Page 12 of 36

Data Sheet AD9215 40 0.6 30 0.4 20 C) m/° 10 0.2 p R (p SB) RRO 0 NL (L 0 E I N –10 AI –0.2 G –20 ––4300 02874-A-025 ––00..64 02874-A-074 –40 –20 0 20 40 60 80 0 128 256 384 512 640 768 896 1024 TEMPERATURE (°C) CODE Figure 27. Gain vs. Temperature External 1 V Reference Figure 29. AD9215-105 Typical INL, fSAMPLE = 105 MSPS, fIN = 2.3 MHz 0.5 0.4 0.3 0.2 B) 0.1 S L L ( 0 N D–0.1 –0.2 –0.3 ––00..54 02874-A-064 0 128 256 384 512 640 768 896 1024 CODE Figure 28. AD9215-105 Typical DNL, fSAMPLE = 105 MSPS, fIN = 2.3 MHz Rev. B | Page 13 of 36

AD9215 Data Sheet APPLYING THE AD9215 THEORY OF OPERATION placed across the inputs to provide dynamic charging currents. The AD9215 architecture consists of a front-end SHA followed This passive network creates a low-pass filter at the ADC’s in- by a pipelined switched capacitor ADC. Each stage provides put; therefore, the precise values are dependent upon the appli- sufficient overlap to correct for flash errors in the preceding cation. In IF undersampling applications, any shunt capacitors stages. The quantized outputs from each stage are combined should be removed. In combination with the driving source into a final 10-bit result in the digital correction logic. The pipe- impedance, they would limit the input bandwidth. lined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding The analog inputs of the AD9215 are not internally dc biased. samples. Sampling occurs on the rising edge of the clock. In ac-coupled applications, the user must provide this bias ex- ternally. V = AVDD/2 is recommended for optimum perfor- The input stage contains a differential SHA that can be config- CM mance, but the device functions over a wider range with rea- ured as ac-coupled or dc-coupled in differential or single-ended sonable performance (see Figure 31). modes. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor 85 DAC and interstage residue amplifier (MDAC). The residue 80 2V p-p SFDR amplifier magnifies the difference between the reconstructed 75 DAC output and the flash input for the next stage in the pipe- line. Redundancy is used in each one of the stages to facilitate 70 digital correction of flash errors. 65 B d The output-staging block aligns the data, carries out the error 60 2V p-p SNR correction, and passes the data to the output buffers. The output 55 buffers are powered from a separate supply, allowing adjust- 50 ment of the output voltage swing. During power-down, the oAuntapluot gb uInffperust g aon idn tRoe af ehrigehn cime pOevdearnvciee swta te. 4405 02874-A-071 0.25 0.75 1.25 1.75 2.25 2.75 The analog input to the AD9215 is a differential switched ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage capacitor SHA that has been designed for optimum perfor- For best dynamic performance, the source impedances driving mance while processing a differential input signal. The SHA VIN+ and VIN− should be matched such that common-mode input can support a wide common-mode range and maintain settling errors are symmetrical. These errors are reduced by the excellent performance, as shown in Figure 31. An input com- common-mode rejection of the ADC. mon-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. An internal differential reference buffer creates positive and H negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of T T the reference buffer is set to midsupply, and the REFT and 0.5pF VIN+ REFB voltages and span are defined as CPAR REFT = 1/2 (AVDD + VREF) T REFB = 1/2 (AVDD − VREF) 0.5pF VIN– CPAR T 02874-A-028 It can be sSepeann f r=o 2m × t h(Re EeqFuTa −ti oRnEsF aBb)o =ve 2 t h×a Vt tRhEeF R EFT and H REFB voltages are symmetrical about the midsupply voltage Figure 30. Switched-Capacitor SHA Input and, by definition, the input span is twice the value of the VREF The clock signal alternatively switches the SHA between sample voltage. mode and hold mode (see Figure 30). When the SHA is The internal voltage reference can be pin-strapped to fixed val- switched into sample mode, the signal source must be capable ues of 0.5 V or 1.0 V or adjusted within the same range as dis- of charging the sample capacitors and settling within one-half cussed in the Internal Reference Connection section. Maximum of a clock cycle. A small resistor in series with each input can SNR performance is achieved with the AD9215 set to the largest help reduce the peak transient current required from the output input span of 2 V p-p. The relative SNR degradation is 3 dB stage of the driving source. Also, a small shunt capacitor can be Rev. B | Page 14 of 36

Data Sheet AD9215 when changing from 2 V p-p mode to 1 V p-p mode. AVDD R VIN+ The SHA may be driven from a source that keeps the signal C peaks within the allowable range for the selected reference volt- 2Vp-p 49.9Ω AD9215 aargee .d Tefhien emdi nasim um and maximum common-mode input levels 1kΩ AVDD R C VINA–GND 02874-A-031 VCM = VREF/2 1kΩ MIN 0.1µF VCM = (AVDD + VREF)/2 MAX Figure 33. Differential Transformer-Coupled Configuration The minimum common-mode input level allows the AD9215 to The signal characteristics must be considered when selecting a accommodate ground-referenced inputs. transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause Although optimum performance is achieved with a differential core saturation, which leads to distortion. input, a single-ended source may be driven into VIN+ or VIN−. Single-Ended Input Configuration In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an A single-ended input may provide adequate performance in appropriate reference. For example, a 2 V p-p signal may be cost-sensitive applications. In this configuration, there is a deg- applied to VIN+ while a 1 V reference is applied to VIN−. The radation in SFDR and distortion performance due to the large AD9215 then accepts a signal varying between 2 V and 0 V. In input common-mode swing. However, if the source impedances the single-ended configuration, distortion performance may on each input are kept matched, there should be little effect on degrade significantly as compared to the differential case. How- SNR performance. Figure 34 details a typical single-ended input ever, the effect is less noticeable at lower input frequencies. configuration. Differential Input Configurations 10µF As previously detailed, optimum performance is achieved while 1kΩ R AVDD driving the AD9215 in a differential input configuration. For VIN+ 2V p-p 49.9Ω 0.1µF 1kΩ C baseband applications, the AD8138 differential driver provides AD9215 excellent performance and a flexible interface to the ADC. The oAuVtDpuDt/ c2o, manmd othne-m droidvee rv coaltna gbee ocfo tnhfeig AurDe8d1 i3n8 a i sS aelalseinly K seeyt tfoil ter 11kkΩΩ AVDD 10µF 0.1µF RC VINA–GND 02874-A-032 topology to provide band limiting of the input signal. Figure 34. Single-Ended Input Configuration 1kΩ CLOCK INPUT AND CONSIDERATIONS 499Ω AVDD 0.1µF 1kΩ 523Ω R VIN+ Typical high speed ADCs use both clock edges to generate a C variety of internal timing signals, and as a result may be sensi- AD8138 AD9215 VCM tive to clock duty cycle. Commonly, a 5% tolerance is required R 1V p-p 49.9Ω 499Ω 499Ω C VIN–AGND 02874-A-030 oathcnat ett hrriees ttciimclosc.e ksT thdheue tA yn Docny9cs2la1em5 t opc lominnagtai neindtasgi ean, cdplyoroncvkaim ddiuinctg yp acenryfc oilnertm setraannbacille icz cleohrca kr- Figure 32. Differential Input Configuration Using the AD8138 signal with a nominal 50% duty cycle. This allows a wide range At input frequencies in the second Nyquist zone and above, the of clock input duty cycles without affecting the performance of performance of most amplifiers is not adequate to achieve the the AD9215. As shown in Figure 25, noise and distortion per- true performance of the AD9215. This is especially true in IF formance are nearly flat over a 50% range of duty cycle. For best undersampling applications where frequencies in the 70 MHz to ac performance, enabling the duty cycle stabilizer is recom- 200 MHz range are being sampled. For these applications, differ- mended for all applications. ential transformer coupling is the recommended input configura- tion. The value of the shunt capacitor is dependant on the input The duty cycle stabilizer uses a delay-locked loop (DLL) to cre- frequency and source impedance and should be reduced or re- ate the nonsampling edge. As a result, any changes to the sam- moved. An example of this is shown in Figure 33. pling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. Rev. B | Page 15 of 36

AD9215 Data Sheet Table 7. Reference Configuration Summary External SENSE Internal Op Amp Resulting VREF Resulting Differential Span Selected Mode Connection Configuration (V) (V p-p) Externally Supplied Reference AVDD N/A N/A 2 × External Reference Internal 0.5 V Reference VREF Voltage Follower (G = 1) 0.5 1.0 Programmed Variable External Divider Noninverting (1 < G < 2) 0.5 × (1 + R2/R1) 2 × VREF Reference Internally Programmed 1 V AGND to 0.2 V Internal Divider 1.0 2.0 Reference Table 8. Digital Output Coding Code VIN+ − VIN− Input Span = VIN+ − VIN− Input Span = Digital Output Offset Binary Digital Output Twos 2 V p-p (V) 1 V p-p (V) (D9••••••D0) Complement (D9••••••D0) 1023 1.000 0.500 11 1111 1111 01 1111 1111 512 0 0 10 0000 0000 00 0000 0000 511 −0.00195 −0.000978 01 1111 1111 11 1111 1111 0 −1.00 −0.5000 00 0000 0000 10 0000 0000 number of output bits switching, which are determined by the High speed, high resolution ADCs are sensitive to the quality encode rate and the characteristics of the analog input signal. of the clock input. The degradation in SNR at a given full-scale input frequency (f ) due only to aperture jitter (t ) can be INPUT A Digital power consumption can be minimized by reducing the calculated with the following equation capacitive load presented to the output drivers. The data in Fig- ure 35 was taken with a 5 pF load on each output driver. SNR Degradation = 20 × log [2 × π × f × t ] 10 INPUT A 40 15 In the equation, the rms aperture jitter, tA, represents the root- AD9215-105 IAVDD 13 sum square of all jitter sources, which include the clock input, 35 analog input signal, and ADC aperture jitter specification. AD9215-65/80 IAVDD 11 Undersampling applications are particularly sensitive to jitter. 9 A) 30 TwAhhDee9 rc2el1 oa5cp.k eP riontuwprueert j sisthuteoprup mlldie asby ef oa tfrrf eecaclotte ctdkh ead sdr iayvnne arasmn saihcloo rgua lsndigg ben eao lsf eitnph aecr aasteesd I (mAVDD 25 57 IDRVDD from the ADC output driver supplies to avoid modulating the 3 clock signal with digital noise. Low jitter, crystal-controlled 20 ofrsocmill aatnoorsth mera ktyep teh oe fb seosut rccloe c(kb ys oguartcinegs., Idfi vthidei cnlgo,c okr i so tgheenre rated 15 IDRVDD –11 02874-A-075 methods), it should be retimed by the original clock at the last 5 15 25 35 45 55 65 75 85 95 105 step. fSAMPLE (MSPS) Figure 35. Supply Current vs. fSAMPLE for fIN = 10.3 MHz Power Dissipation and Standby Mode The analog circuitry is optimally biased so that each speed As shown in Figure 35, the power dissipated by the AD9215 is grade provides excellent performance while affording reduced proportional to its sample rate. The digital power dissipation power consumption. Each speed grade dissipates a baseline does not vary substantially between the three speed grades power at low sample rates that increases linearly with the clock because it is determined primarily by the strength of the digital frequency. drivers and the load on each output bit. The maximum DRVDD By asserting the PDWN pin high, the AD9215 is placed in current can be calculated as standby mode. In this state, the ADC typically dissipates 1 mW IDRVDD = VDRVDD × CLOAD × fCLOCK × N if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting where N is the number of output bits, 10 in the case of the the PDWN pin low returns the AD9215 into its normal opera- AD9215. This maximum current is for the condition of every tional mode. output bit switching on every clock cycle, which can only occur for a full-scale square wave at the Nyquist frequency, fCLOCK/2. In In standby mode, low power dissipation is achieved by shutting practice, the DRVDD current is established by the average down the reference, reference buffer, and biasing networks. The Rev. B | Page 16 of 36

Data Sheet AD9215 decoupling capacitors on REFT and REFB are discharged when  R2 VREF0.51  entering standby mode and then must be recharged when  R1 returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby VIN+ cycles result in proportionally shorter wake-up times. With the VIN– recommended 0.1 μF and 10 μF decoupling capacitors on REFT REFT and REFB, it takes approximately one second to fully discharge 0.1F ADC the reference buffer decoupling capacitors and 7 ms to restore CORE 0.1F 10F full operation. REFB Digital Outputs 0.1F VREF The AD9215 output drivers can be configured to interface with 10F+ 0.1F 7k 0.5V 2.5 V or 3.3 V logic families by matching DRVDD to the digital SELECT LOGIC supply of the interfaced logic. The output drivers are sized to SENSE provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. 7k Aorp lpalrigcea tfiaonnosu rtesq muiaryin rge qthueir Ae DexCte tron adlr bivuef flearrsg eo rc alaptacchietisv. e loads AD9215 02874-A-034 Figure 36. Internal Reference Configuration Timing In all reference configurations, REFT and REFB drive the ADC The AD9215 provides latched data outputs with a pipeline delay conversion core and establish its input span. The input range of of five clock cycles. Data outputs are available one propagation the ADC always equals twice the voltage at the reference pin for delay (tOD) after the rising edge of the clock signal. Refer to Fig- either an internal or an external reference. ure 2 for a detailed timing diagram. The length of the output data lines and loads placed on them VIN+ should be minimized to reduce transients within the AD9215; VIN– REFT these transients can detract from the converter’s dynamic per- 0.1F formance. CAODRCE 0.1F 10F REFB The lowest typical conversion rate of the AD9215 is 5 MSPS. At 0.1F clock rates below 5 MSPS, dynamic performance may degrade. VREF + Voltage Reference 10F 0.1F R2 0.5V SELECT LOGIC A stable and accurate 0.5 V voltage reference is built into the SENSE AD9215. The input range can be adjusted by varying the refer- ence voltage applied to the AD9215, using either the internal R1 reference or an externally applied reference voltage. The input simpaunm o fS NthRe AanDdC D tNraLc kpse rrefoferrmenacnec ev oisl taacghei cehveadn gweist hli ntheaer AlyD. M92a1x5- AD9215 02874-A-035 Figure 37. Programmable Reference Configuration set to the largest input span of 2 V p-p. If the internal reference of the AD9215 is used to drive multiple Internal Reference Connection converters to improve gain matching, the loading of the refer- A comparator within the AD9215 detects the potential at the ence by the other converters must be considered. Figure 38 de- SENSE pin and configures the reference into four possible picts how the internal reference voltage is affected by loading. states, which are summarized in Table 1. If SENSE is grounded, the reference amplifier switch is connected to the internal resis- tor divider (see Figure 36), setting VREF to 1 V. Connecting the SENSE pin to the VREF pin switches the amplifier output to the SENSE pin, configuring the internal op amp circuit as a voltage follower and providing a 0.5 V reference output. If an external resistor divider is connected as shown in Figure 37, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as Rev. B | Page 17 of 36

AD9215 Data Sheet 0.05 Operational Mode Selection As discussed earlier, the AD9215 can output data in either offset 0 binary or twos complement format. There is also a provision for VREF = 0.5V enabling or disabling the clock duty cycle stabilizer (DCS). The R (%) –0.05 MODE pin is a multilevel input that controls the data format O and DCS state. For best ac performance, enabling the duty cycle R R –0.10 E stabilizer is recommended for all applications. The input F E VREF = 1.0V R threshold values and corresponding mode selections are out- V –0.15 lined in Table 9. ––00..2250 02874-A-036 oAfsf sdeet tbaiinleadr yin o Tr atwbloes 9 c, othmep dleamtae fnotr.m at can be selected for either 0 0.5 1.0 1.5 2.0 2.5 3.0 Table 9. Mode Selection ILOAD (mA) MODE Voltage Data Format Duty Cycle Stabilizer Figure 38. VREF Accuracy vs. Load AVDD Twos Complement Disabled External Reference Operation 2/3 AVDD Twos Complement Enabled The use of an external reference may be necessary to enhance 1/3 AVDD Offset Binary Enabled the gain accuracy of the ADC or improve thermal drift charac- AGND (Default) Offset Binary Disabled teristics. When multiple ADCs track one another, a single refer- The MODE pin is internally pulled down to AGND by a 20 kΩ ence (internal or external) may be necessary to reduce gain resistor. matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset EVALUATION BOARD temperature drift. Figure 39 shows the typical drift characteris- The AD9215 evaluation board is no longer in production. The tics of the internal reference in both 1 V and 0.5 V modes. following evaluation board documentation is provided for in- 0.6 formational purposes only. The AD9215 evaluation board provides all of the support cir- 0.5 cuitry required to operate the ADC in its various modes and VREF = 0.5V configurations. The converter can be driven differentially %)0.4 R ( through an AD8351 driver, a transformer, or single-ended. Sep- O R arate power pins are provided to isolate the DUT from the sup- R0.3 E F VREF = 1.0V port circuitry. Each input configuration can be selected by E R V0.2 proper connection of various jumpers (refer to the schematics). Figure 40 shows the typical bench characterization setup used 0.10 02874-A-037 tsuoisg eendva alt losu orauetear cltiehzsee w tahicte hp u evlrtefiromyr maloteaw np cpeehr faoosfr emt hnaeon AisceDe (o9<f2 11t h5pe.s Icrtom inss vc ejrirtitttieecrra.) l P btreho apt- –40 –20 0 20 40 60 80 TEMPERATURE (°C) er filtering of the input signal, to remove harmonics and lower Figure 39. Typical VREF Drift the integrated noise at the input, is also necessary to achieve the When the SENSE pin is tied to AVDD, the internal reference is specified noise performance. disabled, allowing the use of an external reference. An internal Complete schematics and layout plots follow that demonstrate reference buffer loads the external reference with an equivalent the proper routing and grounding techniques that should be 7 kΩ load. The internal buffer still generates the positive and applied at the system level. negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. 3.0V 2.5V 2.5V 5.0V – + – + – + – + AVDDGNDDRVDDGND VDL VAMP REFIN SRIG ANNADL SS YSNMTGH, E2SVI ZpE-pR BAFNILDT-PEARSS XINFPMURT DATA 1R0EMFHOzUT SRIG ANNADL SS YSNMTGH, E2SVI ZpE-pR CLK EVALAUADT9IO2N1 5BOARD P12 PRCOACAPENTSUDSRIENG 02874-A-038 Figure 40. Evaluation Board Connections Rev. B | Page 18 of 36

Data Sheet AD9215 LE6 LE6 LE6 LE6 ORXD13X D12XD11XD10XD9X D8XD7X D6XD5X D4XD3XD2XD1X D0X O O O O H H H H H1MT H2MT H3MT H4MT 16 1514131211 109 16 1514131211 109 D Ω Ω GN P2 220 P1 220 AULT) R R F 1234562P LDDDPDDMNNDDVGGVVAARVD VVVV0550....3225 OVERRANGE BIT (MSB)1 23456 78DRVDDGND 1 234(LSB)56 78 SENSE PIN SOLDERABLE JUMPER:E TO A: EXTERNAL VOLTAGE DIVIDERE TO B: INTERNAL 1V REFERENCE (DEE TO C: EXTERNAL REFERENCEE TO D: INTERNAL 0.5V REFERENCE MODE PIN SOLDERABLE JUMPER:5 TO 1: TWOS COMPLEMENT/DCS OFF5 TO 2: TWOS COMPLEMENT/DCS ON5 TO 3: OFFSET BINARY/DCS ON5 TO 4: OFFSET BINARY/DCS OFF 16 15 14131211 109 C8µ0.1F D 987111 876DDD DRVDDDGND15D5D4D3D2 D1D0 CCCNNNDDD 678 R8Ω1k GND GN 1022 R9OD AD92U4 NWCNDDP 45 P13 MODE2P5 342222 FEEESDRNOVEMS REFBREFTAVDD AGNDVIN+VIN– AGNDAVDD CCKNNLDCD 123 CLK P14 AVDD D 2526 27282930 3132 GN 1P6 R5Ω1k 2P1 R7Ω1k 3P3 R6Ω1k 4P4 D AVDDGNDVIN+VIN– GNDAVDD R25Ω1k N D G AVDD C22µ10F D GN R26Ω1k C21ELECT GND R L1OR FILTER GND C23ELECT R13Ω1k GN S OF S DD V EXTREF1V MAX E1 AVDDC13GNDµ0.10FP11R1P9P8Ω10kP7ABCD EGND P10 R9C12Ωµ10k0.1F C9µ0.10FGNDGNDC11C29µµ0.1F10F GND C7µ0.1F GND R42C6Ω0µ0.1FAVDDR36Ω1k�AMPIN R12Ω0 R4XOUTΩ33 T1R10ADT1–1WTJ1L1 100C26Ω3661XFRIN110pFE 4525CTC15GNDNCC19µ430.1FAMPGNDC1610pFR2GNDµ0.1FXXPRISECC5GNDµ0.1FR11ΩGND36OPTIONAL XFRT2BXOUTFT C1–1–1351R3XX FRINOUTΩ20CT34AMPINBR15GNDBXOUTΩ33PRISECC18µ0.10FR18AR SINGLE ENDEDΩ25R3, R17, R18ONLY ONE SHOULD BEON BOARD AT A TIMEGND 02874-A-039 Figure 41. LFCSP Evaluation Board Schematic, Analog Inputs and DUT Rev. B | Page 19 of 36

AD9215 Data Sheet D N G 1 35 7 91 3 5 7 91 35 79 1 35 7 9 1 11 1 12 2 2 2 23 33 33 1 35 7 9 1 35 7 91 3 5 7 91 3 57 9 1 11 1 12 2 2 2 23 3 33 3 0 4 R E D 12EA PH 2 46 8 0 2 46 8 02 4 6 8 02 4 68 0 1 1 11 1 22 2 2 2 33 3 33 4 2 4 6 810 121416 18 2022 24 26 28 3032 34 36 38 40 AMPINB AMPIN D N F F ND DR ND DRY G C27µ0.1 C17µ0.1 G G B S M 16Ω 17Ω D D R0 R0 N N G G D GN C24µ10F C45µ0.1F 4Ω MP R125 R39Ω1k VA D N G R38Ω1k C44µ0.1F 10 VOCM 9 VPOS8 OPHI 7 OPLO 6 COMM Y R 1 D P 5 Ω VAM ND U3D83 R341.2k G A GND GND DRVDD GND GND DRVDD GND GND PWDN 1 RGP1 2 INHI 3 INLO 4 RPG2 5 3Ω R325 Ω 24 2322 21 20 19 1817 16 1514 13 12 11 109 8 76 5 4 3 21 WNR41 ND R4010k U174LVTH162374 2CLK2OE 2DB2QB 2D72Q7GNDGND2D62Q6 2D52Q5VVCCCC2D42Q4 2D32Q3 GNDGND 2D22Q2 2D12Q11Q81D8 1D71Q7 GNDGND1D61Q61D51Q5VVCCCC1Q41D4 1Q31D3GNDGND1D21Q21D11Q11CLK 11OE NOUT POWER DOUSE R40 OR GVAMP R41Ω10k C28µ0.1F C35µ0.10F R35Ω25 GND I D 25 26 27 2829 30 3132 33 3435 36 37 38 3940 41 4243 44 45 46 4748 MP IN MP R19Ω50 GN CLKAT/DAC DRXD13X GNDD12X D11X RVDD D10XD9X GNDD8X D7XD6X D5X GND D4XD3X RVDDD2XD1X GNDD0X CLKLAT/DAC A A MSB D D LSB 02874-A-040 Figure 42. LFCSP Evaluation Board, Digital Path Rev. B | Page 20 of 36

Data Sheet AD9215 C40µ1F 0 0 0. C37µ1F C46µ10F 0. C20µ10F VAMP GND R22Ω0 L D D N V F G µ C490.001 DR C48C38C1C47C39µ0.001Fµµµµ0.001F0.1F0.1F0.001F LATCH BYPASSING SCHEMATIC SHOWS TWO-GATE DELAY SETUP.FOR ONE DELAY REMOVE R22 AND R37ΩATTACH Rx (Rx = 0) R23RxΩ0R37CLKLAT/DACDNPΩ25 C36µ0.1F ENCX GND VDL C34µ0.1F 367 8D11 14R N W G P C31µ0.1F CX86 1Y 2Y 3Y 4Y U5 SING 74V C30µ0.001F L BYPAS 1A12B14A2B259A310B312A413B4 A C2µF GIT 22 DI DRVDD C41µ0.1F GND R32Ω1k ND 53 R20Ω1kGND R21Ω1k GND R24Ω1k GND G E 5 4 3 4 DDAVDDAVDD C32C33C14C25µµC3µµ0.001F0.1F0.001F10Fµ10F GNDGNDSINGANALOG BYPASSING CLOCK TIMING ADJUSTMENTSFOR A BUFFERED ENCODE USE R28FOR A DIRECT ENCODE USE R27 CLKR28Ω0ENCX ENCENCE51E50R27Ω0 VDL VDLE52 VDLR31C43Ω1kµ0.1FENCODE J2 R30R29E31EΩΩ1k50 GNDGNDVDLGNDE43E VDL V S DRVDL C4C10µ10Fµ22F DUT BYPA 02874-A-041 Figure 43. LFCSP Evaluation Board Schematic, Clock Input Rev. B | Page 21 of 36

AD9215 Data Sheet 02874-A-042 02874-A-043 Figure 44. LFCSP Evaluation Board Layout, Primary Side Figure 45. LFCSP Evaluation Board Layout, Secondary Side Rev. B | Page 22 of 36

Data Sheet AD9215 02874-A-044 02874-A-045 Figure 46. LFCSP Evaluation Board Layout, Ground Plane Figure 47. LFCSP Evaluation Board Layout, Power Plane Rev. B | Page 23 of 36

AD9215 Data Sheet 02874-A-046 02874-A-047 Figure 48. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 49. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev. B | Page 24 of 36

Data Sheet AD9215 Table 10. LFCSP Evaluation Board Bill of Materials (BOM) Recommended Vendor/ Item Qty Omit1 Reference Designator Device Package Value Part Number 1 18 C1, C5, C7, C8, C9, C11, Chip Capacitor 0603 0.1 μF C12, C13, C15, C16, C31, C33, C34, C36, C37, C41, C43, C47 8 C6, C18, C27, C17, C28, C35, C45, C44 2 8 C2, C3, C4, C10, Tantalum Capacitor TAJD 10 μF C20, C22, C25, C29 2 C46, C24, 3 8 C14, C30, C32, C38, Chip Capacitor 0603 0.001 C39 C40, C48, C49 μF 4 1 C19 Chip Capacitor 0603 10 pF 2 C21, C23 5 1 C26 Chip Capacitor 0603 10 pF 6 9 E31, E35, E43, E44, Header EHOLE Jumper Blocks E50, E51, E52, E53 2 E1, E45 7 2 J1, J2 SMA Connector/50 Ω SMA 8 1 L1 Inductor 0603 10 nH Coilcraft/0603CS- 10NXGBU 9 1 P2 Terminal Block TB6 Wieland/25.602.2653.0 z5-530-0625-0 10 1 P12 Header Dual 20-Pin RT HEADER40 Digi-Key S2131-20-ND Angle 11 5 R3, R12, R23, R18, RX Chip Resistor 0603 0 Ω 6 R37, R22, R42, R16, R17, R27 12 2 R4, R15 Chip Resistor 0603 33 Ω 13 14 R5, R6, R7, R8, R13, R20, R21, R24, Chip Resistor 0603 1 Ω R25, R26, R30, R31, R32, R36 14 2 R10, R11 Chip Resistor 0603 36 Ω 15 1 R29 Chip Resistor 0603 50 Ω 1 R19 16 2 RP1, RR2 Resistor Pack R_742 220 Ω Digi-Key CTS/742C163220JTR 17 1 T1 ADT1-1WT AWT1-T1 Mini-Circuits 18 1 U1 74LVTH162374 CMOS TSSOP-48 Register 19 1 U4 AD9215BCP ADC (DUT) CSP-32 Analog Devices, Inc. 20 1 U5 74VCX86M SOIC-14 Fairchild 21 1 PCB AD9XXBCP/PCB PCB Analog Devices, Inc. 22 1 U3 AD8351 Op Amp MSOP-8 Analog Devices, Inc. 23 1 T2 MACOM Transformer ETC1-1-13 1-1 TX MACOM/ETC1-1-13 24 5 R9, R1, R2, R38, R39 Chip Resistor 0603 Select 25 3 R18, R14, R35 Chip Resistor 0603 25 Ω 26 2 R40, R41 Chip Resistor 0603 10 kΩ 27 1 R34 Chip Resistor 1.2 kΩ 28 1 R33 Chip Resistor 110 Ω 1 These items are included in the PCB design but are omitted at assembly. Rev. B | Page 25 of 36

AD9215 Data Sheet 2P 4 PMAV V0.5 ORXD9XD8XD7XD6XD5X D4XD3XD2XD1XD0XNCXNC2X 840-A-47820 LDV 3 V0.3 DNG 161514131211109 161514131211109 2   1 KLCV V0.3 220 220 P2 P1 R R 4 DNG 12345678 12345678 DDVRD V5.2 3 D 2 DNG RVDND 1 DDVA V0.3 DG MODE SELECT CONFIGURATIONE:2C/DCS OFFREFERENCE CONFIGURATIONF:2C/DCS ONA: EXTERNAL VOLTAGE DIVIDER REFERENCEG:OB/DCS ONB: INTERNAL 1V REFERENCEH:OB/DCS OFFC: EXTERNAL REFERENCEVREFD: INTERNAL 0.5V REFERENCE 1V MAXMODE SELECTDRVDD 648E6E7222AVDDEEEEC30+C520.1F10FOPTIONAL7952R822ER4EEGNDAVDD1k10kGNDGNDVDLVCLKAVDDE1E518262121FEEEEC18R150.1FCDBA10kR101k0397C152211EEEE0.1FSENSEE3E2GNDGNDGNDG GNDR9C161kSINGLE-ENDED INPUT OPERATION0.1FE4E8GND1. PLACE R7( 50), R5( 0) AND R46 (25)C29OVERRANGE BITHC172. PLACE C23 (0.1F), C9 (0.1F)10F+0.1F3. REMOVE C33, C1, R34, R6, C32OR1C13(MSB)0.1FGND128ORD9227MODED8326SENSED7R44R45R5C9425AVDD1k1kVREFD600.1FGND524DIFFERENTIALREFBDRVDDAMPININPUT623R6REFTDRGND0722AVDDD5AVDD821R19AGNDD4GNDAINAMP33C8920R33VIN+D310pFC32C7J1L1361019VIN–D20.1F0.001FSECPRI10nHR16GNDC111118AINAGNDD1GNDGNDXXCOM0.1F16GND1217AVDDD0AVDD52GND13E45E1216R7CLKDNC34C5GNDT150C6141510pFPWDNDNCR21R320.1F33GND36OPTIONAL(LSB)GNDDEVICE = AD9215U1R34GNDAVDDPARTS = 10R29R24AVDD1k1kCLKC23AMPINR110.1F1kR110R25ANALOG INPUT OPTIONSOPTIONAL25GND1. R6, R34 FOR DIFFERENTIAL OPERATION2. C1, C33 FOR OP AMP OPERATION3. R7, R46, R5, C9, C23 FOR SINGLE-ENDED OPERATIONE32GNDE11E9R3C14C12AVDD5k0.1F0.1FCOMMON MODEPLEASE JUMPER E45 TO E32 DC VOLTAGE ADJUSTOR JUMPER E45 TO E12 CAPACITOR TO GROUNDGNDGNDGND Figure 50. TSSOPP Evaluation Board Schematic, Analog Inputs and DUT Rev. B | Page 26 of 36

Data Sheet AD9215 D 940-A-47820 N G 97531975319753197531 333332222211111PPPPP PPPPPPPPPPPPPPP U2 PIN PIN M M 403836343230282624222018161412108642 A A PPPPPPPPPPPPPPPPPPPP D NDRXND D GN ND C33µ0.1F C1µ0.1F GDG GN LY G B B M MS OUT OF RANGE BITSTRAP THIS AT ASSE E30 E14 VAMP C47µ10F +GNDC42µ0.1F GND C43R28µ0.001FΩ0 R17Ω0 R27Ω0 GND E13 C41µ0.1F P R49R48ΩΩ1k1k 10VOCMPWUP9VPOSRGP18INHIOPHI7OPLOINLO6RGP2COMM U6DEVICE = AD8351 R30Ω1.2k M 12345 A V P M A 7Ω 161514131211109 161514131211109 VD R410k N G 2Ω RP3Ω220 RP4Ω220 R210k R31Ω100 0Ω 1Ω 12345678 12345678 DAC R525 R525 T/ T/DAC VDL CLKLA GND C44µ0.1F C45µ0.1F A CLKL C3110pF ND VDL GND VDLGNDGND R20Ω150 R23Ω100 AMP R36Ω25 G U474LVT574DEVICE = 74LVT574A 201VCCOE219Y0X0318Y1X1417Y2X2516Y3X3615Y4X4714Y5X5813Y6X6912Y7X71110CPGND U374LVT574DEVICE = 74LVT574A 201VCCOE192Y0X0183Y1X1174Y2X2165Y3X3156Y4X4147Y5X5138Y6X6129Y7X71110CPGND D N G DDDXXXXXXD ORXD9XD8XD7XD6XD5XD4XGNDGND GNGNGND3D2BD1D0NCNC2GN B S S L M Figure 51. TSSOP Evaluation Board, Digital Path Rev. B | Page 27 of 36

AD9215 Data Sheet 52 050-A-47820 R UPOR ETST SSI AY RE LE E DEMOVR18 DRVDD C51C46C21C190.1F0.1F0.1F0.001F GNDDUT DRVDD BYPASSING C39F0.001F ENCX SCHEMATIC SHOWS 1-GATU5FOR TWO-GATE DELAY REVCX86ADD RESISTORS R38 AND 31Y67R252YGND08GNDCLKLAT/DAC113YDRX14R18VCLK0PWR4Y R380R520 DRX EXTERNAL DATA READYOPTIONAL J4C28DRX0.1FR1450 GNDGND D F C360.1 G 74 1A 1B 2A 2B 3A 3B 4A 4B AVD C490.001 C2010F YPASSIN CLK 12459101213 D C350.001F GND LK + NDU5 B E510 R431k GN C340.1F SING VC C380.001F G R370 R350 E5 2 DVCLK C48C500.1F10F AVDD BYPAS C37F0.001F ENCX ENC E52E53 R1k VCLKGN VCLKVDLDRVDDAVDD +++++C2C10C4C322F22F10F22F GNDGNDDUT BYPASSING VDL ++C27C25C24C2610F10F0.1F0.1 GNDU3/U4 BYPASSING ENCODE FROM XORFOR A BUFFERED ENCODE USE R37FOR A DIRECT ENCODE USE R35 ENCAVDD R42C401kENCODE0.1F J3 R40R41501k GNDGNDGND E36E35E44E43 R39R261k1k GNDVCLKGNDVCLK Figure 52. TSSOP Evaluation Board Schematic, Clock Input Rev. B | Page 28 of 36

Data Sheet AD9215 02874-A-051 02874-A-053 Figure 53. TSSOP Evaluation Board Layout, Primary Side Figure 55. TSSOP Evaluation Board Layout, Ground Plane 02874-A-052 02874-A-054 Figure 54. TSSOP Evaluation Board Layout, Secondary Side Figure 56. TSSOP Evaluation Board Layout, Power Plane Rev. B | Page 29 of 36

AD9215 Data Sheet 02874-A-055 02874-A-056 Figure 57. TSSOP Evaluation Board Layout, Primary Silkscreen Figure 58. TSSOP Evaluation Board Layout, Secondary Silkscreen Rev. B | Page 30 of 36

Data Sheet AD9215 Table 11. TSSOP Evaluation Board Bill of Materials (BOM) Recommended Item Qty. Omit Reference Designator Device Package Value Vendor/Part No. 1 11 C2 to C4, C10, C20, Tantalum Capacitor TAJD 10 μF C25, C27, C29, C47, C50, C52 C47 2 2 C5,C8 Chip Capacitor 0603 10 pF 1 C31 3 15 C6, C9, C13, Chip Capacitor 0603 0.1 μF C15 to C18, C21, C24, C26, C30, C32, C34, C36, C40, C46, C48, C51 4 3 C12, C14, C23, C28 Chip Capacitor 0603 Select 5 8 C7, C19, C35, C19, Chip Capacitor 0603 0.001 μF C37 to C39, C49 6 6 C1,C33, C41 to C42, BCAP0402 0402 0.1 μF C44 to C5 7 1 C43 BCAP0402 0402 0.001 μF 8 1 C11 BCAP0603 0603 Select 9 11 R2, R8 to R11, R24, BRES603 0603A 1 kΩ R26, R29, R39, R41 to R45 2 R48, R49 10 4 R6, R25, R34, R37 BRES603 0603A 0 Ω 8 R5, R35, R17 to R18, R27 to R28, R38, R52 11 2 R7, R40 BRES603 0603A 50 Ω 1 R14 12 2 R19, R21 BRES603 0603A 33 Ω 13 2 R32, R33 RES0603 0603A 36 Ω 14 1 R16 BRES603 0603 Select 15 2 R4, R15, BRES603 0603 10 kΩ 16 4 R20, R22 to R23, R47 BRES603 0603A Select 17 2 R48, R49 BRES603 0603 1 kΩ 18 4 R36, R46, R50 to R51 BRES603 0603 25 Ω 19 1 R31 BRES603 0603 100 Ω 20 1 R30 BRES603 0603 1.2 kΩ 21 1 R3 BRES603 0603 5 kΩ 22 1 R1 Potentiometer RJ24FW 10 kΩ 23 4 RP1 to RP4 Resister Pack 220Ω 742C163221 Rev. B | Page 31 of 36

AD9215 Data Sheet Recommended Item Qty. Omit Reference Designator Device Package Value Vendor/Part No. 24 1 L1 Chip Inductor 0603 10 nH Coilcraft/0603CS- 10NXGBU 25 1 T1 1:1 RF Transformer CD542 Mini-Circuits AWT1-1T 26 1 U1 ADC 28TSSOP Analog Devices, Inc. AD9215 27 1 U2 Right Angle 40-Pin Header Samtec TSW-120-08-T-D-RA 28 2 U3, U4 Octal D-Type Flip-Flop Fairchild 74LVT57MSA 29 1 U5 Quad XOR Gate SO14 Fairchild 74VCX86M 30 1 U6 High Speed Amplifier SOMB10 Analog Devices, Inc. AD8351ARM 31 2 J1, J3 SMB Connecter SMBP 1 J4 32 2 P1, P2 Power Connector PTMICRO4 Weiland Z5.531.3425.0 Posts 25.602.5453.0 Top 33 26 E1/E5, E2/E3, E4/E8, Headers/Jumper Blocks TSW-120-07-G-S E9/E11, E6/E7, E16/E17, SMT-100-BK-G E19/E22, E18/E23, E21/20, E35/E51, E36/E50, E43/E53, E44/E52 34 12 E24/E27, E25/E26, E28/E29, Wirehole E13/E14/E30, E12/E32/E45 Rev. B | Page 32 of 36

Data Sheet AD9215 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 COPL0A.1N0ARITY 0.19 SEPALTAINNGE 0.09 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 59. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN 1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.25 PAD 3.10 SQ 2.95 17 8 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE A COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408- Figure 60. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters Rev. B | Page 33 of 36

AD9215 Data Sheet ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9215BRUZ-65 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZ-80 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZ-105 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZRL7-65 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZRL7-80 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BRUZRL7-105 −40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD9215BCPZ-65 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9215BCPZ-80 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 AD9215BCPZ-105 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_WQ) CP-32-7 1 Z = RoHS Compliant Part. Rev. B | Page 34 of 36

Data Sheet AD9215 NOTES Rev. B | Page 35 of 36

AD9215 Data Sheet NOTES ©2003–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02874-0-2/13(B) Rev. B | Page 36 of 36

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD9215BCPZ-80 AD9215BCPZ-105 AD9215BCPZ-65 AD9215BRUZ-65 AD9215BRUZ-105 AD9215BRUZ-80 AD9215BRUZRL7-105 AD9215BRUZRL7-65 AD9215BRUZRL7-80