a 12 Channel, 8-Bit TrimDACs with Power Shutdown AD8802/AD8804 FUNCTIONAL BLOCK DIAGRAM FEATURES Low Cost Replaces 12 Potentiometers CS AD8802/AD8804 VDD Individually Programmable Outputs VREFH CLK 3P-oWwierer SShPuI tCdoomwpna <ti5b5le(cid:109) SWeraitatls I nInpculutding IDD & IREF D7 DAC DA1C OO12 Midscale Preset, AD8802 D11 EN REG O3 Separate VREFL Range Setting, AD8804 DD190 ADDEDCR D0 #1 OO45 +3 V to +5 V Single Supply Operation D8 R O6 D7 O7 APPLICATIONS SER O8 REG O9 Automatic Adjustment O10 Trimmer Replacement SDI D D0 O11 D7 DAC O12 Video and Audio Equipment Gain and Offset Adjustment 12 Portable and Battery Operated Equipment 8 RDEAGC #12 D0 R SHDN GENERAL DESCRIPTION The 12-channel AD8802/AD8804 provides independent digitally- GND RS VREFL (AD8802 ONLY) (AD8804 ONLY) controllable voltage outputs in a compact 20-lead package. This potentiometer divider TrimDAC® allows replacement of the mechanical trimmer function in new designs. The AD8802/ Each DAC has its own DAC latch that holds its output state. AD8804 is ideal for dc voltage adjustment applications. These DAC latches are updated from an internal serial-to- Easily programmed by serial interfaced microcontroller ports, parallel shift register that is loaded from a standard 3-wire the AD8802 with its midscale preset is ideal for potentiometer serial input digital interface. The serial-data-input word is replacement where adjustments start at a nominal value. Appli- decoded where the first 4 bits determine the address of the DAC cations such as gain control of video amplifiers, voltage con- latches to be loaded with the last 8 bits of data. The AD8802/ trolled frequencies and bandwidths in video equipment, AD8804 consumes only 10 m A from 5 V power supplies. In ad- geometric correction and automatic adjustment in CRT com- dition, in shutdown mode reference input current consumption puter graphic displays are a few of the many applications ideally is also reduced to 10 m A while saving the DAC latch settings for suited for these parts. The AD8804 provides independent con- use after return to normal operation. trol of both the top and bottom end of the potentiometer divider The AD8802/AD8804 is available in the 20-pin plastic DIP, the allowing a separate zero-scale voltage setting determined by the SOIC-20 surface mount package, and the 1mm thin TSSOP-20 VREFL pin. This is helpful for maximizing the resolution of package. devices with a limited allowable voltage control range. Internally the AD8802/AD8804 contains 12 voltage-output digital-to-analog converters, sharing a common reference- voltage input. TrimDAC is a registered trademark of Analog Devices, Inc. REV.0 Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1995 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD8802/AD8804–SPECIFICATIONS(V = +3 V (cid:54) 10% or +5 V (cid:54) 10%, V = +V , V = 0 V, –40(cid:56)C DD REFH DD REFL £ T £ +85(cid:56)C unless otherwise noted) A Parameter Symbol Conditions Min Typ1 Max Units STATIC ACCURACY Specifications apply to all DACs Resolution N 8 Bits Differential Nonlinearity Error DNL Guaranteed Monotonic –1 – 1/4 +1 LSB Integral Nonlinearity Error INL –1.5 – 1/2 +1.5 LSB Full-Scale Error G –1 1/2 +1 LSB FSE Zero Code Error V –1 1/4 +1 LSB ZSE DAC Output Resistance R 3 5 8 kW OUT Output Resistance Match D R/R 1.5 % O REFERENCE INPUT Voltage Range2 V 0 V V REFH DD V Pin Available on AD8804 Only 0 V V REFL DD REFH Input Resistance R Digital Inputs = 55 , V = V 1.2 kW REFH H REFH DD REFL Input Resistance3 R Digital Inputs = 55 , V = V 1.2 kW REFL H REFL DD Reference Input Capacitance3 C Digital Inputs all Zeros 32 pF REF0 C Digital Inputs all Ones 32 pF REF1 DIGITAL INPUTS Logic High V V = +5 V 2.4 V IH DD Logic Low V V = +5 V 0.8 V IL DD Logic High V V = +3 V 2.1 V IH DD Logic Low V V = +3 V 0.6 V IL DD Input Current I V = 0 V or + 5 V – 1 m A IL IN Input Capacitance3 C 5 pF IL POWER SUPPLIES4 Power Supply Range V Range 2.7 5.5 V DD Supply Current (CMOS) I V = V or V = 0 V 0.01 10 m A DD IH DD IL Supply Current (TTL) I V = 2.4 V or V = 0.8 V, V = +5.5 V 1 4 mA DD IH IL DD Shutdown Current I SHDN = 0 0.2 10 m A REFH Power Dissipation P V = V or V = 0 V, V = +5.5 V 55 m W DISS IH DD IL DD Power Supply Sensitivity PSRR V = +5 V – 10% 0.001 0.002 %/% DD DYNAMIC PERFORMANCE3 V Settling Time t – 1/2 LSB Error Band 0.6 m s OUT S Crosstalk CT Between Adjacent Outputs5 50 dB SWITCHING CHARACTERISTICS3, 6 Input Clock Pulse Width t , t Clock Level High or Low 15 ns CH CL Data Setup Time t 5 ns DS Data Hold Time t 5 ns DH CS Setup Time t 10 ns CSS CS High Pulse Width t 10 ns CSW Reset Pulse Width t 90 ns RS CLK Rise to CS Rise Hold Time t 20 ns CSH CS Rise to Clock Rise Setup t 10 ns CS1 NOTES 1Typicals represent average readings at +25(cid:176)C. 2V can be any value between GND and V , for the AD8804 V can be any value between GND and V . REFH DD REFL DD 3Guaranteed by design and not subject to production test. 4Digital Input voltages V = 0 V or V for CMOS condition. DAC outputs unloaded. P is calculated from (I · V ). IN DD DISS DD DD 5Measured at a V pin where an adjacent V pin is making a full-scale voltage change (f = 100 kHz). OUT OUT 6See timing diagram for location of measured values. All input control voltages are specified with t = t = 2 ns (10% to 90% of V ) and timed from a voltage level of R F DD 1.6 V. Specifications subject to change without notice. –2– REV. 0

AD8802/AD8804 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATIONS (T = +25(cid:176)C, unless otherwise noted) A VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V VREFH 1 20 VDD VREFH 1 20 VDD V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V REFX DD O1 2 19 RS O1 2 19 O12 Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V DD O2 3 18 O12 O2 3 18 O11 Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V Operating Temperature Range . . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C O3 4 17 O11 O3 4 17 O10 Maximum Junction Temperature (T MAX) . . . . . . . . +150(cid:176) C O4 5 AD8802 16 O10 O4 5 AD8804 16 O9 Storage Temperature . . . . . . . . . . . J. . . . . . . –65(cid:176) C to +150(cid:176) C O5 6 (NToOt Pto V SIEcaWle) 15 O9 O5 6 (NToOt Pto V SIEcaWle) 15 O8 Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300(cid:176) C O6 7 14 O8 O6 7 14 O7 Package Power Dissipation . . . . . . . . . . . . (T MAX – T )/q SHDN 8 13 O7 SHDN 8 13 SDI J A JA Thermal Resistance q CS 9 12 SDI CS 9 12 CLK JA, SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60(cid:176) C/W GND 10 11 CLK GND 10 11 VREFL P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57(cid:176) C/W TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155(cid:176) C/W AD8802 PIN DESCRIPTIONS AD8804 PIN DESCRIPTIONS Pin Name Description Pin Name Description 1 VREF Common DAC Reference Input 1 VREFH Common High-Side DAC Reference Input 2 O1 DAC Output #1, addr = 0000 2 O1 DAC Output #1, addr = 0000 2 2 3 O2 DAC Output #2, addr = 0001 2 3 O2 DAC Output #2, addr = 00012 4 O3 DAC Output #3, addr = 00102 4 O3 DAC Output #3, addr = 00102 5 O4 DAC Output #4, addr = 00112 6 O5 DAC Output #5, addr = 0100 5 O4 DAC Output #4, addr = 0011 2 2 7 O6 DAC Output #6, addr = 0101 2 6 O5 DAC Output #5, addr = 0100 8 SHDN Reference input current goes to zero DAC latch 2 settings maintained 7 O6 DAC Output #6, addr = 0101 2 9 CS Chip Select Input, Active Low. When CS returns 8 SHDN Reference input current goes to zero. DAC high, data in the serial input register is decoded latch settings maintained based on the address bits and loaded input the 9 CS Chip Select Input, Active Low. When CS target DAC register returns high, data in the serial input register is 10 GND Ground decoded based on the address bits and loaded 11 V Common Low-Side DAC Reference Input REFL into the target DAC register 12 CLK Serial Clock Input, Positive Edge Triggered 13 SDI Serial Data Input 10 GND Ground 14 O7 DAC Output #7, addr = 0110 2 11 CLK Serial Clock Input, Positive Edge Triggered 15 O8 DAC Output #8, addr = 0111 2 12 SDI Serial Data Input 16 O9 DAC Output #9, addr = 10002 17 O10 DAC Output #10, addr = 1001 13 O7 DAC Output #7, addr = 0110 2 2 18 O11 DAC Output #11, addr = 1010 2 14 O8 DAC Output #8, addr = 01112 19 O12 DAC Output #12, addr = 10112 15 O9 DAC Output #9, addr = 10002 20 VDD Positive power supply, specified for operation at both +3 V and +5 V 16 O10 DAC Output #10, addr = 1001 2 17 O11 DAC Output #11, addr = 1010 2 ORDERING GUIDE 18 O12 DAC Output #12, addr = 1011 2 Temperature Package Package 19 RS Asynchronous Preset to Midscale Output Model FTN Range Description Option Setting. Loads all DAC Registers with 80 H AD8802AN RS –40(cid:176) C/+85(cid:176) C PDIP-20 N-20 20 V Positive Power Supply, Specified for Operation DD AD8802AR RS –40(cid:176) C/+85(cid:176) C SOL-20 R-20 at Both +3 V and +5 V AD8802ARU RS –40(cid:176) C/+85(cid:176) C TSSOP-20 RU-20 AD8804AN REFL –40(cid:176) C/+85(cid:176) C PDIP-20 N-20 AD8804AR REFL –40(cid:176) C/+85(cid:176) C SOL-20 R-20 AD8804ARU REFL –40(cid:176) C/+85(cid:176) C TSSOP-20 RU-20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. 0 –3–

AD8802/AD8804–Typical Performance Characteristics 1 160 0.75 VVDRDEF =H +=5 +V5V TTAA == ++8255(cid:176)(cid:176)CC 140 VREFL = 0V TA = –40(cid:176)C 0.5 120 A µ 0.25 – 100 INL – LSB–0.250 CURRENT REF 8600 VDD = +5V –0.5 I 40 VREFH = +2V VREFL = 0V ONE DAC CHANGING WITH CODE, –0.75 20 OTHER DACs SET TO 00H TA = +25(cid:176)C –1 0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE – Decimal CODE – Decimal Figure 1.INL vs. Code Figure 4.Input Reference Current vs. Code 1 10k 0.75 TTAA == ++8255(cid:176)(cid:176)CC 0.5 VVVDRRDEEFF =HL +==5 0+VV5V TA = –40(cid:176)C T – nA 1k 0.25 EN VDD = +5.5V B RR VREF = +5.5V S U NL – L 0 WN C 100 I–0.25 DO T U –0.5 SH 10 VDD = +2.7V –0.75 VREF = +2.7V –1 0 0 32 64 96 128 160 192 224 256 –55 –35 –15 5 25 45 65 85 105 125 CODE – Decimal TEMPERATURE – (cid:176)C Figure 2.Differential Nonlinearity Error vs. Code Figure 5.Shutdown Current vs. Temperature 1600 100k VDD = +4.5V VREF = +4.5V 10k VDD = +5.5V 1280 VREFL = 0V VIN = +2.4V TA = +25(cid:176)C A 1k µ SS = 3600 PCS – FREQUENCY 966400 PLY CURRENT 101010 VDD = +5.5V UP VIN = +5.5V S 0.1 320 0.01 0 0.001 0 0.2 0.4 0.6 0.8 1.0 –55 –35 –15 5 25 45 65 85 105 125 ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB TEMPERATURE – (cid:176)C Figure 3.Total Unadjusted Error Histogram Figure 6.Supply Current vs. Temperature –4– REV. 0

AD8802/AD8804 100 TA = +25(cid:176)C ALL DIGITAL INPUTS 10 TIED TOGETHER OUTPUT1: OOH fi FFH A VDD = +5V Y CURRENT – m 01..10 VDD = +5V T2 – 10mV/DIV 19000 Vf =R E1FM =H +z5V L U P P UP 0.01 UT 10 S VDD = +3V O 0% 0.001 10mV 200ns TIME – 0.2µs/DIV 0.0001 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 INPUT VOLTAGE – Volts Figure 10.Adjacent Channel Clock Feedthrough Figure 7.Supply Current vs. Logic Input Voltage 80 5mV 1µs 60 100 90 VDD = +5V OUT1 ALL OUTPUTS SET 5mV/DIV OUTPUT1: 7FH fi 80H dB TO MIDSCALE (80H) VDD = +5V R – 40 VREF = +5V R S CS P 5V/DIV 10 0% 20 5V TIME – 1µs/DIV 0 10 100 1k 10k 100k FREQUENCY – Hz Figure 11.Midscale Transition Figure 8.Power Supply Rejection vs. Frequency 0.01 B VDD = +4.5V LS VREF = +4.5V 6V 2V 5µs OR – 0.005 SVSRE =F L1 7=6 0 PVCS 4V19000 ERR OUT E 2V AL 0V O-SC 0 VDD = +5V ER VREF = +5V N Z CS 5V 01%0 GE I–0.005 0V 0% 5V HAN C TIME – 5µs/DIV –0.01 0 100 200 300 400 500 600 HOURS OF OPERATION AT 150(cid:176)C Figure 9.Large-Signal Settling Time Figure 12.Zero-Scale Error Accelerated by Burn-In REV. 0 –5–

AD8802/AD8804 0.04 1.0 VDD = +4.5V VDD = +4.5V SB VREF = +4.5V VREF = +4.5V ALE ERROR – L 0.02 x +x 2s SS = 176 PCS WCE DRIFT – k 0.5 x + 2s x CSSO D= E1 7=6 5 P5CHS SC 0 AN 0 ULL- x – 2s SIST GE IN F–0.02 PUT RE –0.5 x – 2s N N A I H C –0.04 –1.0 0 100 200 300 400 500 600 0 100 200 300 400 500 600 HOURS OF OPERATION AT 150(cid:176)C HOURS OF OPERATION AT 150(cid:176)C Figure 13.Full-Scale Error Accelerated by Burn-In Figure 14.REF Input Resistance Accelerated by Burn-In OPERATION 1 SDI A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 The AD8802/AD8804 provides twelve channels of program- 0 mable voltage output adjustment capability. Changing the pro- 1 grammed output voltage of each DAC is accomplished by CLK 0 clocking in a 12-bit serial data word into the SDI (Serial Data 1 Input) pin. The format of this data word is four address bits, CS DAC REGISTER LOAD 0 MSB first, followed by 8 data bits, MSB first. Table I provides +5V the serial register data word format. The AD8802/AD8804 has VOUT 0V the following address assignments for the ADDR decode which determines the location of the DAC register receiving the serial Figure 15a.Timing Diagram register data in Bits B7 through B0: DAC# = A3 · 8 + A2 · 4 + A1 · 2 + A0 + 1 DETAIL SERIAL DATA INPUT TIMING (RS = "1") DAC outputs can be changed one at a time in random se- SDI 1 quence. The fast serial-data loading of 33 MHz makes it pos- (DATA IN) 0 AX OR DX AX OR DX t sible to load all 12 DACs in as little time as 4.6m s (13 · 12 · DS tCH tDH tCS1 30ns). The exact timing requirements are shown in Figure 15. 1 CLK 0 Table I. Serial-Data Word Format 1 tCSS tCL tCSH CS tCSW ADDR DATA 0 t S B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 +5V – 1/2 LSB VOUT A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0V – 1/2 LSB ERROR BAND MSB LSB MSB LSB Figure 15b.Detail Timing Diagram 211 210 29 28 27 26 25 24 23 22 21 20 RESET TIMING The AD8802 offers a midscale preset activated by the RS pin 1 tRS simplifying initial setting conditions at first power-up. The RS 0 AD8804 has both a VREFH and a VREFL pin to establish indepen- tS dent positive full-scale and zero-scale settings to optimize reso- +5V lution. Both parts offer a power shutdown SHDN which places VOUT – 1 LSB the DAC structure in a zero power consumption state resulting 2.5V – 1 LSB ERROR BAND in only leakage currents being consumed from the power supply and V inputs. In shutdown mode the DACX register settings Figure 15c.Reset Timing Diagram REF are maintained. When returning to operational mode from power shutdown the DAC outputs return to their previous volt- age settings. –6– REV. 0

AD8802/AD8804 PROGRAMMING THE OUTPUT VOLTAGE ladder, while the REFH reference is sourcing current into the The output voltage range is determined by the external refer- DAC ladder. The DAC design minimizes reference glitch cur- ence connected to V and V pins. See Figure 16 for a REFH REFL rent maintaining minimum interference between DAC channels simplified diagram of the equivalent DAC circuit. In the case of during code changes. the AD8802 its V is internally connected to GND and REFL therefore cannot be offset. V can be tied to V and V DAC OUTPUTS (O1–O12) REFH DD REFL can be tied to GND establishing a basic rail-to-rail voltage out- The twelve DAC outputs present a constant output resistance of put programming range. Other output ranges are established by approximately 5kW independent of code setting. The distribu- the use of different external voltage references. The general tion of R from DAC-to-DAC typically matches within – 1%. OUT transfer equation which determines the programmed output However device-to-device matching is process lot dependent voltage is: having a – 20% variation. The change in R with temperature OUT VO (Dx) = (Dx)/256 · (V – V ) + V Eq. 1 has a 500 ppm/(cid:176) C temperature coefficient. During power shut- REFH REFL REFL down all twelve outputs are open-circuited. where Dx is the data contained in the 8-bit DACx register. TO OTHER DACS CS AD8802/AD8804 VDD VREFH P CH CLK VREFH D7 DA1C O1 N CH MSB 2R OX DD1101 ADENDR RD#EA1GC OOO243 D9 DEC D0 O5 R D8 R O6 DAC D7 O7 REGISTER SER O8 REG O9 D7 2R SDI D D0 D7 OO1101 D6 DAC O12 D0 .. .R 8 RDEAGC 12 .. . #12 .. . D0 R SHDN LSB 2R GND RS VREFL (AD8802 ONLY) (AD8804 ONLY) GND 2R Figure 17.Block Diagram VREFL DIGITAL INTERFACING Figure 16.AD8802/AD8804 Equivalent TrimDAC Circuit The AD8802/AD8804 contains a standard three-wire serial in- For example, when V = +5 V and V = 0 V, the follow- put control interface. The three inputs are clock (CLK), CS and REFH REFL ing output voltages will be generated for the following codes: serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into Output State the serial input register. Standard logic families work well. If D VOx (V = +5 V, V = 0 V) mechanical switches are used for product evaluation, they REFH REFL should be debounced by a flip-flop or other suitable means. Fig- 255 4.98 V Full Scale ure 17 block diagram shows more detail of the internal digital 128 2.50 V Half Scale (Midscale Reset Value) circuitry. When CS is taken active low, the clock can load data 1 0.02 V 1 LSB into the serial register on each positive clock edge, see Table II. 0 0.00 V Zero Scale Table II. Input Logic Control Truth Table REFERENCE INPUTS (VREFH, VREFL) CS CLK Register Activity The reference input pins set the output voltage range of all twelve DACs. In the case of the AD8802 only the V pin is 1 X No effect. REFH available to establish a user designed full-scale output voltage. 0 P Shifts Serial Register One bit loading the next bit The external reference voltage can be any value between 0 and in from the SDI pin. V but must not exceed the V supply voltage. The AD8804 P 1 Clock should be high when the CS returns to the DD DD has access to the V which establishes the zero-scale output inactive state. REFL voltage, any voltage can be applied between 0 V and V . V DD REFL P = Positive Edge, X = Don’t Care. can be smaller or larger in voltage than V since the DAC REFH The data setup and data hold times in the specification table design uses fully bidirectional switches as shown in Figure 16. determine the data valid time requirements. The last 12 bits of The input resistance to the DAC has a code dependent variation the data word entered into the serial register are held when CS which has a nominal worst case measured at 55 , which is ap- H proximately 1.2kW . When V is greater than V , the returns high. At the same time CS goes high it gates the address REFH REFL decoder which enables one of the twelve positive-edge triggered REFL reference must be able to sink current out of the DAC DAC registers, see Figure 18 detail. REV. 0 –7–

AD8802/AD8804 DAC 1 +5V . CS ADDR D..AC 2 DECODE VDD DAC 12 AD8802/ + CLK SERIAL 10µF 0.1µF AD8804 REGISTER SDI DGND Figure 18.Equivalent Control Logic The target DAC register is loaded with the last eight bits of the serial data-word completing one DAC update. Twelve separate 12-bit data words must be clocked in to change all twelve out- Figure 21.Recommended Supply Bypassing for the put settings. AD8802/AD8804 All digital inputs are protected with a series input resistor and Buffering the AD8802/AD8804 Output parallel Zener ESD structure shown in Figure 19. Applies to In many cases, the nominal 5 kW output impedance of the digital input pins CS, SDI, RS, SHDN, CLK AD8802/AD8804 is sufficient to drive succeeding circuitry. If a lower output impedance is required, an external amplifier can 1kW be added. Several examples are shown in Figure 22. One ampli- LOGIC fier of an OP291 is used as a simple buffer to reduce the output resistance of DAC A. The OP291 was chosen primarily for its rail-to-rail input and output operation, but it also offers opera- tion to less than 3 V, low offset voltage, and low supply current. Figure 19.Equivalent ESD Protection Circuit The next two DACs, B and C, are configured in a summing Digital inputs can be driven by voltages exceeding the AD8802/ arrangement where DAC C provides the coarse output voltage AD8804 V supply value. This allows 5 V logic to interface DD setting and DAC B can be used for fine adjustment. The inser- directly to the part when it is operated at 3 V. tion of R1 in series with DAC B attenuates its contribution to the voltage sum node at the DAC C output. APPLICATIONS Supply Bypassing +5V Precision analog products, such as the AD8802/AD8804, re- quire a well filtered power source. Since the AD8802/AD8804 VREFH VDD operate from a single +3 V to +5 V supply, it seems convenient OP291 to simply tap into the digital logic power supply. Unfortunately, VVHL SIMPLE BUFFER the logic supply is often a switch-mode design, which generates 0V TO 5V noise in the 20 kHz to 1 MHz range. In addition, fast logic gates VH can generate glitches hundred of millivolts in amplitude due to VL R1 100kW wiring resistances and inductances. VH SUMMER CIRCUIT VL WITH FINE TRIM If possible, the AD8802/AD8804 should be powered directly ADJUSTMENT from the system power supply. This arrangement, shown in Fig- AD8802/ AD8804 ure 20, will isolate the analog section from the logic switching transients. Even if a separate power supply trace is not available, VREFL GND however, generous supply bypassing will reduce supply-line in- DIGITAL INTERFACING duced errors. Local supply bypassing consisting of a 10 m F tan- OMITTED FOR CLARITY talum electrolytic in parallel with a 0.1 m F ceramic capacitor is Figure 22.Buffering the AD8802/AD8804 Output recommended (Figure 21). Increasing Output Voltage Swing An external amplifier can also be used to extend the output volt- TTL/CMOS LOGIC age swing beyond the power supply rails of the AD8802/AD8804. CIRCUITS +10µF 0.1µF AD8802/ This technique permits an easy digital interface for the DAC, TANT AD8804 while expanding the output swing to take advantage of higher voltage external power supplies. For example, DAC A of Fig- +5V ure 23 is configured to swing from –5 V to +5 V. The actual POWER SUPPLY output voltage is given by: Figure 20.Use Separate Traces to Reduce Power Supply ( ) Noise (cid:86)(cid:79)(cid:85)(cid:84) =(cid:230)Ł (cid:49)+ (cid:82)(cid:82)(cid:70)(cid:246)ł · (cid:50)(cid:68)(cid:53)(cid:54) · (cid:53)(cid:86) (cid:177)(cid:53)(cid:86) (cid:83) where D is the DAC input value (i.e., 0 to 255). This circuit can be combined with the “fine/coarse” circuit of Figure 22 if, for example, a very accurate adjustment around 0 V is desired. –8– REV. 0

AD8802/AD8804 +5V RS RF +5V 100kW 100kW +5V 0.1µF 10µF VDD VREFH –5V TO +4.98V VDD VREFH A OP191 AD8802 AD8802/ –5V SBUF SHSIEFRTI ARLE GDIASTTAER RxD P3.0 SDI O1 AD8804 +12V SHIFT CLOCK TxD P3.1 SCLK B OP193 P1.3 RESET 0V TO +10V 8051 µC P1.2 SHDN O12 GND VREFL P1.1 CS AD8804 100kW ONLY PORT 1 1.31.2 1.1 GND 100kW Figure 24.Interfacing the 8051 m C to an AD8802/AD8804, Figure 23.Increasing Output Voltage Swing Using the Serial Port DAC B of Figure 24 is in a noninverting gain of two configura- Software for the 8051 Interface tions, which increases the available output swing to +10 V. The A software for the AD8802/AD8804 to 8051 interface is feedback resistors can be adjusted to provide any scaling of the shown in Listing 1. The routine transters the 8-bit data stored at output voltage, within the limits of the external op amp power data memory location DAC_VALUE to the AD8802/AD8804 supplies. DAC addressed by the contents of location DAC_ADDR. Microcomputer Interfaces The subroutine begins by setting appropriate bits in the Serial The AD8802/AD8804 serial data input provides an easy inter- Control register to configure the serial port for Mode 0 opera- face to a variety of single-chip microcomputers (m Cs). Many m Cs tion. Next the DAC’s Chip Select input is set low to enable the have a built-in serial data capability that can be used for com- AD8802/AD8804. The DAC address is obtained from memory municating with the DAC. In cases where no serial port is pro- location DAC_ADDR, adjusted to compensate for the 8051’s vided, or it is being used for some other purpose (such as an serial data format, and moved to the serial buffer register. At RS-232 communications interface), the AD8802/AD8804 can this point, serial data transmission begins automatically. When easily be addressed in software. all 8 bits have been sent, the Transmit Interrupt bit is set, and the subroutine then proceeds to send the DAC value stored at Twelve data bits are required to load a value into the AD8802/ location DAC_VALUE. Finally the Chip Select input is re- AD8804 (4 bits for the DAC address and 8 bits for the DAC turned high, causing the appropriate AD8802/AD8804 output value). If more than 12 bits are transmitted before the Chip Se- voltage to change, and the subroutine ends. lect input goes high, the extra (i.e., the most-significant) bits are ignored. This feature is valuable because most m Cs only transmit The 8051 sends data out of its shift register LSB first, while the data in 8-bit increments. Thus, the m C will send 16 bits to the AD8802/AD8804 require data MSB first. The subroutine there- DAC instead of 12 bits. The AD8802/AD8804 will only re- fore includes a BYTESWAP subroutine to reformat the data. spond to the last 12 bits clocked into the SDI port, however, so This routine transfers the MSB-first byte at location SHIFT1 to the serial data interface is not affected. an LSB-first byte at location SHIFT2. The routine rotates the MSB of the first byte into the carry with a Rotate Left Carry in- An 8051 m C Interface struction, then rotates the carry into the MSB of the second byte A typical interface between the AD8802/AD8804 and an 8051 with a Rotate Right Carry instruction. After 8 loops, SHIFT2 m C is shown in Figure 24. This interface uses the 8051’s internal contains the data in the proper format. serial port. The serial port is programmed for Mode 0 opera- tion, which functions as a simple 8-bit shift register. The 8051’s The BYTESWAP routine in Listing 1 is convenient because the Port 3.0 pin functions as the serial data output, while Port 3.1 DAC data can be calculated in normal LSB form. For example, serves as the serial clock. producing a ramp voltage on a DAC is simply a matter of re- peatedly incrementing the DAC_VALUE location and calling When data is written to the Serial Buffer Register (SBUF, at the LD_8802 subroutine. Special Function Register location 99 ), the data is automati- H cally converted to serial format and clocked out via Port 3.0 and If the m C’s hardware serial port is being used for other purposes, Port 3.1. After 8 bits have been transmitted, the Transmit Inter- the AD8802/AD8804 DAC can be loaded by using the parallel rupt flag (SCON.1) is set and the next 8 bits can be transmitted. port. A typical parallel interface is shown in Figure 25. The se- rial data is transmitted to the DAC via the 8051’s Port 1.6 out- The AD8802 and AD8804 require the Chip Select to go low at put, while Port 1.6 acts as the serial clock. the beginning of the serial data transfer. In addition, the SCLK input must be high when the Chip Select input goes high at the Software for the interface of Figure 25 is contained in Listing 2. The end of the transfer. The 8051’s serial clock meets this require- subroutine will send the value stored at location DAC_VALUE to ment, since Port 3.1 both begins and ends the serial data in the the AD8802/AD8804 DAC addressed by location DAC_ADDR. high state. The program begins by setting the AD8802/AD8804’s Serial Clock and Chip Select inputs high, then setting Chip Select low REV. 0 –9–

AD8802/AD8804 ; ; This subroutine loads an AD8802/AD8804 DAC from an 8051 microcomputer, ; using the 8051’s serial port in MODE 0 (Shift Register Mode). ; The DAC value is stored at location DAC_VAL ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations ; PORT1 DATA 90H ;SFR register for port 1 DAC_VALUE DATA 40H ;DAC Value DAC_ADDR DATA 41H ;DAC Address SHIFT1 DATA 042H ;high byte of 16-bit answer SHIFT2 DATA 043H ;low byte of answer SHIFT_COUNT DATA 44H ; ; ORG 100H ;arbitrary start DO_8802: CLR SCON.7 ;set serial CLR SCON.6 ;data mode 0 CLR SCON.5 CLR SCON.1 ;clr transmit flag ORL PORT1.1,#00001110B ;/RS, /SHDN, /CS high CLR PORT1.1 ;set the /CS low MOV SHIFT1,DAC_ADDR ;put DAC value in shift register ACALL BYTESWAP ; MOV SBUF,SHIFT2 ;send the address byte ADDR_WAIT: JNB SCON.1,ADDR_WAIT ;wait until 8 bits are sent CLR SCON.1 ;clear the serial transmit flag MOV SHIFT1,DAC_VALUE ;send the DAC value ACALL BYTESWAP ; MOV SBUF,SHIFT2 ; VALU_WAIT: JNB SCON.1,VALU_WAIT ;wait again CLR SCON.1 ;clear serial flag SETB PORT1.1 ;/CS high, latch data RET ; into AD8801 ; BYTESWAP: MOV SHIFT_COUNT,#8 ;Shift 8 bits SWAP_LOOP: MOV A,SHIFT1 ;Get source byte RLC A ;Rotate MSB to carry MOV SHIFT1,A ;Save new source byte MOV A,SHIFT2 ;Get destination byte RRC A ;Move carry to MSB MOV SHIFT2,A ;Save DJNZ SHIFT_COUNT,SWAP_LOOP ;Done? RET END Listing 1.Software for the 8051 to AD8802/AD8804 Serial Port Interface +5V to start the serial interface process. The DAC address is loaded into the accumulator and four Rotate Right shifts are per- formed. This places the DAC address in the 4 MSBs of the ac- VDD VREFH cumulator. The address is then sent to the AD8802/AD8804 via 8051 µC AD8804 the SEND_SERIAL subroutine. Next, the DAC value is loaded P1.7 SDI into the accumulator and sent to the AD8802/AD8804. Finally, O1 P1.6 the Chip Select input is set high to complete the data transfer CLK P1.5 Unlike the serial port interface of Figure 24, the parallel port in- CS terface only transmits 12 bits to the AD8802/AD8804. Also, the O12 P1.4 SHDN BYTESWAP subroutine is not required for the parallel inter- PORT 1 1.7 1.6 1.5 1.4 GND VREFL face, because data can be shifted out MSB first. However, the results of the two interface methods are exactly identical. In most cases, the decision on which method to use will be deter- mined by whether or not the serial data port is available for Figure 25.An AD8802/AD8804-8051 m C Interface Using communication with the AD8802/AD8804. Parallel Port 1 –10– REV. 0

AD8802/AD8804 ; This 8051 m C subroutine loads an AD8802 or AD8804 DAC with an 8-bit value, ; using the 8051’s parallel port #1. ; The DAC value is stored at location DAC_VALUE ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations PORT1 DATA 90H ;SFR register for port 1 DAC_VALUE DATA 40H ;DAC Value DAC_ADDR DATA 41H ;DAC Address (0 through 7) LOOPCOUNT DATA 43H ;COUNT LOOPS ; ORG 100H ;arbitrary start LD_8804: ORL PORT1,#11110000B ;set CLK, /CS and /SHDN high CLR PORT1.5 ;Set Chip Select low MOV LOOPCOUNT,#4 ;Address is 4 bits MOV A,DAC_ADDR ;Get DAC address RR A ;Rotate the DAC RR A ;address to the Most RR A ;Significant Bits (MSBs) RR A ; ACALL SEND_SERIAL ;Send the address MOV LOOPCOUNT,#8 ;Do 8 bits of data MOV A,DAC_VALUE ACALL SEND_SERIAL ;Send the data SETB PORT1.5 ;Set /CS high RET ;DONE SEND_SERIAL: RLC A ;Move next bit to carry MOV PORT1.7,C ;Move data to SDI CLR PORT1.6 ;Pulse the SETB PORT1.6 ;CLK input DJNZ LOOPCOUNT,SEND_SERIAL ;Loop if not done RET; END Listing 2.Software for the 8051 to AD8802/AD8804 Parallel Port Interface An MC68HC11-to-AD8802/AD8804 Interface A software routine for loading the AD8802/AD8804 from a Like the 8051 m C, the MC68HC11 includes a dedicated serial 68HC11 evaluation board is shown in Listing 3. First, the data port (labeled SPI). The SPI port provides an easy interface MC68HC11 is configured for SPI operation. Bits CPHA and to the AD8802/AD8804 (Figure 27). The interface uses three CPOL define the SPI mode wherein the serial clock (SCK) is lines of Port D for the serial data, and one or two lines from high at the beginning and end of transmission, and data is valid Port C to control the SHDN and RS (AD8802 only) inputs. on the rising edge of SCK. This mode matches the requirements of the AD8802/AD8804. After the registers are saved on the stack, the DAC value and address are transferred to RAM and MC68HC11* AD8802/ the AD8802/AD8804’s CS is driven low. Next, the DAC’s ad- AD8804* dress byte is transferred to the SPDR register, which automati- (PD3)MOSI SDI cally initiates the SPI data transfer. The program tests the SPIF (PD4)SCK CLK bit and loops until the data transfer is complete. Then the DAC (PD5) SS CS value is sent to the SPI. When transmission of the second byte is complete, CS is driven high to load the new data and address PC0 SHDN into the AD8802/AD8804. PC1 RS (AD8802 ONLY) *ADDITIONAL PINS OMITTED FOR CLARITY Figure 26.An AD8802/AD8804-to-MC68HC11 Interface REV. 0 –11–

AD8802/AD8804 * * AD8802/AD8804 to M68HC11 Interface Assembly Program * * M68HC11 Register definitions * PORTC EQU $1003 Port C control register * “0,0,0,0;0,0,RS/, SHDN/” DDRC EQU $1007 Port C data direction PORTD EQU $1008 Port D data register * “0,0,/CS,CLK;SDI,0,0,0” DDRD EQU $1009 Port D data direction SPCR EQU $1028 SPI control register * “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0” SPSR EQU $1029 SPI status register * “SPIF,WCOL,0,MODF;0,0,0,0” SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * SDI RAM variables: SDI1 is encoded from 0H to 7H * SDI2 is encoded from 00H to FFH * AD8802/AD8804 requires two 8-bit loads; upper 4 bits * of SDI1 are ignored. AD8802/AD8804 address bits in last * four LSBs of SDI1. * SDI1 EQU $00 SDI packed byte 1 “0,0,0,0;A3,A2,A1,A0” SDI2 EQU $01 SDI packed byte 2 “DB7–DB4;DB3–DB0” * * Main Program * ORG $C000 Start of user’s RAM in EVB INIT LDS #$CFFF Top of C page RAM * * Initialize Port C Outputs * LDAA #$03 0,0,0,0;0,0,1,1 * /RS-Hi, /SHDN-Hi STAA PORTC Initialize Port C Outputs LDAA #$03 0,0,0,0;0,0,1,1 STAA DDRC /RS and /SHDN are now enabled as outputs * * Initialize Port D Outputs * LDAA #$20 0,0,1,0;0,0,0,0 * /CS-Hi,/CLK-Lo,SDI-Lo STAA PORTD Initialize Port D Outputs LDAA #$38 0,0,1,1;1,0,0,0 STAA DDRD /CS,CLK, and SDI are now enabled as outputs * * Initialize SPI Interface * LDAA #$53 STAA SPCR SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32 * * Call update subroutine * BSR UPDATE Xfer 2 8-bit words to AD8402 JMP $E000 Restart BUFFALO * * Subroutine UPDATE * UPDATE PSHX Save registers X, Y, and A PSHY PSHA * * Enter Contents of SDI1 Data Register –12– REV. 0

AD8802/AD8804 * LDAA $0000 Hi-byte data loaded from memory STAA SDI1 SDI1 = data in location 0000H * * Enter Contents of SDI2 Data Register * LDAA $0001 Low-byte data loaded from memory STAA SDI2 SDI2 = Data in location 0001H * LDX #SDI1 Stack pointer at 1st byte to send via SDI LDY #$1000 Stack pointer at on-chip registers * * Reset AD8802 to one-half scale (AD8804 does not have a Reset input) * BCLR PORTC,Y $02 Assert /RS BSET PORTC,Y $02 De-Assert /RS * * Get AD8802/04 ready for data input * BCLR PORTD,Y $02 Assert /CS * TFRLP LDAA 0,X Get a byte to transfer for SPI STAA SPDR Write SDI data reg to start xfer * WAIT LDAA SPSR Loop to wait for SPIF BPL WAIT SPIF is the MSB of SPSR * INX Increment counter to next byte for xfer CPX #SDI2+1 Are we done yet ? BNE TFRLP If not, xfer the second byte * * Update AD8802 output * BSET PORTD,Y $20 Latch register & update AD8802 * PULA When done, restore registers X, Y & A PULY PULX RTS ** Return to Main Program ** Listing 3.AD8802/AD8804 to MC68HC11 Interface Program Source Code An Intelligent Temperature Control System—Interfacing the interface lines, interrupts, and the serial port lines have been 8051(cid:109)C with the AD8802/AD8804 and TMP14 assigned. The eight port pins may be used as chip selects, in Connecting the 80CL51 m C, or any modern microcontroller, which case an array of eight AD8802/AD8804s controlling with the TMP14 and AD8802/AD8804 yields a powerful tem- twenty-four TMP14 sensors is possible. perature control tool, as shown in Figure 27. For example, the The AD8802/AD8804 and TMP14 are also ideal choices for 80CL51 m C controls the TrimDACs allowing the user to auto- low power applications. These devices have power shutdown matically set the temperature setpoints voltages of the TMP14 modes and operate on a single 5 Volt supply. When their shut- via computer or touch pad, while the TMP14 senses the tem- down modes are activated current consumption is reduced to perature and outputs four open-collector trip-points. Feeding less than 35 m A. However, at high operating frequencies these trip-point outputs back to the 80CL51 m C allow it to sense (12 MHz) the 80CL51 consumes far more energy (18mA typ) whether or not a setpoint has been exceeded. Additional than the AD8802/AD8804 and TMP14 combined. Therefore, 80CL51 m C port pins or TMP14 trip-point outputs may then to achieve a low power design the 80CL51 should operate at its be used to change fan speed (i.e., high, medium, low, off), or lowest possible frequency or be placed in its power-down mode increase/decrease the power level to a heater. (Please refer to the at the end of each instruction sequence. TMP14 data sheet for more applications information.) To use the power-down mode of the 80CL51 m C set PCON.1 The CS (Chip Select) on the AD8802/AD8804 makes applica- as the last instruction executed prior to going into the power- tions that call for large temperature sensor arrays possible. In down mode. If INT2 and INT9 are enabled, the 80CL51 m C addition, the 12 channels of the AD8802/AD8804 allow inde- can be awakened from power-down mode with external inter- pendent setpoint control for all four trip-point outputs on up to rupts. As shown in Figure 28, the TLC555 outputs a pulse three TMP14 temperature sensors. For example, assume that every few seconds providing the interrupt to restart the 80CL51 the 80CL51 m C has eight free port pins available after all user m C which then samples the user input pins, the outputs of the REV. 0 –13–

AD8802/AD8804 TMP14 AD8802/4 VREFH 2.5 VREF HYS P0.0 P3.2 CS O1 SET 1 TRIP 1 USER P3.1 CLK O2 SET 2 TRIP 2 INPUTS P3.0 SDI O3 SET 3 TRIP 3 P0.7 P3.3 O4 SET 4 TRIP 4 80CL51 µP2C.0 3 ATROR 2AnYd I FA DN8E8E0D2E/4D 090–51–28 44 TITFOO N 23EnrEddD TTEEEDMMPP SSEENNSSOORR SLEEP GNVD+ 0.1µ+5FV IF NEEDED P2.1 P2.2 VDD +5V P2.3 0.1µF 10µF GND P1.0/INT2 P2.4 SHDN +5V 0.01µF VCC RS TLC555 DIS 3 OUT THR GND TRIG Figure 27.Temperature Sensor Array with Programmable Setpoints TMP14, and makes the necessary adjustments to the AD8802/ The gain of the SSM2018T is controlled by the voltage at Pin 11. AD8804 before shutting down again. The 80CL51 consumes For maximum attenuation of –100dB a control signal of 3.0 V only 50 m A when operating at 32 kHz, in which case there typ is necessary. The control signal has a scale of –30 mV/dB would be no need for the TLC555, which consumes 1mW typ. centered around 0dB gain for 0 V of control voltage, therefore, for a maximum gain of 40dB a control voltage of –1.2 volts is 12 Channel Programmable Voltage Controlled Amplifier necessary. Now notice that the normal +5V to GND voltage The SSM2018T is a trimless Voltage Controlled Amplifier range of the AD8802/AD8804 does not cover the 3.0 V to (VCA) for volume control in audio systems. The SSM2018T is –1.2V operational gain control range of the SSM2018T. To the first professional quality audio VCA in the marketplace that cover the operating gain range fully and not exceed the maxi- does not require an external trimming potentiometer to mini- mum specified power supply rating requires the O1 output of mize distortion. The TrimDAC shown in Figure 28 is not being AD8802/AD8804 to be level shifted down. In Figure 28, the used to trim distortion, but rather to control the gain of the am- level shifting is accomplished by a Zener diode and 1/4 of an plifier. In this configuration up to twelve SSM2018T can be OP420 quad op amp. For applications that require only digitally controlled. (Please refer to the SSM2018T data sheet for more specifications and applications information.) 18kW 50pF VOUT 0O TPOTI O40NdABL G FAOIRN 1 16 –15V +15V +15V 2 SSM2018T 15 1.2V 50kW 3 14 4 13 15R0OkW OP420A 1µF 18kW 5 12 +V AD8802/4 6 11 7 10 O1 VREFH 1µF 18kW 8 9 NC 47pF VREFL (AD8804 O2– ONLY) O12 REF195 O2 O3 CS V+ OUT IN +15V TO 8 MORE CHANNELS O4–O12 CLK 1µF GND SDI GND 3 TO µC Figure 28.12-Channel Programmable Voltage Controlled Amplifier –14– REV. 0

AD8802/AD8804 +12V VCC R D GAIN B D GAIN G D GAIN 9 13 –H SYNC 15 OUTPUT RGB 5 7, 11, 17 40, 35, 30 CRT CRT VIDEO LM1204 VIDEO CATHODE INPUT 38, 28, 33 RGB FEEDBACK AMP 24 43 BLANK GATE 22 INPUT 21 +4V 20 VCC (+12V) O1 O2 O3 04 O5 O6 O7 VREFH REF195 CS OUT IN +12V TO µC CLK AD8802/4 0.1µF 10µF GND 10µF 0.1µF VCC SDI O1 = 2V O5 = R AGAIN O2 = CONTRAST O6 = B AGAIN O3 = BP CLAMP WIDTH ADJUST O7 = G AGAIN O4 = BLANK LEVEL ADJUST O8 – O12 = NOT USED (FOR BRIGHTNESS CONTROL) Figure 29.A Digitally Controlled LM1204—150 MHz RGB Amplifier System attenuation the optional circuitry inside the dashed box may be between Pins 5 and 7. The input referred noise spectral density removed and replaced with a direct connection from O1 of is only 1.3 nV(cid:214) Hz and power consumption is 125 mW at the AD8802/AD8804 to Pin 11 of SSM2018T. recommended – 5 V supplies. When high gain resolution is desired, V and V may be The decibel gain is “linear in dB,” accurately calibrated, and REFH REFL decoupled from the power rails and shifted closer together. stable over temperature and supply. The gain is controlled at a This technique increases the gain resolution with the unfortu- high impedance (50 MW ), low bias (200 nA) differential input; nate penalty of decreased gain range. the scaling is 25 mV/dB, requiring a gain-control voltage of only 1V to span the central 40 dB of the gain range. An overrange A Digitally Controlled LM1204 150MHz RGB Amplifier and underrange of 1 dB is provided whatever the selected System The LM1204 is an industry standard video amplifier system. range. The gain-control response time is less than 1m s for a 40 Figure 29 illustrates a configuration that removes the usual dB change. The settling time of the AD8802/AD8804 to within seven level setting potentiometers and replaces them with only a – 1/2 LSB band is 0.6 m s making it an excellent choice for con- one IC. The AD8802/AD8804, in addition to being smaller trol of the AD603. and more reliable than mechanical potentiometers, has the The differential gain-control interface allows the use of either added feature of digital control. differential or single-ended positive or negative control voltages, The REF195 is a 5.0V reference used to supply both the power where the common-mode range is –1.2V to 2.0V. Once again and reference voltages to the AD8802/AD8804. This is possible the AD8802/AD8804 is ideally suited to provide the differential because of the high reference output current available (30 mA input range of 1V within the common-mode range of 0 V to typical) together with the low power consumption of the 2V. To accomplish this, place VREFH at 2.0 V and VREFL at 1.0V, then all 256 voltage levels of the AD8804 will fall within AD8802/AD8804. the gain-control range of the AD603. Please refer to the AD603 A Low Noise 90 MHz Programmable Gain Amplifier data sheet for further information regarding gain control, layout, The AD603 is a low noise, voltage-controlled amplifier for use and general operation. in RF and IF AGC systems. It provides accurate, pin selectable The dual OP279 is a rail-to-rail op amp used in Figure 30 to gains of –11 dB to +31 dB with a bandwidth of 90 MHz or drive the inputs V and V because these reference inputs +9dB to +51 dB with a bandwidth of 9 MHz. Any intermedi- REFH REFL are low impedance (2 kW typical). ate gain range may be arranged using one external resistor REV. 0 –15–

AD8802/AD8804 +10V 0.1µF +10V 0.1µF 0.1µF 8 3 6 5 0.1µF 8 100W AD603 7 3 6 5 0.1µF 4 2 AD603 7 1 4 2 5 1 9 7/ REF195 – +5.0V 0 +10V IN OUT 1 – 10µF GND 1µF 10µF 52 0 2 C 30kW 1/2 OP279 O1 O2 O3 O4 1/2 OP279 40kW 2.0V VDD AD8804 1.0V 20kW A VREFH VREFL B 10kW GND SHDN SDI CLK CS TO µC Figure 30.A Low Noise 90 MHz PGA OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 20-Pin Plastic DIP Package 20-Lead SOIC Package (N-20) (R-20) 1.07 (27.18) MAX 0.512 (13.00) 0.496 (12.60) 20 11 0.255 (6.477) 0.245 (6.223) 1 10 20 11 0.32 (8.128) 0.145 (3.M68A3X) PIN 1 00..006105 ((10..5328)) 0.30 (7.62) 00.1.13255 ( (33.4.1279)) 1 10 0.299 (7.60)0.291 (7.40) 0.419 (10.65)0.404 (10.00) 0.125 (3.175) MIN 0.011 (0.28) 0.021 (0.533) 0.11 (2.79) 0.065 (1.66) SEATING 15(cid:176) 0.009 (0.23) PIN 1 0.107 (2.72) 0.015 (0.381) 0.09 (2.28) 0.045 (1.15) PLANE 0 0.089 (2.26) 8(cid:176) 0.011 (0.275) 0.050 0.022 (0.56) 0(cid:176) 0.005 (0.125) (B1.S2C7) 0.014 (0.36) SPELAANTIENG 00..001057 ((00..3188)) 00..003148 ((00..8466)) 20-Lead Thin Surface Mount TSSOP Package (RU-20) A. S. U. 0.260 (6.60) N 0.252 (6.40) D I E T 20 11 N 0.177 (4.50)0.169 (4.30) 0.256 (6.50)0.246 (6.25) PRI 1 10 0.006 (0.15) PIN 1 0.002 (0.05) 0.0433 (1.10) MAX 8(cid:176) 0.028 (0.70) SEPALTAINNGE 0.02B56S C(0.65) 00..00101785 ((00..3109)) 0.0079 (0.20) 0(cid:176) 0.020 (0.50) 0.0035 (0.090) –16– REV. 0

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8802ARU AD8804ARUZ-REEL AD8802ARU-REEL AD8804ARUZ AD8802ARZ-REEL AD8802ARUZ-REEL AD8804ANZ AD8804ARZ-REEL AD8802ARUZ AD8804ARZ AD8802ARZ