Low Power, Rail-to-Rail, Output Precision JFET Amplifier AD8643-EP FEATURES PIN CONFIGURATION Low supply current: 250 μA maximum OUT A 1 14 OUT D Very low input bias current: 1 pA maximum –IN A 2 13 –IN D Low offset voltage: 750 μV maximum +IN A 3 AD8643-EP 12 +IN D Single-supply operation: 5 V to 26 V V+ 4 TOP VIEW 11 V– Dual-supply operation: ±2.5 V to ±13 V (Not to Scale) +IN B 5 10 +IN C Rail-to-rail output –IN B 6 9 –IN C UNno iptyh-agsaei nre svtaebrslael OUT B 7 8 OUT C 09590-103 Figure 1. 14-Lead SOIC (R-14) ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Enhanced product change notification Qualification data available on request APPLICATIONS Line-/battery-powered instruments Photodiode amplifiers Precision current sensing Precision filters Portable audio GENERAL DESCRIPTION The AD8643-EP is a low power, precision JFET input amplifier The AD8643-EP is suitable for applications using multichannel featuring extremely low input bias current and rail-to-rail output. boards that require low power to manage heat. Other applications The ability to swing nearly rail-to-rail at the input and rail-to-rail at include photodiodes and battery management. the output enables designers to buffer CMOS digital-to-analog The AD8643-EP is fully specified over the military temperature converters (DACs), ASICs, and other wide output swing devices range of −55°C to +125°C. This device is available in a 14-lead SOIC. in single-supply systems. The outputs remain stable with capacitive Additional applications information is available in the AD8643 loads of more than 500 pF. data sheet. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

AD8643-EP TABLE OF CONTENTS Features..............................................................................................1  Electrical Characteristics..............................................................3  Enhanced Product Features............................................................1  Absolute Maximum Ratings............................................................5  Applications.......................................................................................1  Thermal Resistance.......................................................................5  Pin Configuration.............................................................................1  ESD Caution...................................................................................5  General Description.........................................................................1  Typical Performance Characteristics..............................................6  Revision History...............................................................................2  Outline Dimensions.......................................................................12  Specifications.....................................................................................3  Ordering Guide..........................................................................12  REVISION HISTORY 1/11—Revision 0: Initial Version Rev. 0 | Page 2 of 12

AD8643-EP SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 5.0 V, V = 2.5 V, T = 25°C, unless otherwise noted. S CM A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 50 1000 μV OS −55°C < T < +85°C 1.8 mV A +85°C < T < +125°C, V = 1.5 V 1.9 mV A CM Input Bias Current I 0.25 1 pA B −55°C < T < +125°C 180 pA A Input Offset Current I 0.5 pA OS −55°C < T < +125°C 60 pA A Input Voltage Range 0 3 V Common-Mode Rejection Ratio CMRR V = 0 V to 2.5 V 74 93 dB CM Large Signal Voltage Gain A R = 10 kΩ, V = 0.5 to 4.5 V 80 140 V/mV VO L O Offset Voltage Drift ΔV /ΔT −55°C < T < +125°C 2.5 μV/°C OS A OUTPUT CHARACTERISTICS Output Voltage High V 4.95 V OH I = 1 mA, −55°C to +125°C 4.94 V L Output Voltage Low V 0.05 V OL I = 1 mA, −55°C to +125°C 0.01 0.05 V L Output Current I ±6 mA OUT POWER SUPPLY Power Supply Rejection Ratio PSRR V = 5 V to 26 V 90 107 dB S Supply Current/Amplifier I 195 250 μA SY −55°C < T < +125°C 270 μA A DYNAMIC PERFORMANCE Slew Rate SR 2 V/μs Gain Bandwidth Product GBP 2.5 MHz Phase Margin Ø 50 Degrees m NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz 4.0 μV p-p N Voltage Noise Density e f = 1 kHz 28.5 nV/√Hz N Current Noise Density i f = 1 kHz 0.5 fA/√Hz N Rev. 0 | Page 3 of 12

AD8643-EP V= ±13 V, V = 0 V, T = 25°C, unless otherwise noted. S CM A Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V 70 1000 μV OS −55° < T < +125°C 1.8 mV A Input Bias Current I 0.25 1 pA B –55°C < T < +125°C 260 pA A Input Offset Current I 0.5 pA OS −55°C < T < +125°C 65 pA A Input Voltage Range −13 +10 V Common-Mode Rejection Ratio CMRR V = −13 V to +10 V 90 107 dB CM Large Signal Voltage Gain A R = 10 kΩ, V = –11 V to +11 V 215 290 V/mV VO L O Offset Voltage Drift ΔV /ΔT −55°C < T < +125°C 2.5 μV/°C OS A OUTPUT CHARACTERISTICS Output Voltage High V 12.95 V OH I = 1 mA, −55°C to +125°C 12.94 V L Output Voltage Low V −12.95 V OL I = 1 mA, −55°C to +125°C −12.94 V L Output Current I ±12 mA OUT POWER SUPPLY Power Supply Rejection Ratio PSRR V = ±2.5 V to ±13 V 90 107 dB S Supply Current/Amplifier I 200 290 μA SY −55°C < T < +125°C 330 μA A DYNAMIC PERFORMANCE Slew Rate SR 3 V/μs Gain Bandwidth Product GBP 3.5 MHz Phase Margin Ø 60 Degrees m NOISE PERFORMANCE Voltage Noise e p-p f = 0.1 Hz to 10 Hz 4.2 μV p-p N Voltage Noise Density e f = 1 kHz 27.5 nV/√Hz N Current Noise Density i f = 1 kHz 0.5 fA/√Hz N Rev. 0 | Page 4 of 12

AD8643-EP ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Absolute maximum ratings apply at 25°C, unless otherwise noted. θ is specified for the worst-case conditions, that is, a device JA Table 3. soldered in a circuit board for surface-mount packages. Parameter Rating Supply Voltage 27.3 V Table 4. Thermal Resistance Input Voltage V− to V+ Package Type θ θ Unit JA JC Differential Input Voltage ±Supply Voltage 14-Lead SOIC (R) 120 36 °C/W Output Short-Circuit Duration Indefinite Storage Temperature Range −65°C to +150°C ESD CAUTION Operating Temperature Range −55°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 12

AD8643-EP TYPICAL PERFORMANCE CHARACTERISTICS 80 20 VSY =±13V VSY = 5V 70 18 VCM = 1.5V 16 60 S ER 14 Y 50 LIFI 12 C P N M REQUE 40 R OF A 108 F 30 E B M 6 U 20 N 4 10 2 0 0 –0.60–0.55–0.50–0.45–0.40–0.35–0.30–0.25–0.20–0.15–0.10V–0.05OS0 (m0.05V)0.100.150.200.250.300.350.400.450.500.550.60 09590-002 0 0.5 1.01.5 2.0 2.5 3.0 3.5 T4.0CV4.5OS5.0 (μV5.5/°C6.0) 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 09590-005 Figure 2. Input Offset Voltage Figure 5. Offset Voltage Drift 16 4.5 14 VSY =±13V 4.0 VSY =±13V TA = 25°C 3.5 S 12 R E 3.0 MPLIFI 10 S (pA) 2.5 F A 8 BIA 2.0 ER O 6 PUT 1.5 B N M I U 1.0 N 4 0.5 2 0 0 –0.5 0 0.5 1.0 1.5 2.0 2.5O3.0FF3.5SE4.0T V4.5OL5.0TA5.5GE6.0 (μV6.5/°C7.0)7.5 8.0 8.5 9.0 9.5 10.0 09590-003 –15 –13 –11 –9 –7 –5 –3 V–C1M (V1) 3 5 7 9 11 13 15 09590-006 Figure 3. Offset Voltage Drift Figure 6. Input Bias Current vs. VCM 70 1000 VSY =±2.5V VSY =±13V 60 A) 100 50 p T ( N Y E NC 40 RR UE CU 10 FREQ 30 BIAS T U 20 P N 1 I 10 0 0.1 –0.60–0.55–0.50–0.45–0.40–0.35–0.30–0.25–0.20–0.15–0.10V–0.05OS0 (m0.05V)0.100.150.200.250.300.350.400.450.500.550.60 09590-004 0 25 50TEMPERA75TURE (°C1)00 125 150 09590-008 Figure 4. Input Offset Voltage Figure 7. Input Bias Current vs. Temperature Rev. 0 | Page 6 of 12

AD8643-EP 1.0 10M VSY = +5V OR±5V 0.8 0.6 0.4 V) pA) 0.2 N (V/ 1M AS ( GAI VSY =±13V NPUT BI –0.20 N-LOOP I –0.4 PE100k VSY =±2.5V O –0.6 –0.8 –1.0 10k –5 –4 –3 –2 –1 VCM0 (V) 1 2 3 4 5 09590-009 0.1 1 10 100 09590-012 Figure 8. Input Bias Current vs. VCM Figure 11. Open-Loop Gain vs. Load Resistance 1000 1000 VSY =±13V 900 A 800 B 700 C 600 100 D V)μ 500 mV) E V (OS 400 (V/VO 300 A 10 200 A. VSY =±13V, VO =±11V, RL = 10kΩ 100 B. VSY =±13V, VO =±11V, RL = 2kΩ C. VSY = +5V, VO = +0.5V/+4.5V, RL = 10kΩ 0 D. VSY = +5V, VO = +0.5V/+4.5V, RL = 2kΩ E. VSY = +5V, VO = +0.5V/+4.5V, RL = 600Ω –100 1 –15 –13 –11 –9 –7 –5 –3 V–C1M (V1) 3 5 7 9 11 13 15 09590-010 –70 –50 –30 –10 T1E0MPE3R0ATU50RE (°7C0) 90 110 130 150 09590-013 Figure 9. Input Offset Voltage (VOS) vs. VCM Figure 12. Open-Loop Gain vs. Temperature 500 600 400 VSY = 5V 500 VSY =±13V 400 300 300 200 200 V) 100 100 μ (S 0 0 O V–100 –100 –200 –200 –300 –300 –400 –400 –500 –500 –600 0 0.5 1.0VCM (V)1.5 2.0 2.5 09590-011 –15 –10 –O5UTPUT VO0LTAGE (V5) 10 15 09590-014 Figure 10. Input Offset Voltage vs. VCM Figure 13. Input Error Voltage vs. Output Voltage for Resistive Loads Rev. 0 | Page 7 of 12

AD8643-EP 250 10000 200 VSY =±5V POS RAIL VSY = 5V VSY– VOH 150 100 RL = 1kΩ mV)1000 OLTAGE (V)μ –55000 RL = R2Lk Ω= 10kΩ RL = 100kΩ N VOLTAGE ( 100 VOL T V–100 TIO U A P–150 R N U I–200 AT 10 S –250 RL = 100kΩ RL = 1kΩ RL = 10kΩ –300 NEG RAIL –350 RL = 2kΩ 1 0 5O0UTPUT1 0V0OLTAG15E0 FROM2 0S0UPPLY2 5R0AIL (m3V0)0 350 09590-015 0.001 0.01 LOA0.D1 CURRENT1 (mA) 10 100 09590-018 Figure 14. Input Error Voltage vs. Output Voltage Figure 17. Output Saturation Voltage vs. Load Current Within 300 mV of Supply Rails 800 70 315 VSY =±13V 700 60 RL = 2kΩ 270 CL = 40pF 50 225 600 40 180 500 GAIN es) B) 30 135 gre 400 AIN (d 20 PHASE 90 SE (De 300 +25°C G 10 45 A +125°C PH 0 0 200 –55°C –10 –45 100 –20 –90 0 4 8 12 VS1Y6 (V) 20 24 28 09590-016 –3010k 100k FREQUENC1YM(Hz) 10M –135 09590-019 Figure 15. Quiescent Current vs. Supply Voltage at Different Temperatures Figure 18. Open-Loop Gain and Phase Margin vs. Frequency 10000 70 315 VSY =±13V 60 RVSLY = = 2 k5VΩ 270 mV)1000 VSY– VOH 50 CL = 40pF 225 LTAGE ( B) 3400 GAIN 113850 grees) ON VO 100 –VSY– VOL AIN (d 20 PHASE 90 SE (De RATI G 10 45 PHA U 0 0 AT 10 S –10 –45 –20 –90 1 –30 –135 0.001 0.01 LOA0.D1 CURRENT1 (mA) 10 100 09590-017 10k 100k FREQUENC1YM(Hz) 10M 09590-020 Figure 16. Output Saturation Voltage vs. Load Current Figure 19. Open-Loop Gain and Phase Margin vs. Frequency Rev. 0 | Page 8 of 12

AD8643-EP 70 140 VSY =±13V VSY = 5V 60 RL = 2kΩ 120 CL = 40pF 50 100 40 80 G = +100 B) 30 B) 60 d d N ( 20 R ( 40 GAI 10 G = +10 CMR 20 0 0 G = +1 –10 –20 –20 –40 –30 –60 1k 10k FRE1Q00UkENCY(Hz)1M 10M 09590-021 1k 10k FREQU1E0N0kCY(Hz) 1M 10M 09590-024 Figure 20. Closed-Loop Gain vs. Frequency Figure 23. CMRR vs. Frequency 70 140 60 120 VSY =±13V 50 100 +PSRR 40 80 G = +100 B) 30 B) 60 AIN (d 20 G = +10 RR (d 40 –PSRR G 10 PS 20 0 0 G = +1 –10 –20 –20 –40 –301k 10k FRE1Q00UkENCY(Hz)1M 10M 09590-022 –601k 10k FREQU1E0N0kCY(Hz) 1M 10M 09590-025 Figure 21. Closed-Loop Gain vs. Frequency Figure 24. PSRR vs. Frequency 140 140 VSY =±13V VSY = 5V 120 120 100 100 +PSRR 80 80 B) 60 B) 60 d d R ( 40 R ( 40 R R –PSRR M S C 20 P 20 0 0 –20 –20 –40 –40 –60 –60 1k 10k FREQU1E0N0kCY(Hz) 1M 10M 09590-023 1k 10k FREQU1E0N0kCY(Hz) 1M 10M 09590-026 Figure 22. CMRR vs. Frequency Figure 25. PSRR vs. Frequency Rev. 0 | Page 9 of 12

AD8643-EP 1000 15 VSY =±13V VS =±13V G = +100 GAIN = +5 10 100 TS + (1%) V) 5 TS + (0.1%) 10 G ( Z ()ΩOUT 1 G = +10 PUT SWIN 0 T G = +1 OU –5 TS– (0.1%) 0.1 –10 TS– (1%) 0.01 –15 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 09590-027 0 0.2 0.4 0.6SE0T.T8LIN1G.0 TIME1. 2(μs)1.4 1.6 1.8 2.0 09590-030 Figure 26. Output Impedance vs. Frequency Figure 29. Output Swing and Error vs. Settling Time 1000 70 VSY = 5V VS =±13V G = +100 60 RL = 10kΩ 100 VAIVN == +1100mV p-p 50 %) )Ω 10 OT ( 40 Z (OUT 1 G = +10 ERSHO 30 OS– G = +1 OV OS+ 20 0.1 10 0.01 0 1k 10k F10R0EkQUENCY 1(HMz) 10M 100M 09590-028 1 10CAPACITANCE (pF1)00 1000 09590-031 Figure 27. Output Impedance vs. Frequency Figure 30. Small Signal Overshoot vs. Load Capacitance T VSY =±13V 70 VS =±2.5V 60 RL = 10kΩ VIN = 100mV p-p 1 AV = +1 VIN 50 %) OT ( 40 OS– O H S R 30 E V O OS+ 20 2 VOUT 10 CH1 10.0V CH2 10.0V MT 4 0 0 μ 0s.00000s A CH1 1.00V 09590-029 01 10CAPACITANCE (pF1)00 1000 09590-032 Figure 28. No Phase Reversal Figure 31. Small Signal Overshoot vs. Load Capacitance Rev. 0 | Page 10 of 12

AD8643-EP 1k VSG = =± +113MV VSY = 5V CH1 p-p = 4.26V Hz) V/ n Y ( 100 T SI N E 1 D E S OI N E 10 G A T L O V CH1 1.00V M1.00s A CH1 –20.0V 09590-033 110 100FREQUENCY (Hz)1k 10k 09590-036 Figure 32. 0.1 Hz to 10 Hz Noise Figure 35. Voltage Noise Density 0.004 VSG = =± 2+.15MV VSY =±13V 8V p-p INPUT LOAD = 100kΩ CH1 p-p = 4.06V 0.001 GAIN = +1 %) 1V p-p INPUT E ( 2V p-p INPUT S0.0001 1 NOI 4V p-p INPUT + D H T 0.00001 CH1 1.00V M1.00s A CH1 –20.0V 09590-034 0.0000011 100 FREQUENCY1 k(Hz) 10k 20k 09590-037 Figure 33. 0.1 Hz to 10 Hz Noise Figure 36. Total Harmonic Distortion + Noise vs. Frequency 1k –40 VSY =±13V –50 20kΩ 2kΩ Hz) –60 – – nV/ –70 VIN + 2kΩ 2kΩ + Y ( 100 –80 T NSI –90 DE B)–100 VIN = 18V p-p OISE (d–110 N VIN = 4.5V p-p E 10 –120 G TA –130 L VO –140 VIN = 9V p-p –150 1 –160 10 100FREQUENCY (Hz)1k 10k 09590-035 20 100 FRE1kQUENCY (Hz)10k 100k 09590-041 Figure 34. Voltage Noise Density Figure 37. Channel Separation Rev. 0 | Page 11 of 12

AD8643-EP OUTLINE DIMENSIONS 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 38. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD8643TRZ-EP −55°C to +125°C 14-lead SOIC_N R-14 AD8643TRZ-EP-R7 −55°C to +125°C 14-lead SOIC_N R-14 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09590-0-1/11(0) Rev. 0 | Page 12 of 12

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD8641AKSZ-REEL AD8641ARZ-REEL AD8643TRZ-EP AD8643ARZ-REEL AD8641AKSZ-REEL7 AD8643TRZ- EP-R7 AD8641ARZ-REEL7 AD8642ARZ AD8641AKSZ-R2 AD8643ARZ-REEL7 AD8643ACPZ-REEL7 AD8643ARZ AD8643ACPZ-R2 AD8643ACPZ-REEL AD8642ARZ-REEL AD8642ARZ-REEL7 AD8642ARMZ-REEL AD8642ARMZ AD8641ARZ